drm/amdgpu: initialize umc ras function

support umc ras function initialization for aldebaran

v2: squash in compile fix

Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7eb70d6..097230b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -53,6 +53,7 @@
 #include "mmhub_v1_7.h"
 #include "umc_v6_1.h"
 #include "umc_v6_0.h"
+#include "umc_v6_7.h"
 #include "hdp_v4_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
@@ -1168,6 +1169,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
                adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
                adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
                break;
+       case CHIP_ALDEBARAN:
+               adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
+               adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+               adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
+               adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
+               if (!adev->gmc.xgmi.connected_to_cpu)
+                       adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
+               if (1 & adev->smuio.funcs->get_die_id(adev))
+                       adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
+               else
+                       adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
+               break;
        default:
                break;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 3a8f787..7da1211 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -28,6 +28,21 @@
 #include "umc/umc_6_7_0_offset.h"
 #include "umc/umc_6_7_0_sh_mask.h"
 
+const uint32_t
+       umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
+               {28, 12, 6, 22},        {19, 3, 9, 25},
+               {20, 4, 30, 14},        {11, 27, 1, 17},
+               {24, 8, 2, 18},         {15, 31, 5, 21},
+               {16, 0, 26, 10},        {7, 23, 29, 13}
+};
+const uint32_t
+       umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
+               {19, 3, 9, 25},         {28, 12, 6, 22},
+               {11, 27, 1, 17},        {20, 4, 30, 14},
+               {15, 31, 5, 21},        {24, 8, 2, 18},
+               {7, 23, 29, 13},        {16, 0, 26, 10}
+};
+
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
                                              uint32_t umc_inst,
                                              uint32_t ch_inst)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 4eb85f2..81b8f18 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -23,6 +23,9 @@
 #ifndef __UMC_V6_7_H__
 #define __UMC_V6_7_H__
 
+#include "soc15_common.h"
+#include "amdgpu.h"
+
 /* EccErrCnt max value */
 #define UMC_V6_7_CE_CNT_MAX            0xffff
 /* umc ce interrupt threshold */
@@ -32,6 +35,18 @@
 
 #define UMC_V6_7_INST_DIST     0x40000
 
+/* number of umc channel instance with memory map register access */
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM          4
+/* number of umc instance with memory map register access */
+#define UMC_V6_7_UMC_INSTANCE_NUM              8
+/* total channel instances in one umc block */
+#define UMC_V6_7_TOTAL_CHANNEL_NUM     (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
+/* UMC regiser per channel offset */
+#define UMC_V6_7_PER_CHANNEL_OFFSET            0x400
 extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
+extern const uint32_t
+       umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
+extern const uint32_t
+       umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
 
 #endif