- return dev_err_probe(port->dev, PTR_ERR(clk_xtal),
- "Failed to get the 'xtal' clock\n");
-
- snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(port->dev),
- "clk81_div4");
- clk81_div4_hw = devm_clk_hw_register_fixed_factor(port->dev,
- clk_name,
- __clk_get_name(clk_baud),
- CLK_SET_RATE_NO_REPARENT,
- 1, 4);
- if (IS_ERR(clk81_div4_hw))
- return PTR_ERR(clk81_div4_hw);
-
- snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(port->dev),
- "xtal_div");
- hw = devm_clk_hw_register_divider_table(port->dev,
- clk_name,
- __clk_get_name(clk_baud),
- CLK_SET_RATE_NO_REPARENT,
- port->membase + AML_UART_REG5,
- 26, 2,
- CLK_DIVIDER_ROUND_CLOSEST,
- xtal_div_table, NULL);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- if (private_data->use_xtal_clk) {
- use_xtal_mux_table = 1;
- use_xtal_mux_parents.hw = hw;
- } else {
- use_xtal_mux_parents.hw = clk81_div4_hw;
- }