drm/amd/pm: correct the runpm handling for BACO supported ASIC

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the
Dstate change. Driver involvement for determining the timing for
BACO enter/exit is not needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index a3b2897..1962a58 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -244,6 +244,9 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
 int smu_v11_0_baco_enter(struct smu_context *smu);
 int smu_v11_0_baco_exit(struct smu_context *smu);
 
+int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
+                                     enum smu_v11_0_baco_seq baco_seq);
+
 int smu_v11_0_mode1_reset(struct smu_context *smu);
 
 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index dab1445..5a967db 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2255,6 +2255,29 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
        return 0;
 }
 
+static int navi10_baco_enter(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+
+       if (adev->in_runpm)
+               return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+       else
+               return smu_v11_0_baco_enter(smu);
+}
+
+static int navi10_baco_exit(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+
+       if (adev->in_runpm) {
+               /* Wait for PMFW handling for the Dstate change */
+               msleep(10);
+               return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+       } else {
+               return smu_v11_0_baco_exit(smu);
+       }
+}
+
 static int navi10_set_default_od_settings(struct smu_context *smu)
 {
        OverDriveTable_t *od_table =
@@ -3105,8 +3128,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .baco_is_support = smu_v11_0_baco_is_support,
        .baco_get_state = smu_v11_0_baco_get_state,
        .baco_set_state = smu_v11_0_baco_set_state,
-       .baco_enter = smu_v11_0_baco_enter,
-       .baco_exit = smu_v11_0_baco_exit,
+       .baco_enter = navi10_baco_enter,
+       .baco_exit = navi10_baco_exit,
        .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
        .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
        .set_default_od_settings = navi10_set_default_od_settings,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index e2a3df7..848efc2 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2121,6 +2121,29 @@ static int sienna_cichlid_run_btc(struct smu_context *smu)
        return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 }
 
+static int sienna_cichlid_baco_enter(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+
+       if (adev->in_runpm)
+               return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+       else
+               return smu_v11_0_baco_enter(smu);
+}
+
+static int sienna_cichlid_baco_exit(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+
+       if (adev->in_runpm) {
+               /* Wait for PMFW handling for the Dstate change */
+               msleep(10);
+               return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+       } else {
+               return smu_v11_0_baco_exit(smu);
+       }
+}
+
 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
@@ -3899,8 +3922,8 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
        .baco_is_support = smu_v11_0_baco_is_support,
        .baco_get_state = smu_v11_0_baco_get_state,
        .baco_set_state = smu_v11_0_baco_set_state,
-       .baco_enter = smu_v11_0_baco_enter,
-       .baco_exit = smu_v11_0_baco_exit,
+       .baco_enter = sienna_cichlid_baco_enter,
+       .baco_exit = sienna_cichlid_baco_exit,
        .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
        .mode1_reset = smu_v11_0_mode1_reset,
        .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index e1e1c26..388c5cb 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1474,7 +1474,8 @@ int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
        return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
 }
 
-static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
+int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
+                                     enum smu_v11_0_baco_seq baco_seq)
 {
        return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
 }
@@ -1578,16 +1579,8 @@ out:
 
 int smu_v11_0_baco_enter(struct smu_context *smu)
 {
-       struct amdgpu_device *adev = smu->adev;
        int ret = 0;
 
-       /* Arcturus does not need this audio workaround */
-       if (adev->asic_type != CHIP_ARCTURUS) {
-               ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
-               if (ret)
-                       return ret;
-       }
-
        ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
        if (ret)
                return ret;