Revert "ARM: sti: Implement dummy L2 cache's write_sec"

This reverts commit 7b8e0188fa717cd9abc4fb52587445b421835c2a.

Initially, STiH410-B2260 was supposed to be secured, that's why
l2c_write_sec was stubbed to avoid secure register access from
non secure world.

But by default, STiH410-B2260 is running in non secure mode,
so L2 cache register accesses are authorized, l2c_write_sec stub
is not needed.

With this patch, L2 cache is configured and performance are enhanced.

Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Alain Volmat <alain.volmat@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index dcb9893..ffecbf2 100644 (file)
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -20,14 +20,6 @@ static const char *const stih41x_dt_match[] __initconst = {
        NULL
 };
 
-static void sti_l2_write_sec(unsigned long val, unsigned reg)
-{
-       /*
-        * We can't write to secure registers as we are in non-secure
-        * mode, until we have some SMI service available.
-        */
-}
-
 DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
        .dt_compat      = stih41x_dt_match,
        .l2c_aux_val    = L2C_AUX_CTRL_SHARED_OVERRIDE |
@@ -36,5 +28,4 @@ DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
                          L2C_AUX_CTRL_WAY_SIZE(4),
        .l2c_aux_mask   = 0xc0000fff,
        .smp            = smp_ops(sti_smp_ops),
-       .l2c_write_sec  = sti_l2_write_sec,
 MACHINE_END