drm/i915: stop setting cache_dirty on discrete

Should not be needed. Even with non-coherent display, we should be using
device local-memory there, and not system memory.

v2: also add a warning in i915_gem_clflush_object

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> #v1
Link: https://patchwork.freedesktop.org/patch/msgid/20211027161813.3094681-4-matthew.auld@intel.com

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index fc76175..8a24800 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -74,6 +74,11 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
 
        assert_object_held(obj);
 
+       if (IS_DGFX(i915)) {
+               WARN_ON_ONCE(obj->cache_dirty);
+               return false;
+       }
+
        /*
         * Stolen memory is always coherent with the GPU as it is explicitly
         * marked as wc by the system, or the system is cache-coherent.
@@ -81,7 +86,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
         * anything not backed by physical memory we consider to be always
         * coherent and not need clflushing.
         */
-       if (!i915_gem_object_has_struct_page(obj) || IS_DGFX(i915)) {
+       if (!i915_gem_object_has_struct_page(obj)) {
                obj->cache_dirty = false;
                return false;
        }

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index d30d5a6..26532c0 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -18,18 +18,28 @@
 
 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+       if (IS_DGFX(i915))
+               return false;
+
        return !(obj->cache_level == I915_CACHE_NONE ||
                 obj->cache_level == I915_CACHE_WT);
 }
 
 bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
        if (obj->cache_dirty)
                return false;
 
        if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
                return true;
 
+       if (IS_DGFX(i915))
+               return false;
+
        /* Currently in use by HW (display engine)? Keep flushed. */
        return i915_gem_object_is_framebuffer(obj);
 }

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 55b0f1d..591ee3c 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -114,18 +114,21 @@ void __i915_gem_object_fini(struct drm_i915_gem_object *obj)
 void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
                                         unsigned int cache_level)
 {
+       struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
        obj->cache_level = cache_level;
 
        if (cache_level != I915_CACHE_NONE)
                obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
                                       I915_BO_CACHE_COHERENT_FOR_WRITE);
-       else if (HAS_LLC(to_i915(obj->base.dev)))
+       else if (HAS_LLC(i915))
                obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ;
        else
                obj->cache_coherent = 0;
 
        obj->cache_dirty =
-               !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE);
+               !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE) &&
+               !IS_DGFX(i915);
 }
 
 bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 308e22a..c4f684b 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -26,6 +26,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 
        /* Make the pages coherent with the GPU (flushing any swapin). */
        if (obj->cache_dirty) {
+               WARN_ON_ONCE(IS_DGFX(i915));
                obj->write_domain = 0;
                if (i915_gem_object_has_struct_page(obj))
                        drm_clflush_sg(pages);