soc: mediatek: mmsys: Add support for MT8167 SoC
authorFabien Parent <fparent@baylibre.com>
Mon, 5 Apr 2021 20:03:53 +0000 (22:03 +0200)
committerMatthias Brugger <matthias.bgg@gmail.com>
Tue, 6 Apr 2021 10:57:10 +0000 (12:57 +0200)
Add routing table for DSI on MT8167 SoC. The registers are mostly
incompatible with the current defines, so new one for MT8167 are added.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210405200354.2194930-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
drivers/soc/mediatek/mt8167-mmsys.h [new file with mode: 0644]
drivers/soc/mediatek/mtk-mmsys.c

diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
new file mode 100644 (file)
index 0000000..2772ef5
--- /dev/null
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8167_MMSYS_H
+#define __SOC_MEDIATEK_MT8167_MMSYS_H
+
+#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN       0x030
+#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN     0x038
+#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN      0x058
+#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN                0x064
+#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN  0x06c
+
+#define MT8167_DITHER_MOUT_EN_RDMA0                    0x1
+#define MT8167_RDMA0_SOUT_DSI0                         0x2
+#define MT8167_DSI0_SEL_IN_RDMA0                       0x1
+
+static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
+       {
+               DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+               MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
+       }, {
+               DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+               MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
+       }, {
+               DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
+               MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0
+       }, {
+               DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+               MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0
+       }, {
+               DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
+               MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0
+       },
+};
+
+#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
index 79e5515..080660e 100644 (file)
@@ -11,6 +11,7 @@
 #include <linux/soc/mediatek/mtk-mmsys.h>
 
 #include "mtk-mmsys.h"
+#include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -33,6 +34,12 @@ static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
        .clk_driver = "clk-mt6797-mm",
 };
 
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+       .clk_driver = "clk-mt8167-mm",
+       .routes = mt8167_mmsys_routing_table,
+       .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
        .clk_driver = "clk-mt8173-mm",
        .routes = mmsys_default_routing_table,
@@ -138,6 +145,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
                .compatible = "mediatek,mt6797-mmsys",
                .data = &mt6797_mmsys_driver_data,
        },
+       {
+               .compatible = "mediatek,mt8167-mmsys",
+               .data = &mt8167_mmsys_driver_data,
+       },
        {
                .compatible = "mediatek,mt8173-mmsys",
                .data = &mt8173_mmsys_driver_data,