Merge tag 'riscv-for-linus-6.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:
 "There's a bunch of fixes/cleanups throughout the tree as usual, but we
  also have a handful of new features:

   - Various improvements to the extension detection and alternative
     patching infrastructure

   - Zbb-optimized string routines

   - Support for cpu-capacity in the RISC-V DT bindings

   - Zicbom no longer depends on toolchain support

   - Some performance and code size improvements to ftrace

   - Support for ARCH_WANT_LD_ORPHAN_WARN

   - Oops now contain the faulting instruction"

* tag 'riscv-for-linus-6.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (67 commits)
  RISC-V: add a spin_shadow_stack declaration
  riscv: mm: hugetlb: Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
  riscv: Add header include guards to insn.h
  riscv: alternative: proceed one more instruction for auipc/jalr pair
  riscv: Avoid enabling interrupts in die()
  riscv, mm: Perform BPF exhandler fixup on page fault
  RISC-V: take text_mutex during alternative patching
  riscv: hwcap: Don't alphabetize ISA extension IDs
  RISC-V: fix ordering of Zbb extension
  riscv: jump_label: Fixup unaligned arch_static_branch function
  RISC-V: Only provide the single-letter extensions in HWCAP
  riscv: mm: fix regression due to update_mmu_cache change
  scripts/decodecode: Add support for RISC-V
  riscv: Add instruction dump to RISC-V splats
  riscv: select ARCH_WANT_LD_ORPHAN_WARN for !XIP_KERNEL
  riscv: vmlinux.lds.S: explicitly catch .init.bss sections from EFI stub
  riscv: vmlinux.lds.S: explicitly catch .riscv.attributes sections
  riscv: vmlinux.lds.S: explicitly catch .rela.dyn symbols
  riscv: lds: define RUNTIME_DISCARD_EXIT
  RISC-V: move some stray __RISCV_INSN_FUNCS definitions from kprobes
  ...

diff --cc Documentation/devicetree/bindings/arm/cpus.yaml
Simple merge

diff --cc arch/riscv/Kconfig
index 9c687da,81eb031..c5e42cc
--- 1/arch/riscv/Kconfig
--- 2/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@@ -12,12 -12,14 +12,13 @@@ config 32BI
  
  config RISCV
        def_bool y
 -      select ARCH_CLOCKSOURCE_INIT
        select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
        select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
+       select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
        select ARCH_HAS_BINFMT_FLAT
        select ARCH_HAS_CURRENT_STACK_POINTER
-       select ARCH_HAS_DEBUG_VM_PGTABLE
        select ARCH_HAS_DEBUG_VIRTUAL if MMU
+       select ARCH_HAS_DEBUG_VM_PGTABLE
        select ARCH_HAS_DEBUG_WX
        select ARCH_HAS_FORTIFY_SOURCE
        select ARCH_HAS_GCOV_PROFILE_ALL

diff --cc arch/riscv/Kconfig.socs
index 4b91367,6591403..1cf69f9
--- 1/arch/riscv/Kconfig.socs
--- 2/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@@ -32,18 -32,9 +32,18 @@@ config SOC_STARFIV
        help
          This enables support for StarFive SoC platform hardware.
  
 +config ARCH_SUNXI
 +      bool "Allwinner sun20i SoCs"
 +      depends on MMU && !XIP_KERNEL
 +      select ERRATA_THEAD
 +      select SUN4I_TIMER
 +      help
 +        This enables support for Allwinner sun20i platform hardware,
 +        including boards based on the D1 and D1s SoCs.
 +
  config ARCH_VIRT
        def_bool SOC_VIRT
-       
+ 
  config SOC_VIRT
        bool "QEMU Virt Machine"
        select CLINT_TIMER if RISCV_M_MODE

diff --cc arch/riscv/Makefile
Simple merge

diff --cc arch/riscv/include/asm/hwcap.h
index 64ad193,8f3994a..e3021b2
--- 1/arch/riscv/include/asm/hwcap.h
--- 2/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -37,43 -24,36 +24,32 @@@
  #define RISCV_ISA_EXT_u               ('u' - 'a')
  
  /*
-  * Increse this to higher value as kernel support more ISA extensions.
+  * These macros represent the logical IDs of each multi-letter RISC-V ISA
+  * extension and are used in the ISA bitmap. The logical IDs start from
+  * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
+  * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
+  * to allocate the bitmap and may be increased when necessary.
+  *
+  * New extensions should just be added to the bottom, rather than added
+  * alphabetically, in order to avoid unnecessary shuffling.
   */
- #define RISCV_ISA_EXT_MAX     64
- #define RISCV_ISA_EXT_NAME_LEN_MAX 32
+ #define RISCV_ISA_EXT_BASE            26
  
- /* The base ID for multi-letter ISA extensions */
- #define RISCV_ISA_EXT_BASE 26
+ #define RISCV_ISA_EXT_SSCOFPMF                26
+ #define RISCV_ISA_EXT_SSTC            27
+ #define RISCV_ISA_EXT_SVINVAL         28
+ #define RISCV_ISA_EXT_SVPBMT          29
+ #define RISCV_ISA_EXT_ZBB             30
+ #define RISCV_ISA_EXT_ZICBOM          31
+ #define RISCV_ISA_EXT_ZIHINTPAUSE     32
  
- /*
-  * This enum represent the logical ID for each multi-letter RISC-V ISA extension.
-  * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
-  * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
-  * extensions while all the multi-letter extensions should define the next
-  * available logical extension id.
-  */
- enum riscv_isa_ext_id {
-       RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
-       RISCV_ISA_EXT_SVPBMT,
-       RISCV_ISA_EXT_ZICBOM,
-       RISCV_ISA_EXT_ZIHINTPAUSE,
-       RISCV_ISA_EXT_SSTC,
-       RISCV_ISA_EXT_SVINVAL,
-       RISCV_ISA_EXT_ID_MAX
- };
- static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
+ #define RISCV_ISA_EXT_MAX             64
+ #define RISCV_ISA_EXT_NAME_LEN_MAX    32
  
- /*
-  * This enum represents the logical ID for each RISC-V ISA extension static
-  * keys. We can use static key to optimize code path if some ISA extensions
-  * are available.
-  */
- enum riscv_isa_ext_key {
-       RISCV_ISA_EXT_KEY_FPU,          /* For 'F' and 'D' */
-       RISCV_ISA_EXT_KEY_SVINVAL,
-       RISCV_ISA_EXT_KEY_MAX,
- };
+ #ifndef __ASSEMBLY__
+ 
+ #include <linux/jump_label.h>
  
 -enum {
 -      CAP_HWCAP = 1,
 -};
 -
  struct riscv_isa_ext_data {
        /* Name of the extension displayed to userspace via /proc/cpuinfo */
        char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];

diff --cc arch/riscv/include/asm/pgtable.h
Simple merge

diff --cc arch/riscv/kernel/vdso.c
Simple merge

diff --cc arch/riscv/kernel/vmlinux.lds.S
Simple merge