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Merge tag 'defconfig-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[linux-2.6-microblaze.git] / arch / x86 / kernel / cpu / resctrl / core.c
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 10fbbc3..4b8813b 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -68,8 +68,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
                        .cache_level            = 3,
                        .cache = {
                                .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 1,
-                               .cbm_idx_offset = 0,
                        },
                        .domains                = domain_init(RDT_RESOURCE_L3),
                        .parse_ctrlval          = parse_cbm,
@@ -79,44 +77,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
                .msr_base               = MSR_IA32_L3_CBM_BASE,
                .msr_update             = cat_wrmsr,
        },
-       [RDT_RESOURCE_L3DATA] =
-       {
-               .r_resctrl = {
-                       .rid                    = RDT_RESOURCE_L3DATA,
-                       .name                   = "L3DATA",
-                       .cache_level            = 3,
-                       .cache = {
-                               .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 2,
-                               .cbm_idx_offset = 0,
-                       },
-                       .domains                = domain_init(RDT_RESOURCE_L3DATA),
-                       .parse_ctrlval          = parse_cbm,
-                       .format_str             = "%d=%0*x",
-                       .fflags                 = RFTYPE_RES_CACHE,
-               },
-               .msr_base               = MSR_IA32_L3_CBM_BASE,
-               .msr_update             = cat_wrmsr,
-       },
-       [RDT_RESOURCE_L3CODE] =
-       {
-               .r_resctrl = {
-                       .rid                    = RDT_RESOURCE_L3CODE,
-                       .name                   = "L3CODE",
-                       .cache_level            = 3,
-                       .cache = {
-                               .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 2,
-                               .cbm_idx_offset = 1,
-                       },
-                       .domains                = domain_init(RDT_RESOURCE_L3CODE),
-                       .parse_ctrlval          = parse_cbm,
-                       .format_str             = "%d=%0*x",
-                       .fflags                 = RFTYPE_RES_CACHE,
-               },
-               .msr_base               = MSR_IA32_L3_CBM_BASE,
-               .msr_update             = cat_wrmsr,
-       },
        [RDT_RESOURCE_L2] =
        {
                .r_resctrl = {
@@ -125,8 +85,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
                        .cache_level            = 2,
                        .cache = {
                                .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 1,
-                               .cbm_idx_offset = 0,
                        },
                        .domains                = domain_init(RDT_RESOURCE_L2),
                        .parse_ctrlval          = parse_cbm,
@@ -136,44 +94,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
                .msr_base               = MSR_IA32_L2_CBM_BASE,
                .msr_update             = cat_wrmsr,
        },
-       [RDT_RESOURCE_L2DATA] =
-       {
-               .r_resctrl = {
-                       .rid                    = RDT_RESOURCE_L2DATA,
-                       .name                   = "L2DATA",
-                       .cache_level            = 2,
-                       .cache = {
-                               .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 2,
-                               .cbm_idx_offset = 0,
-                       },
-                       .domains                = domain_init(RDT_RESOURCE_L2DATA),
-                       .parse_ctrlval          = parse_cbm,
-                       .format_str             = "%d=%0*x",
-                       .fflags                 = RFTYPE_RES_CACHE,
-               },
-               .msr_base               = MSR_IA32_L2_CBM_BASE,
-               .msr_update             = cat_wrmsr,
-       },
-       [RDT_RESOURCE_L2CODE] =
-       {
-               .r_resctrl = {
-                       .rid                    = RDT_RESOURCE_L2CODE,
-                       .name                   = "L2CODE",
-                       .cache_level            = 2,
-                       .cache = {
-                               .min_cbm_bits   = 1,
-                               .cbm_idx_mult   = 2,
-                               .cbm_idx_offset = 1,
-                       },
-                       .domains                = domain_init(RDT_RESOURCE_L2CODE),
-                       .parse_ctrlval          = parse_cbm,
-                       .format_str             = "%d=%0*x",
-                       .fflags                 = RFTYPE_RES_CACHE,
-               },
-               .msr_base               = MSR_IA32_L2_CBM_BASE,
-               .msr_update             = cat_wrmsr,
-       },
        [RDT_RESOURCE_MBA] =
        {
                .r_resctrl = {
@@ -188,11 +108,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
        },
 };
 
-static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
-{
-       return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
-}
-
 /*
  * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
  * as they do not have CPUID enumeration support for Cache allocation.
@@ -349,36 +264,24 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
        r->alloc_enabled = true;
 }
 
-static void rdt_get_cdp_config(int level, int type)
+static void rdt_get_cdp_config(int level)
 {
-       struct rdt_resource *r_l = &rdt_resources_all[level].r_resctrl;
-       struct rdt_hw_resource *hw_res_l = resctrl_to_arch_res(r_l);
-       struct rdt_resource *r = &rdt_resources_all[type].r_resctrl;
-       struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
-
-       hw_res->num_closid = hw_res_l->num_closid / 2;
-       r->cache.cbm_len = r_l->cache.cbm_len;
-       r->default_ctrl = r_l->default_ctrl;
-       r->cache.shareable_bits = r_l->cache.shareable_bits;
-       r->data_width = (r->cache.cbm_len + 3) / 4;
-       r->alloc_capable = true;
        /*
         * By default, CDP is disabled. CDP can be enabled by mount parameter
         * "cdp" during resctrl file system mount time.
         */
-       r->alloc_enabled = false;
+       rdt_resources_all[level].cdp_enabled = false;
+       rdt_resources_all[level].r_resctrl.cdp_capable = true;
 }
 
 static void rdt_get_cdp_l3_config(void)
 {
-       rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);
-       rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);
+       rdt_get_cdp_config(RDT_RESOURCE_L3);
 }
 
 static void rdt_get_cdp_l2_config(void)
 {
-       rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);
-       rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);
+       rdt_get_cdp_config(RDT_RESOURCE_L2);
 }
 
 static void
@@ -427,7 +330,7 @@ cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
        struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 
        for (i = m->low; i < m->high; i++)
-               wrmsrl(hw_res->msr_base + cbm_idx(r, i), hw_dom->ctrl_val[i]);
+               wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
 }
 
 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
@@ -443,6 +346,11 @@ struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
        return NULL;
 }
 
+u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
+{
+       return resctrl_to_arch_res(r)->num_closid;
+}
+
 void rdt_ctrl_update(void *arg)
 {
        struct msr_param *m = arg;
@@ -517,11 +425,13 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
        struct msr_param m;
        u32 *dc, *dm;
 
-       dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), GFP_KERNEL);
+       dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val),
+                          GFP_KERNEL);
        if (!dc)
                return -ENOMEM;
 
-       dm = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->mbps_val), GFP_KERNEL);
+       dm = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->mbps_val),
+                          GFP_KERNEL);
        if (!dm) {
                kfree(dc);
                return -ENOMEM;
@@ -766,13 +676,8 @@ static int resctrl_offline_cpu(unsigned int cpu)
 static __init void rdt_init_padding(void)
 {
        struct rdt_resource *r;
-       int cl;
 
        for_each_alloc_capable_rdt_resource(r) {
-               cl = strlen(r->name);
-               if (cl > max_name_width)
-                       max_name_width = cl;
-
                if (r->data_width > max_data_width)
                        max_data_width = r->data_width;
        }
@@ -966,11 +871,7 @@ static __init void rdt_init_res_defs_intel(void)
                hw_res = resctrl_to_arch_res(r);
 
                if (r->rid == RDT_RESOURCE_L3 ||
-                   r->rid == RDT_RESOURCE_L3DATA ||
-                   r->rid == RDT_RESOURCE_L3CODE ||
-                   r->rid == RDT_RESOURCE_L2 ||
-                   r->rid == RDT_RESOURCE_L2DATA ||
-                   r->rid == RDT_RESOURCE_L2CODE) {
+                   r->rid == RDT_RESOURCE_L2) {
                        r->cache.arch_has_sparse_bitmaps = false;
                        r->cache.arch_has_empty_bitmaps = false;
                        r->cache.arch_has_per_cpu_cfg = false;
@@ -990,11 +891,7 @@ static __init void rdt_init_res_defs_amd(void)
                hw_res = resctrl_to_arch_res(r);
 
                if (r->rid == RDT_RESOURCE_L3 ||
-                   r->rid == RDT_RESOURCE_L3DATA ||
-                   r->rid == RDT_RESOURCE_L3CODE ||
-                   r->rid == RDT_RESOURCE_L2 ||
-                   r->rid == RDT_RESOURCE_L2DATA ||
-                   r->rid == RDT_RESOURCE_L2CODE) {
+                   r->rid == RDT_RESOURCE_L2) {
                        r->cache.arch_has_sparse_bitmaps = true;
                        r->cache.arch_has_empty_bitmaps = true;
                        r->cache.arch_has_per_cpu_cfg = true;
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