tools/testing/nvdimm/test/nfit.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   4  */
   5 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   6 #include <linux/platform_device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/workqueue.h>
   9 #include <linux/libnvdimm.h>
  10 #include <linux/genalloc.h>
  11 #include <linux/vmalloc.h>
  12 #include <linux/device.h>
  13 #include <linux/module.h>
  14 #include <linux/mutex.h>
  15 #include <linux/ndctl.h>
  16 #include <linux/sizes.h>
  17 #include <linux/list.h>
  18 #include <linux/slab.h>
  19 #include <nd-core.h>
  20 #include <intel.h>
  21 #include <nfit.h>
  22 #include <nd.h>
  23 #include "nfit_test.h"
  24 #include "../watermark.h"
  25
  26 #include <asm/mce.h>
  27
  28 /*
  29  * Generate an NFIT table to describe the following topology:
  30  *
  31  * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
  32  *
  33  *                     (a)                       (b)            DIMM   BLK-REGION
  34  *           +----------+--------------+----------+---------+
  35  * +------+  |  blk2.0  |     pm0.0    |  blk2.1  |  pm1.0  |    0      region2
  36  * | imc0 +--+- - - - - region0 - - - -+----------+         +
  37  * +--+---+  |  blk3.0  |     pm0.0    |  blk3.1  |  pm1.0  |    1      region3
  38  *    |      +----------+--------------v----------v         v
  39  * +--+---+                            |                    |
  40  * | cpu0 |                                    region1
  41  * +--+---+                            |                    |
  42  *    |      +-------------------------^----------^         ^
  43  * +--+---+  |                 blk4.0             |  pm1.0  |    2      region4
  44  * | imc1 +--+-------------------------+----------+         +
  45  * +------+  |                 blk5.0             |  pm1.0  |    3      region5
  46  *           +-------------------------+----------+-+-------+
  47  *
  48  * +--+---+
  49  * | cpu1 |
  50  * +--+---+                   (Hotplug DIMM)
  51  *    |      +----------------------------------------------+
  52  * +--+---+  |                 blk6.0/pm7.0                 |    4      region6/7
  53  * | imc0 +--+----------------------------------------------+
  54  * +------+
  55  *
  56  *
  57  * *) In this layout we have four dimms and two memory controllers in one
  58  *    socket.  Each unique interface (BLK or PMEM) to DPA space
  59  *    is identified by a region device with a dynamically assigned id.
  60  *
  61  * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
  62  *    A single PMEM namespace "pm0.0" is created using half of the
  63  *    REGION0 SPA-range.  REGION0 spans dimm0 and dimm1.  PMEM namespace
  64  *    allocate from from the bottom of a region.  The unallocated
  65  *    portion of REGION0 aliases with REGION2 and REGION3.  That
  66  *    unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
  67  *    "blk3.0") starting at the base of each DIMM to offset (a) in those
  68  *    DIMMs.  "pm0.0", "blk2.0" and "blk3.0" are free-form readable
  69  *    names that can be assigned to a namespace.
  70  *
  71  * *) In the last portion of dimm0 and dimm1 we have an interleaved
  72  *    SPA range, REGION1, that spans those two dimms as well as dimm2
  73  *    and dimm3.  Some of REGION1 allocated to a PMEM namespace named
  74  *    "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
  75  *    dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
  76  *    "blk5.0".
  77  *
  78  * *) The portion of dimm2 and dimm3 that do not participate in the
  79  *    REGION1 interleaved SPA range (i.e. the DPA address below offset
  80  *    (b) are also included in the "blk4.0" and "blk5.0" namespaces.
  81  *    Note, that BLK namespaces need not be contiguous in DPA-space, and
  82  *    can consume aliased capacity from multiple interleave sets.
  83  *
  84  * BUS1: Legacy NVDIMM (single contiguous range)
  85  *
  86  *  region2
  87  * +---------------------+
  88  * |---------------------|
  89  * ||       pm2.0       ||
  90  * |---------------------|
  91  * +---------------------+
  92  *
  93  * *) A NFIT-table may describe a simple system-physical-address range
  94  *    with no BLK aliasing.  This type of region may optionally
  95  *    reference an NVDIMM.
  96  */
  97 enum {
  98         NUM_PM  = 3,
  99         NUM_DCR = 5,
 100         NUM_HINTS = 8,
 101         NUM_BDW = NUM_DCR,
 102         NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
 103         NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
 104                 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
 105         DIMM_SIZE = SZ_32M,
 106         LABEL_SIZE = SZ_128K,
 107         SPA_VCD_SIZE = SZ_4M,
 108         SPA0_SIZE = DIMM_SIZE,
 109         SPA1_SIZE = DIMM_SIZE*2,
 110         SPA2_SIZE = DIMM_SIZE,
 111         BDW_SIZE = 64 << 8,
 112         DCR_SIZE = 12,
 113         NUM_NFITS = 2, /* permit testing multiple NFITs per system */
 114 };
 115
 116 struct nfit_test_dcr {
 117         __le64 bdw_addr;
 118         __le32 bdw_status;
 119         __u8 aperature[BDW_SIZE];
 120 };
 121
 122 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
 123         (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
 124          | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
 125
 126 static u32 handle[] = {
 127         [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
 128         [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
 129         [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
 130         [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
 131         [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
 132         [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
 133         [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
 134 };
 135
 136 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)];
 137 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)];
 138 struct nfit_test_sec {
 139         u8 state;
 140         u8 ext_state;
 141         u8 old_state;
 142         u8 passphrase[32];
 143         u8 master_passphrase[32];
 144         u64 overwrite_end_time;
 145 } dimm_sec_info[NUM_DCR];
 146
 147 static const struct nd_intel_smart smart_def = {
 148         .flags = ND_INTEL_SMART_HEALTH_VALID
 149                 | ND_INTEL_SMART_SPARES_VALID
 150                 | ND_INTEL_SMART_ALARM_VALID
 151                 | ND_INTEL_SMART_USED_VALID
 152                 | ND_INTEL_SMART_SHUTDOWN_VALID
 153                 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID
 154                 | ND_INTEL_SMART_MTEMP_VALID
 155                 | ND_INTEL_SMART_CTEMP_VALID,
 156         .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
 157         .media_temperature = 23 * 16,
 158         .ctrl_temperature = 25 * 16,
 159         .pmic_temperature = 40 * 16,
 160         .spares = 75,
 161         .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
 162                 | ND_INTEL_SMART_TEMP_TRIP,
 163         .ait_status = 1,
 164         .life_used = 5,
 165         .shutdown_state = 0,
 166         .shutdown_count = 42,
 167         .vendor_size = 0,
 168 };
 169
 170 struct nfit_test_fw {
 171         enum intel_fw_update_state state;
 172         u32 context;
 173         u64 version;
 174         u32 size_received;
 175         u64 end_time;
 176         bool armed;
 177         bool missed_activate;
 178         unsigned long last_activate;
 179 };
 180
 181 struct nfit_test {
 182         struct acpi_nfit_desc acpi_desc;
 183         struct platform_device pdev;
 184         struct list_head resources;
 185         void *nfit_buf;
 186         dma_addr_t nfit_dma;
 187         size_t nfit_size;
 188         size_t nfit_filled;
 189         int dcr_idx;
 190         int num_dcr;
 191         int num_pm;
 192         void **dimm;
 193         dma_addr_t *dimm_dma;
 194         void **flush;
 195         dma_addr_t *flush_dma;
 196         void **label;
 197         dma_addr_t *label_dma;
 198         void **spa_set;
 199         dma_addr_t *spa_set_dma;
 200         struct nfit_test_dcr **dcr;
 201         dma_addr_t *dcr_dma;
 202         int (*alloc)(struct nfit_test *t);
 203         void (*setup)(struct nfit_test *t);
 204         int setup_hotplug;
 205         union acpi_object **_fit;
 206         dma_addr_t _fit_dma;
 207         struct ars_state {
 208                 struct nd_cmd_ars_status *ars_status;
 209                 unsigned long deadline;
 210                 spinlock_t lock;
 211         } ars_state;
 212         struct device *dimm_dev[ARRAY_SIZE(handle)];
 213         struct nd_intel_smart *smart;
 214         struct nd_intel_smart_threshold *smart_threshold;
 215         struct badrange badrange;
 216         struct work_struct work;
 217         struct nfit_test_fw *fw;
 218 };
 219
 220 static struct workqueue_struct *nfit_wq;
 221
 222 static struct gen_pool *nfit_pool;
 223
 224 static const char zero_key[NVDIMM_PASSPHRASE_LEN];
 225
 226 static struct nfit_test *to_nfit_test(struct device *dev)
 227 {
 228         struct platform_device *pdev = to_platform_device(dev);
 229
 230         return container_of(pdev, struct nfit_test, pdev);
 231 }
 232
 233 static int nd_intel_test_get_fw_info(struct nfit_test *t,
 234                 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
 235                 int idx)
 236 {
 237         struct device *dev = &t->pdev.dev;
 238         struct nfit_test_fw *fw = &t->fw[idx];
 239
 240         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
 241                         __func__, t, nd_cmd, buf_len, idx);
 242
 243         if (buf_len < sizeof(*nd_cmd))
 244                 return -EINVAL;
 245
 246         nd_cmd->status = 0;
 247         nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
 248         nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
 249         nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
 250         nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
 251         nd_cmd->update_cap = 0;
 252         nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
 253         nd_cmd->run_version = 0;
 254         nd_cmd->updated_version = fw->version;
 255
 256         return 0;
 257 }
 258
 259 static int nd_intel_test_start_update(struct nfit_test *t,
 260                 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
 261                 int idx)
 262 {
 263         struct device *dev = &t->pdev.dev;
 264         struct nfit_test_fw *fw = &t->fw[idx];
 265
 266         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 267                         __func__, t, nd_cmd, buf_len, idx);
 268
 269         if (buf_len < sizeof(*nd_cmd))
 270                 return -EINVAL;
 271
 272         if (fw->state != FW_STATE_NEW) {
 273                 /* extended status, FW update in progress */
 274                 nd_cmd->status = 0x10007;
 275                 return 0;
 276         }
 277
 278         fw->state = FW_STATE_IN_PROGRESS;
 279         fw->context++;
 280         fw->size_received = 0;
 281         nd_cmd->status = 0;
 282         nd_cmd->context = fw->context;
 283
 284         dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
 285
 286         return 0;
 287 }
 288
 289 static int nd_intel_test_send_data(struct nfit_test *t,
 290                 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
 291                 int idx)
 292 {
 293         struct device *dev = &t->pdev.dev;
 294         struct nfit_test_fw *fw = &t->fw[idx];
 295         u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
 296
 297         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 298                         __func__, t, nd_cmd, buf_len, idx);
 299
 300         if (buf_len < sizeof(*nd_cmd))
 301                 return -EINVAL;
 302
 303
 304         dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
 305         dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
 306         dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
 307                         nd_cmd->data[nd_cmd->length-1]);
 308
 309         if (fw->state != FW_STATE_IN_PROGRESS) {
 310                 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
 311                 *status = 0x5;
 312                 return 0;
 313         }
 314
 315         if (nd_cmd->context != fw->context) {
 316                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 317                                 __func__, nd_cmd->context, fw->context);
 318                 *status = 0x10007;
 319                 return 0;
 320         }
 321
 322         /*
 323          * check offset + len > size of fw storage
 324          * check length is > max send length
 325          */
 326         if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
 327                         nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
 328                 *status = 0x3;
 329                 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
 330                 return 0;
 331         }
 332
 333         fw->size_received += nd_cmd->length;
 334         dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
 335                         __func__, nd_cmd->length, fw->size_received);
 336         *status = 0;
 337         return 0;
 338 }
 339
 340 static int nd_intel_test_finish_fw(struct nfit_test *t,
 341                 struct nd_intel_fw_finish_update *nd_cmd,
 342                 unsigned int buf_len, int idx)
 343 {
 344         struct device *dev = &t->pdev.dev;
 345         struct nfit_test_fw *fw = &t->fw[idx];
 346
 347         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 348                         __func__, t, nd_cmd, buf_len, idx);
 349
 350         if (fw->state == FW_STATE_UPDATED) {
 351                 /* update already done, need activation */
 352                 nd_cmd->status = 0x20007;
 353                 return 0;
 354         }
 355
 356         dev_dbg(dev, "%s: context: %#x  ctrl_flags: %#x\n",
 357                         __func__, nd_cmd->context, nd_cmd->ctrl_flags);
 358
 359         switch (nd_cmd->ctrl_flags) {
 360         case 0: /* finish */
 361                 if (nd_cmd->context != fw->context) {
 362                         dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 363                                         __func__, nd_cmd->context,
 364                                         fw->context);
 365                         nd_cmd->status = 0x10007;
 366                         return 0;
 367                 }
 368                 nd_cmd->status = 0;
 369                 fw->state = FW_STATE_VERIFY;
 370                 /* set 1 second of time for firmware "update" */
 371                 fw->end_time = jiffies + HZ;
 372                 break;
 373
 374         case 1: /* abort */
 375                 fw->size_received = 0;
 376                 /* successfully aborted status */
 377                 nd_cmd->status = 0x40007;
 378                 fw->state = FW_STATE_NEW;
 379                 dev_dbg(dev, "%s: abort successful\n", __func__);
 380                 break;
 381
 382         default: /* bad control flag */
 383                 dev_warn(dev, "%s: unknown control flag: %#x\n",
 384                                 __func__, nd_cmd->ctrl_flags);
 385                 return -EINVAL;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int nd_intel_test_finish_query(struct nfit_test *t,
 392                 struct nd_intel_fw_finish_query *nd_cmd,
 393                 unsigned int buf_len, int idx)
 394 {
 395         struct device *dev = &t->pdev.dev;
 396         struct nfit_test_fw *fw = &t->fw[idx];
 397
 398         dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
 399                         __func__, t, nd_cmd, buf_len, idx);
 400
 401         if (buf_len < sizeof(*nd_cmd))
 402                 return -EINVAL;
 403
 404         if (nd_cmd->context != fw->context) {
 405                 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
 406                                 __func__, nd_cmd->context, fw->context);
 407                 nd_cmd->status = 0x10007;
 408                 return 0;
 409         }
 410
 411         dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
 412
 413         switch (fw->state) {
 414         case FW_STATE_NEW:
 415                 nd_cmd->updated_fw_rev = 0;
 416                 nd_cmd->status = 0;
 417                 dev_dbg(dev, "%s: new state\n", __func__);
 418                 break;
 419
 420         case FW_STATE_IN_PROGRESS:
 421                 /* sequencing error */
 422                 nd_cmd->status = 0x40007;
 423                 nd_cmd->updated_fw_rev = 0;
 424                 dev_dbg(dev, "%s: sequence error\n", __func__);
 425                 break;
 426
 427         case FW_STATE_VERIFY:
 428                 if (time_is_after_jiffies64(fw->end_time)) {
 429                         nd_cmd->updated_fw_rev = 0;
 430                         nd_cmd->status = 0x20007;
 431                         dev_dbg(dev, "%s: still verifying\n", __func__);
 432                         break;
 433                 }
 434                 dev_dbg(dev, "%s: transition out verify\n", __func__);
 435                 fw->state = FW_STATE_UPDATED;
 436                 fw->missed_activate = false;
 437                 /* fall through */
 438         case FW_STATE_UPDATED:
 439                 nd_cmd->status = 0;
 440                 /* bogus test version */
 441                 fw->version = nd_cmd->updated_fw_rev =
 442                         INTEL_FW_FAKE_VERSION;
 443                 dev_dbg(dev, "%s: updated\n", __func__);
 444                 break;
 445
 446         default: /* we should never get here */
 447                 return -EINVAL;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
 454                 unsigned int buf_len)
 455 {
 456         if (buf_len < sizeof(*nd_cmd))
 457                 return -EINVAL;
 458
 459         nd_cmd->status = 0;
 460         nd_cmd->config_size = LABEL_SIZE;
 461         nd_cmd->max_xfer = SZ_4K;
 462
 463         return 0;
 464 }
 465
 466 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
 467                 *nd_cmd, unsigned int buf_len, void *label)
 468 {
 469         unsigned int len, offset = nd_cmd->in_offset;
 470         int rc;
 471
 472         if (buf_len < sizeof(*nd_cmd))
 473                 return -EINVAL;
 474         if (offset >= LABEL_SIZE)
 475                 return -EINVAL;
 476         if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
 477                 return -EINVAL;
 478
 479         nd_cmd->status = 0;
 480         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 481         memcpy(nd_cmd->out_buf, label + offset, len);
 482         rc = buf_len - sizeof(*nd_cmd) - len;
 483
 484         return rc;
 485 }
 486
 487 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
 488                 unsigned int buf_len, void *label)
 489 {
 490         unsigned int len, offset = nd_cmd->in_offset;
 491         u32 *status;
 492         int rc;
 493
 494         if (buf_len < sizeof(*nd_cmd))
 495                 return -EINVAL;
 496         if (offset >= LABEL_SIZE)
 497                 return -EINVAL;
 498         if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
 499                 return -EINVAL;
 500
 501         status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
 502         *status = 0;
 503         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 504         memcpy(label + offset, nd_cmd->in_buf, len);
 505         rc = buf_len - sizeof(*nd_cmd) - (len + 4);
 506
 507         return rc;
 508 }
 509
 510 #define NFIT_TEST_CLEAR_ERR_UNIT 256
 511
 512 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
 513                 unsigned int buf_len)
 514 {
 515         int ars_recs;
 516
 517         if (buf_len < sizeof(*nd_cmd))
 518                 return -EINVAL;
 519
 520         /* for testing, only store up to n records that fit within 4k */
 521         ars_recs = SZ_4K / sizeof(struct nd_ars_record);
 522
 523         nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
 524                 + ars_recs * sizeof(struct nd_ars_record);
 525         nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
 526         nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
 527
 528         return 0;
 529 }
 530
 531 static void post_ars_status(struct ars_state *ars_state,
 532                 struct badrange *badrange, u64 addr, u64 len)
 533 {
 534         struct nd_cmd_ars_status *ars_status;
 535         struct nd_ars_record *ars_record;
 536         struct badrange_entry *be;
 537         u64 end = addr + len - 1;
 538         int i = 0;
 539
 540         ars_state->deadline = jiffies + 1*HZ;
 541         ars_status = ars_state->ars_status;
 542         ars_status->status = 0;
 543         ars_status->address = addr;
 544         ars_status->length = len;
 545         ars_status->type = ND_ARS_PERSISTENT;
 546
 547         spin_lock(&badrange->lock);
 548         list_for_each_entry(be, &badrange->list, list) {
 549                 u64 be_end = be->start + be->length - 1;
 550                 u64 rstart, rend;
 551
 552                 /* skip entries outside the range */
 553                 if (be_end < addr || be->start > end)
 554                         continue;
 555
 556                 rstart = (be->start < addr) ? addr : be->start;
 557                 rend = (be_end < end) ? be_end : end;
 558                 ars_record = &ars_status->records[i];
 559                 ars_record->handle = 0;
 560                 ars_record->err_address = rstart;
 561                 ars_record->length = rend - rstart + 1;
 562                 i++;
 563         }
 564         spin_unlock(&badrange->lock);
 565         ars_status->num_records = i;
 566         ars_status->out_length = sizeof(struct nd_cmd_ars_status)
 567                 + i * sizeof(struct nd_ars_record);
 568 }
 569
 570 static int nfit_test_cmd_ars_start(struct nfit_test *t,
 571                 struct ars_state *ars_state,
 572                 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
 573                 int *cmd_rc)
 574 {
 575         if (buf_len < sizeof(*ars_start))
 576                 return -EINVAL;
 577
 578         spin_lock(&ars_state->lock);
 579         if (time_before(jiffies, ars_state->deadline)) {
 580                 ars_start->status = NFIT_ARS_START_BUSY;
 581                 *cmd_rc = -EBUSY;
 582         } else {
 583                 ars_start->status = 0;
 584                 ars_start->scrub_time = 1;
 585                 post_ars_status(ars_state, &t->badrange, ars_start->address,
 586                                 ars_start->length);
 587                 *cmd_rc = 0;
 588         }
 589         spin_unlock(&ars_state->lock);
 590
 591         return 0;
 592 }
 593
 594 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
 595                 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
 596                 int *cmd_rc)
 597 {
 598         if (buf_len < ars_state->ars_status->out_length)
 599                 return -EINVAL;
 600
 601         spin_lock(&ars_state->lock);
 602         if (time_before(jiffies, ars_state->deadline)) {
 603                 memset(ars_status, 0, buf_len);
 604                 ars_status->status = NFIT_ARS_STATUS_BUSY;
 605                 ars_status->out_length = sizeof(*ars_status);
 606                 *cmd_rc = -EBUSY;
 607         } else {
 608                 memcpy(ars_status, ars_state->ars_status,
 609                                 ars_state->ars_status->out_length);
 610                 *cmd_rc = 0;
 611         }
 612         spin_unlock(&ars_state->lock);
 613         return 0;
 614 }
 615
 616 static int nfit_test_cmd_clear_error(struct nfit_test *t,
 617                 struct nd_cmd_clear_error *clear_err,
 618                 unsigned int buf_len, int *cmd_rc)
 619 {
 620         const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
 621         if (buf_len < sizeof(*clear_err))
 622                 return -EINVAL;
 623
 624         if ((clear_err->address & mask) || (clear_err->length & mask))
 625                 return -EINVAL;
 626
 627         badrange_forget(&t->badrange, clear_err->address, clear_err->length);
 628         clear_err->status = 0;
 629         clear_err->cleared = clear_err->length;
 630         *cmd_rc = 0;
 631         return 0;
 632 }
 633
 634 struct region_search_spa {
 635         u64 addr;
 636         struct nd_region *region;
 637 };
 638
 639 static int is_region_device(struct device *dev)
 640 {
 641         return !strncmp(dev->kobj.name, "region", 6);
 642 }
 643
 644 static int nfit_test_search_region_spa(struct device *dev, void *data)
 645 {
 646         struct region_search_spa *ctx = data;
 647         struct nd_region *nd_region;
 648         resource_size_t ndr_end;
 649
 650         if (!is_region_device(dev))
 651                 return 0;
 652
 653         nd_region = to_nd_region(dev);
 654         ndr_end = nd_region->ndr_start + nd_region->ndr_size;
 655
 656         if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
 657                 ctx->region = nd_region;
 658                 return 1;
 659         }
 660
 661         return 0;
 662 }
 663
 664 static int nfit_test_search_spa(struct nvdimm_bus *bus,
 665                 struct nd_cmd_translate_spa *spa)
 666 {
 667         int ret;
 668         struct nd_region *nd_region = NULL;
 669         struct nvdimm *nvdimm = NULL;
 670         struct nd_mapping *nd_mapping = NULL;
 671         struct region_search_spa ctx = {
 672                 .addr = spa->spa,
 673                 .region = NULL,
 674         };
 675         u64 dpa;
 676
 677         ret = device_for_each_child(&bus->dev, &ctx,
 678                                 nfit_test_search_region_spa);
 679
 680         if (!ret)
 681                 return -ENODEV;
 682
 683         nd_region = ctx.region;
 684
 685         dpa = ctx.addr - nd_region->ndr_start;
 686
 687         /*
 688          * last dimm is selected for test
 689          */
 690         nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
 691         nvdimm = nd_mapping->nvdimm;
 692
 693         spa->devices[0].nfit_device_handle = handle[nvdimm->id];
 694         spa->num_nvdimms = 1;
 695         spa->devices[0].dpa = dpa;
 696
 697         return 0;
 698 }
 699
 700 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
 701                 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
 702 {
 703         if (buf_len < spa->translate_length)
 704                 return -EINVAL;
 705
 706         if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
 707                 spa->status = 2;
 708
 709         return 0;
 710 }
 711
 712 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
 713                 struct nd_intel_smart *smart_data)
 714 {
 715         if (buf_len < sizeof(*smart))
 716                 return -EINVAL;
 717         memcpy(smart, smart_data, sizeof(*smart));
 718         return 0;
 719 }
 720
 721 static int nfit_test_cmd_smart_threshold(
 722                 struct nd_intel_smart_threshold *out,
 723                 unsigned int buf_len,
 724                 struct nd_intel_smart_threshold *smart_t)
 725 {
 726         if (buf_len < sizeof(*smart_t))
 727                 return -EINVAL;
 728         memcpy(out, smart_t, sizeof(*smart_t));
 729         return 0;
 730 }
 731
 732 static void smart_notify(struct device *bus_dev,
 733                 struct device *dimm_dev, struct nd_intel_smart *smart,
 734                 struct nd_intel_smart_threshold *thresh)
 735 {
 736         dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
 737                         __func__, thresh->alarm_control, thresh->spares,
 738                         smart->spares, thresh->media_temperature,
 739                         smart->media_temperature, thresh->ctrl_temperature,
 740                         smart->ctrl_temperature);
 741         if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
 742                                 && smart->spares
 743                                 <= thresh->spares)
 744                         || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
 745                                 && smart->media_temperature
 746                                 >= thresh->media_temperature)
 747                         || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
 748                                 && smart->ctrl_temperature
 749                                 >= thresh->ctrl_temperature)
 750                         || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
 751                         || (smart->shutdown_state != 0)) {
 752                 device_lock(bus_dev);
 753                 __acpi_nvdimm_notify(dimm_dev, 0x81);
 754                 device_unlock(bus_dev);
 755         }
 756 }
 757
 758 static int nfit_test_cmd_smart_set_threshold(
 759                 struct nd_intel_smart_set_threshold *in,
 760                 unsigned int buf_len,
 761                 struct nd_intel_smart_threshold *thresh,
 762                 struct nd_intel_smart *smart,
 763                 struct device *bus_dev, struct device *dimm_dev)
 764 {
 765         unsigned int size;
 766
 767         size = sizeof(*in) - 4;
 768         if (buf_len < size)
 769                 return -EINVAL;
 770         memcpy(thresh->data, in, size);
 771         in->status = 0;
 772         smart_notify(bus_dev, dimm_dev, smart, thresh);
 773
 774         return 0;
 775 }
 776
 777 static int nfit_test_cmd_smart_inject(
 778                 struct nd_intel_smart_inject *inj,
 779                 unsigned int buf_len,
 780                 struct nd_intel_smart_threshold *thresh,
 781                 struct nd_intel_smart *smart,
 782                 struct device *bus_dev, struct device *dimm_dev)
 783 {
 784         if (buf_len != sizeof(*inj))
 785                 return -EINVAL;
 786
 787         if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) {
 788                 if (inj->mtemp_enable)
 789                         smart->media_temperature = inj->media_temperature;
 790                 else
 791                         smart->media_temperature = smart_def.media_temperature;
 792         }
 793         if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) {
 794                 if (inj->spare_enable)
 795                         smart->spares = inj->spares;
 796                 else
 797                         smart->spares = smart_def.spares;
 798         }
 799         if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) {
 800                 if (inj->fatal_enable)
 801                         smart->health = ND_INTEL_SMART_FATAL_HEALTH;
 802                 else
 803                         smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH;
 804         }
 805         if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) {
 806                 if (inj->unsafe_shutdown_enable) {
 807                         smart->shutdown_state = 1;
 808                         smart->shutdown_count++;
 809                 } else
 810                         smart->shutdown_state = 0;
 811         }
 812         inj->status = 0;
 813         smart_notify(bus_dev, dimm_dev, smart, thresh);
 814
 815         return 0;
 816 }
 817
 818 static void uc_error_notify(struct work_struct *work)
 819 {
 820         struct nfit_test *t = container_of(work, typeof(*t), work);
 821
 822         __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
 823 }
 824
 825 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
 826                 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
 827 {
 828         int rc;
 829
 830         if (buf_len != sizeof(*err_inj)) {
 831                 rc = -EINVAL;
 832                 goto err;
 833         }
 834
 835         if (err_inj->err_inj_spa_range_length <= 0) {
 836                 rc = -EINVAL;
 837                 goto err;
 838         }
 839
 840         rc =  badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
 841                         err_inj->err_inj_spa_range_length);
 842         if (rc < 0)
 843                 goto err;
 844
 845         if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
 846                 queue_work(nfit_wq, &t->work);
 847
 848         err_inj->status = 0;
 849         return 0;
 850
 851 err:
 852         err_inj->status = NFIT_ARS_INJECT_INVALID;
 853         return rc;
 854 }
 855
 856 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
 857                 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
 858 {
 859         int rc;
 860
 861         if (buf_len != sizeof(*err_clr)) {
 862                 rc = -EINVAL;
 863                 goto err;
 864         }
 865
 866         if (err_clr->err_inj_clr_spa_range_length <= 0) {
 867                 rc = -EINVAL;
 868                 goto err;
 869         }
 870
 871         badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
 872                         err_clr->err_inj_clr_spa_range_length);
 873
 874         err_clr->status = 0;
 875         return 0;
 876
 877 err:
 878         err_clr->status = NFIT_ARS_INJECT_INVALID;
 879         return rc;
 880 }
 881
 882 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
 883                 struct nd_cmd_ars_err_inj_stat *err_stat,
 884                 unsigned int buf_len)
 885 {
 886         struct badrange_entry *be;
 887         int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
 888         int i = 0;
 889
 890         err_stat->status = 0;
 891         spin_lock(&t->badrange.lock);
 892         list_for_each_entry(be, &t->badrange.list, list) {
 893                 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
 894                 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
 895                 i++;
 896                 if (i > max)
 897                         break;
 898         }
 899         spin_unlock(&t->badrange.lock);
 900         err_stat->inj_err_rec_count = i;
 901
 902         return 0;
 903 }
 904
 905 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
 906                 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
 907 {
 908         struct device *dev = &t->pdev.dev;
 909
 910         if (buf_len < sizeof(*nd_cmd))
 911                 return -EINVAL;
 912
 913         switch (nd_cmd->enable) {
 914         case 0:
 915                 nd_cmd->status = 0;
 916                 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
 917                                 __func__);
 918                 break;
 919         case 1:
 920                 nd_cmd->status = 0;
 921                 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
 922                                 __func__);
 923                 break;
 924         default:
 925                 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
 926                 nd_cmd->status = 0x3;
 927                 break;
 928         }
 929
 930
 931         return 0;
 932 }
 933
 934 static int override_return_code(int dimm, unsigned int func, int rc)
 935 {
 936         if ((1 << func) & dimm_fail_cmd_flags[dimm]) {
 937                 if (dimm_fail_cmd_code[dimm])
 938                         return dimm_fail_cmd_code[dimm];
 939                 return -EIO;
 940         }
 941         return rc;
 942 }
 943
 944 static int nd_intel_test_cmd_security_status(struct nfit_test *t,
 945                 struct nd_intel_get_security_state *nd_cmd,
 946                 unsigned int buf_len, int dimm)
 947 {
 948         struct device *dev = &t->pdev.dev;
 949         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 950
 951         nd_cmd->status = 0;
 952         nd_cmd->state = sec->state;
 953         nd_cmd->extended_state = sec->ext_state;
 954         dev_dbg(dev, "security state (%#x) returned\n", nd_cmd->state);
 955
 956         return 0;
 957 }
 958
 959 static int nd_intel_test_cmd_unlock_unit(struct nfit_test *t,
 960                 struct nd_intel_unlock_unit *nd_cmd,
 961                 unsigned int buf_len, int dimm)
 962 {
 963         struct device *dev = &t->pdev.dev;
 964         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 965
 966         if (!(sec->state & ND_INTEL_SEC_STATE_LOCKED) ||
 967                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
 968                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
 969                 dev_dbg(dev, "unlock unit: invalid state: %#x\n",
 970                                 sec->state);
 971         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
 972                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
 973                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
 974                 dev_dbg(dev, "unlock unit: invalid passphrase\n");
 975         } else {
 976                 nd_cmd->status = 0;
 977                 sec->state = ND_INTEL_SEC_STATE_ENABLED;
 978                 dev_dbg(dev, "Unit unlocked\n");
 979         }
 980
 981         dev_dbg(dev, "unlocking status returned: %#x\n", nd_cmd->status);
 982         return 0;
 983 }
 984
 985 static int nd_intel_test_cmd_set_pass(struct nfit_test *t,
 986                 struct nd_intel_set_passphrase *nd_cmd,
 987                 unsigned int buf_len, int dimm)
 988 {
 989         struct device *dev = &t->pdev.dev;
 990         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
 991
 992         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
 993                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
 994                 dev_dbg(dev, "set passphrase: wrong security state\n");
 995         } else if (memcmp(nd_cmd->old_pass, sec->passphrase,
 996                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
 997                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
 998                 dev_dbg(dev, "set passphrase: wrong passphrase\n");
 999         } else {
1000                 memcpy(sec->passphrase, nd_cmd->new_pass,
1001                                 ND_INTEL_PASSPHRASE_SIZE);
1002                 sec->state |= ND_INTEL_SEC_STATE_ENABLED;
1003                 nd_cmd->status = 0;
1004                 dev_dbg(dev, "passphrase updated\n");
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int nd_intel_test_cmd_freeze_lock(struct nfit_test *t,
1011                 struct nd_intel_freeze_lock *nd_cmd,
1012                 unsigned int buf_len, int dimm)
1013 {
1014         struct device *dev = &t->pdev.dev;
1015         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1016
1017         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)) {
1018                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1019                 dev_dbg(dev, "freeze lock: wrong security state\n");
1020         } else {
1021                 sec->state |= ND_INTEL_SEC_STATE_FROZEN;
1022                 nd_cmd->status = 0;
1023                 dev_dbg(dev, "security frozen\n");
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int nd_intel_test_cmd_disable_pass(struct nfit_test *t,
1030                 struct nd_intel_disable_passphrase *nd_cmd,
1031                 unsigned int buf_len, int dimm)
1032 {
1033         struct device *dev = &t->pdev.dev;
1034         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1035
1036         if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) ||
1037                         (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
1038                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1039                 dev_dbg(dev, "disable passphrase: wrong security state\n");
1040         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1041                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1042                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1043                 dev_dbg(dev, "disable passphrase: wrong passphrase\n");
1044         } else {
1045                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1046                 sec->state = 0;
1047                 dev_dbg(dev, "disable passphrase: done\n");
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int nd_intel_test_cmd_secure_erase(struct nfit_test *t,
1054                 struct nd_intel_secure_erase *nd_cmd,
1055                 unsigned int buf_len, int dimm)
1056 {
1057         struct device *dev = &t->pdev.dev;
1058         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1059
1060         if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
1061                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1062                 dev_dbg(dev, "secure erase: wrong security state\n");
1063         } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1064                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1065                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1066                 dev_dbg(dev, "secure erase: wrong passphrase\n");
1067         } else {
1068                 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)
1069                                 && (memcmp(nd_cmd->passphrase, zero_key,
1070                                         ND_INTEL_PASSPHRASE_SIZE) != 0)) {
1071                         dev_dbg(dev, "invalid zero key\n");
1072                         return 0;
1073                 }
1074                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1075                 memset(sec->master_passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1076                 sec->state = 0;
1077                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1078                 dev_dbg(dev, "secure erase: done\n");
1079         }
1080
1081         return 0;
1082 }
1083
1084 static int nd_intel_test_cmd_overwrite(struct nfit_test *t,
1085                 struct nd_intel_overwrite *nd_cmd,
1086                 unsigned int buf_len, int dimm)
1087 {
1088         struct device *dev = &t->pdev.dev;
1089         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1090
1091         if ((sec->state & ND_INTEL_SEC_STATE_ENABLED) &&
1092                         memcmp(nd_cmd->passphrase, sec->passphrase,
1093                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1094                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1095                 dev_dbg(dev, "overwrite: wrong passphrase\n");
1096                 return 0;
1097         }
1098
1099         sec->old_state = sec->state;
1100         sec->state = ND_INTEL_SEC_STATE_OVERWRITE;
1101         dev_dbg(dev, "overwrite progressing.\n");
1102         sec->overwrite_end_time = get_jiffies_64() + 5 * HZ;
1103
1104         return 0;
1105 }
1106
1107 static int nd_intel_test_cmd_query_overwrite(struct nfit_test *t,
1108                 struct nd_intel_query_overwrite *nd_cmd,
1109                 unsigned int buf_len, int dimm)
1110 {
1111         struct device *dev = &t->pdev.dev;
1112         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1113
1114         if (!(sec->state & ND_INTEL_SEC_STATE_OVERWRITE)) {
1115                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR;
1116                 return 0;
1117         }
1118
1119         if (time_is_before_jiffies64(sec->overwrite_end_time)) {
1120                 sec->overwrite_end_time = 0;
1121                 sec->state = sec->old_state;
1122                 sec->old_state = 0;
1123                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1124                 dev_dbg(dev, "overwrite is complete\n");
1125         } else
1126                 nd_cmd->status = ND_INTEL_STATUS_OQUERY_INPROGRESS;
1127         return 0;
1128 }
1129
1130 static int nd_intel_test_cmd_master_set_pass(struct nfit_test *t,
1131                 struct nd_intel_set_master_passphrase *nd_cmd,
1132                 unsigned int buf_len, int dimm)
1133 {
1134         struct device *dev = &t->pdev.dev;
1135         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1136
1137         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1138                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1139                 dev_dbg(dev, "master set passphrase: in wrong state\n");
1140         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1141                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1142                 dev_dbg(dev, "master set passphrase: in wrong security state\n");
1143         } else if (memcmp(nd_cmd->old_pass, sec->master_passphrase,
1144                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1145                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1146                 dev_dbg(dev, "master set passphrase: wrong passphrase\n");
1147         } else {
1148                 memcpy(sec->master_passphrase, nd_cmd->new_pass,
1149                                 ND_INTEL_PASSPHRASE_SIZE);
1150                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1151                 dev_dbg(dev, "master passphrase: updated\n");
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t,
1158                 struct nd_intel_master_secure_erase *nd_cmd,
1159                 unsigned int buf_len, int dimm)
1160 {
1161         struct device *dev = &t->pdev.dev;
1162         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1163
1164         if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1165                 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1166                 dev_dbg(dev, "master secure erase: in wrong state\n");
1167         } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1168                 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1169                 dev_dbg(dev, "master secure erase: in wrong security state\n");
1170         } else if (memcmp(nd_cmd->passphrase, sec->master_passphrase,
1171                                 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1172                 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1173                 dev_dbg(dev, "master secure erase: wrong passphrase\n");
1174         } else {
1175                 /* we do not erase master state passphrase ever */
1176                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1177                 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1178                 sec->state = 0;
1179                 dev_dbg(dev, "master secure erase: done\n");
1180         }
1181
1182         return 0;
1183 }
1184
1185 static unsigned long last_activate;
1186
1187 static int nvdimm_bus_intel_fw_activate_businfo(struct nfit_test *t,
1188                 struct nd_intel_bus_fw_activate_businfo *nd_cmd,
1189                 unsigned int buf_len)
1190 {
1191         int i, armed = 0;
1192         int state;
1193         u64 tmo;
1194
1195         for (i = 0; i < NUM_DCR; i++) {
1196                 struct nfit_test_fw *fw = &t->fw[i];
1197
1198                 if (fw->armed)
1199                         armed++;
1200         }
1201
1202         /*
1203          * Emulate 3 second activation max, and 1 second incremental
1204          * quiesce time per dimm requiring multiple activates to get all
1205          * DIMMs updated.
1206          */
1207         if (armed)
1208                 state = ND_INTEL_FWA_ARMED;
1209         else if (!last_activate || time_after(jiffies, last_activate + 3 * HZ))
1210                 state = ND_INTEL_FWA_IDLE;
1211         else
1212                 state = ND_INTEL_FWA_BUSY;
1213
1214         tmo = armed * USEC_PER_SEC;
1215         *nd_cmd = (struct nd_intel_bus_fw_activate_businfo) {
1216                 .capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
1217                         | ND_INTEL_BUS_FWA_CAP_OSQUIESCE
1218                         | ND_INTEL_BUS_FWA_CAP_RESET,
1219                 .state = state,
1220                 .activate_tmo = tmo,
1221                 .cpu_quiesce_tmo = tmo,
1222                 .io_quiesce_tmo = tmo,
1223                 .max_quiesce_tmo = 3 * USEC_PER_SEC,
1224         };
1225
1226         return 0;
1227 }
1228
1229 static int nvdimm_bus_intel_fw_activate(struct nfit_test *t,
1230                 struct nd_intel_bus_fw_activate *nd_cmd,
1231                 unsigned int buf_len)
1232 {
1233         struct nd_intel_bus_fw_activate_businfo info;
1234         u32 status = 0;
1235         int i;
1236
1237         nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
1238         if (info.state == ND_INTEL_FWA_BUSY)
1239                 status = ND_INTEL_BUS_FWA_STATUS_BUSY;
1240         else if (info.activate_tmo > info.max_quiesce_tmo)
1241                 status = ND_INTEL_BUS_FWA_STATUS_TMO;
1242         else if (info.state == ND_INTEL_FWA_IDLE)
1243                 status = ND_INTEL_BUS_FWA_STATUS_NOARM;
1244
1245         dev_dbg(&t->pdev.dev, "status: %d\n", status);
1246         nd_cmd->status = status;
1247         if (status && status != ND_INTEL_BUS_FWA_STATUS_TMO)
1248                 return 0;
1249
1250         last_activate = jiffies;
1251         for (i = 0; i < NUM_DCR; i++) {
1252                 struct nfit_test_fw *fw = &t->fw[i];
1253
1254                 if (!fw->armed)
1255                         continue;
1256                 if (fw->state != FW_STATE_UPDATED)
1257                         fw->missed_activate = true;
1258                 else
1259                         fw->state = FW_STATE_NEW;
1260                 fw->armed = false;
1261                 fw->last_activate = last_activate;
1262         }
1263
1264         return 0;
1265 }
1266
1267 static int nd_intel_test_cmd_fw_activate_dimminfo(struct nfit_test *t,
1268                 struct nd_intel_fw_activate_dimminfo *nd_cmd,
1269                 unsigned int buf_len, int dimm)
1270 {
1271         struct nd_intel_bus_fw_activate_businfo info;
1272         struct nfit_test_fw *fw = &t->fw[dimm];
1273         u32 result, state;
1274
1275         nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
1276
1277         if (info.state == ND_INTEL_FWA_BUSY)
1278                 state = ND_INTEL_FWA_BUSY;
1279         else if (info.state == ND_INTEL_FWA_IDLE)
1280                 state = ND_INTEL_FWA_IDLE;
1281         else if (fw->armed)
1282                 state = ND_INTEL_FWA_ARMED;
1283         else
1284                 state = ND_INTEL_FWA_IDLE;
1285
1286         result = ND_INTEL_DIMM_FWA_NONE;
1287         if (last_activate && fw->last_activate == last_activate &&
1288                         state == ND_INTEL_FWA_IDLE) {
1289                 if (fw->missed_activate)
1290                         result = ND_INTEL_DIMM_FWA_NOTSTAGED;
1291                 else
1292                         result = ND_INTEL_DIMM_FWA_SUCCESS;
1293         }
1294
1295         *nd_cmd = (struct nd_intel_fw_activate_dimminfo) {
1296                 .result = result,
1297                 .state = state,
1298         };
1299
1300         return 0;
1301 }
1302
1303 static int nd_intel_test_cmd_fw_activate_arm(struct nfit_test *t,
1304                 struct nd_intel_fw_activate_arm *nd_cmd,
1305                 unsigned int buf_len, int dimm)
1306 {
1307         struct nfit_test_fw *fw = &t->fw[dimm];
1308
1309         fw->armed = nd_cmd->activate_arm == ND_INTEL_DIMM_FWA_ARM;
1310         nd_cmd->status = 0;
1311         return 0;
1312 }
1313
1314 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
1315 {
1316         int i;
1317
1318         /* lookup per-dimm data */
1319         for (i = 0; i < ARRAY_SIZE(handle); i++)
1320                 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
1321                         break;
1322         if (i >= ARRAY_SIZE(handle))
1323                 return -ENXIO;
1324         return i;
1325 }
1326
1327 static void nfit_ctl_dbg(struct acpi_nfit_desc *acpi_desc,
1328                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1329                 unsigned int len)
1330 {
1331         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1332         unsigned int func = cmd;
1333         unsigned int family = 0;
1334
1335         if (cmd == ND_CMD_CALL) {
1336                 struct nd_cmd_pkg *pkg = buf;
1337
1338                 len = pkg->nd_size_in;
1339                 family = pkg->nd_family;
1340                 buf = pkg->nd_payload;
1341                 func = pkg->nd_command;
1342         }
1343         dev_dbg(&t->pdev.dev, "%s family: %d cmd: %d: func: %d input length: %d\n",
1344                         nvdimm ? nvdimm_name(nvdimm) : "bus", family, cmd, func,
1345                         len);
1346         print_hex_dump_debug("nvdimm in  ", DUMP_PREFIX_OFFSET, 16, 4,
1347                         buf, min(len, 256u), true);
1348 }
1349
1350 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
1351                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1352                 unsigned int buf_len, int *cmd_rc)
1353 {
1354         struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1355         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1356         unsigned int func = cmd;
1357         int i, rc = 0, __cmd_rc;
1358
1359         if (!cmd_rc)
1360                 cmd_rc = &__cmd_rc;
1361         *cmd_rc = 0;
1362
1363         nfit_ctl_dbg(acpi_desc, nvdimm, cmd, buf, buf_len);
1364
1365         if (nvdimm) {
1366                 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
1367                 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
1368
1369                 if (!nfit_mem)
1370                         return -ENOTTY;
1371
1372                 if (cmd == ND_CMD_CALL) {
1373                         struct nd_cmd_pkg *call_pkg = buf;
1374
1375                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1376                         buf = (void *) call_pkg->nd_payload;
1377                         func = call_pkg->nd_command;
1378                         if (call_pkg->nd_family != nfit_mem->family)
1379                                 return -ENOTTY;
1380
1381                         i = get_dimm(nfit_mem, func);
1382                         if (i < 0)
1383                                 return i;
1384                         if (i >= NUM_DCR) {
1385                                 dev_WARN_ONCE(&t->pdev.dev, 1,
1386                                                 "ND_CMD_CALL only valid for nfit_test0\n");
1387                                 return -EINVAL;
1388                         }
1389
1390                         switch (func) {
1391                         case NVDIMM_INTEL_GET_SECURITY_STATE:
1392                                 rc = nd_intel_test_cmd_security_status(t,
1393                                                 buf, buf_len, i);
1394                                 break;
1395                         case NVDIMM_INTEL_UNLOCK_UNIT:
1396                                 rc = nd_intel_test_cmd_unlock_unit(t,
1397                                                 buf, buf_len, i);
1398                                 break;
1399                         case NVDIMM_INTEL_SET_PASSPHRASE:
1400                                 rc = nd_intel_test_cmd_set_pass(t,
1401                                                 buf, buf_len, i);
1402                                 break;
1403                         case NVDIMM_INTEL_DISABLE_PASSPHRASE:
1404                                 rc = nd_intel_test_cmd_disable_pass(t,
1405                                                 buf, buf_len, i);
1406                                 break;
1407                         case NVDIMM_INTEL_FREEZE_LOCK:
1408                                 rc = nd_intel_test_cmd_freeze_lock(t,
1409                                                 buf, buf_len, i);
1410                                 break;
1411                         case NVDIMM_INTEL_SECURE_ERASE:
1412                                 rc = nd_intel_test_cmd_secure_erase(t,
1413                                                 buf, buf_len, i);
1414                                 break;
1415                         case NVDIMM_INTEL_OVERWRITE:
1416                                 rc = nd_intel_test_cmd_overwrite(t,
1417                                                 buf, buf_len, i);
1418                                 break;
1419                         case NVDIMM_INTEL_QUERY_OVERWRITE:
1420                                 rc = nd_intel_test_cmd_query_overwrite(t,
1421                                                 buf, buf_len, i);
1422                                 break;
1423                         case NVDIMM_INTEL_SET_MASTER_PASSPHRASE:
1424                                 rc = nd_intel_test_cmd_master_set_pass(t,
1425                                                 buf, buf_len, i);
1426                                 break;
1427                         case NVDIMM_INTEL_MASTER_SECURE_ERASE:
1428                                 rc = nd_intel_test_cmd_master_secure_erase(t,
1429                                                 buf, buf_len, i);
1430                                 break;
1431                         case NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO:
1432                                 rc = nd_intel_test_cmd_fw_activate_dimminfo(
1433                                         t, buf, buf_len, i);
1434                                 break;
1435                         case NVDIMM_INTEL_FW_ACTIVATE_ARM:
1436                                 rc = nd_intel_test_cmd_fw_activate_arm(
1437                                         t, buf, buf_len, i);
1438                                 break;
1439                         case ND_INTEL_ENABLE_LSS_STATUS:
1440                                 rc = nd_intel_test_cmd_set_lss_status(t,
1441                                                 buf, buf_len);
1442                                 break;
1443                         case ND_INTEL_FW_GET_INFO:
1444                                 rc = nd_intel_test_get_fw_info(t, buf,
1445                                                 buf_len, i);
1446                                 break;
1447                         case ND_INTEL_FW_START_UPDATE:
1448                                 rc = nd_intel_test_start_update(t, buf,
1449                                                 buf_len, i);
1450                                 break;
1451                         case ND_INTEL_FW_SEND_DATA:
1452                                 rc = nd_intel_test_send_data(t, buf,
1453                                                 buf_len, i);
1454                                 break;
1455                         case ND_INTEL_FW_FINISH_UPDATE:
1456                                 rc = nd_intel_test_finish_fw(t, buf,
1457                                                 buf_len, i);
1458                                 break;
1459                         case ND_INTEL_FW_FINISH_QUERY:
1460                                 rc = nd_intel_test_finish_query(t, buf,
1461                                                 buf_len, i);
1462                                 break;
1463                         case ND_INTEL_SMART:
1464                                 rc = nfit_test_cmd_smart(buf, buf_len,
1465                                                 &t->smart[i]);
1466                                 break;
1467                         case ND_INTEL_SMART_THRESHOLD:
1468                                 rc = nfit_test_cmd_smart_threshold(buf,
1469                                                 buf_len,
1470                                                 &t->smart_threshold[i]);
1471                                 break;
1472                         case ND_INTEL_SMART_SET_THRESHOLD:
1473                                 rc = nfit_test_cmd_smart_set_threshold(buf,
1474                                                 buf_len,
1475                                                 &t->smart_threshold[i],
1476                                                 &t->smart[i],
1477                                                 &t->pdev.dev, t->dimm_dev[i]);
1478                                 break;
1479                         case ND_INTEL_SMART_INJECT:
1480                                 rc = nfit_test_cmd_smart_inject(buf,
1481                                                 buf_len,
1482                                                 &t->smart_threshold[i],
1483                                                 &t->smart[i],
1484                                                 &t->pdev.dev, t->dimm_dev[i]);
1485                                 break;
1486                         default:
1487                                 return -ENOTTY;
1488                         }
1489                         return override_return_code(i, func, rc);
1490                 }
1491
1492                 if (!test_bit(cmd, &cmd_mask)
1493                                 || !test_bit(func, &nfit_mem->dsm_mask))
1494                         return -ENOTTY;
1495
1496                 i = get_dimm(nfit_mem, func);
1497                 if (i < 0)
1498                         return i;
1499
1500                 switch (func) {
1501                 case ND_CMD_GET_CONFIG_SIZE:
1502                         rc = nfit_test_cmd_get_config_size(buf, buf_len);
1503                         break;
1504                 case ND_CMD_GET_CONFIG_DATA:
1505                         rc = nfit_test_cmd_get_config_data(buf, buf_len,
1506                                 t->label[i - t->dcr_idx]);
1507                         break;
1508                 case ND_CMD_SET_CONFIG_DATA:
1509                         rc = nfit_test_cmd_set_config_data(buf, buf_len,
1510                                 t->label[i - t->dcr_idx]);
1511                         break;
1512                 default:
1513                         return -ENOTTY;
1514                 }
1515                 return override_return_code(i, func, rc);
1516         } else {
1517                 struct ars_state *ars_state = &t->ars_state;
1518                 struct nd_cmd_pkg *call_pkg = buf;
1519
1520                 if (!nd_desc)
1521                         return -ENOTTY;
1522
1523                 if (cmd == ND_CMD_CALL && call_pkg->nd_family
1524                                 == NVDIMM_BUS_FAMILY_NFIT) {
1525                         func = call_pkg->nd_command;
1526                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1527                         buf = (void *) call_pkg->nd_payload;
1528
1529                         switch (func) {
1530                         case NFIT_CMD_TRANSLATE_SPA:
1531                                 rc = nfit_test_cmd_translate_spa(
1532                                         acpi_desc->nvdimm_bus, buf, buf_len);
1533                                 return rc;
1534                         case NFIT_CMD_ARS_INJECT_SET:
1535                                 rc = nfit_test_cmd_ars_error_inject(t, buf,
1536                                         buf_len);
1537                                 return rc;
1538                         case NFIT_CMD_ARS_INJECT_CLEAR:
1539                                 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1540                                         buf_len);
1541                                 return rc;
1542                         case NFIT_CMD_ARS_INJECT_GET:
1543                                 rc = nfit_test_cmd_ars_inject_status(t, buf,
1544                                         buf_len);
1545                                 return rc;
1546                         default:
1547                                 return -ENOTTY;
1548                         }
1549                 } else if (cmd == ND_CMD_CALL && call_pkg->nd_family
1550                                 == NVDIMM_BUS_FAMILY_INTEL) {
1551                         func = call_pkg->nd_command;
1552                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1553                         buf = (void *) call_pkg->nd_payload;
1554
1555                         switch (func) {
1556                         case NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO:
1557                                 rc = nvdimm_bus_intel_fw_activate_businfo(t,
1558                                                 buf, buf_len);
1559                                 return rc;
1560                         case NVDIMM_BUS_INTEL_FW_ACTIVATE:
1561                                 rc = nvdimm_bus_intel_fw_activate(t, buf,
1562                                                 buf_len);
1563                                 return rc;
1564                         default:
1565                                 return -ENOTTY;
1566                         }
1567                 } else if (cmd == ND_CMD_CALL)
1568                         return -ENOTTY;
1569
1570                 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1571                         return -ENOTTY;
1572
1573                 switch (func) {
1574                 case ND_CMD_ARS_CAP:
1575                         rc = nfit_test_cmd_ars_cap(buf, buf_len);
1576                         break;
1577                 case ND_CMD_ARS_START:
1578                         rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1579                                         buf_len, cmd_rc);
1580                         break;
1581                 case ND_CMD_ARS_STATUS:
1582                         rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1583                                         cmd_rc);
1584                         break;
1585                 case ND_CMD_CLEAR_ERROR:
1586                         rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1587                         break;
1588                 default:
1589                         return -ENOTTY;
1590                 }
1591         }
1592
1593         return rc;
1594 }
1595
1596 static DEFINE_SPINLOCK(nfit_test_lock);
1597 static struct nfit_test *instances[NUM_NFITS];
1598
1599 static void release_nfit_res(void *data)
1600 {
1601         struct nfit_test_resource *nfit_res = data;
1602
1603         spin_lock(&nfit_test_lock);
1604         list_del(&nfit_res->list);
1605         spin_unlock(&nfit_test_lock);
1606
1607         if (resource_size(&nfit_res->res) >= DIMM_SIZE)
1608                 gen_pool_free(nfit_pool, nfit_res->res.start,
1609                                 resource_size(&nfit_res->res));
1610         vfree(nfit_res->buf);
1611         kfree(nfit_res);
1612 }
1613
1614 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1615                 void *buf)
1616 {
1617         struct device *dev = &t->pdev.dev;
1618         struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1619                         GFP_KERNEL);
1620         int rc;
1621
1622         if (!buf || !nfit_res || !*dma)
1623                 goto err;
1624         rc = devm_add_action(dev, release_nfit_res, nfit_res);
1625         if (rc)
1626                 goto err;
1627         INIT_LIST_HEAD(&nfit_res->list);
1628         memset(buf, 0, size);
1629         nfit_res->dev = dev;
1630         nfit_res->buf = buf;
1631         nfit_res->res.start = *dma;
1632         nfit_res->res.end = *dma + size - 1;
1633         nfit_res->res.name = "NFIT";
1634         spin_lock_init(&nfit_res->lock);
1635         INIT_LIST_HEAD(&nfit_res->requests);
1636         spin_lock(&nfit_test_lock);
1637         list_add(&nfit_res->list, &t->resources);
1638         spin_unlock(&nfit_test_lock);
1639
1640         return nfit_res->buf;
1641  err:
1642         if (*dma && size >= DIMM_SIZE)
1643                 gen_pool_free(nfit_pool, *dma, size);
1644         if (buf)
1645                 vfree(buf);
1646         kfree(nfit_res);
1647         return NULL;
1648 }
1649
1650 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1651 {
1652         struct genpool_data_align data = {
1653                 .align = SZ_128M,
1654         };
1655         void *buf = vmalloc(size);
1656
1657         if (size >= DIMM_SIZE)
1658                 *dma = gen_pool_alloc_algo(nfit_pool, size,
1659                                 gen_pool_first_fit_align, &data);
1660         else
1661                 *dma = (unsigned long) buf;
1662         return __test_alloc(t, size, dma, buf);
1663 }
1664
1665 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1666 {
1667         int i;
1668
1669         for (i = 0; i < ARRAY_SIZE(instances); i++) {
1670                 struct nfit_test_resource *n, *nfit_res = NULL;
1671                 struct nfit_test *t = instances[i];
1672
1673                 if (!t)
1674                         continue;
1675                 spin_lock(&nfit_test_lock);
1676                 list_for_each_entry(n, &t->resources, list) {
1677                         if (addr >= n->res.start && (addr < n->res.start
1678                                                 + resource_size(&n->res))) {
1679                                 nfit_res = n;
1680                                 break;
1681                         } else if (addr >= (unsigned long) n->buf
1682                                         && (addr < (unsigned long) n->buf
1683                                                 + resource_size(&n->res))) {
1684                                 nfit_res = n;
1685                                 break;
1686                         }
1687                 }
1688                 spin_unlock(&nfit_test_lock);
1689                 if (nfit_res)
1690                         return nfit_res;
1691         }
1692
1693         return NULL;
1694 }
1695
1696 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1697 {
1698         /* for testing, only store up to n records that fit within 4k */
1699         ars_state->ars_status = devm_kzalloc(dev,
1700                         sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1701         if (!ars_state->ars_status)
1702                 return -ENOMEM;
1703         spin_lock_init(&ars_state->lock);
1704         return 0;
1705 }
1706
1707 static void put_dimms(void *data)
1708 {
1709         struct nfit_test *t = data;
1710         int i;
1711
1712         for (i = 0; i < t->num_dcr; i++)
1713                 if (t->dimm_dev[i])
1714                         device_unregister(t->dimm_dev[i]);
1715 }
1716
1717 static struct class *nfit_test_dimm;
1718
1719 static int dimm_name_to_id(struct device *dev)
1720 {
1721         int dimm;
1722
1723         if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1724                 return -ENXIO;
1725         return dimm;
1726 }
1727
1728 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1729                 char *buf)
1730 {
1731         int dimm = dimm_name_to_id(dev);
1732
1733         if (dimm < 0)
1734                 return dimm;
1735
1736         return sprintf(buf, "%#x\n", handle[dimm]);
1737 }
1738 DEVICE_ATTR_RO(handle);
1739
1740 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1741                 char *buf)
1742 {
1743         int dimm = dimm_name_to_id(dev);
1744
1745         if (dimm < 0)
1746                 return dimm;
1747
1748         return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1749 }
1750
1751 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1752                 const char *buf, size_t size)
1753 {
1754         int dimm = dimm_name_to_id(dev);
1755         unsigned long val;
1756         ssize_t rc;
1757
1758         if (dimm < 0)
1759                 return dimm;
1760
1761         rc = kstrtol(buf, 0, &val);
1762         if (rc)
1763                 return rc;
1764
1765         dimm_fail_cmd_flags[dimm] = val;
1766         return size;
1767 }
1768 static DEVICE_ATTR_RW(fail_cmd);
1769
1770 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1771                 char *buf)
1772 {
1773         int dimm = dimm_name_to_id(dev);
1774
1775         if (dimm < 0)
1776                 return dimm;
1777
1778         return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1779 }
1780
1781 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1782                 const char *buf, size_t size)
1783 {
1784         int dimm = dimm_name_to_id(dev);
1785         unsigned long val;
1786         ssize_t rc;
1787
1788         if (dimm < 0)
1789                 return dimm;
1790
1791         rc = kstrtol(buf, 0, &val);
1792         if (rc)
1793                 return rc;
1794
1795         dimm_fail_cmd_code[dimm] = val;
1796         return size;
1797 }
1798 static DEVICE_ATTR_RW(fail_cmd_code);
1799
1800 static ssize_t lock_dimm_store(struct device *dev,
1801                 struct device_attribute *attr, const char *buf, size_t size)
1802 {
1803         int dimm = dimm_name_to_id(dev);
1804         struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1805
1806         sec->state = ND_INTEL_SEC_STATE_ENABLED | ND_INTEL_SEC_STATE_LOCKED;
1807         return size;
1808 }
1809 static DEVICE_ATTR_WO(lock_dimm);
1810
1811 static struct attribute *nfit_test_dimm_attributes[] = {
1812         &dev_attr_fail_cmd.attr,
1813         &dev_attr_fail_cmd_code.attr,
1814         &dev_attr_handle.attr,
1815         &dev_attr_lock_dimm.attr,
1816         NULL,
1817 };
1818
1819 static struct attribute_group nfit_test_dimm_attribute_group = {
1820         .attrs = nfit_test_dimm_attributes,
1821 };
1822
1823 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1824         &nfit_test_dimm_attribute_group,
1825         NULL,
1826 };
1827
1828 static int nfit_test_dimm_init(struct nfit_test *t)
1829 {
1830         int i;
1831
1832         if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1833                 return -ENOMEM;
1834         for (i = 0; i < t->num_dcr; i++) {
1835                 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1836                                 &t->pdev.dev, 0, NULL,
1837                                 nfit_test_dimm_attribute_groups,
1838                                 "test_dimm%d", i + t->dcr_idx);
1839                 if (!t->dimm_dev[i])
1840                         return -ENOMEM;
1841         }
1842         return 0;
1843 }
1844
1845 static void security_init(struct nfit_test *t)
1846 {
1847         int i;
1848
1849         for (i = 0; i < t->num_dcr; i++) {
1850                 struct nfit_test_sec *sec = &dimm_sec_info[i];
1851
1852                 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1853         }
1854 }
1855
1856 static void smart_init(struct nfit_test *t)
1857 {
1858         int i;
1859         const struct nd_intel_smart_threshold smart_t_data = {
1860                 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1861                         | ND_INTEL_SMART_TEMP_TRIP,
1862                 .media_temperature = 40 * 16,
1863                 .ctrl_temperature = 30 * 16,
1864                 .spares = 5,
1865         };
1866
1867         for (i = 0; i < t->num_dcr; i++) {
1868                 memcpy(&t->smart[i], &smart_def, sizeof(smart_def));
1869                 memcpy(&t->smart_threshold[i], &smart_t_data,
1870                                 sizeof(smart_t_data));
1871         }
1872 }
1873
1874 static size_t sizeof_spa(struct acpi_nfit_system_address *spa)
1875 {
1876         /* until spa location cookie support is added... */
1877         return sizeof(*spa) - 8;
1878 }
1879
1880 static int nfit_test0_alloc(struct nfit_test *t)
1881 {
1882         struct acpi_nfit_system_address *spa = NULL;
1883         size_t nfit_size = sizeof_spa(spa) * NUM_SPA
1884                         + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1885                         + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1886                         + offsetof(struct acpi_nfit_control_region,
1887                                         window_size) * NUM_DCR
1888                         + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1889                         + (sizeof(struct acpi_nfit_flush_address)
1890                                         + sizeof(u64) * NUM_HINTS) * NUM_DCR
1891                         + sizeof(struct acpi_nfit_capabilities);
1892         int i;
1893
1894         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1895         if (!t->nfit_buf)
1896                 return -ENOMEM;
1897         t->nfit_size = nfit_size;
1898
1899         t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1900         if (!t->spa_set[0])
1901                 return -ENOMEM;
1902
1903         t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1904         if (!t->spa_set[1])
1905                 return -ENOMEM;
1906
1907         t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1908         if (!t->spa_set[2])
1909                 return -ENOMEM;
1910
1911         for (i = 0; i < t->num_dcr; i++) {
1912                 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1913                 if (!t->dimm[i])
1914                         return -ENOMEM;
1915
1916                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1917                 if (!t->label[i])
1918                         return -ENOMEM;
1919                 sprintf(t->label[i], "label%d", i);
1920
1921                 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1922                                         sizeof(u64) * NUM_HINTS),
1923                                 &t->flush_dma[i]);
1924                 if (!t->flush[i])
1925                         return -ENOMEM;
1926         }
1927
1928         for (i = 0; i < t->num_dcr; i++) {
1929                 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1930                 if (!t->dcr[i])
1931                         return -ENOMEM;
1932         }
1933
1934         t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1935         if (!t->_fit)
1936                 return -ENOMEM;
1937
1938         if (nfit_test_dimm_init(t))
1939                 return -ENOMEM;
1940         smart_init(t);
1941         security_init(t);
1942         return ars_state_init(&t->pdev.dev, &t->ars_state);
1943 }
1944
1945 static int nfit_test1_alloc(struct nfit_test *t)
1946 {
1947         struct acpi_nfit_system_address *spa = NULL;
1948         size_t nfit_size = sizeof_spa(spa) * 2
1949                 + sizeof(struct acpi_nfit_memory_map) * 2
1950                 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1951         int i;
1952
1953         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1954         if (!t->nfit_buf)
1955                 return -ENOMEM;
1956         t->nfit_size = nfit_size;
1957
1958         t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1959         if (!t->spa_set[0])
1960                 return -ENOMEM;
1961
1962         for (i = 0; i < t->num_dcr; i++) {
1963                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1964                 if (!t->label[i])
1965                         return -ENOMEM;
1966                 sprintf(t->label[i], "label%d", i);
1967         }
1968
1969         t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1970         if (!t->spa_set[1])
1971                 return -ENOMEM;
1972
1973         if (nfit_test_dimm_init(t))
1974                 return -ENOMEM;
1975         smart_init(t);
1976         return ars_state_init(&t->pdev.dev, &t->ars_state);
1977 }
1978
1979 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1980 {
1981         dcr->vendor_id = 0xabcd;
1982         dcr->device_id = 0;
1983         dcr->revision_id = 1;
1984         dcr->valid_fields = 1;
1985         dcr->manufacturing_location = 0xa;
1986         dcr->manufacturing_date = cpu_to_be16(2016);
1987 }
1988
1989 static void nfit_test0_setup(struct nfit_test *t)
1990 {
1991         const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1992                 + (sizeof(u64) * NUM_HINTS);
1993         struct acpi_nfit_desc *acpi_desc;
1994         struct acpi_nfit_memory_map *memdev;
1995         void *nfit_buf = t->nfit_buf;
1996         struct acpi_nfit_system_address *spa;
1997         struct acpi_nfit_control_region *dcr;
1998         struct acpi_nfit_data_region *bdw;
1999         struct acpi_nfit_flush_address *flush;
2000         struct acpi_nfit_capabilities *pcap;
2001         unsigned int offset = 0, i;
2002         unsigned long *acpi_mask;
2003
2004         /*
2005          * spa0 (interleave first half of dimm0 and dimm1, note storage
2006          * does not actually alias the related block-data-window
2007          * regions)
2008          */
2009         spa = nfit_buf;
2010         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2011         spa->header.length = sizeof_spa(spa);
2012         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2013         spa->range_index = 0+1;
2014         spa->address = t->spa_set_dma[0];
2015         spa->length = SPA0_SIZE;
2016         offset += spa->header.length;
2017
2018         /*
2019          * spa1 (interleave last half of the 4 DIMMS, note storage
2020          * does not actually alias the related block-data-window
2021          * regions)
2022          */
2023         spa = nfit_buf + offset;
2024         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2025         spa->header.length = sizeof_spa(spa);
2026         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2027         spa->range_index = 1+1;
2028         spa->address = t->spa_set_dma[1];
2029         spa->length = SPA1_SIZE;
2030         offset += spa->header.length;
2031
2032         /* spa2 (dcr0) dimm0 */
2033         spa = nfit_buf + offset;
2034         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2035         spa->header.length = sizeof_spa(spa);
2036         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2037         spa->range_index = 2+1;
2038         spa->address = t->dcr_dma[0];
2039         spa->length = DCR_SIZE;
2040         offset += spa->header.length;
2041
2042         /* spa3 (dcr1) dimm1 */
2043         spa = nfit_buf + offset;
2044         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2045         spa->header.length = sizeof_spa(spa);
2046         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2047         spa->range_index = 3+1;
2048         spa->address = t->dcr_dma[1];
2049         spa->length = DCR_SIZE;
2050         offset += spa->header.length;
2051
2052         /* spa4 (dcr2) dimm2 */
2053         spa = nfit_buf + offset;
2054         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2055         spa->header.length = sizeof_spa(spa);
2056         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2057         spa->range_index = 4+1;
2058         spa->address = t->dcr_dma[2];
2059         spa->length = DCR_SIZE;
2060         offset += spa->header.length;
2061
2062         /* spa5 (dcr3) dimm3 */
2063         spa = nfit_buf + offset;
2064         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2065         spa->header.length = sizeof_spa(spa);
2066         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2067         spa->range_index = 5+1;
2068         spa->address = t->dcr_dma[3];
2069         spa->length = DCR_SIZE;
2070         offset += spa->header.length;
2071
2072         /* spa6 (bdw for dcr0) dimm0 */
2073         spa = nfit_buf + offset;
2074         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2075         spa->header.length = sizeof_spa(spa);
2076         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2077         spa->range_index = 6+1;
2078         spa->address = t->dimm_dma[0];
2079         spa->length = DIMM_SIZE;
2080         offset += spa->header.length;
2081
2082         /* spa7 (bdw for dcr1) dimm1 */
2083         spa = nfit_buf + offset;
2084         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2085         spa->header.length = sizeof_spa(spa);
2086         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2087         spa->range_index = 7+1;
2088         spa->address = t->dimm_dma[1];
2089         spa->length = DIMM_SIZE;
2090         offset += spa->header.length;
2091
2092         /* spa8 (bdw for dcr2) dimm2 */
2093         spa = nfit_buf + offset;
2094         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2095         spa->header.length = sizeof_spa(spa);
2096         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2097         spa->range_index = 8+1;
2098         spa->address = t->dimm_dma[2];
2099         spa->length = DIMM_SIZE;
2100         offset += spa->header.length;
2101
2102         /* spa9 (bdw for dcr3) dimm3 */
2103         spa = nfit_buf + offset;
2104         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2105         spa->header.length = sizeof_spa(spa);
2106         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2107         spa->range_index = 9+1;
2108         spa->address = t->dimm_dma[3];
2109         spa->length = DIMM_SIZE;
2110         offset += spa->header.length;
2111
2112         /* mem-region0 (spa0, dimm0) */
2113         memdev = nfit_buf + offset;
2114         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2115         memdev->header.length = sizeof(*memdev);
2116         memdev->device_handle = handle[0];
2117         memdev->physical_id = 0;
2118         memdev->region_id = 0;
2119         memdev->range_index = 0+1;
2120         memdev->region_index = 4+1;
2121         memdev->region_size = SPA0_SIZE/2;
2122         memdev->region_offset = 1;
2123         memdev->address = 0;
2124         memdev->interleave_index = 0;
2125         memdev->interleave_ways = 2;
2126         offset += memdev->header.length;
2127
2128         /* mem-region1 (spa0, dimm1) */
2129         memdev = nfit_buf + offset;
2130         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2131         memdev->header.length = sizeof(*memdev);
2132         memdev->device_handle = handle[1];
2133         memdev->physical_id = 1;
2134         memdev->region_id = 0;
2135         memdev->range_index = 0+1;
2136         memdev->region_index = 5+1;
2137         memdev->region_size = SPA0_SIZE/2;
2138         memdev->region_offset = (1 << 8);
2139         memdev->address = 0;
2140         memdev->interleave_index = 0;
2141         memdev->interleave_ways = 2;
2142         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2143         offset += memdev->header.length;
2144
2145         /* mem-region2 (spa1, dimm0) */
2146         memdev = nfit_buf + offset;
2147         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2148         memdev->header.length = sizeof(*memdev);
2149         memdev->device_handle = handle[0];
2150         memdev->physical_id = 0;
2151         memdev->region_id = 1;
2152         memdev->range_index = 1+1;
2153         memdev->region_index = 4+1;
2154         memdev->region_size = SPA1_SIZE/4;
2155         memdev->region_offset = (1 << 16);
2156         memdev->address = SPA0_SIZE/2;
2157         memdev->interleave_index = 0;
2158         memdev->interleave_ways = 4;
2159         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2160         offset += memdev->header.length;
2161
2162         /* mem-region3 (spa1, dimm1) */
2163         memdev = nfit_buf + offset;
2164         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2165         memdev->header.length = sizeof(*memdev);
2166         memdev->device_handle = handle[1];
2167         memdev->physical_id = 1;
2168         memdev->region_id = 1;
2169         memdev->range_index = 1+1;
2170         memdev->region_index = 5+1;
2171         memdev->region_size = SPA1_SIZE/4;
2172         memdev->region_offset = (1 << 24);
2173         memdev->address = SPA0_SIZE/2;
2174         memdev->interleave_index = 0;
2175         memdev->interleave_ways = 4;
2176         offset += memdev->header.length;
2177
2178         /* mem-region4 (spa1, dimm2) */
2179         memdev = nfit_buf + offset;
2180         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2181         memdev->header.length = sizeof(*memdev);
2182         memdev->device_handle = handle[2];
2183         memdev->physical_id = 2;
2184         memdev->region_id = 0;
2185         memdev->range_index = 1+1;
2186         memdev->region_index = 6+1;
2187         memdev->region_size = SPA1_SIZE/4;
2188         memdev->region_offset = (1ULL << 32);
2189         memdev->address = SPA0_SIZE/2;
2190         memdev->interleave_index = 0;
2191         memdev->interleave_ways = 4;
2192         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2193         offset += memdev->header.length;
2194
2195         /* mem-region5 (spa1, dimm3) */
2196         memdev = nfit_buf + offset;
2197         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2198         memdev->header.length = sizeof(*memdev);
2199         memdev->device_handle = handle[3];
2200         memdev->physical_id = 3;
2201         memdev->region_id = 0;
2202         memdev->range_index = 1+1;
2203         memdev->region_index = 7+1;
2204         memdev->region_size = SPA1_SIZE/4;
2205         memdev->region_offset = (1ULL << 40);
2206         memdev->address = SPA0_SIZE/2;
2207         memdev->interleave_index = 0;
2208         memdev->interleave_ways = 4;
2209         offset += memdev->header.length;
2210
2211         /* mem-region6 (spa/dcr0, dimm0) */
2212         memdev = nfit_buf + offset;
2213         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2214         memdev->header.length = sizeof(*memdev);
2215         memdev->device_handle = handle[0];
2216         memdev->physical_id = 0;
2217         memdev->region_id = 0;
2218         memdev->range_index = 2+1;
2219         memdev->region_index = 0+1;
2220         memdev->region_size = 0;
2221         memdev->region_offset = 0;
2222         memdev->address = 0;
2223         memdev->interleave_index = 0;
2224         memdev->interleave_ways = 1;
2225         offset += memdev->header.length;
2226
2227         /* mem-region7 (spa/dcr1, dimm1) */
2228         memdev = nfit_buf + offset;
2229         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2230         memdev->header.length = sizeof(*memdev);
2231         memdev->device_handle = handle[1];
2232         memdev->physical_id = 1;
2233         memdev->region_id = 0;
2234         memdev->range_index = 3+1;
2235         memdev->region_index = 1+1;
2236         memdev->region_size = 0;
2237         memdev->region_offset = 0;
2238         memdev->address = 0;
2239         memdev->interleave_index = 0;
2240         memdev->interleave_ways = 1;
2241         offset += memdev->header.length;
2242
2243         /* mem-region8 (spa/dcr2, dimm2) */
2244         memdev = nfit_buf + offset;
2245         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2246         memdev->header.length = sizeof(*memdev);
2247         memdev->device_handle = handle[2];
2248         memdev->physical_id = 2;
2249         memdev->region_id = 0;
2250         memdev->range_index = 4+1;
2251         memdev->region_index = 2+1;
2252         memdev->region_size = 0;
2253         memdev->region_offset = 0;
2254         memdev->address = 0;
2255         memdev->interleave_index = 0;
2256         memdev->interleave_ways = 1;
2257         offset += memdev->header.length;
2258
2259         /* mem-region9 (spa/dcr3, dimm3) */
2260         memdev = nfit_buf + offset;
2261         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2262         memdev->header.length = sizeof(*memdev);
2263         memdev->device_handle = handle[3];
2264         memdev->physical_id = 3;
2265         memdev->region_id = 0;
2266         memdev->range_index = 5+1;
2267         memdev->region_index = 3+1;
2268         memdev->region_size = 0;
2269         memdev->region_offset = 0;
2270         memdev->address = 0;
2271         memdev->interleave_index = 0;
2272         memdev->interleave_ways = 1;
2273         offset += memdev->header.length;
2274
2275         /* mem-region10 (spa/bdw0, dimm0) */
2276         memdev = nfit_buf + offset;
2277         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2278         memdev->header.length = sizeof(*memdev);
2279         memdev->device_handle = handle[0];
2280         memdev->physical_id = 0;
2281         memdev->region_id = 0;
2282         memdev->range_index = 6+1;
2283         memdev->region_index = 0+1;
2284         memdev->region_size = 0;
2285         memdev->region_offset = 0;
2286         memdev->address = 0;
2287         memdev->interleave_index = 0;
2288         memdev->interleave_ways = 1;
2289         offset += memdev->header.length;
2290
2291         /* mem-region11 (spa/bdw1, dimm1) */
2292         memdev = nfit_buf + offset;
2293         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2294         memdev->header.length = sizeof(*memdev);
2295         memdev->device_handle = handle[1];
2296         memdev->physical_id = 1;
2297         memdev->region_id = 0;
2298         memdev->range_index = 7+1;
2299         memdev->region_index = 1+1;
2300         memdev->region_size = 0;
2301         memdev->region_offset = 0;
2302         memdev->address = 0;
2303         memdev->interleave_index = 0;
2304         memdev->interleave_ways = 1;
2305         offset += memdev->header.length;
2306
2307         /* mem-region12 (spa/bdw2, dimm2) */
2308         memdev = nfit_buf + offset;
2309         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2310         memdev->header.length = sizeof(*memdev);
2311         memdev->device_handle = handle[2];
2312         memdev->physical_id = 2;
2313         memdev->region_id = 0;
2314         memdev->range_index = 8+1;
2315         memdev->region_index = 2+1;
2316         memdev->region_size = 0;
2317         memdev->region_offset = 0;
2318         memdev->address = 0;
2319         memdev->interleave_index = 0;
2320         memdev->interleave_ways = 1;
2321         offset += memdev->header.length;
2322
2323         /* mem-region13 (spa/dcr3, dimm3) */
2324         memdev = nfit_buf + offset;
2325         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2326         memdev->header.length = sizeof(*memdev);
2327         memdev->device_handle = handle[3];
2328         memdev->physical_id = 3;
2329         memdev->region_id = 0;
2330         memdev->range_index = 9+1;
2331         memdev->region_index = 3+1;
2332         memdev->region_size = 0;
2333         memdev->region_offset = 0;
2334         memdev->address = 0;
2335         memdev->interleave_index = 0;
2336         memdev->interleave_ways = 1;
2337         memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2338         offset += memdev->header.length;
2339
2340         /* dcr-descriptor0: blk */
2341         dcr = nfit_buf + offset;
2342         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2343         dcr->header.length = sizeof(*dcr);
2344         dcr->region_index = 0+1;
2345         dcr_common_init(dcr);
2346         dcr->serial_number = ~handle[0];
2347         dcr->code = NFIT_FIC_BLK;
2348         dcr->windows = 1;
2349         dcr->window_size = DCR_SIZE;
2350         dcr->command_offset = 0;
2351         dcr->command_size = 8;
2352         dcr->status_offset = 8;
2353         dcr->status_size = 4;
2354         offset += dcr->header.length;
2355
2356         /* dcr-descriptor1: blk */
2357         dcr = nfit_buf + offset;
2358         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2359         dcr->header.length = sizeof(*dcr);
2360         dcr->region_index = 1+1;
2361         dcr_common_init(dcr);
2362         dcr->serial_number = ~handle[1];
2363         dcr->code = NFIT_FIC_BLK;
2364         dcr->windows = 1;
2365         dcr->window_size = DCR_SIZE;
2366         dcr->command_offset = 0;
2367         dcr->command_size = 8;
2368         dcr->status_offset = 8;
2369         dcr->status_size = 4;
2370         offset += dcr->header.length;
2371
2372         /* dcr-descriptor2: blk */
2373         dcr = nfit_buf + offset;
2374         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2375         dcr->header.length = sizeof(*dcr);
2376         dcr->region_index = 2+1;
2377         dcr_common_init(dcr);
2378         dcr->serial_number = ~handle[2];
2379         dcr->code = NFIT_FIC_BLK;
2380         dcr->windows = 1;
2381         dcr->window_size = DCR_SIZE;
2382         dcr->command_offset = 0;
2383         dcr->command_size = 8;
2384         dcr->status_offset = 8;
2385         dcr->status_size = 4;
2386         offset += dcr->header.length;
2387
2388         /* dcr-descriptor3: blk */
2389         dcr = nfit_buf + offset;
2390         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2391         dcr->header.length = sizeof(*dcr);
2392         dcr->region_index = 3+1;
2393         dcr_common_init(dcr);
2394         dcr->serial_number = ~handle[3];
2395         dcr->code = NFIT_FIC_BLK;
2396         dcr->windows = 1;
2397         dcr->window_size = DCR_SIZE;
2398         dcr->command_offset = 0;
2399         dcr->command_size = 8;
2400         dcr->status_offset = 8;
2401         dcr->status_size = 4;
2402         offset += dcr->header.length;
2403
2404         /* dcr-descriptor0: pmem */
2405         dcr = nfit_buf + offset;
2406         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2407         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2408                         window_size);
2409         dcr->region_index = 4+1;
2410         dcr_common_init(dcr);
2411         dcr->serial_number = ~handle[0];
2412         dcr->code = NFIT_FIC_BYTEN;
2413         dcr->windows = 0;
2414         offset += dcr->header.length;
2415
2416         /* dcr-descriptor1: pmem */
2417         dcr = nfit_buf + offset;
2418         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2419         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2420                         window_size);
2421         dcr->region_index = 5+1;
2422         dcr_common_init(dcr);
2423         dcr->serial_number = ~handle[1];
2424         dcr->code = NFIT_FIC_BYTEN;
2425         dcr->windows = 0;
2426         offset += dcr->header.length;
2427
2428         /* dcr-descriptor2: pmem */
2429         dcr = nfit_buf + offset;
2430         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2431         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2432                         window_size);
2433         dcr->region_index = 6+1;
2434         dcr_common_init(dcr);
2435         dcr->serial_number = ~handle[2];
2436         dcr->code = NFIT_FIC_BYTEN;
2437         dcr->windows = 0;
2438         offset += dcr->header.length;
2439
2440         /* dcr-descriptor3: pmem */
2441         dcr = nfit_buf + offset;
2442         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2443         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2444                         window_size);
2445         dcr->region_index = 7+1;
2446         dcr_common_init(dcr);
2447         dcr->serial_number = ~handle[3];
2448         dcr->code = NFIT_FIC_BYTEN;
2449         dcr->windows = 0;
2450         offset += dcr->header.length;
2451
2452         /* bdw0 (spa/dcr0, dimm0) */
2453         bdw = nfit_buf + offset;
2454         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2455         bdw->header.length = sizeof(*bdw);
2456         bdw->region_index = 0+1;
2457         bdw->windows = 1;
2458         bdw->offset = 0;
2459         bdw->size = BDW_SIZE;
2460         bdw->capacity = DIMM_SIZE;
2461         bdw->start_address = 0;
2462         offset += bdw->header.length;
2463
2464         /* bdw1 (spa/dcr1, dimm1) */
2465         bdw = nfit_buf + offset;
2466         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2467         bdw->header.length = sizeof(*bdw);
2468         bdw->region_index = 1+1;
2469         bdw->windows = 1;
2470         bdw->offset = 0;
2471         bdw->size = BDW_SIZE;
2472         bdw->capacity = DIMM_SIZE;
2473         bdw->start_address = 0;
2474         offset += bdw->header.length;
2475
2476         /* bdw2 (spa/dcr2, dimm2) */
2477         bdw = nfit_buf + offset;
2478         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2479         bdw->header.length = sizeof(*bdw);
2480         bdw->region_index = 2+1;
2481         bdw->windows = 1;
2482         bdw->offset = 0;
2483         bdw->size = BDW_SIZE;
2484         bdw->capacity = DIMM_SIZE;
2485         bdw->start_address = 0;
2486         offset += bdw->header.length;
2487
2488         /* bdw3 (spa/dcr3, dimm3) */
2489         bdw = nfit_buf + offset;
2490         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2491         bdw->header.length = sizeof(*bdw);
2492         bdw->region_index = 3+1;
2493         bdw->windows = 1;
2494         bdw->offset = 0;
2495         bdw->size = BDW_SIZE;
2496         bdw->capacity = DIMM_SIZE;
2497         bdw->start_address = 0;
2498         offset += bdw->header.length;
2499
2500         /* flush0 (dimm0) */
2501         flush = nfit_buf + offset;
2502         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2503         flush->header.length = flush_hint_size;
2504         flush->device_handle = handle[0];
2505         flush->hint_count = NUM_HINTS;
2506         for (i = 0; i < NUM_HINTS; i++)
2507                 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
2508         offset += flush->header.length;
2509
2510         /* flush1 (dimm1) */
2511         flush = nfit_buf + offset;
2512         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2513         flush->header.length = flush_hint_size;
2514         flush->device_handle = handle[1];
2515         flush->hint_count = NUM_HINTS;
2516         for (i = 0; i < NUM_HINTS; i++)
2517                 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
2518         offset += flush->header.length;
2519
2520         /* flush2 (dimm2) */
2521         flush = nfit_buf + offset;
2522         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2523         flush->header.length = flush_hint_size;
2524         flush->device_handle = handle[2];
2525         flush->hint_count = NUM_HINTS;
2526         for (i = 0; i < NUM_HINTS; i++)
2527                 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
2528         offset += flush->header.length;
2529
2530         /* flush3 (dimm3) */
2531         flush = nfit_buf + offset;
2532         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2533         flush->header.length = flush_hint_size;
2534         flush->device_handle = handle[3];
2535         flush->hint_count = NUM_HINTS;
2536         for (i = 0; i < NUM_HINTS; i++)
2537                 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
2538         offset += flush->header.length;
2539
2540         /* platform capabilities */
2541         pcap = nfit_buf + offset;
2542         pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
2543         pcap->header.length = sizeof(*pcap);
2544         pcap->highest_capability = 1;
2545         pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
2546         offset += pcap->header.length;
2547
2548         if (t->setup_hotplug) {
2549                 /* dcr-descriptor4: blk */
2550                 dcr = nfit_buf + offset;
2551                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2552                 dcr->header.length = sizeof(*dcr);
2553                 dcr->region_index = 8+1;
2554                 dcr_common_init(dcr);
2555                 dcr->serial_number = ~handle[4];
2556                 dcr->code = NFIT_FIC_BLK;
2557                 dcr->windows = 1;
2558                 dcr->window_size = DCR_SIZE;
2559                 dcr->command_offset = 0;
2560                 dcr->command_size = 8;
2561                 dcr->status_offset = 8;
2562                 dcr->status_size = 4;
2563                 offset += dcr->header.length;
2564
2565                 /* dcr-descriptor4: pmem */
2566                 dcr = nfit_buf + offset;
2567                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2568                 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2569                                 window_size);
2570                 dcr->region_index = 9+1;
2571                 dcr_common_init(dcr);
2572                 dcr->serial_number = ~handle[4];
2573                 dcr->code = NFIT_FIC_BYTEN;
2574                 dcr->windows = 0;
2575                 offset += dcr->header.length;
2576
2577                 /* bdw4 (spa/dcr4, dimm4) */
2578                 bdw = nfit_buf + offset;
2579                 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2580                 bdw->header.length = sizeof(*bdw);
2581                 bdw->region_index = 8+1;
2582                 bdw->windows = 1;
2583                 bdw->offset = 0;
2584                 bdw->size = BDW_SIZE;
2585                 bdw->capacity = DIMM_SIZE;
2586                 bdw->start_address = 0;
2587                 offset += bdw->header.length;
2588
2589                 /* spa10 (dcr4) dimm4 */
2590                 spa = nfit_buf + offset;
2591                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2592                 spa->header.length = sizeof_spa(spa);
2593                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2594                 spa->range_index = 10+1;
2595                 spa->address = t->dcr_dma[4];
2596                 spa->length = DCR_SIZE;
2597                 offset += spa->header.length;
2598
2599                 /*
2600                  * spa11 (single-dimm interleave for hotplug, note storage
2601                  * does not actually alias the related block-data-window
2602                  * regions)
2603                  */
2604                 spa = nfit_buf + offset;
2605                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2606                 spa->header.length = sizeof_spa(spa);
2607                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2608                 spa->range_index = 11+1;
2609                 spa->address = t->spa_set_dma[2];
2610                 spa->length = SPA0_SIZE;
2611                 offset += spa->header.length;
2612
2613                 /* spa12 (bdw for dcr4) dimm4 */
2614                 spa = nfit_buf + offset;
2615                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2616                 spa->header.length = sizeof_spa(spa);
2617                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2618                 spa->range_index = 12+1;
2619                 spa->address = t->dimm_dma[4];
2620                 spa->length = DIMM_SIZE;
2621                 offset += spa->header.length;
2622
2623                 /* mem-region14 (spa/dcr4, dimm4) */
2624                 memdev = nfit_buf + offset;
2625                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2626                 memdev->header.length = sizeof(*memdev);
2627                 memdev->device_handle = handle[4];
2628                 memdev->physical_id = 4;
2629                 memdev->region_id = 0;
2630                 memdev->range_index = 10+1;
2631                 memdev->region_index = 8+1;
2632                 memdev->region_size = 0;
2633                 memdev->region_offset = 0;
2634                 memdev->address = 0;
2635                 memdev->interleave_index = 0;
2636                 memdev->interleave_ways = 1;
2637                 offset += memdev->header.length;
2638
2639                 /* mem-region15 (spa11, dimm4) */
2640                 memdev = nfit_buf + offset;
2641                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2642                 memdev->header.length = sizeof(*memdev);
2643                 memdev->device_handle = handle[4];
2644                 memdev->physical_id = 4;
2645                 memdev->region_id = 0;
2646                 memdev->range_index = 11+1;
2647                 memdev->region_index = 9+1;
2648                 memdev->region_size = SPA0_SIZE;
2649                 memdev->region_offset = (1ULL << 48);
2650                 memdev->address = 0;
2651                 memdev->interleave_index = 0;
2652                 memdev->interleave_ways = 1;
2653                 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2654                 offset += memdev->header.length;
2655
2656                 /* mem-region16 (spa/bdw4, dimm4) */
2657                 memdev = nfit_buf + offset;
2658                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2659                 memdev->header.length = sizeof(*memdev);
2660                 memdev->device_handle = handle[4];
2661                 memdev->physical_id = 4;
2662                 memdev->region_id = 0;
2663                 memdev->range_index = 12+1;
2664                 memdev->region_index = 8+1;
2665                 memdev->region_size = 0;
2666                 memdev->region_offset = 0;
2667                 memdev->address = 0;
2668                 memdev->interleave_index = 0;
2669                 memdev->interleave_ways = 1;
2670                 offset += memdev->header.length;
2671
2672                 /* flush3 (dimm4) */
2673                 flush = nfit_buf + offset;
2674                 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2675                 flush->header.length = flush_hint_size;
2676                 flush->device_handle = handle[4];
2677                 flush->hint_count = NUM_HINTS;
2678                 for (i = 0; i < NUM_HINTS; i++)
2679                         flush->hint_address[i] = t->flush_dma[4]
2680                                 + i * sizeof(u64);
2681                 offset += flush->header.length;
2682
2683                 /* sanity check to make sure we've filled the buffer */
2684                 WARN_ON(offset != t->nfit_size);
2685         }
2686
2687         t->nfit_filled = offset;
2688
2689         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2690                         SPA0_SIZE);
2691
2692         acpi_desc = &t->acpi_desc;
2693         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2694         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2695         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2696         set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2697         set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2698         set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2699         set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2700         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2701         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2702         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2703         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2704         set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2705         set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_dsm_mask);
2706         set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_dsm_mask);
2707         set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_dsm_mask);
2708         set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_dsm_mask);
2709         set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2710         set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2711         set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2712         set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2713         set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2714         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2715         set_bit(NVDIMM_INTEL_GET_SECURITY_STATE,
2716                         &acpi_desc->dimm_cmd_force_en);
2717         set_bit(NVDIMM_INTEL_SET_PASSPHRASE, &acpi_desc->dimm_cmd_force_en);
2718         set_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE,
2719                         &acpi_desc->dimm_cmd_force_en);
2720         set_bit(NVDIMM_INTEL_UNLOCK_UNIT, &acpi_desc->dimm_cmd_force_en);
2721         set_bit(NVDIMM_INTEL_FREEZE_LOCK, &acpi_desc->dimm_cmd_force_en);
2722         set_bit(NVDIMM_INTEL_SECURE_ERASE, &acpi_desc->dimm_cmd_force_en);
2723         set_bit(NVDIMM_INTEL_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2724         set_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2725         set_bit(NVDIMM_INTEL_SET_MASTER_PASSPHRASE,
2726                         &acpi_desc->dimm_cmd_force_en);
2727         set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE,
2728                         &acpi_desc->dimm_cmd_force_en);
2729         set_bit(NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO, &acpi_desc->dimm_cmd_force_en);
2730         set_bit(NVDIMM_INTEL_FW_ACTIVATE_ARM, &acpi_desc->dimm_cmd_force_en);
2731
2732         acpi_mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL];
2733         set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO, acpi_mask);
2734         set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE, acpi_mask);
2735 }
2736
2737 static void nfit_test1_setup(struct nfit_test *t)
2738 {
2739         size_t offset;
2740         void *nfit_buf = t->nfit_buf;
2741         struct acpi_nfit_memory_map *memdev;
2742         struct acpi_nfit_control_region *dcr;
2743         struct acpi_nfit_system_address *spa;
2744         struct acpi_nfit_desc *acpi_desc;
2745
2746         offset = 0;
2747         /* spa0 (flat range with no bdw aliasing) */
2748         spa = nfit_buf + offset;
2749         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2750         spa->header.length = sizeof_spa(spa);
2751         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2752         spa->range_index = 0+1;
2753         spa->address = t->spa_set_dma[0];
2754         spa->length = SPA2_SIZE;
2755         offset += spa->header.length;
2756
2757         /* virtual cd region */
2758         spa = nfit_buf + offset;
2759         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2760         spa->header.length = sizeof_spa(spa);
2761         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2762         spa->range_index = 0;
2763         spa->address = t->spa_set_dma[1];
2764         spa->length = SPA_VCD_SIZE;
2765         offset += spa->header.length;
2766
2767         /* mem-region0 (spa0, dimm0) */
2768         memdev = nfit_buf + offset;
2769         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2770         memdev->header.length = sizeof(*memdev);
2771         memdev->device_handle = handle[5];
2772         memdev->physical_id = 0;
2773         memdev->region_id = 0;
2774         memdev->range_index = 0+1;
2775         memdev->region_index = 0+1;
2776         memdev->region_size = SPA2_SIZE;
2777         memdev->region_offset = 0;
2778         memdev->address = 0;
2779         memdev->interleave_index = 0;
2780         memdev->interleave_ways = 1;
2781         memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2782                 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2783                 | ACPI_NFIT_MEM_NOT_ARMED;
2784         offset += memdev->header.length;
2785
2786         /* dcr-descriptor0 */
2787         dcr = nfit_buf + offset;
2788         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2789         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2790                         window_size);
2791         dcr->region_index = 0+1;
2792         dcr_common_init(dcr);
2793         dcr->serial_number = ~handle[5];
2794         dcr->code = NFIT_FIC_BYTE;
2795         dcr->windows = 0;
2796         offset += dcr->header.length;
2797
2798         memdev = nfit_buf + offset;
2799         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2800         memdev->header.length = sizeof(*memdev);
2801         memdev->device_handle = handle[6];
2802         memdev->physical_id = 0;
2803         memdev->region_id = 0;
2804         memdev->range_index = 0;
2805         memdev->region_index = 0+2;
2806         memdev->region_size = SPA2_SIZE;
2807         memdev->region_offset = 0;
2808         memdev->address = 0;
2809         memdev->interleave_index = 0;
2810         memdev->interleave_ways = 1;
2811         memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2812         offset += memdev->header.length;
2813
2814         /* dcr-descriptor1 */
2815         dcr = nfit_buf + offset;
2816         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2817         dcr->header.length = offsetof(struct acpi_nfit_control_region,
2818                         window_size);
2819         dcr->region_index = 0+2;
2820         dcr_common_init(dcr);
2821         dcr->serial_number = ~handle[6];
2822         dcr->code = NFIT_FIC_BYTE;
2823         dcr->windows = 0;
2824         offset += dcr->header.length;
2825
2826         /* sanity check to make sure we've filled the buffer */
2827         WARN_ON(offset != t->nfit_size);
2828
2829         t->nfit_filled = offset;
2830
2831         post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2832                         SPA2_SIZE);
2833
2834         acpi_desc = &t->acpi_desc;
2835         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2836         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2837         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2838         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2839         set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2840         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2841         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2842         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2843 }
2844
2845 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2846                 void *iobuf, u64 len, int rw)
2847 {
2848         struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2849         struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2850         struct nd_region *nd_region = &ndbr->nd_region;
2851         unsigned int lane;
2852
2853         lane = nd_region_acquire_lane(nd_region);
2854         if (rw)
2855                 memcpy(mmio->addr.base + dpa, iobuf, len);
2856         else {
2857                 memcpy(iobuf, mmio->addr.base + dpa, len);
2858
2859                 /* give us some some coverage of the arch_invalidate_pmem() API */
2860                 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2861         }
2862         nd_region_release_lane(nd_region, lane);
2863
2864         return 0;
2865 }
2866
2867 static unsigned long nfit_ctl_handle;
2868
2869 union acpi_object *result;
2870
2871 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2872                 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2873 {
2874         if (handle != &nfit_ctl_handle)
2875                 return ERR_PTR(-ENXIO);
2876
2877         return result;
2878 }
2879
2880 static int setup_result(void *buf, size_t size)
2881 {
2882         result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2883         if (!result)
2884                 return -ENOMEM;
2885         result->package.type = ACPI_TYPE_BUFFER,
2886         result->buffer.pointer = (void *) (result + 1);
2887         result->buffer.length = size;
2888         memcpy(result->buffer.pointer, buf, size);
2889         memset(buf, 0, size);
2890         return 0;
2891 }
2892
2893 static int nfit_ctl_test(struct device *dev)
2894 {
2895         int rc, cmd_rc;
2896         struct nvdimm *nvdimm;
2897         struct acpi_device *adev;
2898         struct nfit_mem *nfit_mem;
2899         struct nd_ars_record *record;
2900         struct acpi_nfit_desc *acpi_desc;
2901         const u64 test_val = 0x0123456789abcdefULL;
2902         unsigned long mask, cmd_size, offset;
2903         struct nfit_ctl_test_cmd {
2904                 struct nd_cmd_pkg pkg;
2905                 union {
2906                         struct nd_cmd_get_config_size cfg_size;
2907                         struct nd_cmd_clear_error clear_err;
2908                         struct nd_cmd_ars_status ars_stat;
2909                         struct nd_cmd_ars_cap ars_cap;
2910                         struct nd_intel_bus_fw_activate_businfo fwa_info;
2911                         char buf[sizeof(struct nd_cmd_ars_status)
2912                                 + sizeof(struct nd_ars_record)];
2913                 };
2914         } cmd;
2915
2916         adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2917         if (!adev)
2918                 return -ENOMEM;
2919         *adev = (struct acpi_device) {
2920                 .handle = &nfit_ctl_handle,
2921                 .dev = {
2922                         .init_name = "test-adev",
2923                 },
2924         };
2925
2926         acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2927         if (!acpi_desc)
2928                 return -ENOMEM;
2929         *acpi_desc = (struct acpi_nfit_desc) {
2930                 .nd_desc = {
2931                         .cmd_mask = 1UL << ND_CMD_ARS_CAP
2932                                 | 1UL << ND_CMD_ARS_START
2933                                 | 1UL << ND_CMD_ARS_STATUS
2934                                 | 1UL << ND_CMD_CLEAR_ERROR
2935                                 | 1UL << ND_CMD_CALL,
2936                         .module = THIS_MODULE,
2937                         .provider_name = "ACPI.NFIT",
2938                         .ndctl = acpi_nfit_ctl,
2939                         .bus_family_mask = 1UL << NVDIMM_BUS_FAMILY_NFIT
2940                                 | 1UL << NVDIMM_BUS_FAMILY_INTEL,
2941                 },
2942                 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2943                         | 1UL << NFIT_CMD_ARS_INJECT_SET
2944                         | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2945                         | 1UL << NFIT_CMD_ARS_INJECT_GET,
2946                 .family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL] =
2947                         NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK,
2948                 .dev = &adev->dev,
2949         };
2950
2951         nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2952         if (!nfit_mem)
2953                 return -ENOMEM;
2954
2955         mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2956                 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2957                 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2958                 | 1UL << ND_CMD_VENDOR;
2959         *nfit_mem = (struct nfit_mem) {
2960                 .adev = adev,
2961                 .family = NVDIMM_FAMILY_INTEL,
2962                 .dsm_mask = mask,
2963         };
2964
2965         nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2966         if (!nvdimm)
2967                 return -ENOMEM;
2968         *nvdimm = (struct nvdimm) {
2969                 .provider_data = nfit_mem,
2970                 .cmd_mask = mask,
2971                 .dev = {
2972                         .init_name = "test-dimm",
2973                 },
2974         };
2975
2976
2977         /* basic checkout of a typical 'get config size' command */
2978         cmd_size = sizeof(cmd.cfg_size);
2979         cmd.cfg_size = (struct nd_cmd_get_config_size) {
2980                 .status = 0,
2981                 .config_size = SZ_128K,
2982                 .max_xfer = SZ_4K,
2983         };
2984         rc = setup_result(cmd.buf, cmd_size);
2985         if (rc)
2986                 return rc;
2987         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2988                         cmd.buf, cmd_size, &cmd_rc);
2989
2990         if (rc < 0 || cmd_rc || cmd.cfg_size.status != 0
2991                         || cmd.cfg_size.config_size != SZ_128K
2992                         || cmd.cfg_size.max_xfer != SZ_4K) {
2993                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2994                                 __func__, __LINE__, rc, cmd_rc);
2995                 return -EIO;
2996         }
2997
2998
2999         /* test ars_status with zero output */
3000         cmd_size = offsetof(struct nd_cmd_ars_status, address);
3001         cmd.ars_stat = (struct nd_cmd_ars_status) {
3002                 .out_length = 0,
3003         };
3004         rc = setup_result(cmd.buf, cmd_size);
3005         if (rc)
3006                 return rc;
3007         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3008                         cmd.buf, cmd_size, &cmd_rc);
3009
3010         if (rc < 0 || cmd_rc) {
3011                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3012                                 __func__, __LINE__, rc, cmd_rc);
3013                 return -EIO;
3014         }
3015
3016
3017         /* test ars_cap with benign extended status */
3018         cmd_size = sizeof(cmd.ars_cap);
3019         cmd.ars_cap = (struct nd_cmd_ars_cap) {
3020                 .status = ND_ARS_PERSISTENT << 16,
3021         };
3022         offset = offsetof(struct nd_cmd_ars_cap, status);
3023         rc = setup_result(cmd.buf + offset, cmd_size - offset);
3024         if (rc)
3025                 return rc;
3026         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
3027                         cmd.buf, cmd_size, &cmd_rc);
3028
3029         if (rc < 0 || cmd_rc) {
3030                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3031                                 __func__, __LINE__, rc, cmd_rc);
3032                 return -EIO;
3033         }
3034
3035
3036         /* test ars_status with 'status' trimmed from 'out_length' */
3037         cmd_size = sizeof(cmd.ars_stat) + sizeof(struct nd_ars_record);
3038         cmd.ars_stat = (struct nd_cmd_ars_status) {
3039                 .out_length = cmd_size - 4,
3040         };
3041         record = &cmd.ars_stat.records[0];
3042         *record = (struct nd_ars_record) {
3043                 .length = test_val,
3044         };
3045         rc = setup_result(cmd.buf, cmd_size);
3046         if (rc)
3047                 return rc;
3048         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3049                         cmd.buf, cmd_size, &cmd_rc);
3050
3051         if (rc < 0 || cmd_rc || record->length != test_val) {
3052                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3053                                 __func__, __LINE__, rc, cmd_rc);
3054                 return -EIO;
3055         }
3056
3057
3058         /* test ars_status with 'Output (Size)' including 'status' */
3059         cmd_size = sizeof(cmd.ars_stat) + sizeof(struct nd_ars_record);
3060         cmd.ars_stat = (struct nd_cmd_ars_status) {
3061                 .out_length = cmd_size,
3062         };
3063         record = &cmd.ars_stat.records[0];
3064         *record = (struct nd_ars_record) {
3065                 .length = test_val,
3066         };
3067         rc = setup_result(cmd.buf, cmd_size);
3068         if (rc)
3069                 return rc;
3070         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3071                         cmd.buf, cmd_size, &cmd_rc);
3072
3073         if (rc < 0 || cmd_rc || record->length != test_val) {
3074                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3075                                 __func__, __LINE__, rc, cmd_rc);
3076                 return -EIO;
3077         }
3078
3079
3080         /* test extended status for get_config_size results in failure */
3081         cmd_size = sizeof(cmd.cfg_size);
3082         cmd.cfg_size = (struct nd_cmd_get_config_size) {
3083                 .status = 1 << 16,
3084         };
3085         rc = setup_result(cmd.buf, cmd_size);
3086         if (rc)
3087                 return rc;
3088         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
3089                         cmd.buf, cmd_size, &cmd_rc);
3090
3091         if (rc < 0 || cmd_rc >= 0) {
3092                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3093                                 __func__, __LINE__, rc, cmd_rc);
3094                 return -EIO;
3095         }
3096
3097         /* test clear error */
3098         cmd_size = sizeof(cmd.clear_err);
3099         cmd.clear_err = (struct nd_cmd_clear_error) {
3100                 .length = 512,
3101                 .cleared = 512,
3102         };
3103         rc = setup_result(cmd.buf, cmd_size);
3104         if (rc)
3105                 return rc;
3106         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
3107                         cmd.buf, cmd_size, &cmd_rc);
3108         if (rc < 0 || cmd_rc) {
3109                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3110                                 __func__, __LINE__, rc, cmd_rc);
3111                 return -EIO;
3112         }
3113
3114         /* test firmware activate bus info */
3115         cmd_size = sizeof(cmd.fwa_info);
3116         cmd = (struct nfit_ctl_test_cmd) {
3117                 .pkg = {
3118                         .nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO,
3119                         .nd_family = NVDIMM_BUS_FAMILY_INTEL,
3120                         .nd_size_out = cmd_size,
3121                         .nd_fw_size = cmd_size,
3122                 },
3123                 .fwa_info = {
3124                         .state = ND_INTEL_FWA_IDLE,
3125                         .capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
3126                                 | ND_INTEL_BUS_FWA_CAP_OSQUIESCE,
3127                         .activate_tmo = 1,
3128                         .cpu_quiesce_tmo = 1,
3129                         .io_quiesce_tmo = 1,
3130                         .max_quiesce_tmo = 1,
3131                 },
3132         };
3133         rc = setup_result(cmd.buf, cmd_size);
3134         if (rc)
3135                 return rc;
3136         rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CALL,
3137                         &cmd, sizeof(cmd.pkg) + cmd_size, &cmd_rc);
3138         if (rc < 0 || cmd_rc) {
3139                 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3140                                 __func__, __LINE__, rc, cmd_rc);
3141                 return -EIO;
3142         }
3143
3144         return 0;
3145 }
3146
3147 static int nfit_test_probe(struct platform_device *pdev)
3148 {
3149         struct nvdimm_bus_descriptor *nd_desc;
3150         struct acpi_nfit_desc *acpi_desc;
3151         struct device *dev = &pdev->dev;
3152         struct nfit_test *nfit_test;
3153         struct nfit_mem *nfit_mem;
3154         union acpi_object *obj;
3155         int rc;
3156
3157         if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
3158                 rc = nfit_ctl_test(&pdev->dev);
3159                 if (rc)
3160                         return rc;
3161         }
3162
3163         nfit_test = to_nfit_test(&pdev->dev);
3164
3165         /* common alloc */
3166         if (nfit_test->num_dcr) {
3167                 int num = nfit_test->num_dcr;
3168
3169                 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
3170                                 GFP_KERNEL);
3171                 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
3172                                 GFP_KERNEL);
3173                 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
3174                                 GFP_KERNEL);
3175                 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
3176                                 GFP_KERNEL);
3177                 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
3178                                 GFP_KERNEL);
3179                 nfit_test->label_dma = devm_kcalloc(dev, num,
3180                                 sizeof(dma_addr_t), GFP_KERNEL);
3181                 nfit_test->dcr = devm_kcalloc(dev, num,
3182                                 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
3183                 nfit_test->dcr_dma = devm_kcalloc(dev, num,
3184                                 sizeof(dma_addr_t), GFP_KERNEL);
3185                 nfit_test->smart = devm_kcalloc(dev, num,
3186                                 sizeof(struct nd_intel_smart), GFP_KERNEL);
3187                 nfit_test->smart_threshold = devm_kcalloc(dev, num,
3188                                 sizeof(struct nd_intel_smart_threshold),
3189                                 GFP_KERNEL);
3190                 nfit_test->fw = devm_kcalloc(dev, num,
3191                                 sizeof(struct nfit_test_fw), GFP_KERNEL);
3192                 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
3193                                 && nfit_test->label_dma && nfit_test->dcr
3194                                 && nfit_test->dcr_dma && nfit_test->flush
3195                                 && nfit_test->flush_dma
3196                                 && nfit_test->fw)
3197                         /* pass */;
3198                 else
3199                         return -ENOMEM;
3200         }
3201
3202         if (nfit_test->num_pm) {
3203                 int num = nfit_test->num_pm;
3204
3205                 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
3206                                 GFP_KERNEL);
3207                 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
3208                                 sizeof(dma_addr_t), GFP_KERNEL);
3209                 if (nfit_test->spa_set && nfit_test->spa_set_dma)
3210                         /* pass */;
3211                 else
3212                         return -ENOMEM;
3213         }
3214
3215         /* per-nfit specific alloc */
3216         if (nfit_test->alloc(nfit_test))
3217                 return -ENOMEM;
3218
3219         nfit_test->setup(nfit_test);
3220         acpi_desc = &nfit_test->acpi_desc;
3221         acpi_nfit_desc_init(acpi_desc, &pdev->dev);
3222         acpi_desc->blk_do_io = nfit_test_blk_do_io;
3223         nd_desc = &acpi_desc->nd_desc;
3224         nd_desc->provider_name = NULL;
3225         nd_desc->module = THIS_MODULE;
3226         nd_desc->ndctl = nfit_test_ctl;
3227
3228         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
3229                         nfit_test->nfit_filled);
3230         if (rc)
3231                 return rc;
3232
3233         rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
3234         if (rc)
3235                 return rc;
3236
3237         if (nfit_test->setup != nfit_test0_setup)
3238                 return 0;
3239
3240         nfit_test->setup_hotplug = 1;
3241         nfit_test->setup(nfit_test);
3242
3243         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3244         if (!obj)
3245                 return -ENOMEM;
3246         obj->type = ACPI_TYPE_BUFFER;
3247         obj->buffer.length = nfit_test->nfit_size;
3248         obj->buffer.pointer = nfit_test->nfit_buf;
3249         *(nfit_test->_fit) = obj;
3250         __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
3251
3252         /* associate dimm devices with nfit_mem data for notification testing */
3253         mutex_lock(&acpi_desc->init_mutex);
3254         list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
3255                 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
3256                 int i;
3257
3258                 for (i = 0; i < ARRAY_SIZE(handle); i++)
3259                         if (nfit_handle == handle[i])
3260                                 dev_set_drvdata(nfit_test->dimm_dev[i],
3261                                                 nfit_mem);
3262         }
3263         mutex_unlock(&acpi_desc->init_mutex);
3264
3265         return 0;
3266 }
3267
3268 static int nfit_test_remove(struct platform_device *pdev)
3269 {
3270         return 0;
3271 }
3272
3273 static void nfit_test_release(struct device *dev)
3274 {
3275         struct nfit_test *nfit_test = to_nfit_test(dev);
3276
3277         kfree(nfit_test);
3278 }
3279
3280 static const struct platform_device_id nfit_test_id[] = {
3281         { KBUILD_MODNAME },
3282         { },
3283 };
3284
3285 static struct platform_driver nfit_test_driver = {
3286         .probe = nfit_test_probe,
3287         .remove = nfit_test_remove,
3288         .driver = {
3289                 .name = KBUILD_MODNAME,
3290         },
3291         .id_table = nfit_test_id,
3292 };
3293
3294 static __init int nfit_test_init(void)
3295 {
3296         int rc, i;
3297
3298         pmem_test();
3299         libnvdimm_test();
3300         acpi_nfit_test();
3301         device_dax_test();
3302         dax_pmem_test();
3303         dax_pmem_core_test();
3304 #ifdef CONFIG_DEV_DAX_PMEM_COMPAT
3305         dax_pmem_compat_test();
3306 #endif
3307
3308         nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
3309
3310         nfit_wq = create_singlethread_workqueue("nfit");
3311         if (!nfit_wq)
3312                 return -ENOMEM;
3313
3314         nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
3315         if (IS_ERR(nfit_test_dimm)) {
3316                 rc = PTR_ERR(nfit_test_dimm);
3317                 goto err_register;
3318         }
3319
3320         nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE);
3321         if (!nfit_pool) {
3322                 rc = -ENOMEM;
3323                 goto err_register;
3324         }
3325
3326         if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) {
3327                 rc = -ENOMEM;
3328                 goto err_register;
3329         }
3330
3331         for (i = 0; i < NUM_NFITS; i++) {
3332                 struct nfit_test *nfit_test;
3333                 struct platform_device *pdev;
3334
3335                 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
3336                 if (!nfit_test) {
3337                         rc = -ENOMEM;
3338                         goto err_register;
3339                 }
3340                 INIT_LIST_HEAD(&nfit_test->resources);
3341                 badrange_init(&nfit_test->badrange);
3342                 switch (i) {
3343                 case 0:
3344                         nfit_test->num_pm = NUM_PM;
3345                         nfit_test->dcr_idx = 0;
3346                         nfit_test->num_dcr = NUM_DCR;
3347                         nfit_test->alloc = nfit_test0_alloc;
3348                         nfit_test->setup = nfit_test0_setup;
3349                         break;
3350                 case 1:
3351                         nfit_test->num_pm = 2;
3352                         nfit_test->dcr_idx = NUM_DCR;
3353                         nfit_test->num_dcr = 2;
3354                         nfit_test->alloc = nfit_test1_alloc;
3355                         nfit_test->setup = nfit_test1_setup;
3356                         break;
3357                 default:
3358                         rc = -EINVAL;
3359                         goto err_register;
3360                 }
3361                 pdev = &nfit_test->pdev;
3362                 pdev->name = KBUILD_MODNAME;
3363                 pdev->id = i;
3364                 pdev->dev.release = nfit_test_release;
3365                 rc = platform_device_register(pdev);
3366                 if (rc) {
3367                         put_device(&pdev->dev);
3368                         goto err_register;
3369                 }
3370                 get_device(&pdev->dev);
3371
3372                 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3373                 if (rc)
3374                         goto err_register;
3375
3376                 instances[i] = nfit_test;
3377                 INIT_WORK(&nfit_test->work, uc_error_notify);
3378         }
3379
3380         rc = platform_driver_register(&nfit_test_driver);
3381         if (rc)
3382                 goto err_register;
3383         return 0;
3384
3385  err_register:
3386         if (nfit_pool)
3387                 gen_pool_destroy(nfit_pool);
3388
3389         destroy_workqueue(nfit_wq);
3390         for (i = 0; i < NUM_NFITS; i++)
3391                 if (instances[i])
3392                         platform_device_unregister(&instances[i]->pdev);
3393         nfit_test_teardown();
3394         for (i = 0; i < NUM_NFITS; i++)
3395                 if (instances[i])
3396                         put_device(&instances[i]->pdev.dev);
3397
3398         return rc;
3399 }
3400
3401 static __exit void nfit_test_exit(void)
3402 {
3403         int i;
3404
3405         flush_workqueue(nfit_wq);
3406         destroy_workqueue(nfit_wq);
3407         for (i = 0; i < NUM_NFITS; i++)
3408                 platform_device_unregister(&instances[i]->pdev);
3409         platform_driver_unregister(&nfit_test_driver);
3410         nfit_test_teardown();
3411
3412         gen_pool_destroy(nfit_pool);
3413
3414         for (i = 0; i < NUM_NFITS; i++)
3415                 put_device(&instances[i]->pdev.dev);
3416         class_destroy(nfit_test_dimm);
3417 }
3418
3419 module_init(nfit_test_init);
3420 module_exit(nfit_test_exit);
3421 MODULE_LICENSE("GPL v2");
3422 MODULE_AUTHOR("Intel Corporation");