1 // SPDX-License-Identifier: GPL-2.0-only
3 * turbostat -- show CPU frequency and C-state residency
4 * on modern Intel and AMD processors.
6 * Copyright (c) 2013 Intel Corporation.
7 * Len Brown <len.brown@intel.com>
12 #include INTEL_FAMILY_HEADER
17 #include <sys/types.h>
20 #include <sys/select.h>
21 #include <sys/resource.h>
33 #include <sys/capability.h>
36 #include <linux/perf_event.h>
37 #include <asm/unistd.h>
40 char *proc_stat = "/proc/stat";
43 int *fd_instr_count_percpu;
44 struct timeval interval_tv = { 5, 0 };
45 struct timespec interval_ts = { 5, 0 };
47 /* Save original CPU model */
48 unsigned int model_orig;
50 unsigned int num_iterations;
54 unsigned int sums_need_wide_columns;
55 unsigned int rapl_joules;
56 unsigned int summary_only;
57 unsigned int list_header_only;
58 unsigned int dump_only;
59 unsigned int do_snb_cstates;
60 unsigned int do_knl_cstates;
61 unsigned int do_slm_cstates;
62 unsigned int use_c1_residency_msr;
63 unsigned int has_aperf;
65 unsigned int do_irtl_snb;
66 unsigned int do_irtl_hsw;
67 unsigned int units = 1000000; /* MHz etc */
68 unsigned int genuine_intel;
69 unsigned int authentic_amd;
70 unsigned int hygon_genuine;
71 unsigned int max_level, max_extended_level;
72 unsigned int has_invariant_tsc;
73 unsigned int do_nhm_platform_info;
74 unsigned int no_MSR_MISC_PWR_MGMT;
75 unsigned int aperf_mperf_multiplier = 1;
78 unsigned int has_base_hz;
79 double tsc_tweak = 1.0;
80 unsigned int show_pkg_only;
81 unsigned int show_core_only;
82 char *output_buffer, *outp;
87 unsigned long long gfx_cur_rc6_ms;
88 unsigned long long cpuidle_cur_cpu_lpi_us;
89 unsigned long long cpuidle_cur_sys_lpi_us;
90 unsigned int gfx_cur_mhz;
91 unsigned int gfx_act_mhz;
93 unsigned int tj_max_override;
95 double rapl_power_units, rapl_time_units;
96 double rapl_dram_energy_units, rapl_energy_units;
97 double rapl_joule_counter_range;
98 unsigned int do_core_perf_limit_reasons;
99 unsigned int has_automatic_cstate_conversion;
100 unsigned int dis_cstate_prewake;
101 unsigned int do_gfx_perf_limit_reasons;
102 unsigned int do_ring_perf_limit_reasons;
103 unsigned int crystal_hz;
104 unsigned long long tsc_hz;
106 double discover_bclk(unsigned int family, unsigned int model);
107 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
108 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
109 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
110 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
111 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
112 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
113 unsigned int has_misc_feature_control;
114 unsigned int first_counter_read = 1;
117 #define RAPL_PKG (1 << 0)
118 /* 0x610 MSR_PKG_POWER_LIMIT */
119 /* 0x611 MSR_PKG_ENERGY_STATUS */
120 #define RAPL_PKG_PERF_STATUS (1 << 1)
121 /* 0x613 MSR_PKG_PERF_STATUS */
122 #define RAPL_PKG_POWER_INFO (1 << 2)
123 /* 0x614 MSR_PKG_POWER_INFO */
125 #define RAPL_DRAM (1 << 3)
126 /* 0x618 MSR_DRAM_POWER_LIMIT */
127 /* 0x619 MSR_DRAM_ENERGY_STATUS */
128 #define RAPL_DRAM_PERF_STATUS (1 << 4)
129 /* 0x61b MSR_DRAM_PERF_STATUS */
130 #define RAPL_DRAM_POWER_INFO (1 << 5)
131 /* 0x61c MSR_DRAM_POWER_INFO */
133 #define RAPL_CORES_POWER_LIMIT (1 << 6)
134 /* 0x638 MSR_PP0_POWER_LIMIT */
135 #define RAPL_CORE_POLICY (1 << 7)
136 /* 0x63a MSR_PP0_POLICY */
138 #define RAPL_GFX (1 << 8)
139 /* 0x640 MSR_PP1_POWER_LIMIT */
140 /* 0x641 MSR_PP1_ENERGY_STATUS */
141 /* 0x642 MSR_PP1_POLICY */
143 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
144 /* 0x639 MSR_PP0_ENERGY_STATUS */
145 #define RAPL_PER_CORE_ENERGY (1 << 10)
146 /* Indicates cores energy collection is per-core,
147 * not per-package. */
148 #define RAPL_AMD_F17H (1 << 11)
149 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
150 /* 0xc001029a MSR_CORE_ENERGY_STAT */
151 /* 0xc001029b MSR_PKG_ENERGY_STAT */
152 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
153 #define TJMAX_DEFAULT 100
155 /* MSRs that are not yet in the kernel-provided header. */
156 #define MSR_RAPL_PWR_UNIT 0xc0010299
157 #define MSR_CORE_ENERGY_STAT 0xc001029a
158 #define MSR_PKG_ENERGY_STAT 0xc001029b
160 #define MAX(a, b) ((a) > (b) ? (a) : (b))
163 * buffer size used by sscanf() for added column names
164 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
166 #define NAME_BYTES 20
167 #define PATH_BYTES 128
172 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
173 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
174 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
175 #define MAX_ADDED_COUNTERS 8
176 #define MAX_ADDED_THREAD_COUNTERS 24
177 #define BITMASK_SIZE 32
180 struct timeval tv_begin;
181 struct timeval tv_end;
182 struct timeval tv_delta;
183 unsigned long long tsc;
184 unsigned long long aperf;
185 unsigned long long mperf;
186 unsigned long long c1;
187 unsigned long long instr_count;
188 unsigned long long irq_count;
189 unsigned int smi_count;
191 unsigned int apic_id;
192 unsigned int x2apic_id;
195 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
196 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
197 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
198 } *thread_even, *thread_odd;
201 unsigned long long c3;
202 unsigned long long c6;
203 unsigned long long c7;
204 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
205 unsigned int core_temp_c;
206 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
207 unsigned int core_id;
208 unsigned long long counter[MAX_ADDED_COUNTERS];
209 } *core_even, *core_odd;
212 unsigned long long pc2;
213 unsigned long long pc3;
214 unsigned long long pc6;
215 unsigned long long pc7;
216 unsigned long long pc8;
217 unsigned long long pc9;
218 unsigned long long pc10;
219 unsigned long long cpu_lpi;
220 unsigned long long sys_lpi;
221 unsigned long long pkg_wtd_core_c0;
222 unsigned long long pkg_any_core_c0;
223 unsigned long long pkg_any_gfxe_c0;
224 unsigned long long pkg_both_core_gfxe_c0;
225 long long gfx_rc6_ms;
226 unsigned int gfx_mhz;
227 unsigned int gfx_act_mhz;
228 unsigned int package_id;
229 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
230 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
231 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
232 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
233 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
234 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
235 unsigned int pkg_temp_c;
236 unsigned long long counter[MAX_ADDED_COUNTERS];
237 } *package_even, *package_odd;
239 #define ODD_COUNTERS thread_odd, core_odd, package_odd
240 #define EVEN_COUNTERS thread_even, core_even, package_even
242 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
245 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
246 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
247 ((core_no) * topo.threads_per_core) + \
250 #define GET_CORE(core_base, core_no, node_no, pkg_no) \
252 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
253 ((node_no) * topo.cores_per_node) + \
256 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
258 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
259 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
260 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
263 unsigned int msr_num;
264 char name[NAME_BYTES];
265 char path[PATH_BYTES];
267 enum counter_type type;
268 enum counter_format format;
269 struct msr_counter *next;
271 #define FLAGS_HIDE (1 << 0)
272 #define FLAGS_SHOW (1 << 1)
273 #define SYSFS_PERCPU (1 << 1)
277 * The accumulated sum of MSR is defined as a monotonic
278 * increasing MSR, it will be accumulated periodically,
279 * despite its register's bit width.
291 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
293 struct msr_sum_array {
294 /* get_msr_sum() = sum + (get_msr() - last) */
296 /*The accumulated MSR value is updated by the timer */
297 unsigned long long sum;
298 /*The MSR footprint recorded in last timer */
299 unsigned long long last;
300 } entries[IDX_COUNT];
303 /* The percpu MSR sum array.*/
304 struct msr_sum_array *per_cpu_msr_sum;
306 off_t idx_to_offset(int idx)
312 if (do_rapl & RAPL_AMD_F17H)
313 offset = MSR_PKG_ENERGY_STAT;
315 offset = MSR_PKG_ENERGY_STATUS;
317 case IDX_DRAM_ENERGY:
318 offset = MSR_DRAM_ENERGY_STATUS;
321 offset = MSR_PP0_ENERGY_STATUS;
324 offset = MSR_PP1_ENERGY_STATUS;
327 offset = MSR_PKG_PERF_STATUS;
330 offset = MSR_DRAM_PERF_STATUS;
338 int offset_to_idx(off_t offset)
343 case MSR_PKG_ENERGY_STATUS:
344 case MSR_PKG_ENERGY_STAT:
345 idx = IDX_PKG_ENERGY;
347 case MSR_DRAM_ENERGY_STATUS:
348 idx = IDX_DRAM_ENERGY;
350 case MSR_PP0_ENERGY_STATUS:
351 idx = IDX_PP0_ENERGY;
353 case MSR_PP1_ENERGY_STATUS:
354 idx = IDX_PP1_ENERGY;
356 case MSR_PKG_PERF_STATUS:
359 case MSR_DRAM_PERF_STATUS:
368 int idx_valid(int idx)
372 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
373 case IDX_DRAM_ENERGY:
374 return do_rapl & RAPL_DRAM;
376 return do_rapl & RAPL_CORES_ENERGY_STATUS;
378 return do_rapl & RAPL_GFX;
380 return do_rapl & RAPL_PKG_PERF_STATUS;
382 return do_rapl & RAPL_DRAM_PERF_STATUS;
388 struct sys_counters {
389 unsigned int added_thread_counters;
390 unsigned int added_core_counters;
391 unsigned int added_package_counters;
392 struct msr_counter *tp;
393 struct msr_counter *cp;
394 struct msr_counter *pp;
397 struct system_summary {
398 struct thread_data threads;
399 struct core_data cores;
400 struct pkg_data packages;
403 struct cpu_topology {
404 int physical_package_id;
407 int physical_node_id;
408 int logical_node_id; /* 0-based count within the package */
409 int physical_core_id;
411 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
423 int threads_per_core;
426 struct timeval tv_even, tv_odd, tv_delta;
428 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
429 int *irqs_per_cpu; /* indexed by cpu_num */
431 void setup_all_buffers(void);
434 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
435 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
437 int cpu_is_not_present(int cpu)
439 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
443 * run func(thread, core, package) in topology order
444 * skip non-present cpus
447 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
448 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
450 int retval, pkg_no, core_no, thread_no, node_no;
452 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
453 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
454 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
455 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
456 struct thread_data *t;
460 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
462 if (cpu_is_not_present(t->cpu_id))
465 c = GET_CORE(core_base, core_no, node_no, pkg_no);
466 p = GET_PKG(pkg_base, pkg_no);
468 retval = func(t, c, p);
478 int cpu_migrate(int cpu)
480 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
481 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
482 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
488 int get_msr_fd(int cpu)
498 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
499 fd = open(pathname, O_RDONLY);
501 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
508 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
510 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
513 static int perf_instr_count_open(int cpu_num)
515 struct perf_event_attr pea;
518 memset(&pea, 0, sizeof(struct perf_event_attr));
519 pea.type = PERF_TYPE_HARDWARE;
520 pea.size = sizeof(struct perf_event_attr);
521 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
523 /* counter for cpu_num, including user + kernel and all processes */
524 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
526 err(-1, "cpu%d: perf instruction counter\n", cpu_num);
531 int get_instr_count_fd(int cpu)
533 if (fd_instr_count_percpu[cpu])
534 return fd_instr_count_percpu[cpu];
536 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
538 return fd_instr_count_percpu[cpu];
541 int get_msr(int cpu, off_t offset, unsigned long long *msr)
545 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
547 if (retval != sizeof *msr)
548 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
554 * This list matches the column headers, except
555 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
556 * 2. Core and CPU are moved to the end, we can't have strings that contain them
557 * matching on them for --show and --hide.
559 struct msr_counter bic[] = {
561 { 0x0, "Time_Of_Day_Seconds" },
569 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL },
615 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
616 #define BIC_USEC (1ULL << 0)
617 #define BIC_TOD (1ULL << 1)
618 #define BIC_Package (1ULL << 2)
619 #define BIC_Node (1ULL << 3)
620 #define BIC_Avg_MHz (1ULL << 4)
621 #define BIC_Busy (1ULL << 5)
622 #define BIC_Bzy_MHz (1ULL << 6)
623 #define BIC_TSC_MHz (1ULL << 7)
624 #define BIC_IRQ (1ULL << 8)
625 #define BIC_SMI (1ULL << 9)
626 #define BIC_sysfs (1ULL << 10)
627 #define BIC_CPU_c1 (1ULL << 11)
628 #define BIC_CPU_c3 (1ULL << 12)
629 #define BIC_CPU_c6 (1ULL << 13)
630 #define BIC_CPU_c7 (1ULL << 14)
631 #define BIC_ThreadC (1ULL << 15)
632 #define BIC_CoreTmp (1ULL << 16)
633 #define BIC_CoreCnt (1ULL << 17)
634 #define BIC_PkgTmp (1ULL << 18)
635 #define BIC_GFX_rc6 (1ULL << 19)
636 #define BIC_GFXMHz (1ULL << 20)
637 #define BIC_Pkgpc2 (1ULL << 21)
638 #define BIC_Pkgpc3 (1ULL << 22)
639 #define BIC_Pkgpc6 (1ULL << 23)
640 #define BIC_Pkgpc7 (1ULL << 24)
641 #define BIC_Pkgpc8 (1ULL << 25)
642 #define BIC_Pkgpc9 (1ULL << 26)
643 #define BIC_Pkgpc10 (1ULL << 27)
644 #define BIC_CPU_LPI (1ULL << 28)
645 #define BIC_SYS_LPI (1ULL << 29)
646 #define BIC_PkgWatt (1ULL << 30)
647 #define BIC_CorWatt (1ULL << 31)
648 #define BIC_GFXWatt (1ULL << 32)
649 #define BIC_PkgCnt (1ULL << 33)
650 #define BIC_RAMWatt (1ULL << 34)
651 #define BIC_PKG__ (1ULL << 35)
652 #define BIC_RAM__ (1ULL << 36)
653 #define BIC_Pkg_J (1ULL << 37)
654 #define BIC_Cor_J (1ULL << 38)
655 #define BIC_GFX_J (1ULL << 39)
656 #define BIC_RAM_J (1ULL << 40)
657 #define BIC_Mod_c6 (1ULL << 41)
658 #define BIC_Totl_c0 (1ULL << 42)
659 #define BIC_Any_c0 (1ULL << 43)
660 #define BIC_GFX_c0 (1ULL << 44)
661 #define BIC_CPUGFX (1ULL << 45)
662 #define BIC_Core (1ULL << 46)
663 #define BIC_CPU (1ULL << 47)
664 #define BIC_APIC (1ULL << 48)
665 #define BIC_X2APIC (1ULL << 49)
666 #define BIC_Die (1ULL << 50)
667 #define BIC_GFXACTMHz (1ULL << 51)
668 #define BIC_IPC (1ULL << 52)
670 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
672 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
673 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
675 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
676 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
677 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
678 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
679 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
680 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
682 #define MAX_DEFERRED 16
683 char *deferred_skip_names[MAX_DEFERRED];
684 int deferred_skip_index;
687 * HIDE_LIST - hide this list of counters, show the rest [default]
688 * SHOW_LIST - show this list of counters, hide the rest
690 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
695 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
697 "Turbostat forks the specified COMMAND and prints statistics\n"
698 "when COMMAND completes.\n"
699 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
700 "to print statistics, until interrupted.\n"
701 " -a, --add add a counter\n"
702 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
703 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
704 " {core | package | j,k,l..m,n-p }\n"
705 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
706 " -D, --Dump displays the raw counter values\n"
707 " -e, --enable [all | column]\n"
708 " shows all or the specified disabled column\n"
709 " -H, --hide [column|column,column,...]\n"
710 " hide the specified column(s)\n"
711 " -i, --interval sec.subsec\n"
712 " Override default 5-second measurement interval\n"
713 " -J, --Joules displays energy in Joules instead of Watts\n"
714 " -l, --list list column headers only\n"
715 " -n, --num_iterations num\n"
716 " number of the measurement iterations\n"
718 " create or truncate \"file\" for all output\n"
719 " -q, --quiet skip decoding system configuration header\n"
720 " -s, --show [column|column,column,...]\n"
721 " show only the specified column(s)\n"
723 " limits output to 1-line system summary per interval\n"
724 " -T, --TCC temperature\n"
725 " sets the Thermal Control Circuit temperature in\n"
727 " -h, --help print this help message\n"
728 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
733 * for all the strings in comma separate name_list,
734 * set the approprate bit in return value.
736 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
739 unsigned long long retval = 0;
744 comma = strchr(name_list, ',');
749 if (!strcmp(name_list, "all"))
752 for (i = 0; i < MAX_BIC; ++i) {
753 if (!strcmp(name_list, bic[i].name)) {
754 retval |= (1ULL << i);
759 if (mode == SHOW_LIST) {
760 fprintf(stderr, "Invalid counter name: %s\n", name_list);
763 deferred_skip_names[deferred_skip_index++] = name_list;
765 fprintf(stderr, "deferred \"%s\"\n", name_list);
766 if (deferred_skip_index >= MAX_DEFERRED) {
767 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
768 MAX_DEFERRED, name_list);
782 void print_header(char *delim)
784 struct msr_counter *mp;
787 if (DO_BIC(BIC_USEC))
788 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
790 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
791 if (DO_BIC(BIC_Package))
792 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
794 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
795 if (DO_BIC(BIC_Node))
796 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
797 if (DO_BIC(BIC_Core))
798 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
800 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
801 if (DO_BIC(BIC_APIC))
802 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
803 if (DO_BIC(BIC_X2APIC))
804 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
805 if (DO_BIC(BIC_Avg_MHz))
806 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
807 if (DO_BIC(BIC_Busy))
808 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
809 if (DO_BIC(BIC_Bzy_MHz))
810 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
811 if (DO_BIC(BIC_TSC_MHz))
812 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
815 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
817 if (DO_BIC(BIC_IRQ)) {
818 if (sums_need_wide_columns)
819 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
821 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
825 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
827 for (mp = sys.tp; mp; mp = mp->next) {
829 if (mp->format == FORMAT_RAW) {
831 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
833 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
835 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
836 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
838 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
842 if (DO_BIC(BIC_CPU_c1))
843 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
844 if (DO_BIC(BIC_CPU_c3))
845 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
846 if (DO_BIC(BIC_CPU_c6))
847 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
848 if (DO_BIC(BIC_CPU_c7))
849 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
851 if (DO_BIC(BIC_Mod_c6))
852 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
854 if (DO_BIC(BIC_CoreTmp))
855 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
857 if (do_rapl && !rapl_joules) {
858 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
859 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
860 } else if (do_rapl && rapl_joules) {
861 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
862 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
865 for (mp = sys.cp; mp; mp = mp->next) {
866 if (mp->format == FORMAT_RAW) {
868 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
870 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
872 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
873 outp += sprintf(outp, "%s%8s", delim, mp->name);
875 outp += sprintf(outp, "%s%s", delim, mp->name);
879 if (DO_BIC(BIC_PkgTmp))
880 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
882 if (DO_BIC(BIC_GFX_rc6))
883 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
885 if (DO_BIC(BIC_GFXMHz))
886 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
888 if (DO_BIC(BIC_GFXACTMHz))
889 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
891 if (DO_BIC(BIC_Totl_c0))
892 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
893 if (DO_BIC(BIC_Any_c0))
894 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
895 if (DO_BIC(BIC_GFX_c0))
896 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
897 if (DO_BIC(BIC_CPUGFX))
898 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
900 if (DO_BIC(BIC_Pkgpc2))
901 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
902 if (DO_BIC(BIC_Pkgpc3))
903 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
904 if (DO_BIC(BIC_Pkgpc6))
905 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
906 if (DO_BIC(BIC_Pkgpc7))
907 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
908 if (DO_BIC(BIC_Pkgpc8))
909 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
910 if (DO_BIC(BIC_Pkgpc9))
911 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
912 if (DO_BIC(BIC_Pkgpc10))
913 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
914 if (DO_BIC(BIC_CPU_LPI))
915 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
916 if (DO_BIC(BIC_SYS_LPI))
917 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
919 if (do_rapl && !rapl_joules) {
920 if (DO_BIC(BIC_PkgWatt))
921 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
922 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
923 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
924 if (DO_BIC(BIC_GFXWatt))
925 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
926 if (DO_BIC(BIC_RAMWatt))
927 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
928 if (DO_BIC(BIC_PKG__))
929 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
930 if (DO_BIC(BIC_RAM__))
931 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
932 } else if (do_rapl && rapl_joules) {
933 if (DO_BIC(BIC_Pkg_J))
934 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
935 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
936 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
937 if (DO_BIC(BIC_GFX_J))
938 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
939 if (DO_BIC(BIC_RAM_J))
940 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
941 if (DO_BIC(BIC_PKG__))
942 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
943 if (DO_BIC(BIC_RAM__))
944 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
946 for (mp = sys.pp; mp; mp = mp->next) {
947 if (mp->format == FORMAT_RAW) {
949 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
951 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
953 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
954 outp += sprintf(outp, "%s%8s", delim, mp->name);
956 outp += sprintf(outp, "%s%s", delim, mp->name);
960 outp += sprintf(outp, "\n");
963 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
966 struct msr_counter *mp;
968 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
971 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
972 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
973 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
974 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
975 outp += sprintf(outp, "c1: %016llX\n", t->c1);
978 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
981 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
983 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
985 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
986 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
991 outp += sprintf(outp, "core: %d\n", c->core_id);
992 outp += sprintf(outp, "c3: %016llX\n", c->c3);
993 outp += sprintf(outp, "c6: %016llX\n", c->c6);
994 outp += sprintf(outp, "c7: %016llX\n", c->c7);
995 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
996 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
998 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
999 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
1001 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
1005 outp += sprintf(outp, "package: %d\n", p->package_id);
1007 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1008 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1009 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1010 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1012 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
1013 if (DO_BIC(BIC_Pkgpc3))
1014 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
1015 if (DO_BIC(BIC_Pkgpc6))
1016 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
1017 if (DO_BIC(BIC_Pkgpc7))
1018 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
1019 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1020 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1021 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
1022 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1023 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
1024 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1025 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1026 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1027 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1028 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1029 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
1030 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
1032 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1033 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
1037 outp += sprintf(outp, "\n");
1043 * column formatting convention & formats
1045 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1047 double interval_float, tsc;
1050 struct msr_counter *mp;
1054 /* if showing only 1st thread in core and this isn't one, bail out */
1055 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1058 /* if showing only 1st thread in pkg and this isn't one, bail out */
1059 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1062 /*if not summary line and --cpu is used */
1063 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1066 if (DO_BIC(BIC_USEC)) {
1067 /* on each row, print how many usec each timestamp took to gather */
1070 timersub(&t->tv_end, &t->tv_begin, &tv);
1071 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1074 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1075 if (DO_BIC(BIC_TOD))
1076 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1078 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
1080 tsc = t->tsc * tsc_tweak;
1082 /* topo columns, print blanks on 1st (average) line */
1083 if (t == &average.threads) {
1084 if (DO_BIC(BIC_Package))
1085 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1086 if (DO_BIC(BIC_Die))
1087 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1088 if (DO_BIC(BIC_Node))
1089 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1090 if (DO_BIC(BIC_Core))
1091 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1092 if (DO_BIC(BIC_CPU))
1093 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1094 if (DO_BIC(BIC_APIC))
1095 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1096 if (DO_BIC(BIC_X2APIC))
1097 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1099 if (DO_BIC(BIC_Package)) {
1101 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
1103 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1105 if (DO_BIC(BIC_Die)) {
1107 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1109 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1111 if (DO_BIC(BIC_Node)) {
1113 outp += sprintf(outp, "%s%d",
1114 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
1116 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1118 if (DO_BIC(BIC_Core)) {
1120 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
1122 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1124 if (DO_BIC(BIC_CPU))
1125 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
1126 if (DO_BIC(BIC_APIC))
1127 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1128 if (DO_BIC(BIC_X2APIC))
1129 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
1132 if (DO_BIC(BIC_Avg_MHz))
1133 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
1135 if (DO_BIC(BIC_Busy))
1136 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
1138 if (DO_BIC(BIC_Bzy_MHz)) {
1141 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
1143 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1144 tsc / units * t->aperf / t->mperf / interval_float);
1147 if (DO_BIC(BIC_TSC_MHz))
1148 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
1150 if (DO_BIC(BIC_IPC))
1151 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1154 if (DO_BIC(BIC_IRQ)) {
1155 if (sums_need_wide_columns)
1156 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
1158 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
1162 if (DO_BIC(BIC_SMI))
1163 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1165 /* Added counters */
1166 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1167 if (mp->format == FORMAT_RAW) {
1168 if (mp->width == 32)
1170 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
1172 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
1173 } else if (mp->format == FORMAT_DELTA) {
1174 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1175 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
1177 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
1178 } else if (mp->format == FORMAT_PERCENT) {
1179 if (mp->type == COUNTER_USEC)
1181 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1182 t->counter[i] / interval_float / 10000);
1184 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
1189 if (DO_BIC(BIC_CPU_c1))
1190 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
1192 /* print per-core data only for 1st thread in core */
1193 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1196 if (DO_BIC(BIC_CPU_c3))
1197 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
1198 if (DO_BIC(BIC_CPU_c6))
1199 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
1200 if (DO_BIC(BIC_CPU_c7))
1201 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
1204 if (DO_BIC(BIC_Mod_c6))
1205 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
1207 if (DO_BIC(BIC_CoreTmp))
1208 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
1210 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1211 if (mp->format == FORMAT_RAW) {
1212 if (mp->width == 32)
1214 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
1216 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
1217 } else if (mp->format == FORMAT_DELTA) {
1218 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1219 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
1221 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
1222 } else if (mp->format == FORMAT_PERCENT) {
1223 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
1229 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1231 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
1232 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1233 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1235 /* print per-package data only for 1st core in package */
1236 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1240 if (DO_BIC(BIC_PkgTmp))
1241 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
1244 if (DO_BIC(BIC_GFX_rc6)) {
1245 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
1246 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
1248 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1249 p->gfx_rc6_ms / 10.0 / interval_float);
1254 if (DO_BIC(BIC_GFXMHz))
1255 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
1258 if (DO_BIC(BIC_GFXACTMHz))
1259 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1261 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
1262 if (DO_BIC(BIC_Totl_c0))
1263 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
1264 if (DO_BIC(BIC_Any_c0))
1265 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
1266 if (DO_BIC(BIC_GFX_c0))
1267 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
1268 if (DO_BIC(BIC_CPUGFX))
1269 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
1271 if (DO_BIC(BIC_Pkgpc2))
1272 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
1273 if (DO_BIC(BIC_Pkgpc3))
1274 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
1275 if (DO_BIC(BIC_Pkgpc6))
1276 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
1277 if (DO_BIC(BIC_Pkgpc7))
1278 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
1279 if (DO_BIC(BIC_Pkgpc8))
1280 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
1281 if (DO_BIC(BIC_Pkgpc9))
1282 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
1283 if (DO_BIC(BIC_Pkgpc10))
1284 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
1286 if (DO_BIC(BIC_CPU_LPI))
1288 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
1289 if (DO_BIC(BIC_SYS_LPI))
1291 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
1293 if (DO_BIC(BIC_PkgWatt))
1295 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
1296 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1298 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
1299 if (DO_BIC(BIC_GFXWatt))
1301 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
1302 if (DO_BIC(BIC_RAMWatt))
1304 sprintf(outp, fmt8, (printed++ ? delim : ""),
1305 p->energy_dram * rapl_dram_energy_units / interval_float);
1306 if (DO_BIC(BIC_Pkg_J))
1307 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
1308 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1309 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
1310 if (DO_BIC(BIC_GFX_J))
1311 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
1312 if (DO_BIC(BIC_RAM_J))
1313 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
1314 if (DO_BIC(BIC_PKG__))
1316 sprintf(outp, fmt8, (printed++ ? delim : ""),
1317 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
1318 if (DO_BIC(BIC_RAM__))
1320 sprintf(outp, fmt8, (printed++ ? delim : ""),
1321 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
1323 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1324 if (mp->format == FORMAT_RAW) {
1325 if (mp->width == 32)
1327 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
1329 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
1330 } else if (mp->format == FORMAT_DELTA) {
1331 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1332 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
1334 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
1335 } else if (mp->format == FORMAT_PERCENT) {
1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
1341 if (*(outp - 1) != '\n')
1342 outp += sprintf(outp, "\n");
1347 void flush_output_stdout(void)
1356 fputs(output_buffer, filep);
1359 outp = output_buffer;
1362 void flush_output_stderr(void)
1364 fputs(output_buffer, outf);
1366 outp = output_buffer;
1369 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1373 if (!printed || !summary_only)
1376 format_counters(&average.threads, &average.cores, &average.packages);
1383 for_all_cpus(format_counters, t, c, p);
1386 #define DELTA_WRAP32(new, old) \
1387 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
1389 int delta_package(struct pkg_data *new, struct pkg_data *old)
1392 struct msr_counter *mp;
1394 if (DO_BIC(BIC_Totl_c0))
1395 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
1396 if (DO_BIC(BIC_Any_c0))
1397 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
1398 if (DO_BIC(BIC_GFX_c0))
1399 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
1400 if (DO_BIC(BIC_CPUGFX))
1401 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
1403 old->pc2 = new->pc2 - old->pc2;
1404 if (DO_BIC(BIC_Pkgpc3))
1405 old->pc3 = new->pc3 - old->pc3;
1406 if (DO_BIC(BIC_Pkgpc6))
1407 old->pc6 = new->pc6 - old->pc6;
1408 if (DO_BIC(BIC_Pkgpc7))
1409 old->pc7 = new->pc7 - old->pc7;
1410 old->pc8 = new->pc8 - old->pc8;
1411 old->pc9 = new->pc9 - old->pc9;
1412 old->pc10 = new->pc10 - old->pc10;
1413 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1414 old->sys_lpi = new->sys_lpi - old->sys_lpi;
1415 old->pkg_temp_c = new->pkg_temp_c;
1417 /* flag an error when rc6 counter resets/wraps */
1418 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
1419 old->gfx_rc6_ms = -1;
1421 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1423 old->gfx_mhz = new->gfx_mhz;
1424 old->gfx_act_mhz = new->gfx_act_mhz;
1426 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1427 old->energy_cores = new->energy_cores - old->energy_cores;
1428 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1429 old->energy_dram = new->energy_dram - old->energy_dram;
1430 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1431 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
1433 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1434 if (mp->format == FORMAT_RAW)
1435 old->counter[i] = new->counter[i];
1437 old->counter[i] = new->counter[i] - old->counter[i];
1443 void delta_core(struct core_data *new, struct core_data *old)
1446 struct msr_counter *mp;
1448 old->c3 = new->c3 - old->c3;
1449 old->c6 = new->c6 - old->c6;
1450 old->c7 = new->c7 - old->c7;
1451 old->core_temp_c = new->core_temp_c;
1452 old->mc6_us = new->mc6_us - old->mc6_us;
1454 DELTA_WRAP32(new->core_energy, old->core_energy);
1456 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1457 if (mp->format == FORMAT_RAW)
1458 old->counter[i] = new->counter[i];
1460 old->counter[i] = new->counter[i] - old->counter[i];
1464 int soft_c1_residency_display(int bic)
1466 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1469 return DO_BIC_READ(bic);
1475 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
1478 struct msr_counter *mp;
1480 /* we run cpuid just the 1st time, copy the results */
1481 if (DO_BIC(BIC_APIC))
1482 new->apic_id = old->apic_id;
1483 if (DO_BIC(BIC_X2APIC))
1484 new->x2apic_id = old->x2apic_id;
1487 * the timestamps from start of measurement interval are in "old"
1488 * the timestamp from end of measurement interval are in "new"
1489 * over-write old w/ new so we can print end of interval values
1492 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
1493 old->tv_begin = new->tv_begin;
1494 old->tv_end = new->tv_end;
1496 old->tsc = new->tsc - old->tsc;
1498 /* check for TSC < 1 Mcycles over interval */
1499 if (old->tsc < (1000 * 1000))
1500 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1501 "You can disable all c-states by booting with \"idle=poll\"\n"
1502 "or just the deep ones with \"processor.max_cstate=1\"");
1504 old->c1 = new->c1 - old->c1;
1506 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
1507 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1508 old->aperf = new->aperf - old->aperf;
1509 old->mperf = new->mperf - old->mperf;
1515 if (use_c1_residency_msr) {
1517 * Some models have a dedicated C1 residency MSR,
1518 * which should be more accurate than the derivation below.
1522 * As counter collection is not atomic,
1523 * it is possible for mperf's non-halted cycles + idle states
1524 * to exceed TSC's all cycles: show c1 = 0% in that case.
1526 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
1529 /* normal case, derive c1 */
1530 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1531 - core_delta->c6 - core_delta->c7;
1535 if (old->mperf == 0) {
1537 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1538 old->mperf = 1; /* divide by 0 protection */
1541 if (DO_BIC(BIC_IPC))
1542 old->instr_count = new->instr_count - old->instr_count;
1544 if (DO_BIC(BIC_IRQ))
1545 old->irq_count = new->irq_count - old->irq_count;
1547 if (DO_BIC(BIC_SMI))
1548 old->smi_count = new->smi_count - old->smi_count;
1550 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1551 if (mp->format == FORMAT_RAW)
1552 old->counter[i] = new->counter[i];
1554 old->counter[i] = new->counter[i] - old->counter[i];
1559 int delta_cpu(struct thread_data *t, struct core_data *c,
1560 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
1564 /* calculate core delta only for 1st thread in core */
1565 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1568 /* always calculate thread delta */
1569 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1573 /* calculate package delta only for 1st core in package */
1574 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1575 retval = delta_package(p, p2);
1580 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1583 struct msr_counter *mp;
1585 t->tv_begin.tv_sec = 0;
1586 t->tv_begin.tv_usec = 0;
1587 t->tv_end.tv_sec = 0;
1588 t->tv_end.tv_usec = 0;
1589 t->tv_delta.tv_sec = 0;
1590 t->tv_delta.tv_usec = 0;
1602 /* tells format_counters to dump all fields from this set */
1603 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1612 p->pkg_wtd_core_c0 = 0;
1613 p->pkg_any_core_c0 = 0;
1614 p->pkg_any_gfxe_c0 = 0;
1615 p->pkg_both_core_gfxe_c0 = 0;
1618 if (DO_BIC(BIC_Pkgpc3))
1620 if (DO_BIC(BIC_Pkgpc6))
1622 if (DO_BIC(BIC_Pkgpc7))
1632 p->energy_cores = 0;
1634 p->rapl_pkg_perf_status = 0;
1635 p->rapl_dram_perf_status = 0;
1641 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1644 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1647 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1651 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1654 struct msr_counter *mp;
1656 /* copy un-changing apic_id's */
1657 if (DO_BIC(BIC_APIC))
1658 average.threads.apic_id = t->apic_id;
1659 if (DO_BIC(BIC_X2APIC))
1660 average.threads.x2apic_id = t->x2apic_id;
1662 /* remember first tv_begin */
1663 if (average.threads.tv_begin.tv_sec == 0)
1664 average.threads.tv_begin = t->tv_begin;
1666 /* remember last tv_end */
1667 average.threads.tv_end = t->tv_end;
1669 average.threads.tsc += t->tsc;
1670 average.threads.aperf += t->aperf;
1671 average.threads.mperf += t->mperf;
1672 average.threads.c1 += t->c1;
1674 average.threads.instr_count += t->instr_count;
1676 average.threads.irq_count += t->irq_count;
1677 average.threads.smi_count += t->smi_count;
1679 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1680 if (mp->format == FORMAT_RAW)
1682 average.threads.counter[i] += t->counter[i];
1685 /* sum per-core values only for 1st thread in core */
1686 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1689 average.cores.c3 += c->c3;
1690 average.cores.c6 += c->c6;
1691 average.cores.c7 += c->c7;
1692 average.cores.mc6_us += c->mc6_us;
1694 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1696 average.cores.core_energy += c->core_energy;
1698 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1699 if (mp->format == FORMAT_RAW)
1701 average.cores.counter[i] += c->counter[i];
1704 /* sum per-pkg values only for 1st core in pkg */
1705 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1708 if (DO_BIC(BIC_Totl_c0))
1709 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1710 if (DO_BIC(BIC_Any_c0))
1711 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1712 if (DO_BIC(BIC_GFX_c0))
1713 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1714 if (DO_BIC(BIC_CPUGFX))
1715 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1717 average.packages.pc2 += p->pc2;
1718 if (DO_BIC(BIC_Pkgpc3))
1719 average.packages.pc3 += p->pc3;
1720 if (DO_BIC(BIC_Pkgpc6))
1721 average.packages.pc6 += p->pc6;
1722 if (DO_BIC(BIC_Pkgpc7))
1723 average.packages.pc7 += p->pc7;
1724 average.packages.pc8 += p->pc8;
1725 average.packages.pc9 += p->pc9;
1726 average.packages.pc10 += p->pc10;
1728 average.packages.cpu_lpi = p->cpu_lpi;
1729 average.packages.sys_lpi = p->sys_lpi;
1731 average.packages.energy_pkg += p->energy_pkg;
1732 average.packages.energy_dram += p->energy_dram;
1733 average.packages.energy_cores += p->energy_cores;
1734 average.packages.energy_gfx += p->energy_gfx;
1736 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1737 average.packages.gfx_mhz = p->gfx_mhz;
1738 average.packages.gfx_act_mhz = p->gfx_act_mhz;
1740 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1742 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1743 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1745 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1746 if (mp->format == FORMAT_RAW)
1748 average.packages.counter[i] += p->counter[i];
1754 * sum the counters for all cpus in the system
1755 * compute the weighted average
1757 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1760 struct msr_counter *mp;
1762 clear_counters(&average.threads, &average.cores, &average.packages);
1764 for_all_cpus(sum_counters, t, c, p);
1766 /* Use the global time delta for the average. */
1767 average.threads.tv_delta = tv_delta;
1769 average.threads.tsc /= topo.num_cpus;
1770 average.threads.aperf /= topo.num_cpus;
1771 average.threads.mperf /= topo.num_cpus;
1772 average.threads.instr_count /= topo.num_cpus;
1773 average.threads.c1 /= topo.num_cpus;
1775 if (average.threads.irq_count > 9999999)
1776 sums_need_wide_columns = 1;
1778 average.cores.c3 /= topo.num_cores;
1779 average.cores.c6 /= topo.num_cores;
1780 average.cores.c7 /= topo.num_cores;
1781 average.cores.mc6_us /= topo.num_cores;
1783 if (DO_BIC(BIC_Totl_c0))
1784 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1785 if (DO_BIC(BIC_Any_c0))
1786 average.packages.pkg_any_core_c0 /= topo.num_packages;
1787 if (DO_BIC(BIC_GFX_c0))
1788 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1789 if (DO_BIC(BIC_CPUGFX))
1790 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1792 average.packages.pc2 /= topo.num_packages;
1793 if (DO_BIC(BIC_Pkgpc3))
1794 average.packages.pc3 /= topo.num_packages;
1795 if (DO_BIC(BIC_Pkgpc6))
1796 average.packages.pc6 /= topo.num_packages;
1797 if (DO_BIC(BIC_Pkgpc7))
1798 average.packages.pc7 /= topo.num_packages;
1800 average.packages.pc8 /= topo.num_packages;
1801 average.packages.pc9 /= topo.num_packages;
1802 average.packages.pc10 /= topo.num_packages;
1804 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1805 if (mp->format == FORMAT_RAW)
1807 if (mp->type == COUNTER_ITEMS) {
1808 if (average.threads.counter[i] > 9999999)
1809 sums_need_wide_columns = 1;
1812 average.threads.counter[i] /= topo.num_cpus;
1814 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1815 if (mp->format == FORMAT_RAW)
1817 if (mp->type == COUNTER_ITEMS) {
1818 if (average.cores.counter[i] > 9999999)
1819 sums_need_wide_columns = 1;
1821 average.cores.counter[i] /= topo.num_cores;
1823 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1824 if (mp->format == FORMAT_RAW)
1826 if (mp->type == COUNTER_ITEMS) {
1827 if (average.packages.counter[i] > 9999999)
1828 sums_need_wide_columns = 1;
1830 average.packages.counter[i] /= topo.num_packages;
1834 static unsigned long long rdtsc(void)
1836 unsigned int low, high;
1838 asm volatile ("rdtsc":"=a" (low), "=d"(high));
1840 return low | ((unsigned long long)high) << 32;
1844 * Open a file, and exit on failure
1846 FILE *fopen_or_die(const char *path, const char *mode)
1848 FILE *filep = fopen(path, mode);
1851 err(1, "%s: open failed", path);
1856 * snapshot_sysfs_counter()
1858 * return snapshot of given counter
1860 unsigned long long snapshot_sysfs_counter(char *path)
1864 unsigned long long counter;
1866 fp = fopen_or_die(path, "r");
1868 retval = fscanf(fp, "%lld", &counter);
1870 err(1, "snapshot_sysfs_counter(%s)", path);
1877 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1879 if (mp->msr_num != 0) {
1880 if (get_msr(cpu, mp->msr_num, counterp))
1883 char path[128 + PATH_BYTES];
1885 if (mp->flags & SYSFS_PERCPU) {
1886 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
1888 *counterp = snapshot_sysfs_counter(path);
1890 *counterp = snapshot_sysfs_counter(mp->path);
1897 int get_epb(int cpu)
1899 char path[128 + PATH_BYTES];
1900 unsigned long long msr;
1904 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
1906 fp = fopen(path, "r");
1910 ret = fscanf(fp, "%d", &epb);
1912 err(1, "%s(%s)", __func__, path);
1919 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
1924 void get_apic_id(struct thread_data *t)
1926 unsigned int eax, ebx, ecx, edx;
1928 if (DO_BIC(BIC_APIC)) {
1929 eax = ebx = ecx = edx = 0;
1930 __cpuid(1, eax, ebx, ecx, edx);
1932 t->apic_id = (ebx >> 24) & 0xff;
1935 if (!DO_BIC(BIC_X2APIC))
1938 if (authentic_amd || hygon_genuine) {
1939 unsigned int topology_extensions;
1941 if (max_extended_level < 0x8000001e)
1944 eax = ebx = ecx = edx = 0;
1945 __cpuid(0x80000001, eax, ebx, ecx, edx);
1946 topology_extensions = ecx & (1 << 22);
1948 if (topology_extensions == 0)
1951 eax = ebx = ecx = edx = 0;
1952 __cpuid(0x8000001e, eax, ebx, ecx, edx);
1961 if (max_level < 0xb)
1965 __cpuid(0xb, eax, ebx, ecx, edx);
1968 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
1969 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
1975 * acquire and record local counters for that cpu
1977 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1979 int cpu = t->cpu_id;
1980 unsigned long long msr;
1981 int aperf_mperf_retry_count = 0;
1982 struct msr_counter *mp;
1985 if (cpu_migrate(cpu)) {
1986 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
1990 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
1992 if (first_counter_read)
1995 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1997 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
1998 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2001 * The TSC, APERF and MPERF must be read together for
2002 * APERF/MPERF and MPERF/TSC to give accurate results.
2004 * Unfortunately, APERF and MPERF are read by
2005 * individual system call, so delays may occur
2006 * between them. If the time to read them
2007 * varies by a large amount, we re-read them.
2011 * This initial dummy APERF read has been seen to
2012 * reduce jitter in the subsequent reads.
2015 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2018 t->tsc = rdtsc(); /* re-read close to APERF */
2020 tsc_before = t->tsc;
2022 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2025 tsc_between = rdtsc();
2027 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
2030 tsc_after = rdtsc();
2032 aperf_time = tsc_between - tsc_before;
2033 mperf_time = tsc_after - tsc_between;
2036 * If the system call latency to read APERF and MPERF
2037 * differ by more than 2x, then try again.
2039 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2040 aperf_mperf_retry_count++;
2041 if (aperf_mperf_retry_count < 5)
2044 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
2046 aperf_mperf_retry_count = 0;
2048 t->aperf = t->aperf * aperf_mperf_multiplier;
2049 t->mperf = t->mperf * aperf_mperf_multiplier;
2052 if (DO_BIC(BIC_IPC))
2053 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2056 if (DO_BIC(BIC_IRQ))
2057 t->irq_count = irqs_per_cpu[cpu];
2058 if (DO_BIC(BIC_SMI)) {
2059 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2061 t->smi_count = msr & 0xFFFFFFFF;
2063 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
2064 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2068 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2069 if (get_mp(cpu, mp, &t->counter[i]))
2073 /* collect core counters only for 1st thread in core */
2074 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2077 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
2078 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2082 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
2083 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2085 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) {
2086 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2090 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
2091 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2093 else if (t->is_atom) {
2095 * For Atom CPUs that has core cstate deeper than c6,
2096 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2097 * Minus CC7 (and deeper cstates) residency to get
2098 * accturate cc6 residency.
2104 if (DO_BIC(BIC_Mod_c6))
2105 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2108 if (DO_BIC(BIC_CoreTmp)) {
2109 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2111 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
2114 if (do_rapl & RAPL_AMD_F17H) {
2115 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2117 c->core_energy = msr & 0xFFFFFFFF;
2120 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2121 if (get_mp(cpu, mp, &c->counter[i]))
2125 /* collect package counters only for 1st core in package */
2126 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2129 if (DO_BIC(BIC_Totl_c0)) {
2130 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2133 if (DO_BIC(BIC_Any_c0)) {
2134 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2137 if (DO_BIC(BIC_GFX_c0)) {
2138 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2141 if (DO_BIC(BIC_CPUGFX)) {
2142 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2145 if (DO_BIC(BIC_Pkgpc3))
2146 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2148 if (DO_BIC(BIC_Pkgpc6)) {
2149 if (do_slm_cstates) {
2150 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2153 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2158 if (DO_BIC(BIC_Pkgpc2))
2159 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2161 if (DO_BIC(BIC_Pkgpc7))
2162 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2164 if (DO_BIC(BIC_Pkgpc8))
2165 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2167 if (DO_BIC(BIC_Pkgpc9))
2168 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2170 if (DO_BIC(BIC_Pkgpc10))
2171 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2174 if (DO_BIC(BIC_CPU_LPI))
2175 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2176 if (DO_BIC(BIC_SYS_LPI))
2177 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2179 if (do_rapl & RAPL_PKG) {
2180 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
2182 p->energy_pkg = msr;
2184 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
2185 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
2187 p->energy_cores = msr;
2189 if (do_rapl & RAPL_DRAM) {
2190 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
2192 p->energy_dram = msr;
2194 if (do_rapl & RAPL_GFX) {
2195 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
2197 p->energy_gfx = msr;
2199 if (do_rapl & RAPL_PKG_PERF_STATUS) {
2200 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
2202 p->rapl_pkg_perf_status = msr;
2204 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
2205 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
2207 p->rapl_dram_perf_status = msr;
2209 if (do_rapl & RAPL_AMD_F17H) {
2210 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
2212 p->energy_pkg = msr;
2214 if (DO_BIC(BIC_PkgTmp)) {
2215 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2217 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
2220 if (DO_BIC(BIC_GFX_rc6))
2221 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2223 if (DO_BIC(BIC_GFXMHz))
2224 p->gfx_mhz = gfx_cur_mhz;
2226 if (DO_BIC(BIC_GFXACTMHz))
2227 p->gfx_act_mhz = gfx_act_mhz;
2229 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2230 if (get_mp(cpu, mp, &p->counter[i]))
2234 gettimeofday(&t->tv_end, (struct timezone *)NULL);
2240 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2241 * If you change the values, note they are used both in comparisons
2242 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2245 #define PCLUKN 0 /* Unknown */
2246 #define PCLRSV 1 /* Reserved */
2247 #define PCL__0 2 /* PC0 */
2248 #define PCL__1 3 /* PC1 */
2249 #define PCL__2 4 /* PC2 */
2250 #define PCL__3 5 /* PC3 */
2251 #define PCL__4 6 /* PC4 */
2252 #define PCL__6 7 /* PC6 */
2253 #define PCL_6N 8 /* PC6 No Retention */
2254 #define PCL_6R 9 /* PC6 Retention */
2255 #define PCL__7 10 /* PC7 */
2256 #define PCL_7S 11 /* PC7 Shrink */
2257 #define PCL__8 12 /* PC8 */
2258 #define PCL__9 13 /* PC9 */
2259 #define PCL_10 14 /* PC10 */
2260 #define PCLUNL 15 /* Unlimited */
2262 int pkg_cstate_limit = PCLUKN;
2263 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
2264 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2267 int nhm_pkg_cstate_limits[16] =
2268 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2270 int snb_pkg_cstate_limits[16] =
2271 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2273 int hsw_pkg_cstate_limits[16] =
2274 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2276 int slv_pkg_cstate_limits[16] =
2277 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2279 int amt_pkg_cstate_limits[16] =
2280 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2282 int phi_pkg_cstate_limits[16] =
2283 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2285 int glm_pkg_cstate_limits[16] =
2286 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2288 int skx_pkg_cstate_limits[16] =
2289 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2291 int icx_pkg_cstate_limits[16] =
2292 { PCL__0, PCL__2, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2295 static void calculate_tsc_tweak()
2297 tsc_tweak = base_hz / tsc_hz;
2300 void prewake_cstate_probe(unsigned int family, unsigned int model);
2302 static void dump_nhm_platform_info(void)
2304 unsigned long long msr;
2307 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2309 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
2311 ratio = (msr >> 40) & 0xFF;
2312 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
2314 ratio = (msr >> 8) & 0xFF;
2315 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2317 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
2318 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
2319 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
2321 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2322 if (dis_cstate_prewake)
2323 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
2328 static void dump_hsw_turbo_ratio_limits(void)
2330 unsigned long long msr;
2333 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
2335 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
2337 ratio = (msr >> 8) & 0xFF;
2339 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
2341 ratio = (msr >> 0) & 0xFF;
2343 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
2347 static void dump_ivt_turbo_ratio_limits(void)
2349 unsigned long long msr;
2352 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
2354 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
2356 ratio = (msr >> 56) & 0xFF;
2358 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
2360 ratio = (msr >> 48) & 0xFF;
2362 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
2364 ratio = (msr >> 40) & 0xFF;
2366 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
2368 ratio = (msr >> 32) & 0xFF;
2370 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
2372 ratio = (msr >> 24) & 0xFF;
2374 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
2376 ratio = (msr >> 16) & 0xFF;
2378 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
2380 ratio = (msr >> 8) & 0xFF;
2382 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
2384 ratio = (msr >> 0) & 0xFF;
2386 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
2390 int has_turbo_ratio_group_limits(int family, int model)
2397 case INTEL_FAM6_ATOM_GOLDMONT:
2398 case INTEL_FAM6_SKYLAKE_X:
2399 case INTEL_FAM6_ICELAKE_X:
2400 case INTEL_FAM6_ATOM_GOLDMONT_D:
2401 case INTEL_FAM6_ATOM_TREMONT_D:
2407 static void dump_turbo_ratio_limits(int family, int model)
2409 unsigned long long msr, core_counts;
2410 unsigned int ratio, group_size;
2412 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2413 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
2415 if (has_turbo_ratio_group_limits(family, model)) {
2416 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2417 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2419 core_counts = 0x0807060504030201;
2422 ratio = (msr >> 56) & 0xFF;
2423 group_size = (core_counts >> 56) & 0xFF;
2425 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2426 ratio, bclk, ratio * bclk, group_size);
2428 ratio = (msr >> 48) & 0xFF;
2429 group_size = (core_counts >> 48) & 0xFF;
2431 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2432 ratio, bclk, ratio * bclk, group_size);
2434 ratio = (msr >> 40) & 0xFF;
2435 group_size = (core_counts >> 40) & 0xFF;
2437 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2438 ratio, bclk, ratio * bclk, group_size);
2440 ratio = (msr >> 32) & 0xFF;
2441 group_size = (core_counts >> 32) & 0xFF;
2443 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2444 ratio, bclk, ratio * bclk, group_size);
2446 ratio = (msr >> 24) & 0xFF;
2447 group_size = (core_counts >> 24) & 0xFF;
2449 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2450 ratio, bclk, ratio * bclk, group_size);
2452 ratio = (msr >> 16) & 0xFF;
2453 group_size = (core_counts >> 16) & 0xFF;
2455 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2456 ratio, bclk, ratio * bclk, group_size);
2458 ratio = (msr >> 8) & 0xFF;
2459 group_size = (core_counts >> 8) & 0xFF;
2461 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2462 ratio, bclk, ratio * bclk, group_size);
2464 ratio = (msr >> 0) & 0xFF;
2465 group_size = (core_counts >> 0) & 0xFF;
2467 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2468 ratio, bclk, ratio * bclk, group_size);
2472 static void dump_atom_turbo_ratio_limits(void)
2474 unsigned long long msr;
2477 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2478 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2480 ratio = (msr >> 0) & 0x3F;
2482 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
2484 ratio = (msr >> 8) & 0x3F;
2486 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
2488 ratio = (msr >> 16) & 0x3F;
2490 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2492 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2493 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2495 ratio = (msr >> 24) & 0x3F;
2497 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
2499 ratio = (msr >> 16) & 0x3F;
2501 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
2503 ratio = (msr >> 8) & 0x3F;
2505 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
2507 ratio = (msr >> 0) & 0x3F;
2509 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
2512 static void dump_knl_turbo_ratio_limits(void)
2514 const unsigned int buckets_no = 7;
2516 unsigned long long msr;
2517 int delta_cores, delta_ratio;
2519 unsigned int cores[buckets_no];
2520 unsigned int ratio[buckets_no];
2522 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2524 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
2527 * Turbo encoding in KNL is as follows:
2529 * [7:1] -- Base value of number of active cores of bucket 1.
2530 * [15:8] -- Base value of freq ratio of bucket 1.
2531 * [20:16] -- +ve delta of number of active cores of bucket 2.
2532 * i.e. active cores of bucket 2 =
2533 * active cores of bucket 1 + delta
2534 * [23:21] -- Negative delta of freq ratio of bucket 2.
2535 * i.e. freq ratio of bucket 2 =
2536 * freq ratio of bucket 1 - delta
2537 * [28:24]-- +ve delta of number of active cores of bucket 3.
2538 * [31:29]-- -ve delta of freq ratio of bucket 3.
2539 * [36:32]-- +ve delta of number of active cores of bucket 4.
2540 * [39:37]-- -ve delta of freq ratio of bucket 4.
2541 * [44:40]-- +ve delta of number of active cores of bucket 5.
2542 * [47:45]-- -ve delta of freq ratio of bucket 5.
2543 * [52:48]-- +ve delta of number of active cores of bucket 6.
2544 * [55:53]-- -ve delta of freq ratio of bucket 6.
2545 * [60:56]-- +ve delta of number of active cores of bucket 7.
2546 * [63:61]-- -ve delta of freq ratio of bucket 7.
2550 cores[b_nr] = (msr & 0xFF) >> 1;
2551 ratio[b_nr] = (msr >> 8) & 0xFF;
2553 for (i = 16; i < 64; i += 8) {
2554 delta_cores = (msr >> i) & 0x1F;
2555 delta_ratio = (msr >> (i + 5)) & 0x7;
2557 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2558 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2562 for (i = buckets_no - 1; i >= 0; i--)
2563 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
2565 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2566 ratio[i], bclk, ratio[i] * bclk, cores[i]);
2569 static void dump_nhm_cst_cfg(void)
2571 unsigned long long msr;
2573 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2575 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
2577 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
2578 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2579 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2580 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2581 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
2582 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
2584 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
2585 if (has_automatic_cstate_conversion) {
2586 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
2589 fprintf(outf, ")\n");
2594 static void dump_config_tdp(void)
2596 unsigned long long msr;
2598 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
2599 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
2600 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
2602 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
2603 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
2605 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2606 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2607 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2608 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
2610 fprintf(outf, ")\n");
2612 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
2613 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
2615 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2616 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2617 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2618 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
2620 fprintf(outf, ")\n");
2622 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
2623 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
2625 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2626 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2627 fprintf(outf, ")\n");
2629 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
2630 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
2631 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
2632 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2633 fprintf(outf, ")\n");
2636 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2638 void print_irtl(void)
2640 unsigned long long msr;
2642 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2643 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2644 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2645 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2647 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2648 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2649 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2650 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2652 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2653 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2654 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2655 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2660 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2661 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2662 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2663 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2665 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2666 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2667 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2668 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2670 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2671 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2672 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2673 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2677 void free_fd_percpu(void)
2681 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
2682 if (fd_percpu[i] != 0)
2683 close(fd_percpu[i]);
2689 void free_all_buffers(void)
2693 CPU_FREE(cpu_present_set);
2694 cpu_present_set = NULL;
2695 cpu_present_setsize = 0;
2697 CPU_FREE(cpu_affinity_set);
2698 cpu_affinity_set = NULL;
2699 cpu_affinity_setsize = 0;
2707 package_even = NULL;
2717 free(output_buffer);
2718 output_buffer = NULL;
2723 free(irq_column_2_cpu);
2726 for (i = 0; i <= topo.max_cpu_num; ++i) {
2727 if (cpus[i].put_ids)
2728 CPU_FREE(cpus[i].put_ids);
2734 * Parse a file containing a single int.
2735 * Return 0 if file can not be opened
2736 * Exit if file can be opened, but can not be parsed
2738 int parse_int_file(const char *fmt, ...)
2741 char path[PATH_MAX];
2745 va_start(args, fmt);
2746 vsnprintf(path, sizeof(path), fmt, args);
2748 filep = fopen(path, "r");
2751 if (fscanf(filep, "%d", &value) != 1)
2752 err(1, "%s: failed to parse number from file", path);
2758 * cpu_is_first_core_in_package(cpu)
2759 * return 1 if given CPU is 1st core in package
2761 int cpu_is_first_core_in_package(int cpu)
2763 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2766 int get_physical_package_id(int cpu)
2768 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2771 int get_die_id(int cpu)
2773 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
2776 int get_core_id(int cpu)
2778 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2781 void set_node_data(void)
2783 int pkg, node, lnode, cpu, cpux;
2786 /* initialize logical_node_id */
2787 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
2788 cpus[cpu].logical_node_id = -1;
2791 for (pkg = 0; pkg < topo.num_packages; pkg++) {
2793 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
2794 if (cpus[cpu].physical_package_id != pkg)
2796 /* find a cpu with an unset logical_node_id */
2797 if (cpus[cpu].logical_node_id != -1)
2799 cpus[cpu].logical_node_id = lnode;
2800 node = cpus[cpu].physical_node_id;
2803 * find all matching cpus on this pkg and set
2804 * the logical_node_id
2806 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
2807 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2808 cpus[cpux].logical_node_id = lnode;
2813 if (lnode > topo.nodes_per_pkg)
2814 topo.nodes_per_pkg = lnode;
2816 if (cpu_count >= topo.max_cpu_num)
2821 int get_physical_node_id(struct cpu_topology *thiscpu)
2826 int cpu = thiscpu->logical_cpu_id;
2828 for (i = 0; i <= topo.max_cpu_num; i++) {
2829 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
2830 filep = fopen(path, "r");
2839 int get_thread_siblings(struct cpu_topology *thiscpu)
2841 char path[80], character;
2844 int so, shift, sib_core;
2845 int cpu = thiscpu->logical_cpu_id;
2846 int offset = topo.max_cpu_num + 1;
2850 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
2851 if (thiscpu->thread_id < 0)
2852 thiscpu->thread_id = thread_id++;
2853 if (!thiscpu->put_ids)
2856 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
2857 CPU_ZERO_S(size, thiscpu->put_ids);
2859 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
2860 filep = fopen(path, "r");
2863 warnx("%s: open failed", path);
2867 offset -= BITMASK_SIZE;
2868 if (fscanf(filep, "%lx%c", &map, &character) != 2)
2869 err(1, "%s: failed to parse file", path);
2870 for (shift = 0; shift < BITMASK_SIZE; shift++) {
2871 if ((map >> shift) & 0x1) {
2872 so = shift + offset;
2873 sib_core = get_core_id(so);
2874 if (sib_core == thiscpu->physical_core_id) {
2875 CPU_SET_S(so, size, thiscpu->put_ids);
2876 if ((so != cpu) && (cpus[so].thread_id < 0))
2877 cpus[so].thread_id = thread_id++;
2881 } while (!strncmp(&character, ",", 1));
2884 return CPU_COUNT_S(size, thiscpu->put_ids);
2888 * run func(thread, core, package) in topology order
2889 * skip non-present cpus
2892 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
2893 struct pkg_data *, struct thread_data *, struct core_data *,
2894 struct pkg_data *), struct thread_data *thread_base,
2895 struct core_data *core_base, struct pkg_data *pkg_base,
2896 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
2898 int retval, pkg_no, node_no, core_no, thread_no;
2900 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2901 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
2902 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
2903 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
2904 struct thread_data *t, *t2;
2905 struct core_data *c, *c2;
2906 struct pkg_data *p, *p2;
2908 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
2910 if (cpu_is_not_present(t->cpu_id))
2913 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
2915 c = GET_CORE(core_base, core_no, node_no, pkg_no);
2916 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
2918 p = GET_PKG(pkg_base, pkg_no);
2919 p2 = GET_PKG(pkg_base2, pkg_no);
2921 retval = func(t, c, p, t2, c2, p2);
2932 * run func(cpu) on every cpu in /proc/stat
2933 * return max_cpu number
2935 int for_all_proc_cpus(int (func) (int))
2941 fp = fopen_or_die(proc_stat, "r");
2943 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2945 err(1, "%s: failed to parse format", proc_stat);
2948 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
2952 retval = func(cpu_num);
2962 void re_initialize(void)
2965 setup_all_buffers();
2966 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2969 void set_max_cpu_num(void)
2973 unsigned long dummy;
2976 base_cpu = sched_getcpu();
2978 err(1, "cannot find calling cpu ID");
2979 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
2981 filep = fopen_or_die(pathname, "r");
2982 topo.max_cpu_num = 0;
2983 while (fscanf(filep, "%lx,", &dummy) == 1)
2984 topo.max_cpu_num += BITMASK_SIZE;
2986 topo.max_cpu_num--; /* 0 based */
2991 * remember the last one seen, it will be the max
2993 int count_cpus(int cpu)
2999 int mark_cpu_present(int cpu)
3001 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
3005 int init_thread_id(int cpu)
3007 cpus[cpu].thread_id = -1;
3012 * snapshot_proc_interrupts()
3014 * read and record summary of /proc/interrupts
3016 * return 1 if config change requires a restart, else return 0
3018 int snapshot_proc_interrupts(void)
3024 fp = fopen_or_die("/proc/interrupts", "r");
3028 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3029 for (column = 0; column < topo.num_cpus; ++column) {
3032 retval = fscanf(fp, " CPU%d", &cpu_number);
3036 if (cpu_number > topo.max_cpu_num) {
3037 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3041 irq_column_2_cpu[column] = cpu_number;
3042 irqs_per_cpu[cpu_number] = 0;
3045 /* read /proc/interrupt count lines and sum up irqs per cpu */
3050 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3054 /* read the count per cpu */
3055 for (column = 0; column < topo.num_cpus; ++column) {
3057 int cpu_number, irq_count;
3059 retval = fscanf(fp, " %d", &irq_count);
3063 cpu_number = irq_column_2_cpu[column];
3064 irqs_per_cpu[cpu_number] += irq_count;
3068 while (getc(fp) != '\n') ; /* flush interrupt description */
3075 * snapshot_gfx_rc6_ms()
3077 * record snapshot of
3078 * /sys/class/drm/card0/power/rc6_residency_ms
3080 * return 1 if config change requires a restart, else return 0
3082 int snapshot_gfx_rc6_ms(void)
3087 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3089 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3099 * snapshot_gfx_mhz()
3101 * record snapshot of
3102 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3104 * return 1 if config change requires a restart, else return 0
3106 int snapshot_gfx_mhz(void)
3112 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3118 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3126 * snapshot_gfx_cur_mhz()
3128 * record snapshot of
3129 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3131 * return 1 if config change requires a restart, else return 0
3133 int snapshot_gfx_act_mhz(void)
3139 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3145 retval = fscanf(fp, "%d", &gfx_act_mhz);
3147 err(1, "GFX ACT MHz");
3153 * snapshot_cpu_lpi()
3155 * record snapshot of
3156 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
3158 int snapshot_cpu_lpi_us(void)
3163 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3165 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
3167 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3168 BIC_NOT_PRESENT(BIC_CPU_LPI);
3179 * snapshot_sys_lpi()
3181 * record snapshot of sys_lpi_file
3183 int snapshot_sys_lpi_us(void)
3188 fp = fopen_or_die(sys_lpi_file, "r");
3190 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
3192 fprintf(stderr, "Disabling Low Power Idle System output\n");
3193 BIC_NOT_PRESENT(BIC_SYS_LPI);
3203 * snapshot /proc and /sys files
3205 * return 1 if configuration restart needed, else return 0
3207 int snapshot_proc_sysfs_files(void)
3209 if (DO_BIC(BIC_IRQ))
3210 if (snapshot_proc_interrupts())
3213 if (DO_BIC(BIC_GFX_rc6))
3214 snapshot_gfx_rc6_ms();
3216 if (DO_BIC(BIC_GFXMHz))
3219 if (DO_BIC(BIC_GFXACTMHz))
3220 snapshot_gfx_act_mhz();
3222 if (DO_BIC(BIC_CPU_LPI))
3223 snapshot_cpu_lpi_us();
3225 if (DO_BIC(BIC_SYS_LPI))
3226 snapshot_sys_lpi_us();
3233 static void signal_handler(int signal)
3239 fprintf(stderr, " SIGINT\n");
3243 fprintf(stderr, "SIGUSR1\n");
3248 void setup_signal_handler(void)
3250 struct sigaction sa;
3252 memset(&sa, 0, sizeof(sa));
3254 sa.sa_handler = &signal_handler;
3256 if (sigaction(SIGINT, &sa, NULL) < 0)
3257 err(1, "sigaction SIGINT");
3258 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3259 err(1, "sigaction SIGUSR1");
3264 struct timeval tout;
3265 struct timespec rest;
3270 FD_SET(0, &readfds);
3273 nanosleep(&interval_ts, NULL);
3278 retval = select(1, &readfds, NULL, NULL, &tout);
3281 switch (getc(stdin)) {
3287 * 'stdin' is a pipe closed on the other end. There
3288 * won't be any further input.
3291 /* Sleep the rest of the time */
3292 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3293 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3294 nanosleep(&rest, NULL);
3299 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3302 unsigned long long msr_cur, msr_last;
3304 if (!per_cpu_msr_sum)
3307 idx = offset_to_idx(offset);
3310 /* get_msr_sum() = sum + (get_msr() - last) */
3311 ret = get_msr(cpu, offset, &msr_cur);
3314 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3315 DELTA_WRAP32(msr_cur, msr_last);
3316 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3323 /* Timer callback, update the sum of MSRs periodically. */
3324 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3327 int cpu = t->cpu_id;
3329 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3330 unsigned long long msr_cur, msr_last;
3335 offset = idx_to_offset(i);
3338 ret = get_msr(cpu, offset, &msr_cur);
3340 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
3344 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3345 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3347 DELTA_WRAP32(msr_cur, msr_last);
3348 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3353 static void msr_record_handler(union sigval v)
3355 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3358 void msr_sum_record(void)
3360 struct itimerspec its;
3361 struct sigevent sev;
3363 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3364 if (!per_cpu_msr_sum) {
3365 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3369 * Signal handler might be restricted, so use thread notifier instead.
3371 memset(&sev, 0, sizeof(struct sigevent));
3372 sev.sigev_notify = SIGEV_THREAD;
3373 sev.sigev_notify_function = msr_record_handler;
3375 sev.sigev_value.sival_ptr = &timerid;
3376 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3377 fprintf(outf, "Can not create timer.\n");
3381 its.it_value.tv_sec = 0;
3382 its.it_value.tv_nsec = 1;
3384 * A wraparound time has been calculated early.
3385 * Some sources state that the peak power for a
3386 * microprocessor is usually 1.5 times the TDP rating,
3387 * use 2 * TDP for safety.
3389 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3390 its.it_interval.tv_nsec = 0;
3392 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3393 fprintf(outf, "Can not set timer.\n");
3399 timer_delete(timerid);
3401 free(per_cpu_msr_sum);
3404 void turbostat_loop()
3410 setup_signal_handler();
3415 snapshot_proc_sysfs_files();
3416 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3417 first_counter_read = 0;
3420 } else if (retval == -1) {
3421 if (restarted > 10) {
3429 gettimeofday(&tv_even, (struct timezone *)NULL);
3432 if (for_all_proc_cpus(cpu_is_not_present)) {
3437 if (snapshot_proc_sysfs_files())
3439 retval = for_all_cpus(get_counters, ODD_COUNTERS);
3442 } else if (retval == -1) {
3446 gettimeofday(&tv_odd, (struct timezone *)NULL);
3447 timersub(&tv_odd, &tv_even, &tv_delta);
3448 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3452 compute_average(EVEN_COUNTERS);
3453 format_all_counters(EVEN_COUNTERS);
3454 flush_output_stdout();
3457 if (num_iterations && ++done_iters >= num_iterations)
3460 if (snapshot_proc_sysfs_files())
3462 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3465 } else if (retval == -1) {
3469 gettimeofday(&tv_even, (struct timezone *)NULL);
3470 timersub(&tv_even, &tv_odd, &tv_delta);
3471 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
3475 compute_average(ODD_COUNTERS);
3476 format_all_counters(ODD_COUNTERS);
3477 flush_output_stdout();
3480 if (num_iterations && ++done_iters >= num_iterations)
3485 void check_dev_msr()
3490 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3491 if (stat(pathname, &sb))
3492 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
3493 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
3497 * check for CAP_SYS_RAWIO
3498 * return 0 on success
3501 int check_for_cap_sys_rawio(void)
3504 cap_flag_value_t cap_flag_value;
3506 caps = cap_get_proc();
3508 err(-6, "cap_get_proc\n");
3510 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
3511 err(-6, "cap_get\n");
3513 if (cap_flag_value != CAP_SET) {
3514 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
3518 if (cap_free(caps) == -1)
3519 err(-6, "cap_free\n");
3524 void check_permissions(void)
3529 /* check for CAP_SYS_RAWIO */
3530 do_exit += check_for_cap_sys_rawio();
3532 /* test file permissions */
3533 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3534 if (euidaccess(pathname, R_OK)) {
3536 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
3539 /* if all else fails, thell them to be root */
3542 warnx("... or simply run as root");
3549 * NHM adds support for additional MSRs:
3551 * MSR_SMI_COUNT 0x00000034
3553 * MSR_PLATFORM_INFO 0x000000ce
3554 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
3556 * MSR_MISC_PWR_MGMT 0x000001aa
3558 * MSR_PKG_C3_RESIDENCY 0x000003f8
3559 * MSR_PKG_C6_RESIDENCY 0x000003f9
3560 * MSR_CORE_C3_RESIDENCY 0x000003fc
3561 * MSR_CORE_C6_RESIDENCY 0x000003fd
3564 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
3565 * sets has_misc_feature_control
3567 int probe_nhm_msrs(unsigned int family, unsigned int model)
3569 unsigned long long msr;
3570 unsigned int base_ratio;
3571 int *pkg_cstate_limits;
3579 bclk = discover_bclk(family, model);
3582 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
3583 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3584 pkg_cstate_limits = nhm_pkg_cstate_limits;
3586 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
3587 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
3588 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3589 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3590 pkg_cstate_limits = snb_pkg_cstate_limits;
3591 has_misc_feature_control = 1;
3593 case INTEL_FAM6_HASWELL: /* HSW */
3594 case INTEL_FAM6_HASWELL_G: /* HSW */
3595 case INTEL_FAM6_HASWELL_X: /* HSX */
3596 case INTEL_FAM6_HASWELL_L: /* HSW */
3597 case INTEL_FAM6_BROADWELL: /* BDW */
3598 case INTEL_FAM6_BROADWELL_G: /* BDW */
3599 case INTEL_FAM6_BROADWELL_X: /* BDX */
3600 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3601 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3602 pkg_cstate_limits = hsw_pkg_cstate_limits;
3603 has_misc_feature_control = 1;
3605 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3606 pkg_cstate_limits = skx_pkg_cstate_limits;
3607 has_misc_feature_control = 1;
3609 case INTEL_FAM6_ICELAKE_X: /* ICX */
3610 pkg_cstate_limits = icx_pkg_cstate_limits;
3611 has_misc_feature_control = 1;
3613 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3614 no_MSR_MISC_PWR_MGMT = 1;
3615 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
3616 pkg_cstate_limits = slv_pkg_cstate_limits;
3618 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
3619 pkg_cstate_limits = amt_pkg_cstate_limits;
3620 no_MSR_MISC_PWR_MGMT = 1;
3622 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
3623 pkg_cstate_limits = phi_pkg_cstate_limits;
3625 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3626 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3627 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
3628 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
3629 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
3630 pkg_cstate_limits = glm_pkg_cstate_limits;
3635 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3636 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
3638 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3639 base_ratio = (msr >> 8) & 0xFF;
3641 base_hz = base_ratio * bclk * 1000000;
3647 * SLV client has support for unique MSRs:
3649 * MSR_CC6_DEMOTION_POLICY_CONFIG
3650 * MSR_MC6_DEMOTION_POLICY_CONFIG
3653 int has_slv_msrs(unsigned int family, unsigned int model)
3659 case INTEL_FAM6_ATOM_SILVERMONT:
3660 case INTEL_FAM6_ATOM_SILVERMONT_MID:
3661 case INTEL_FAM6_ATOM_AIRMONT_MID:
3667 int is_dnv(unsigned int family, unsigned int model)
3674 case INTEL_FAM6_ATOM_GOLDMONT_D:
3680 int is_bdx(unsigned int family, unsigned int model)
3687 case INTEL_FAM6_BROADWELL_X:
3693 int is_skx(unsigned int family, unsigned int model)
3700 case INTEL_FAM6_SKYLAKE_X:
3706 int is_icx(unsigned int family, unsigned int model)
3713 case INTEL_FAM6_ICELAKE_X:
3719 int is_ehl(unsigned int family, unsigned int model)
3725 case INTEL_FAM6_ATOM_TREMONT:
3731 int is_jvl(unsigned int family, unsigned int model)
3737 case INTEL_FAM6_ATOM_TREMONT_D:
3743 int has_turbo_ratio_limit(unsigned int family, unsigned int model)
3745 if (has_slv_msrs(family, model))
3749 /* Nehalem compatible, but do not include turbo-ratio limit support */
3750 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3751 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
3758 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
3760 if (has_slv_msrs(family, model))
3766 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
3775 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3776 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3783 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
3792 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3799 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
3808 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3815 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
3824 case INTEL_FAM6_ATOM_GOLDMONT:
3825 case INTEL_FAM6_SKYLAKE_X:
3826 case INTEL_FAM6_ICELAKE_X:
3833 int has_config_tdp(unsigned int family, unsigned int model)
3842 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3843 case INTEL_FAM6_HASWELL: /* HSW */
3844 case INTEL_FAM6_HASWELL_X: /* HSX */
3845 case INTEL_FAM6_HASWELL_L: /* HSW */
3846 case INTEL_FAM6_HASWELL_G: /* HSW */
3847 case INTEL_FAM6_BROADWELL: /* BDW */
3848 case INTEL_FAM6_BROADWELL_G: /* BDW */
3849 case INTEL_FAM6_BROADWELL_X: /* BDX */
3850 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3851 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3852 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3853 case INTEL_FAM6_ICELAKE_X: /* ICX */
3855 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3864 * 0: Tcc Offset not supported (Default)
3865 * 6: Bit 29:24 of MSR_PLATFORM_INFO
3866 * 4: Bit 27:24 of MSR_PLATFORM_INFO
3868 void check_tcc_offset(int model)
3870 unsigned long long msr;
3876 case INTEL_FAM6_SKYLAKE_L:
3877 case INTEL_FAM6_SKYLAKE:
3878 case INTEL_FAM6_KABYLAKE_L:
3879 case INTEL_FAM6_KABYLAKE:
3880 case INTEL_FAM6_ICELAKE_L:
3881 case INTEL_FAM6_ICELAKE:
3882 case INTEL_FAM6_TIGERLAKE_L:
3883 case INTEL_FAM6_TIGERLAKE:
3884 case INTEL_FAM6_COMETLAKE:
3885 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
3886 msr = (msr >> 30) & 1;
3888 tcc_offset_bits = 6;
3896 static void remove_underbar(char *s)
3909 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
3911 if (!do_nhm_platform_info)
3914 dump_nhm_platform_info();
3916 if (has_hsw_turbo_ratio_limit(family, model))
3917 dump_hsw_turbo_ratio_limits();
3919 if (has_ivt_turbo_ratio_limit(family, model))
3920 dump_ivt_turbo_ratio_limits();
3922 if (has_turbo_ratio_limit(family, model))
3923 dump_turbo_ratio_limits(family, model);
3925 if (has_atom_turbo_ratio_limit(family, model))
3926 dump_atom_turbo_ratio_limits();
3928 if (has_knl_turbo_ratio_limit(family, model))
3929 dump_knl_turbo_ratio_limits();
3931 if (has_config_tdp(family, model))
3937 static void dump_sysfs_file(char *path)
3940 char cpuidle_buf[64];
3942 input = fopen(path, "r");
3943 if (input == NULL) {
3945 fprintf(outf, "NSFOD %s\n", path);
3948 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
3949 err(1, "%s: failed to read file", path);
3952 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
3955 static void dump_sysfs_cstate_config(void)
3964 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
3965 fprintf(outf, "cpuidle not loaded\n");
3969 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
3970 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
3971 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
3973 for (state = 0; state < 10; ++state) {
3975 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
3976 input = fopen(path, "r");
3979 if (!fgets(name_buf, sizeof(name_buf), input))
3980 err(1, "%s: failed to read file", path);
3982 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
3983 sp = strchr(name_buf, '-');
3985 sp = strchrnul(name_buf, '\n');
3989 remove_underbar(name_buf);
3991 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
3992 input = fopen(path, "r");
3995 if (!fgets(desc, sizeof(desc), input))
3996 err(1, "%s: failed to read file", path);
3998 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4003 static void dump_sysfs_pstate_config(void)
4006 char driver_buf[64];
4007 char governor_buf[64];
4011 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
4012 input = fopen(path, "r");
4013 if (input == NULL) {
4014 fprintf(outf, "NSFOD %s\n", path);
4017 if (!fgets(driver_buf, sizeof(driver_buf), input))
4018 err(1, "%s: failed to read file", path);
4021 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
4022 input = fopen(path, "r");
4023 if (input == NULL) {
4024 fprintf(outf, "NSFOD %s\n", path);
4027 if (!fgets(governor_buf, sizeof(governor_buf), input))
4028 err(1, "%s: failed to read file", path);
4031 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4032 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4034 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4035 input = fopen(path, "r");
4036 if (input != NULL) {
4037 if (fscanf(input, "%d", &turbo) != 1)
4038 err(1, "%s: failed to parse number from file", path);
4039 fprintf(outf, "cpufreq boost: %d\n", turbo);
4043 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4044 input = fopen(path, "r");
4045 if (input != NULL) {
4046 if (fscanf(input, "%d", &turbo) != 1)
4047 err(1, "%s: failed to parse number from file", path);
4048 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4055 * Decode the ENERGY_PERF_BIAS MSR
4057 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4067 /* EPB is per-package */
4068 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4071 if (cpu_migrate(cpu)) {
4072 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
4081 case ENERGY_PERF_BIAS_PERFORMANCE:
4082 epb_string = "performance";
4084 case ENERGY_PERF_BIAS_NORMAL:
4085 epb_string = "balanced";
4087 case ENERGY_PERF_BIAS_POWERSAVE:
4088 epb_string = "powersave";
4091 epb_string = "custom";
4094 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
4101 * Decode the MSR_HWP_CAPABILITIES
4103 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4105 unsigned long long msr;
4113 /* MSR_HWP_CAPABILITIES is per-package */
4114 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4117 if (cpu_migrate(cpu)) {
4118 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
4122 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4125 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
4127 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4128 if ((msr & (1 << 0)) == 0)
4131 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4134 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
4135 "(high %d guar %d eff %d low %d)\n",
4137 (unsigned int)HWP_HIGHEST_PERF(msr),
4138 (unsigned int)HWP_GUARANTEED_PERF(msr),
4139 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
4141 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4144 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
4145 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4147 (unsigned int)(((msr) >> 0) & 0xff),
4148 (unsigned int)(((msr) >> 8) & 0xff),
4149 (unsigned int)(((msr) >> 16) & 0xff),
4150 (unsigned int)(((msr) >> 24) & 0xff),
4151 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
4154 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4157 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
4158 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
4160 (unsigned int)(((msr) >> 0) & 0xff),
4161 (unsigned int)(((msr) >> 8) & 0xff),
4162 (unsigned int)(((msr) >> 16) & 0xff),
4163 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
4165 if (has_hwp_notify) {
4166 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4169 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
4170 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
4171 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
4173 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4176 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
4177 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
4178 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x2) ? "" : "No-");
4184 * print_perf_limit()
4186 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4188 unsigned long long msr;
4194 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4197 if (cpu_migrate(cpu)) {
4198 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
4202 if (do_core_perf_limit_reasons) {
4203 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
4204 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4205 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
4206 (msr & 1 << 15) ? "bit15, " : "",
4207 (msr & 1 << 14) ? "bit14, " : "",
4208 (msr & 1 << 13) ? "Transitions, " : "",
4209 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4210 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4211 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4212 (msr & 1 << 9) ? "CorePwr, " : "",
4213 (msr & 1 << 8) ? "Amps, " : "",
4214 (msr & 1 << 6) ? "VR-Therm, " : "",
4215 (msr & 1 << 5) ? "Auto-HWP, " : "",
4216 (msr & 1 << 4) ? "Graphics, " : "",
4217 (msr & 1 << 2) ? "bit2, " : "",
4218 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
4219 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
4220 (msr & 1 << 31) ? "bit31, " : "",
4221 (msr & 1 << 30) ? "bit30, " : "",
4222 (msr & 1 << 29) ? "Transitions, " : "",
4223 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4224 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4225 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4226 (msr & 1 << 25) ? "CorePwr, " : "",
4227 (msr & 1 << 24) ? "Amps, " : "",
4228 (msr & 1 << 22) ? "VR-Therm, " : "",
4229 (msr & 1 << 21) ? "Auto-HWP, " : "",
4230 (msr & 1 << 20) ? "Graphics, " : "",
4231 (msr & 1 << 18) ? "bit18, " : "",
4232 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
4235 if (do_gfx_perf_limit_reasons) {
4236 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
4237 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4238 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
4239 (msr & 1 << 0) ? "PROCHOT, " : "",
4240 (msr & 1 << 1) ? "ThermStatus, " : "",
4241 (msr & 1 << 4) ? "Graphics, " : "",
4242 (msr & 1 << 6) ? "VR-Therm, " : "",
4243 (msr & 1 << 8) ? "Amps, " : "",
4244 (msr & 1 << 9) ? "GFXPwr, " : "",
4245 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4246 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
4247 (msr & 1 << 16) ? "PROCHOT, " : "",
4248 (msr & 1 << 17) ? "ThermStatus, " : "",
4249 (msr & 1 << 20) ? "Graphics, " : "",
4250 (msr & 1 << 22) ? "VR-Therm, " : "",
4251 (msr & 1 << 24) ? "Amps, " : "",
4252 (msr & 1 << 25) ? "GFXPwr, " : "",
4253 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4255 if (do_ring_perf_limit_reasons) {
4256 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
4257 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4258 fprintf(outf, " (Active: %s%s%s%s%s%s)",
4259 (msr & 1 << 0) ? "PROCHOT, " : "",
4260 (msr & 1 << 1) ? "ThermStatus, " : "",
4261 (msr & 1 << 6) ? "VR-Therm, " : "",
4262 (msr & 1 << 8) ? "Amps, " : "",
4263 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4264 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
4265 (msr & 1 << 16) ? "PROCHOT, " : "",
4266 (msr & 1 << 17) ? "ThermStatus, " : "",
4267 (msr & 1 << 22) ? "VR-Therm, " : "",
4268 (msr & 1 << 24) ? "Amps, " : "",
4269 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4274 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
4275 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
4277 double get_tdp_intel(unsigned int model)
4279 unsigned long long msr;
4281 if (do_rapl & RAPL_PKG_POWER_INFO)
4282 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
4283 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4286 case INTEL_FAM6_ATOM_SILVERMONT:
4287 case INTEL_FAM6_ATOM_SILVERMONT_D:
4294 double get_tdp_amd(unsigned int family)
4296 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4301 * rapl_dram_energy_units_probe()
4302 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4304 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
4306 /* only called for genuine_intel, family 6 */
4309 case INTEL_FAM6_HASWELL_X: /* HSX */
4310 case INTEL_FAM6_BROADWELL_X: /* BDX */
4311 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4312 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4313 return (rapl_dram_energy_units = 15.3 / 1000000);
4315 return (rapl_energy_units);
4319 void rapl_probe_intel(unsigned int family, unsigned int model)
4321 unsigned long long msr;
4322 unsigned int time_unit;
4329 case INTEL_FAM6_SANDYBRIDGE:
4330 case INTEL_FAM6_IVYBRIDGE:
4331 case INTEL_FAM6_HASWELL: /* HSW */
4332 case INTEL_FAM6_HASWELL_L: /* HSW */
4333 case INTEL_FAM6_HASWELL_G: /* HSW */
4334 case INTEL_FAM6_BROADWELL: /* BDW */
4335 case INTEL_FAM6_BROADWELL_G: /* BDW */
4336 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
4338 BIC_PRESENT(BIC_Pkg_J);
4339 BIC_PRESENT(BIC_Cor_J);
4340 BIC_PRESENT(BIC_GFX_J);
4342 BIC_PRESENT(BIC_PkgWatt);
4343 BIC_PRESENT(BIC_CorWatt);
4344 BIC_PRESENT(BIC_GFXWatt);
4347 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4348 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4349 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
4351 BIC_PRESENT(BIC_Pkg_J);
4353 BIC_PRESENT(BIC_PkgWatt);
4355 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4357 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4358 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4360 BIC_PRESENT(BIC_Pkg_J);
4361 BIC_PRESENT(BIC_Cor_J);
4362 BIC_PRESENT(BIC_RAM_J);
4363 BIC_PRESENT(BIC_GFX_J);
4365 BIC_PRESENT(BIC_PkgWatt);
4366 BIC_PRESENT(BIC_CorWatt);
4367 BIC_PRESENT(BIC_RAMWatt);
4368 BIC_PRESENT(BIC_GFXWatt);
4371 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4372 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4373 BIC_PRESENT(BIC_PKG__);
4375 BIC_PRESENT(BIC_Pkg_J);
4377 BIC_PRESENT(BIC_PkgWatt);
4379 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4380 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4382 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4383 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4384 BIC_PRESENT(BIC_PKG__);
4385 BIC_PRESENT(BIC_RAM__);
4387 BIC_PRESENT(BIC_Pkg_J);
4388 BIC_PRESENT(BIC_Cor_J);
4389 BIC_PRESENT(BIC_RAM_J);
4390 BIC_PRESENT(BIC_GFX_J);
4392 BIC_PRESENT(BIC_PkgWatt);
4393 BIC_PRESENT(BIC_CorWatt);
4394 BIC_PRESENT(BIC_RAMWatt);
4395 BIC_PRESENT(BIC_GFXWatt);
4398 case INTEL_FAM6_HASWELL_X: /* HSX */
4399 case INTEL_FAM6_BROADWELL_X: /* BDX */
4400 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4401 case INTEL_FAM6_ICELAKE_X: /* ICX */
4402 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4404 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4405 RAPL_PKG_POWER_INFO;
4406 BIC_PRESENT(BIC_PKG__);
4407 BIC_PRESENT(BIC_RAM__);
4409 BIC_PRESENT(BIC_Pkg_J);
4410 BIC_PRESENT(BIC_RAM_J);
4412 BIC_PRESENT(BIC_PkgWatt);
4413 BIC_PRESENT(BIC_RAMWatt);
4416 case INTEL_FAM6_SANDYBRIDGE_X:
4417 case INTEL_FAM6_IVYBRIDGE_X:
4419 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
4420 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
4421 BIC_PRESENT(BIC_PKG__);
4422 BIC_PRESENT(BIC_RAM__);
4424 BIC_PRESENT(BIC_Pkg_J);
4425 BIC_PRESENT(BIC_Cor_J);
4426 BIC_PRESENT(BIC_RAM_J);
4428 BIC_PRESENT(BIC_PkgWatt);
4429 BIC_PRESENT(BIC_CorWatt);
4430 BIC_PRESENT(BIC_RAMWatt);
4433 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
4434 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
4435 do_rapl = RAPL_PKG | RAPL_CORES;
4437 BIC_PRESENT(BIC_Pkg_J);
4438 BIC_PRESENT(BIC_Cor_J);
4440 BIC_PRESENT(BIC_PkgWatt);
4441 BIC_PRESENT(BIC_CorWatt);
4444 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4446 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4447 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
4448 BIC_PRESENT(BIC_PKG__);
4449 BIC_PRESENT(BIC_RAM__);
4451 BIC_PRESENT(BIC_Pkg_J);
4452 BIC_PRESENT(BIC_Cor_J);
4453 BIC_PRESENT(BIC_RAM_J);
4455 BIC_PRESENT(BIC_PkgWatt);
4456 BIC_PRESENT(BIC_CorWatt);
4457 BIC_PRESENT(BIC_RAMWatt);
4464 /* units on package 0, verify later other packages match */
4465 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
4468 rapl_power_units = 1.0 / (1 << (msr & 0xF));
4469 if (model == INTEL_FAM6_ATOM_SILVERMONT)
4470 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4472 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
4474 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4476 time_unit = msr >> 16 & 0xF;
4480 rapl_time_units = 1.0 / (1 << (time_unit));
4482 tdp = get_tdp_intel(model);
4484 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4486 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4489 void rapl_probe_amd(unsigned int family, unsigned int model)
4491 unsigned long long msr;
4492 unsigned int eax, ebx, ecx, edx;
4493 unsigned int has_rapl = 0;
4496 if (max_extended_level >= 0x80000007) {
4497 __cpuid(0x80000007, eax, ebx, ecx, edx);
4498 /* RAPL (Fam 17h+) */
4499 has_rapl = edx & (1 << 14);
4502 if (!has_rapl || family < 0x17)
4505 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
4507 BIC_PRESENT(BIC_Pkg_J);
4508 BIC_PRESENT(BIC_Cor_J);
4510 BIC_PRESENT(BIC_PkgWatt);
4511 BIC_PRESENT(BIC_CorWatt);
4514 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
4517 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
4518 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
4519 rapl_power_units = ldexp(1.0, -(msr & 0xf));
4521 tdp = get_tdp_amd(family);
4523 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4525 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4531 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
4533 void rapl_probe(unsigned int family, unsigned int model)
4536 rapl_probe_intel(family, model);
4537 if (authentic_amd || hygon_genuine)
4538 rapl_probe_amd(family, model);
4541 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
4550 case INTEL_FAM6_HASWELL: /* HSW */
4551 case INTEL_FAM6_HASWELL_L: /* HSW */
4552 case INTEL_FAM6_HASWELL_G: /* HSW */
4553 do_gfx_perf_limit_reasons = 1;
4554 case INTEL_FAM6_HASWELL_X: /* HSX */
4555 do_core_perf_limit_reasons = 1;
4556 do_ring_perf_limit_reasons = 1;
4562 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
4564 if (is_skx(family, model) || is_bdx(family, model) || is_icx(family, model))
4565 has_automatic_cstate_conversion = 1;
4568 void prewake_cstate_probe(unsigned int family, unsigned int model)
4570 if (is_icx(family, model))
4571 dis_cstate_prewake = 1;
4574 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4576 unsigned long long msr;
4577 unsigned int dts, dts2;
4580 if (!(do_dts || do_ptm))
4585 /* DTS is per-core, no need to print for each thread */
4586 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
4589 if (cpu_migrate(cpu)) {
4590 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
4594 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
4595 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
4598 dts = (msr >> 16) & 0x7F;
4599 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
4601 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
4604 dts = (msr >> 16) & 0x7F;
4605 dts2 = (msr >> 8) & 0x7F;
4606 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4607 cpu, msr, tj_max - dts, tj_max - dts2);
4610 if (do_dts && debug) {
4611 unsigned int resolution;
4613 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
4616 dts = (msr >> 16) & 0x7F;
4617 resolution = (msr >> 27) & 0xF;
4618 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
4619 cpu, msr, tj_max - dts, resolution);
4621 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
4624 dts = (msr >> 16) & 0x7F;
4625 dts2 = (msr >> 8) & 0x7F;
4626 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4627 cpu, msr, tj_max - dts, tj_max - dts2);
4633 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
4635 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
4637 ((msr >> 15) & 1) ? "EN" : "DIS",
4638 ((msr >> 0) & 0x7FFF) * rapl_power_units,
4639 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
4640 (((msr >> 16) & 1) ? "EN" : "DIS"));
4645 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4647 unsigned long long msr;
4648 const char *msr_name;
4654 /* RAPL counters are per package, so print only for 1st thread/package */
4655 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4659 if (cpu_migrate(cpu)) {
4660 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
4664 if (do_rapl & RAPL_AMD_F17H) {
4665 msr_name = "MSR_RAPL_PWR_UNIT";
4666 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
4669 msr_name = "MSR_RAPL_POWER_UNIT";
4670 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
4674 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
4675 rapl_power_units, rapl_energy_units, rapl_time_units);
4677 if (do_rapl & RAPL_PKG_POWER_INFO) {
4679 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
4682 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4684 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4685 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4686 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4687 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4690 if (do_rapl & RAPL_PKG) {
4692 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
4695 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
4696 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
4698 print_power_limit_msr(cpu, msr, "PKG Limit #1");
4699 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
4701 ((msr >> 47) & 1) ? "EN" : "DIS",
4702 ((msr >> 32) & 0x7FFF) * rapl_power_units,
4703 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
4704 ((msr >> 48) & 1) ? "EN" : "DIS");
4707 if (do_rapl & RAPL_DRAM_POWER_INFO) {
4708 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
4711 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4713 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4714 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4715 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4716 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4718 if (do_rapl & RAPL_DRAM) {
4719 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
4721 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
4722 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4724 print_power_limit_msr(cpu, msr, "DRAM Limit");
4726 if (do_rapl & RAPL_CORE_POLICY) {
4727 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
4730 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
4732 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
4733 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
4735 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
4736 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4737 print_power_limit_msr(cpu, msr, "Cores Limit");
4739 if (do_rapl & RAPL_GFX) {
4740 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
4743 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
4745 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
4747 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
4748 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
4749 print_power_limit_msr(cpu, msr, "GFX Limit");
4755 * SNB adds support for additional MSRs:
4757 * MSR_PKG_C7_RESIDENCY 0x000003fa
4758 * MSR_CORE_C7_RESIDENCY 0x000003fe
4759 * MSR_PKG_C2_RESIDENCY 0x0000060d
4762 int has_snb_msrs(unsigned int family, unsigned int model)
4768 case INTEL_FAM6_SANDYBRIDGE:
4769 case INTEL_FAM6_SANDYBRIDGE_X:
4770 case INTEL_FAM6_IVYBRIDGE: /* IVB */
4771 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
4772 case INTEL_FAM6_HASWELL: /* HSW */
4773 case INTEL_FAM6_HASWELL_X: /* HSW */
4774 case INTEL_FAM6_HASWELL_L: /* HSW */
4775 case INTEL_FAM6_HASWELL_G: /* HSW */
4776 case INTEL_FAM6_BROADWELL: /* BDW */
4777 case INTEL_FAM6_BROADWELL_G: /* BDW */
4778 case INTEL_FAM6_BROADWELL_X: /* BDX */
4779 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4780 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4781 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4782 case INTEL_FAM6_ICELAKE_X: /* ICX */
4783 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4784 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4785 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4786 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4787 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4794 * HSW ULT added support for C8/C9/C10 MSRs:
4796 * MSR_PKG_C8_RESIDENCY 0x00000630
4797 * MSR_PKG_C9_RESIDENCY 0x00000631
4798 * MSR_PKG_C10_RESIDENCY 0x00000632
4800 * MSR_PKGC8_IRTL 0x00000633
4801 * MSR_PKGC9_IRTL 0x00000634
4802 * MSR_PKGC10_IRTL 0x00000635
4805 int has_c8910_msrs(unsigned int family, unsigned int model)
4811 case INTEL_FAM6_HASWELL_L: /* HSW */
4812 case INTEL_FAM6_BROADWELL: /* BDW */
4813 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4814 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4815 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4816 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4817 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4824 * SKL adds support for additional MSRS:
4826 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
4827 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
4828 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
4829 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
4831 int has_skl_msrs(unsigned int family, unsigned int model)
4837 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4838 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4844 int is_slm(unsigned int family, unsigned int model)
4849 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
4850 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
4856 int is_knl(unsigned int family, unsigned int model)
4861 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4867 int is_cnl(unsigned int family, unsigned int model)
4873 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4880 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
4882 if (is_knl(family, model))
4887 #define SLM_BCLK_FREQS 5
4888 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
4890 double slm_bclk(void)
4892 unsigned long long msr = 3;
4896 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
4897 fprintf(outf, "SLM BCLK: unknown\n");
4900 if (i >= SLM_BCLK_FREQS) {
4901 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
4904 freq = slm_freq_table[i];
4907 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
4912 double discover_bclk(unsigned int family, unsigned int model)
4914 if (has_snb_msrs(family, model) || is_knl(family, model))
4916 else if (is_slm(family, model))
4922 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4924 unsigned int eax, ebx, ecx, edx;
4929 if (cpu_migrate(t->cpu_id)) {
4930 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
4934 if (max_level < 0x1a)
4937 __cpuid(0x1a, eax, ebx, ecx, edx);
4938 eax = (eax >> 24) & 0xFF;
4945 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
4946 * the Thermal Control Circuit (TCC) activates.
4947 * This is usually equal to tjMax.
4949 * Older processors do not have this MSR, so there we guess,
4950 * but also allow cmdline over-ride with -T.
4952 * Several MSR temperature values are in units of degrees-C
4953 * below this value, including the Digital Thermal Sensor (DTS),
4954 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
4956 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4958 unsigned long long msr;
4959 unsigned int tcc_default, tcc_offset;
4962 /* tj_max is used only for dts or ptm */
4963 if (!(do_dts || do_ptm))
4966 /* this is a per-package concept */
4967 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4971 if (cpu_migrate(cpu)) {
4972 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
4976 if (tj_max_override != 0) {
4977 tj_max = tj_max_override;
4978 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
4982 /* Temperature Target MSR is Nehalem and newer only */
4983 if (!do_nhm_platform_info)
4986 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
4989 tcc_default = (msr >> 16) & 0xFF;
4992 switch (tcc_offset_bits) {
4994 tcc_offset = (msr >> 24) & 0xF;
4995 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
4996 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
4999 tcc_offset = (msr >> 24) & 0x3F;
5000 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5001 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5004 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
5012 tj_max = tcc_default;
5017 tj_max = TJMAX_DEFAULT;
5018 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
5023 void decode_feature_control_msr(void)
5025 unsigned long long msr;
5027 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
5028 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
5029 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
5032 void decode_misc_enable_msr(void)
5034 unsigned long long msr;
5039 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
5040 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
5042 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5043 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
5044 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
5045 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5046 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
5049 void decode_misc_feature_control(void)
5051 unsigned long long msr;
5053 if (!has_misc_feature_control)
5056 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
5058 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5059 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5060 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
5064 * Decode MSR_MISC_PWR_MGMT
5066 * Decode the bits according to the Nehalem documentation
5067 * bit[0] seems to continue to have same meaning going forward
5070 void decode_misc_pwr_mgmt_msr(void)
5072 unsigned long long msr;
5074 if (!do_nhm_platform_info)
5077 if (no_MSR_MISC_PWR_MGMT)
5080 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
5081 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
5083 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
5087 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5089 * This MSRs are present on Silvermont processors,
5090 * Intel Atom processor E3000 series (Baytrail), and friends.
5092 void decode_c6_demotion_policy_msr(void)
5094 unsigned long long msr;
5096 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5097 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5098 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5100 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5101 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5102 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5106 * When models are the same, for the purpose of turbostat, reuse
5108 unsigned int intel_model_duplicates(unsigned int model)
5112 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
5113 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
5114 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
5115 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5116 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5117 return INTEL_FAM6_NEHALEM;
5119 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
5120 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5121 return INTEL_FAM6_NEHALEM_EX;
5123 case INTEL_FAM6_XEON_PHI_KNM:
5124 return INTEL_FAM6_XEON_PHI_KNL;
5126 case INTEL_FAM6_BROADWELL_X:
5127 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
5128 return INTEL_FAM6_BROADWELL_X;
5130 case INTEL_FAM6_SKYLAKE_L:
5131 case INTEL_FAM6_SKYLAKE:
5132 case INTEL_FAM6_KABYLAKE_L:
5133 case INTEL_FAM6_KABYLAKE:
5134 case INTEL_FAM6_COMETLAKE_L:
5135 case INTEL_FAM6_COMETLAKE:
5136 return INTEL_FAM6_SKYLAKE_L;
5138 case INTEL_FAM6_ICELAKE_L:
5139 case INTEL_FAM6_ICELAKE_NNPI:
5140 case INTEL_FAM6_TIGERLAKE_L:
5141 case INTEL_FAM6_TIGERLAKE:
5142 case INTEL_FAM6_ROCKETLAKE:
5143 case INTEL_FAM6_LAKEFIELD:
5144 case INTEL_FAM6_ALDERLAKE:
5145 case INTEL_FAM6_ALDERLAKE_L:
5146 return INTEL_FAM6_CANNONLAKE_L;
5148 case INTEL_FAM6_ATOM_TREMONT_L:
5149 return INTEL_FAM6_ATOM_TREMONT;
5151 case INTEL_FAM6_ICELAKE_D:
5152 case INTEL_FAM6_SAPPHIRERAPIDS_X:
5153 return INTEL_FAM6_ICELAKE_X;
5158 void print_dev_latency(void)
5160 char *path = "/dev/cpu_dma_latency";
5165 fd = open(path, O_RDONLY);
5167 warn("fopen %s\n", path);
5171 retval = read(fd, (void *)&value, sizeof(int));
5172 if (retval != sizeof(int)) {
5173 warn("read %s\n", path);
5177 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
5183 * Linux-perf manages the the HW instructions-retired counter
5184 * by enabling when requested, and hiding rollover
5186 void linux_perf_init(void)
5188 if (!BIC_IS_ENABLED(BIC_IPC))
5191 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5194 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5195 if (fd_instr_count_percpu == NULL)
5196 err(-1, "calloc fd_instr_count_percpu");
5198 BIC_PRESENT(BIC_IPC);
5201 void process_cpuid()
5203 unsigned int eax, ebx, ecx, edx;
5204 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
5205 unsigned int has_turbo;
5206 unsigned long long ucode_patch = 0;
5208 eax = ebx = ecx = edx = 0;
5210 __cpuid(0, max_level, ebx, ecx, edx);
5212 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
5214 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5216 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5220 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5221 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
5223 __cpuid(1, fms, ebx, ecx, edx);
5224 family = (fms >> 8) & 0xf;
5225 model = (fms >> 4) & 0xf;
5226 stepping = fms & 0xf;
5228 family += (fms >> 20) & 0xff;
5230 model += ((fms >> 16) & 0xf) << 4;
5234 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
5235 warnx("get_msr(UCODE)\n");
5238 * check max extended function levels of CPUID.
5239 * This is needed to check for invariant TSC.
5240 * This check is valid for both Intel and AMD.
5242 ebx = ecx = edx = 0;
5243 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
5246 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
5247 family, model, stepping, family, model, stepping,
5248 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
5249 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
5250 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5251 ecx_flags & (1 << 0) ? "SSE3" : "-",
5252 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5253 ecx_flags & (1 << 6) ? "SMX" : "-",
5254 ecx_flags & (1 << 7) ? "EIST" : "-",
5255 ecx_flags & (1 << 8) ? "TM2" : "-",
5256 edx_flags & (1 << 4) ? "TSC" : "-",
5257 edx_flags & (1 << 5) ? "MSR" : "-",
5258 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
5259 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
5261 if (genuine_intel) {
5263 model = intel_model_duplicates(model);
5266 if (!(edx_flags & (1 << 5)))
5267 errx(1, "CPUID: no MSR");
5269 if (max_extended_level >= 0x80000007) {
5272 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5273 * this check is valid for both Intel and AMD
5275 __cpuid(0x80000007, eax, ebx, ecx, edx);
5276 has_invariant_tsc = edx & (1 << 8);
5280 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5281 * this check is valid for both Intel and AMD
5284 __cpuid(0x6, eax, ebx, ecx, edx);
5285 has_aperf = ecx & (1 << 0);
5287 BIC_PRESENT(BIC_Avg_MHz);
5288 BIC_PRESENT(BIC_Busy);
5289 BIC_PRESENT(BIC_Bzy_MHz);
5291 do_dts = eax & (1 << 0);
5293 BIC_PRESENT(BIC_CoreTmp);
5294 has_turbo = eax & (1 << 1);
5295 do_ptm = eax & (1 << 6);
5297 BIC_PRESENT(BIC_PkgTmp);
5298 has_hwp = eax & (1 << 7);
5299 has_hwp_notify = eax & (1 << 8);
5300 has_hwp_activity_window = eax & (1 << 9);
5301 has_hwp_epp = eax & (1 << 10);
5302 has_hwp_pkg = eax & (1 << 11);
5303 has_epb = ecx & (1 << 3);
5306 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
5307 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5308 has_aperf ? "" : "No-",
5309 has_turbo ? "" : "No-",
5310 do_dts ? "" : "No-",
5311 do_ptm ? "" : "No-",
5312 has_hwp ? "" : "No-",
5313 has_hwp_notify ? "" : "No-",
5314 has_hwp_activity_window ? "" : "No-",
5315 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
5318 decode_misc_enable_msr();
5320 if (max_level >= 0x7 && !quiet) {
5325 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5327 has_sgx = ebx & (1 << 2);
5328 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
5331 decode_feature_control_msr();
5334 if (max_level >= 0x15) {
5335 unsigned int eax_crystal;
5336 unsigned int ebx_tsc;
5339 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5341 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5342 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
5346 if (!quiet && (ebx != 0))
5347 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
5348 eax_crystal, ebx_tsc, crystal_hz);
5350 if (crystal_hz == 0)
5352 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5353 crystal_hz = 24000000; /* 24.0 MHz */
5355 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
5356 crystal_hz = 25000000; /* 25.0 MHz */
5358 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5359 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5360 crystal_hz = 19200000; /* 19.2 MHz */
5367 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
5369 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
5370 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
5374 if (max_level >= 0x16) {
5375 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5378 * CPUID 16H Base MHz, Max MHz, Bus MHz
5380 base_mhz = max_mhz = bus_mhz = edx = 0;
5382 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
5384 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
5385 base_mhz, max_mhz, bus_mhz);
5389 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5391 BIC_PRESENT(BIC_IRQ);
5392 BIC_PRESENT(BIC_TSC_MHz);
5394 if (probe_nhm_msrs(family, model)) {
5395 do_nhm_platform_info = 1;
5396 BIC_PRESENT(BIC_CPU_c1);
5397 BIC_PRESENT(BIC_CPU_c3);
5398 BIC_PRESENT(BIC_CPU_c6);
5399 BIC_PRESENT(BIC_SMI);
5401 do_snb_cstates = has_snb_msrs(family, model);
5404 BIC_PRESENT(BIC_CPU_c7);
5406 do_irtl_snb = has_snb_msrs(family, model);
5407 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
5408 BIC_PRESENT(BIC_Pkgpc2);
5409 if (pkg_cstate_limit >= PCL__3)
5410 BIC_PRESENT(BIC_Pkgpc3);
5411 if (pkg_cstate_limit >= PCL__6)
5412 BIC_PRESENT(BIC_Pkgpc6);
5413 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
5414 BIC_PRESENT(BIC_Pkgpc7);
5415 if (has_slv_msrs(family, model)) {
5416 BIC_NOT_PRESENT(BIC_Pkgpc2);
5417 BIC_NOT_PRESENT(BIC_Pkgpc3);
5418 BIC_PRESENT(BIC_Pkgpc6);
5419 BIC_NOT_PRESENT(BIC_Pkgpc7);
5420 BIC_PRESENT(BIC_Mod_c6);
5421 use_c1_residency_msr = 1;
5423 if (is_jvl(family, model)) {
5424 BIC_NOT_PRESENT(BIC_CPU_c3);
5425 BIC_NOT_PRESENT(BIC_CPU_c7);
5426 BIC_NOT_PRESENT(BIC_Pkgpc2);
5427 BIC_NOT_PRESENT(BIC_Pkgpc3);
5428 BIC_NOT_PRESENT(BIC_Pkgpc6);
5429 BIC_NOT_PRESENT(BIC_Pkgpc7);
5431 if (is_dnv(family, model)) {
5432 BIC_PRESENT(BIC_CPU_c1);
5433 BIC_NOT_PRESENT(BIC_CPU_c3);
5434 BIC_NOT_PRESENT(BIC_Pkgpc3);
5435 BIC_NOT_PRESENT(BIC_CPU_c7);
5436 BIC_NOT_PRESENT(BIC_Pkgpc7);
5437 use_c1_residency_msr = 1;
5439 if (is_skx(family, model) || is_icx(family, model)) {
5440 BIC_NOT_PRESENT(BIC_CPU_c3);
5441 BIC_NOT_PRESENT(BIC_Pkgpc3);
5442 BIC_NOT_PRESENT(BIC_CPU_c7);
5443 BIC_NOT_PRESENT(BIC_Pkgpc7);
5445 if (is_bdx(family, model)) {
5446 BIC_NOT_PRESENT(BIC_CPU_c7);
5447 BIC_NOT_PRESENT(BIC_Pkgpc7);
5449 if (has_c8910_msrs(family, model)) {
5450 if (pkg_cstate_limit >= PCL__8)
5451 BIC_PRESENT(BIC_Pkgpc8);
5452 if (pkg_cstate_limit >= PCL__9)
5453 BIC_PRESENT(BIC_Pkgpc9);
5454 if (pkg_cstate_limit >= PCL_10)
5455 BIC_PRESENT(BIC_Pkgpc10);
5457 do_irtl_hsw = has_c8910_msrs(family, model);
5458 if (has_skl_msrs(family, model)) {
5459 BIC_PRESENT(BIC_Totl_c0);
5460 BIC_PRESENT(BIC_Any_c0);
5461 BIC_PRESENT(BIC_GFX_c0);
5462 BIC_PRESENT(BIC_CPUGFX);
5464 do_slm_cstates = is_slm(family, model);
5465 do_knl_cstates = is_knl(family, model);
5467 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
5468 BIC_NOT_PRESENT(BIC_CPU_c3);
5471 decode_misc_pwr_mgmt_msr();
5473 if (!quiet && has_slv_msrs(family, model))
5474 decode_c6_demotion_policy_msr();
5476 rapl_probe(family, model);
5477 perf_limit_reasons_probe(family, model);
5478 automatic_cstate_conversion_probe(family, model);
5480 check_tcc_offset(model_orig);
5483 dump_cstate_pstate_config_info(family, model);
5486 print_dev_latency();
5488 dump_sysfs_cstate_config();
5490 dump_sysfs_pstate_config();
5492 if (has_skl_msrs(family, model) || is_ehl(family, model))
5493 calculate_tsc_tweak();
5495 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
5496 BIC_PRESENT(BIC_GFX_rc6);
5498 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
5499 BIC_PRESENT(BIC_GFXMHz);
5501 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
5502 BIC_PRESENT(BIC_GFXACTMHz);
5504 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
5505 BIC_PRESENT(BIC_CPU_LPI);
5507 BIC_NOT_PRESENT(BIC_CPU_LPI);
5509 if (!access(sys_lpi_file_sysfs, R_OK)) {
5510 sys_lpi_file = sys_lpi_file_sysfs;
5511 BIC_PRESENT(BIC_SYS_LPI);
5512 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
5513 sys_lpi_file = sys_lpi_file_debugfs;
5514 BIC_PRESENT(BIC_SYS_LPI);
5516 sys_lpi_file_sysfs = NULL;
5517 BIC_NOT_PRESENT(BIC_SYS_LPI);
5521 decode_misc_feature_control();
5527 * in /dev/cpu/ return success for names that are numbers
5528 * ie. filter out ".", "..", "microcode".
5530 int dir_filter(const struct dirent *dirp)
5532 if (isdigit(dirp->d_name[0]))
5538 int open_dev_cpu_msr(int dummy1)
5543 void topology_probe()
5546 int max_core_id = 0;
5547 int max_package_id = 0;
5549 int max_siblings = 0;
5551 /* Initialize num_cpus, max_cpu_num */
5554 for_all_proc_cpus(count_cpus);
5555 if (!summary_only && topo.num_cpus > 1)
5556 BIC_PRESENT(BIC_CPU);
5559 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
5561 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
5563 err(1, "calloc cpus");
5566 * Allocate and initialize cpu_present_set
5568 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
5569 if (cpu_present_set == NULL)
5570 err(3, "CPU_ALLOC");
5571 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5572 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5573 for_all_proc_cpus(mark_cpu_present);
5576 * Validate that all cpus in cpu_subset are also in cpu_present_set
5578 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5579 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5580 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
5581 err(1, "cpu%d not present", i);
5585 * Allocate and initialize cpu_affinity_set
5587 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
5588 if (cpu_affinity_set == NULL)
5589 err(3, "CPU_ALLOC");
5590 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5591 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5593 for_all_proc_cpus(init_thread_id);
5597 * find max_core_id, max_package_id
5599 for (i = 0; i <= topo.max_cpu_num; ++i) {
5602 if (cpu_is_not_present(i)) {
5604 fprintf(outf, "cpu%d NOT PRESENT\n", i);
5608 cpus[i].logical_cpu_id = i;
5610 /* get package information */
5611 cpus[i].physical_package_id = get_physical_package_id(i);
5612 if (cpus[i].physical_package_id > max_package_id)
5613 max_package_id = cpus[i].physical_package_id;
5615 /* get die information */
5616 cpus[i].die_id = get_die_id(i);
5617 if (cpus[i].die_id > max_die_id)
5618 max_die_id = cpus[i].die_id;
5620 /* get numa node information */
5621 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5622 if (cpus[i].physical_node_id > topo.max_node_num)
5623 topo.max_node_num = cpus[i].physical_node_id;
5625 /* get core information */
5626 cpus[i].physical_core_id = get_core_id(i);
5627 if (cpus[i].physical_core_id > max_core_id)
5628 max_core_id = cpus[i].physical_core_id;
5630 /* get thread information */
5631 siblings = get_thread_siblings(&cpus[i]);
5632 if (siblings > max_siblings)
5633 max_siblings = siblings;
5634 if (cpus[i].thread_id == 0)
5638 topo.cores_per_node = max_core_id + 1;
5640 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
5641 if (!summary_only && topo.cores_per_node > 1)
5642 BIC_PRESENT(BIC_Core);
5644 topo.num_die = max_die_id + 1;
5646 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
5647 if (!summary_only && topo.num_die > 1)
5648 BIC_PRESENT(BIC_Die);
5650 topo.num_packages = max_package_id + 1;
5652 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
5653 if (!summary_only && topo.num_packages > 1)
5654 BIC_PRESENT(BIC_Package);
5658 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
5659 if (!summary_only && topo.nodes_per_pkg > 1)
5660 BIC_PRESENT(BIC_Node);
5662 topo.threads_per_core = max_siblings;
5664 fprintf(outf, "max_siblings %d\n", max_siblings);
5669 for (i = 0; i <= topo.max_cpu_num; ++i) {
5670 if (cpu_is_not_present(i))
5673 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
5674 i, cpus[i].physical_package_id, cpus[i].die_id,
5675 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
5680 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
5683 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
5684 int num_threads = topo.threads_per_core * num_cores;
5686 *t = calloc(num_threads, sizeof(struct thread_data));
5690 for (i = 0; i < num_threads; i++)
5691 (*t)[i].cpu_id = -1;
5693 *c = calloc(num_cores, sizeof(struct core_data));
5697 for (i = 0; i < num_cores; i++)
5698 (*c)[i].core_id = -1;
5700 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
5704 for (i = 0; i < topo.num_packages; i++)
5705 (*p)[i].package_id = i;
5709 err(1, "calloc counters");
5715 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
5717 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
5719 int pkg_id = cpus[cpu_id].physical_package_id;
5720 int node_id = cpus[cpu_id].logical_node_id;
5721 int core_id = cpus[cpu_id].physical_core_id;
5722 int thread_id = cpus[cpu_id].thread_id;
5723 struct thread_data *t;
5724 struct core_data *c;
5727 /* Workaround for systems where physical_node_id==-1
5728 * and logical_node_id==(-1 - topo.num_cpus)
5733 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
5734 c = GET_CORE(core_base, core_id, node_id, pkg_id);
5735 p = GET_PKG(pkg_base, pkg_id);
5738 if (thread_id == 0) {
5739 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
5740 if (cpu_is_first_core_in_package(cpu_id))
5741 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
5744 c->core_id = core_id;
5745 p->package_id = pkg_id;
5748 int initialize_counters(int cpu_id)
5750 init_counter(EVEN_COUNTERS, cpu_id);
5751 init_counter(ODD_COUNTERS, cpu_id);
5755 void allocate_output_buffer()
5757 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
5758 outp = output_buffer;
5760 err(-1, "calloc output buffer");
5763 void allocate_fd_percpu(void)
5765 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5766 if (fd_percpu == NULL)
5767 err(-1, "calloc fd_percpu");
5770 void allocate_irq_buffers(void)
5772 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
5773 if (irq_column_2_cpu == NULL)
5774 err(-1, "calloc %d", topo.num_cpus);
5776 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5777 if (irqs_per_cpu == NULL)
5778 err(-1, "calloc %d", topo.max_cpu_num + 1);
5781 void setup_all_buffers(void)
5784 allocate_irq_buffers();
5785 allocate_fd_percpu();
5786 allocate_counters(&thread_even, &core_even, &package_even);
5787 allocate_counters(&thread_odd, &core_odd, &package_odd);
5788 allocate_output_buffer();
5789 for_all_proc_cpus(initialize_counters);
5792 void set_base_cpu(void)
5794 base_cpu = sched_getcpu();
5796 err(-ENODEV, "No valid cpus found");
5799 fprintf(outf, "base_cpu = %d\n", base_cpu);
5802 void turbostat_init()
5804 setup_all_buffers();
5807 check_permissions();
5812 for_all_cpus(print_hwp, ODD_COUNTERS);
5815 for_all_cpus(print_epb, ODD_COUNTERS);
5818 for_all_cpus(print_perf_limit, ODD_COUNTERS);
5821 for_all_cpus(print_rapl, ODD_COUNTERS);
5823 for_all_cpus(set_temperature_target, ODD_COUNTERS);
5825 for_all_cpus(get_cpu_type, ODD_COUNTERS);
5826 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
5829 for_all_cpus(print_thermal, ODD_COUNTERS);
5831 if (!quiet && do_irtl_snb)
5835 int fork_it(char **argv)
5840 snapshot_proc_sysfs_files();
5841 status = for_all_cpus(get_counters, EVEN_COUNTERS);
5842 first_counter_read = 0;
5845 /* clear affinity side-effect of get_counters() */
5846 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
5847 gettimeofday(&tv_even, (struct timezone *)NULL);
5852 execvp(argv[0], argv);
5853 err(errno, "exec %s", argv[0]);
5857 if (child_pid == -1)
5860 signal(SIGINT, SIG_IGN);
5861 signal(SIGQUIT, SIG_IGN);
5862 if (waitpid(child_pid, &status, 0) == -1)
5863 err(status, "waitpid");
5865 if (WIFEXITED(status))
5866 status = WEXITSTATUS(status);
5869 * n.b. fork_it() does not check for errors from for_all_cpus()
5870 * because re-starting is problematic when forking
5872 snapshot_proc_sysfs_files();
5873 for_all_cpus(get_counters, ODD_COUNTERS);
5874 gettimeofday(&tv_odd, (struct timezone *)NULL);
5875 timersub(&tv_odd, &tv_even, &tv_delta);
5876 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
5877 fprintf(outf, "%s: Counter reset detected\n", progname);
5879 compute_average(EVEN_COUNTERS);
5880 format_all_counters(EVEN_COUNTERS);
5883 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
5885 flush_output_stderr();
5890 int get_and_dump_counters(void)
5894 snapshot_proc_sysfs_files();
5895 status = for_all_cpus(get_counters, ODD_COUNTERS);
5899 status = for_all_cpus(dump_counters, ODD_COUNTERS);
5903 flush_output_stdout();
5908 void print_version()
5910 fprintf(outf, "turbostat version 21.03.12" " - Len Brown <lenb@kernel.org>\n");
5913 int add_counter(unsigned int msr_num, char *path, char *name,
5914 unsigned int width, enum counter_scope scope,
5915 enum counter_type type, enum counter_format format, int flags)
5917 struct msr_counter *msrp;
5919 msrp = calloc(1, sizeof(struct msr_counter));
5925 msrp->msr_num = msr_num;
5926 strncpy(msrp->name, name, NAME_BYTES - 1);
5928 strncpy(msrp->path, path, PATH_BYTES - 1);
5929 msrp->width = width;
5931 msrp->format = format;
5932 msrp->flags = flags;
5937 msrp->next = sys.tp;
5939 sys.added_thread_counters++;
5940 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
5941 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
5947 msrp->next = sys.cp;
5949 sys.added_core_counters++;
5950 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
5951 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
5957 msrp->next = sys.pp;
5959 sys.added_package_counters++;
5960 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
5961 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
5970 void parse_add_command(char *add_command)
5974 char name_buffer[NAME_BYTES] = "";
5977 enum counter_scope scope = SCOPE_CPU;
5978 enum counter_type type = COUNTER_CYCLES;
5979 enum counter_format format = FORMAT_DELTA;
5981 while (add_command) {
5983 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
5986 if (sscanf(add_command, "msr%d", &msr_num) == 1)
5989 if (*add_command == '/') {
5994 if (sscanf(add_command, "u%d", &width) == 1) {
5995 if ((width == 32) || (width == 64))
5999 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6003 if (!strncmp(add_command, "core", strlen("core"))) {
6007 if (!strncmp(add_command, "package", strlen("package"))) {
6008 scope = SCOPE_PACKAGE;
6011 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6012 type = COUNTER_CYCLES;
6015 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6016 type = COUNTER_SECONDS;
6019 if (!strncmp(add_command, "usec", strlen("usec"))) {
6020 type = COUNTER_USEC;
6023 if (!strncmp(add_command, "raw", strlen("raw"))) {
6024 format = FORMAT_RAW;
6027 if (!strncmp(add_command, "delta", strlen("delta"))) {
6028 format = FORMAT_DELTA;
6031 if (!strncmp(add_command, "percent", strlen("percent"))) {
6032 format = FORMAT_PERCENT;
6036 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6039 eos = strchr(name_buffer, ',');
6046 add_command = strchr(add_command, ',');
6048 *add_command = '\0';
6053 if ((msr_num == 0) && (path == NULL)) {
6054 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
6058 /* generate default column header */
6059 if (*name_buffer == '\0') {
6061 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6063 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6066 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
6075 int is_deferred_skip(char *name)
6079 for (i = 0; i < deferred_skip_index; ++i)
6080 if (!strcmp(name, deferred_skip_names[i]))
6085 void probe_sysfs(void)
6093 if (!DO_BIC(BIC_sysfs))
6096 for (state = 10; state >= 0; --state) {
6098 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6099 input = fopen(path, "r");
6102 if (!fgets(name_buf, sizeof(name_buf), input))
6103 err(1, "%s: failed to read file", path);
6105 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6106 sp = strchr(name_buf, '-');
6108 sp = strchrnul(name_buf, '\n');
6112 remove_underbar(name_buf);
6116 sprintf(path, "cpuidle/state%d/time", state);
6118 if (is_deferred_skip(name_buf))
6121 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
6124 for (state = 10; state >= 0; --state) {
6126 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6127 input = fopen(path, "r");
6130 if (!fgets(name_buf, sizeof(name_buf), input))
6131 err(1, "%s: failed to read file", path);
6132 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6133 sp = strchr(name_buf, '-');
6135 sp = strchrnul(name_buf, '\n');
6139 remove_underbar(name_buf);
6141 sprintf(path, "cpuidle/state%d/usage", state);
6143 if (is_deferred_skip(name_buf))
6146 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
6152 * parse cpuset with following syntax
6153 * 1,2,4..6,8-10 and set bits in cpu_subset
6155 void parse_cpu_command(char *optarg)
6157 unsigned int start, end;
6160 if (!strcmp(optarg, "core")) {
6166 if (!strcmp(optarg, "package")) {
6172 if (show_core_only || show_pkg_only)
6175 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6176 if (cpu_subset == NULL)
6177 err(3, "CPU_ALLOC");
6178 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6180 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6184 while (next && *next) {
6186 if (*next == '-') /* no negative cpu numbers */
6189 start = strtoul(next, &next, 10);
6191 if (start >= CPU_SUBSET_MAXCPUS)
6193 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6204 next += 1; /* start range */
6205 } else if (*next == '.') {
6208 next += 1; /* start range */
6213 end = strtoul(next, &next, 10);
6217 while (++start <= end) {
6218 if (start >= CPU_SUBSET_MAXCPUS)
6220 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6225 else if (*next != '\0')
6232 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6237 void cmdline(int argc, char **argv)
6240 int option_index = 0;
6241 static struct option long_options[] = {
6242 { "add", required_argument, 0, 'a' },
6243 { "cpu", required_argument, 0, 'c' },
6244 { "Dump", no_argument, 0, 'D' },
6245 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6246 { "enable", required_argument, 0, 'e' },
6247 { "interval", required_argument, 0, 'i' },
6248 { "IPC", no_argument, 0, 'I' },
6249 { "num_iterations", required_argument, 0, 'n' },
6250 { "help", no_argument, 0, 'h' },
6251 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6252 { "Joules", no_argument, 0, 'J' },
6253 { "list", no_argument, 0, 'l' },
6254 { "out", required_argument, 0, 'o' },
6255 { "quiet", no_argument, 0, 'q' },
6256 { "show", required_argument, 0, 's' },
6257 { "Summary", no_argument, 0, 'S' },
6258 { "TCC", required_argument, 0, 'T' },
6259 { "version", no_argument, 0, 'v' },
6265 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
6268 parse_add_command(optarg);
6271 parse_cpu_command(optarg);
6277 /* --enable specified counter */
6278 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
6282 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6286 * --hide: do not show those specified
6287 * multiple invocations simply clear more bits in enabled mask
6289 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
6297 double interval = strtod(optarg, NULL);
6299 if (interval < 0.001) {
6300 fprintf(outf, "interval %f seconds is too small\n", interval);
6304 interval_tv.tv_sec = interval_ts.tv_sec = interval;
6305 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
6306 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
6313 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6318 outf = fopen_or_die(optarg, "w");
6324 num_iterations = strtod(optarg, NULL);
6326 if (num_iterations <= 0) {
6327 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
6333 * --show: show only those specified
6334 * The 1st invocation will clear and replace the enabled mask
6335 * subsequent invocations can add to it.
6338 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6340 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6347 tj_max_override = atoi(optarg);
6357 int main(int argc, char **argv)
6360 cmdline(argc, argv);
6369 /* dump counters and exit */
6371 return get_and_dump_counters();
6373 /* list header and exit */
6374 if (list_header_only) {
6376 flush_output_stdout();
6382 * if any params left, it must be a command to fork
6385 return fork_it(argv + optind);