tools/perf/pmu-events/empty-pmu-events.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * An empty pmu-events.c file used when there is no architecture json files in
   4  * arch or when the jevents.py script cannot be run.
   5  *
   6  * The test cpu/soc is provided for testing.
   7  */
   8 #include "pmu-events/pmu-events.h"
   9
  10 static const struct pmu_event pme_test_soc_cpu[] = {
  11         {
  12                 .name = "l3_cache_rd",
  13                 .event = "event=0x40",
  14                 .desc = "L3 cache access, read",
  15                 .topic = "cache",
  16                 .long_desc = "Attributable Level 3 cache access, read",
  17         },
  18         {
  19                 .name = "segment_reg_loads.any",
  20                 .event = "event=0x6,period=200000,umask=0x80",
  21                 .desc = "Number of segment register loads",
  22                 .topic = "other",
  23         },
  24         {
  25                 .name = "dispatch_blocked.any",
  26                 .event = "event=0x9,period=200000,umask=0x20",
  27                 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
  28                 .topic = "other",
  29         },
  30         {
  31                 .name = "eist_trans",
  32                 .event = "event=0x3a,period=200000,umask=0x0",
  33                 .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
  34                 .topic = "other",
  35         },
  36         {
  37                 .name = "uncore_hisi_ddrc.flux_wcmd",
  38                 .event = "event=0x2",
  39                 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
  40                 .topic = "uncore",
  41                 .long_desc = "DDRC write commands",
  42                 .pmu = "hisi_sccl,ddrc",
  43         },
  44         {
  45                 .name = "unc_cbo_xsnp_response.miss_eviction",
  46                 .event = "event=0x22,umask=0x81",
  47                 .desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ",
  48                 .topic = "uncore",
  49                 .long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
  50                 .pmu = "uncore_cbox",
  51         },
  52         {
  53                 .name = "event-hyphen",
  54                 .event = "event=0xe0,umask=0x00",
  55                 .desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ",
  56                 .topic = "uncore",
  57                 .long_desc = "UNC_CBO_HYPHEN",
  58                 .pmu = "uncore_cbox",
  59         },
  60         {
  61                 .name = "event-two-hyph",
  62                 .event = "event=0xc0,umask=0x00",
  63                 .desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ",
  64                 .topic = "uncore",
  65                 .long_desc = "UNC_CBO_TWO_HYPH",
  66                 .pmu = "uncore_cbox",
  67         },
  68         {
  69                 .name = "uncore_hisi_l3c.rd_hit_cpipe",
  70                 .event = "event=0x7",
  71                 .desc = "Total read hits. Unit: hisi_sccl,l3c ",
  72                 .topic = "uncore",
  73                 .long_desc = "Total read hits",
  74                 .pmu = "hisi_sccl,l3c",
  75         },
  76         {
  77                 .name = "uncore_imc_free_running.cache_miss",
  78                 .event = "event=0x12",
  79                 .desc = "Total cache misses. Unit: uncore_imc_free_running ",
  80                 .topic = "uncore",
  81                 .long_desc = "Total cache misses",
  82                 .pmu = "uncore_imc_free_running",
  83         },
  84         {
  85                 .name = "uncore_imc.cache_hits",
  86                 .event = "event=0x34",
  87                 .desc = "Total cache hits. Unit: uncore_imc ",
  88                 .topic = "uncore",
  89                 .long_desc = "Total cache hits",
  90                 .pmu = "uncore_imc",
  91         },
  92         {
  93                 .name = "bp_l1_btb_correct",
  94                 .event = "event=0x8a",
  95                 .desc = "L1 BTB Correction",
  96                 .topic = "branch",
  97         },
  98         {
  99                 .name = "bp_l2_btb_correct",
 100                 .event = "event=0x8b",
 101                 .desc = "L2 BTB Correction",
 102                 .topic = "branch",
 103         },
 104         {
 105                 .name = 0,
 106                 .event = 0,
 107                 .desc = 0,
 108         },
 109 };
 110
 111 const struct pmu_events_map pmu_events_map[] = {
 112         {
 113                 .arch = "testarch",
 114                 .cpuid = "testcpu",
 115                 .version = "v1",
 116                 .type = "core",
 117                 .table = pme_test_soc_cpu,
 118         },
 119         {
 120                 .arch = 0,
 121                 .cpuid = 0,
 122                 .version = 0,
 123                 .type = 0,
 124                 .table = 0,
 125         },
 126 };
 127
 128 static const struct pmu_event pme_test_soc_sys[] = {
 129         {
 130                 .name = "sys_ddr_pmu.write_cycles",
 131                 .event = "event=0x2b",
 132                 .desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ",
 133                 .compat = "v8",
 134                 .topic = "uncore",
 135                 .pmu = "uncore_sys_ddr_pmu",
 136         },
 137         {
 138                 .name = "sys_ccn_pmu.read_cycles",
 139                 .event = "config=0x2c",
 140                 .desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ",
 141                 .compat = "0x01",
 142                 .topic = "uncore",
 143                 .pmu = "uncore_sys_ccn_pmu",
 144         },
 145         {
 146                 .name = 0,
 147                 .event = 0,
 148                 .desc = 0,
 149         },
 150 };
 151
 152 const struct pmu_sys_events pmu_sys_event_tables[] = {
 153         {
 154                 .table = pme_test_soc_sys,
 155                 .name = "pme_test_soc_sys",
 156         },
 157         {
 158                 .table = 0
 159         },
 160 };