tools/perf/pmu-events/empty-pmu-events.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * An empty pmu-events.c file used when there is no architecture json files in
   4  * arch or when the jevents.py script cannot be run.
   5  *
   6  * The test cpu/soc is provided for testing.
   7  */
   8 #include "pmu-events/pmu-events.h"
   9 #include "util/header.h"
  10 #include "util/pmu.h"
  11 #include <string.h>
  12 #include <stddef.h>
  13
  14 static const struct pmu_event pme_test_soc_cpu[] = {
  15         {
  16                 .name = "l3_cache_rd",
  17                 .event = "event=0x40",
  18                 .desc = "L3 cache access, read",
  19                 .topic = "cache",
  20                 .long_desc = "Attributable Level 3 cache access, read",
  21         },
  22         {
  23                 .name = "segment_reg_loads.any",
  24                 .event = "event=0x6,period=200000,umask=0x80",
  25                 .desc = "Number of segment register loads",
  26                 .topic = "other",
  27         },
  28         {
  29                 .name = "dispatch_blocked.any",
  30                 .event = "event=0x9,period=200000,umask=0x20",
  31                 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
  32                 .topic = "other",
  33         },
  34         {
  35                 .name = "eist_trans",
  36                 .event = "event=0x3a,period=200000,umask=0x0",
  37                 .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
  38                 .topic = "other",
  39         },
  40         {
  41                 .name = "uncore_hisi_ddrc.flux_wcmd",
  42                 .event = "event=0x2",
  43                 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
  44                 .topic = "uncore",
  45                 .long_desc = "DDRC write commands",
  46                 .pmu = "hisi_sccl,ddrc",
  47         },
  48         {
  49                 .name = "unc_cbo_xsnp_response.miss_eviction",
  50                 .event = "event=0x22,umask=0x81",
  51                 .desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ",
  52                 .topic = "uncore",
  53                 .long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
  54                 .pmu = "uncore_cbox",
  55         },
  56         {
  57                 .name = "event-hyphen",
  58                 .event = "event=0xe0,umask=0x00",
  59                 .desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ",
  60                 .topic = "uncore",
  61                 .long_desc = "UNC_CBO_HYPHEN",
  62                 .pmu = "uncore_cbox",
  63         },
  64         {
  65                 .name = "event-two-hyph",
  66                 .event = "event=0xc0,umask=0x00",
  67                 .desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ",
  68                 .topic = "uncore",
  69                 .long_desc = "UNC_CBO_TWO_HYPH",
  70                 .pmu = "uncore_cbox",
  71         },
  72         {
  73                 .name = "uncore_hisi_l3c.rd_hit_cpipe",
  74                 .event = "event=0x7",
  75                 .desc = "Total read hits. Unit: hisi_sccl,l3c ",
  76                 .topic = "uncore",
  77                 .long_desc = "Total read hits",
  78                 .pmu = "hisi_sccl,l3c",
  79         },
  80         {
  81                 .name = "uncore_imc_free_running.cache_miss",
  82                 .event = "event=0x12",
  83                 .desc = "Total cache misses. Unit: uncore_imc_free_running ",
  84                 .topic = "uncore",
  85                 .long_desc = "Total cache misses",
  86                 .pmu = "uncore_imc_free_running",
  87         },
  88         {
  89                 .name = "uncore_imc.cache_hits",
  90                 .event = "event=0x34",
  91                 .desc = "Total cache hits. Unit: uncore_imc ",
  92                 .topic = "uncore",
  93                 .long_desc = "Total cache hits",
  94                 .pmu = "uncore_imc",
  95         },
  96         {
  97                 .name = "bp_l1_btb_correct",
  98                 .event = "event=0x8a",
  99                 .desc = "L1 BTB Correction",
 100                 .topic = "branch",
 101         },
 102         {
 103                 .name = "bp_l2_btb_correct",
 104                 .event = "event=0x8b",
 105                 .desc = "L2 BTB Correction",
 106                 .topic = "branch",
 107         },
 108         {
 109                 .name = 0,
 110                 .event = 0,
 111                 .desc = 0,
 112         },
 113 };
 114
 115
 116 /*
 117  * Map a CPU to its table of PMU events. The CPU is identified by the
 118  * cpuid field, which is an arch-specific identifier for the CPU.
 119  * The identifier specified in tools/perf/pmu-events/arch/xxx/mapfile
 120  * must match the get_cpuid_str() in tools/perf/arch/xxx/util/header.c)
 121  *
 122  * The  cpuid can contain any character other than the comma.
 123  */
 124 struct pmu_events_map {
 125         const char *arch;
 126         const char *cpuid;
 127         const struct pmu_event *table;
 128 };
 129
 130 /*
 131  * Global table mapping each known CPU for the architecture to its
 132  * table of PMU events.
 133  */
 134 static const struct pmu_events_map pmu_events_map[] = {
 135         {
 136                 .arch = "testarch",
 137                 .cpuid = "testcpu",
 138                 .table = pme_test_soc_cpu,
 139         },
 140         {
 141                 .arch = 0,
 142                 .cpuid = 0,
 143                 .table = 0,
 144         },
 145 };
 146
 147 static const struct pmu_event pme_test_soc_sys[] = {
 148         {
 149                 .name = "sys_ddr_pmu.write_cycles",
 150                 .event = "event=0x2b",
 151                 .desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ",
 152                 .compat = "v8",
 153                 .topic = "uncore",
 154                 .pmu = "uncore_sys_ddr_pmu",
 155         },
 156         {
 157                 .name = "sys_ccn_pmu.read_cycles",
 158                 .event = "config=0x2c",
 159                 .desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ",
 160                 .compat = "0x01",
 161                 .topic = "uncore",
 162                 .pmu = "uncore_sys_ccn_pmu",
 163         },
 164         {
 165                 .name = 0,
 166                 .event = 0,
 167                 .desc = 0,
 168         },
 169 };
 170
 171 struct pmu_sys_events {
 172         const char *name;
 173         const struct pmu_event *table;
 174 };
 175
 176 static const struct pmu_sys_events pmu_sys_event_tables[] = {
 177         {
 178                 .table = pme_test_soc_sys,
 179                 .name = "pme_test_soc_sys",
 180         },
 181         {
 182                 .table = 0
 183         },
 184 };
 185
 186 const struct pmu_event *perf_pmu__find_table(struct perf_pmu *pmu)
 187 {
 188         const struct pmu_event *table = NULL;
 189         char *cpuid = perf_pmu__getcpuid(pmu);
 190         int i;
 191
 192         /* on some platforms which uses cpus map, cpuid can be NULL for
 193          * PMUs other than CORE PMUs.
 194          */
 195         if (!cpuid)
 196                 return NULL;
 197
 198         i = 0;
 199         for (;;) {
 200                 const struct pmu_events_map *map = &pmu_events_map[i++];
 201
 202                 if (!map->table)
 203                         break;
 204
 205                 if (!strcmp_cpuid_str(map->cpuid, cpuid)) {
 206                         table = map->table;
 207                         break;
 208                 }
 209         }
 210         free(cpuid);
 211         return table;
 212 }
 213
 214 const struct pmu_event *find_core_events_table(const char *arch, const char *cpuid)
 215 {
 216         for (const struct pmu_events_map *tables = &pmu_events_map[0];
 217              tables->table;
 218              tables++) {
 219                 if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(tables->cpuid, cpuid))
 220                         return tables->table;
 221         }
 222         return NULL;
 223 }
 224
 225 int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data)
 226 {
 227         for (const struct pmu_events_map *tables = &pmu_events_map[0];
 228              tables->table;
 229              tables++) {
 230                 for (const struct pmu_event *pe = &tables->table[0];
 231                      pe->name || pe->metric_group || pe->metric_name;
 232                      pe++) {
 233                         int ret = fn(pe, &tables->table[0], data);
 234
 235                         if (ret)
 236                                 return ret;
 237                 }
 238         }
 239         return 0;
 240 }
 241
 242 const struct pmu_event *find_sys_events_table(const char *name)
 243 {
 244         for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
 245              tables->name;
 246              tables++) {
 247                 if (!strcmp(tables->name, name))
 248                         return tables->table;
 249         }
 250         return NULL;
 251 }
 252
 253 int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data)
 254 {
 255         for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
 256              tables->name;
 257              tables++) {
 258                 for (const struct pmu_event *pe = &tables->table[0];
 259                      pe->name || pe->metric_group || pe->metric_name;
 260                      pe++) {
 261                         int ret = fn(pe, &tables->table[0], data);
 262
 263                         if (ret)
 264                                 return ret;
 265                 }
 266         }
 267         return 0;
 268 }