tools/perf/pmu-events/empty-pmu-events.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * An empty pmu-events.c file used when there is no architecture json files in
   4  * arch or when the jevents.py script cannot be run.
   5  *
   6  * The test cpu/soc is provided for testing.
   7  */
   8 #include "pmu-events/pmu-events.h"
   9 #include <string.h>
  10 #include <stddef.h>
  11
  12 static const struct pmu_event pme_test_soc_cpu[] = {
  13         {
  14                 .name = "l3_cache_rd",
  15                 .event = "event=0x40",
  16                 .desc = "L3 cache access, read",
  17                 .topic = "cache",
  18                 .long_desc = "Attributable Level 3 cache access, read",
  19         },
  20         {
  21                 .name = "segment_reg_loads.any",
  22                 .event = "event=0x6,period=200000,umask=0x80",
  23                 .desc = "Number of segment register loads",
  24                 .topic = "other",
  25         },
  26         {
  27                 .name = "dispatch_blocked.any",
  28                 .event = "event=0x9,period=200000,umask=0x20",
  29                 .desc = "Memory cluster signals to block micro-op dispatch for any reason",
  30                 .topic = "other",
  31         },
  32         {
  33                 .name = "eist_trans",
  34                 .event = "event=0x3a,period=200000,umask=0x0",
  35                 .desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
  36                 .topic = "other",
  37         },
  38         {
  39                 .name = "uncore_hisi_ddrc.flux_wcmd",
  40                 .event = "event=0x2",
  41                 .desc = "DDRC write commands. Unit: hisi_sccl,ddrc ",
  42                 .topic = "uncore",
  43                 .long_desc = "DDRC write commands",
  44                 .pmu = "hisi_sccl,ddrc",
  45         },
  46         {
  47                 .name = "unc_cbo_xsnp_response.miss_eviction",
  48                 .event = "event=0x22,umask=0x81",
  49                 .desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox ",
  50                 .topic = "uncore",
  51                 .long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
  52                 .pmu = "uncore_cbox",
  53         },
  54         {
  55                 .name = "event-hyphen",
  56                 .event = "event=0xe0,umask=0x00",
  57                 .desc = "UNC_CBO_HYPHEN. Unit: uncore_cbox ",
  58                 .topic = "uncore",
  59                 .long_desc = "UNC_CBO_HYPHEN",
  60                 .pmu = "uncore_cbox",
  61         },
  62         {
  63                 .name = "event-two-hyph",
  64                 .event = "event=0xc0,umask=0x00",
  65                 .desc = "UNC_CBO_TWO_HYPH. Unit: uncore_cbox ",
  66                 .topic = "uncore",
  67                 .long_desc = "UNC_CBO_TWO_HYPH",
  68                 .pmu = "uncore_cbox",
  69         },
  70         {
  71                 .name = "uncore_hisi_l3c.rd_hit_cpipe",
  72                 .event = "event=0x7",
  73                 .desc = "Total read hits. Unit: hisi_sccl,l3c ",
  74                 .topic = "uncore",
  75                 .long_desc = "Total read hits",
  76                 .pmu = "hisi_sccl,l3c",
  77         },
  78         {
  79                 .name = "uncore_imc_free_running.cache_miss",
  80                 .event = "event=0x12",
  81                 .desc = "Total cache misses. Unit: uncore_imc_free_running ",
  82                 .topic = "uncore",
  83                 .long_desc = "Total cache misses",
  84                 .pmu = "uncore_imc_free_running",
  85         },
  86         {
  87                 .name = "uncore_imc.cache_hits",
  88                 .event = "event=0x34",
  89                 .desc = "Total cache hits. Unit: uncore_imc ",
  90                 .topic = "uncore",
  91                 .long_desc = "Total cache hits",
  92                 .pmu = "uncore_imc",
  93         },
  94         {
  95                 .name = "bp_l1_btb_correct",
  96                 .event = "event=0x8a",
  97                 .desc = "L1 BTB Correction",
  98                 .topic = "branch",
  99         },
 100         {
 101                 .name = "bp_l2_btb_correct",
 102                 .event = "event=0x8b",
 103                 .desc = "L2 BTB Correction",
 104                 .topic = "branch",
 105         },
 106         {
 107                 .name = 0,
 108                 .event = 0,
 109                 .desc = 0,
 110         },
 111 };
 112
 113 const struct pmu_events_map pmu_events_map[] = {
 114         {
 115                 .arch = "testarch",
 116                 .cpuid = "testcpu",
 117                 .table = pme_test_soc_cpu,
 118         },
 119         {
 120                 .arch = 0,
 121                 .cpuid = 0,
 122                 .table = 0,
 123         },
 124 };
 125
 126 static const struct pmu_event pme_test_soc_sys[] = {
 127         {
 128                 .name = "sys_ddr_pmu.write_cycles",
 129                 .event = "event=0x2b",
 130                 .desc = "ddr write-cycles event. Unit: uncore_sys_ddr_pmu ",
 131                 .compat = "v8",
 132                 .topic = "uncore",
 133                 .pmu = "uncore_sys_ddr_pmu",
 134         },
 135         {
 136                 .name = "sys_ccn_pmu.read_cycles",
 137                 .event = "config=0x2c",
 138                 .desc = "ccn read-cycles event. Unit: uncore_sys_ccn_pmu ",
 139                 .compat = "0x01",
 140                 .topic = "uncore",
 141                 .pmu = "uncore_sys_ccn_pmu",
 142         },
 143         {
 144                 .name = 0,
 145                 .event = 0,
 146                 .desc = 0,
 147         },
 148 };
 149
 150 struct pmu_sys_events {
 151         const char *name;
 152         const struct pmu_event *table;
 153 };
 154
 155 static const struct pmu_sys_events pmu_sys_event_tables[] = {
 156         {
 157                 .table = pme_test_soc_sys,
 158                 .name = "pme_test_soc_sys",
 159         },
 160         {
 161                 .table = 0
 162         },
 163 };
 164
 165 const struct pmu_event *find_sys_events_table(const char *name)
 166 {
 167         for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
 168              tables->name;
 169              tables++) {
 170                 if (!strcmp(tables->name, name))
 171                         return tables->table;
 172         }
 173         return NULL;
 174 }
 175
 176 int pmu_for_each_sys_event(pmu_event_iter_fn fn, void *data)
 177 {
 178         for (const struct pmu_sys_events *tables = &pmu_sys_event_tables[0];
 179              tables->name;
 180              tables++) {
 181                 for (const struct pmu_event *pe = &tables->table[0];
 182                      pe->name || pe->metric_group || pe->metric_name;
 183                      pe++) {
 184                         int ret = fn(pe, data);
 185
 186                         if (ret)
 187                                 return ret;
 188                 }
 189         }
 190         return 0;
 191 }