4 "EventName": "PM_EXEC_STALL_DMISS_L2L3",
5 "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
9 "EventName": "PM_EXEC_STALL_LOAD_FINISH",
10 "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ."
14 "EventName": "PM_RUN_CYC_SMT2_MODE",
15 "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
19 "EventName": "PM_RUN_INST_CMPL_CONC",
20 "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
24 "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
25 "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
29 "EventName": "PM_EXEC_STALL_LOAD",
30 "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
34 "EventName": "PM_EXEC_STALL_PTESYNC",
35 "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
39 "EventName": "PM_THRESH_EXC_128",
40 "BriefDescription": "Threshold counter exceeded a value of 128."
44 "EventName": "PM_BR_MPRED_CMPL",
45 "BriefDescription": "A mispredicted branch completed. Includes direction and target."