6 perf-intel-pt - Support for Intel Processor Trace within perf tools
11 'perf record' -e intel_pt//
16 Intel Processor Trace (Intel PT) is an extension of Intel Architecture that
17 collects information about software execution such as control flow, execution
18 modes and timings and formats it into highly compressed binary packets.
19 Technical details are documented in the Intel 64 and IA-32 Architectures
20 Software Developer Manuals, Chapter 36 Intel Processor Trace.
22 Intel PT is first supported in Intel Core M and 5th generation Intel Core
23 processors that are based on the Intel micro-architecture code name Broadwell.
25 Trace data is collected by 'perf record' and stored within the perf.data file.
26 See below for options to 'perf record'.
28 Trace data must be 'decoded' which involves walking the object code and matching
29 the trace data packets. For example a TNT packet only tells whether a
30 conditional branch was taken or not taken, so to make use of that packet the
31 decoder must know precisely which instruction was being executed.
33 Decoding is done on-the-fly. The decoder outputs samples in the same format as
34 samples output by perf hardware events, for example as though the "instructions"
35 or "branches" events had been recorded. Presently 3 tools support this:
36 'perf script', 'perf report' and 'perf inject'. See below for more information
39 The main distinguishing feature of Intel PT is that the decoder can determine
40 the exact flow of software execution. Intel PT can be used to understand why
41 and how did software get to a certain point, or behave a certain way. The
42 software does not have to be recompiled, so Intel PT works with debug or release
43 builds, however the executed images are needed - which makes use in JIT-compiled
44 environments, or with self-modified code, a challenge. Also symbols need to be
45 provided to make sense of addresses.
47 A limitation of Intel PT is that it produces huge amounts of trace data
48 (hundreds of megabytes per second per core) which takes a long time to decode,
49 for example two or three orders of magnitude longer than it took to collect.
50 Another limitation is the performance impact of tracing, something that will
51 vary depending on the use-case and architecture.
57 It is important to start small. That is because it is easy to capture vastly
58 more data than can possibly be processed.
60 The simplest thing to do with Intel PT is userspace profiling of small programs.
61 Data is captured with 'perf record' e.g. to trace 'ls' userspace-only:
63 perf record -e intel_pt//u ls
65 And profiled with 'perf report' e.g.
69 To also trace kernel space presents a problem, namely kernel self-modifying
70 code. A fairly good kernel image is available in /proc/kcore but to get an
71 accurate image a copy of /proc/kcore needs to be made under the same conditions
72 as the data capture. 'perf record' can make a copy of /proc/kcore if the option
73 --kcore is used, but access to /proc/kcore is restricted e.g.
75 sudo perf record -o pt_ls --kcore -e intel_pt// -- ls
77 which will create a directory named 'pt_ls' and put the perf.data file (named
78 simply 'data') and copies of /proc/kcore, /proc/kallsyms and /proc/modules into
79 it. The other tools understand the directory format, so to use 'perf report'
82 sudo perf report -i pt_ls
84 Because samples are synthesized after-the-fact, the sampling period can be
85 selected for reporting. e.g. sample every microsecond
87 sudo perf report pt_ls --itrace=i1usge
89 See the sections below for more information about the --itrace option.
91 Beware the smaller the period, the more samples that are produced, and the
92 longer it takes to process them.
94 Also note that the coarseness of Intel PT timing information will start to
95 distort the statistical value of the sampling as the sampling period becomes
98 To represent software control flow, "branches" samples are produced. By default
99 a branch sample is synthesized for every single branch. To get an idea what
100 data is available you can use the 'perf script' tool with all itrace sampling
101 options, which will list all the samples.
103 perf record -e intel_pt//u ls
104 perf script --itrace=ibxwpe
106 An interesting field that is not printed by default is 'flags' which can be
107 displayed as follows:
109 perf script --itrace=ibxwpe -F+flags
111 The flags are "bcrosyiABEx" which stand for branch, call, return, conditional,
112 system, asynchronous, interrupt, transaction abort, trace begin, trace end, and
113 in transaction, respectively.
115 Another interesting field that is not printed by default is 'ipc' which can be
116 displayed as follows:
118 perf script --itrace=be -F+ipc
120 There are two ways that instructions-per-cycle (IPC) can be calculated depending
123 If the 'cyc' config term (see config terms section below) was used, then IPC is
124 calculated using the cycle count from CYC packets, otherwise MTC packets are
125 used - refer to the 'mtc' config term. When MTC is used, however, the values
126 are less accurate because the timing is less accurate.
128 Because Intel PT does not update the cycle count on every branch or instruction,
129 the values will often be zero. When there are values, they will be the number
130 of instructions and number of cycles since the last update, and thus represent
131 the average IPC since the last IPC for that event type. Note IPC for "branches"
132 events is calculated separately from IPC for "instructions" events.
134 Also note that the IPC instruction count may or may not include the current
135 instruction. If the cycle count is associated with an asynchronous branch
136 (e.g. page fault or interrupt), then the instruction count does not include the
137 current instruction, otherwise it does. That is consistent with whether or not
138 that instruction has retired when the cycle count is updated.
140 Another note, in the case of "branches" events, non-taken branches are not
141 presently sampled, so IPC values for them do not appear e.g. a CYC packet with a
142 TNT packet that starts with a non-taken branch. To see every possible IPC
143 value, "instructions" events can be used e.g. --itrace=i0ns
145 While it is possible to create scripts to analyze the data, an alternative
146 approach is available to export the data to a sqlite or postgresql database.
147 Refer to script export-to-sqlite.py or export-to-postgresql.py for more details,
148 and to script exported-sql-viewer.py for an example of using the database.
150 There is also script intel-pt-events.py which provides an example of how to
151 unpack the raw data for power events and PTWRITE.
153 As mentioned above, it is easy to capture too much data. One way to limit the
154 data captured is to use 'snapshot' mode which is explained further below.
155 Refer to 'new snapshot option' and 'Intel PT modes of operation' further below.
157 Another problem that will be experienced is decoder errors. They can be caused
158 by inability to access the executed image, self-modified or JIT-ed code, or the
159 inability to match side-band information (such as context switches and mmaps)
160 which results in the decoder not knowing what code was executed.
162 There is also the problem of perf not being able to copy the data fast enough,
163 resulting in data lost because the buffer was full. See 'Buffer handling' below
173 The Intel PT kernel driver creates a new PMU for Intel PT. PMU events are
174 selected by providing the PMU name followed by the "config" separated by slashes.
175 An enhancement has been made to allow default "config" e.g. the option
179 will use a default config value. Currently that is the same as
181 -e intel_pt/tsc,noretcomp=0/
185 -e intel_pt/tsc=1,noretcomp=0/
187 Note there are now new config terms - see section 'config terms' further below.
189 The config terms are listed in /sys/devices/intel_pt/format. They are bit
190 fields within the config member of the struct perf_event_attr which is
191 passed to the kernel by the perf_event_open system call. They correspond to bit
192 fields in the IA32_RTIT_CTL MSR. Here is a list of them and their definitions:
194 $ grep -H . /sys/bus/event_source/devices/intel_pt/format/*
195 /sys/bus/event_source/devices/intel_pt/format/cyc:config:1
196 /sys/bus/event_source/devices/intel_pt/format/cyc_thresh:config:19-22
197 /sys/bus/event_source/devices/intel_pt/format/mtc:config:9
198 /sys/bus/event_source/devices/intel_pt/format/mtc_period:config:14-17
199 /sys/bus/event_source/devices/intel_pt/format/noretcomp:config:11
200 /sys/bus/event_source/devices/intel_pt/format/psb_period:config:24-27
201 /sys/bus/event_source/devices/intel_pt/format/tsc:config:10
203 Note that the default config must be overridden for each term i.e.
205 -e intel_pt/noretcomp=0/
209 -e intel_pt/tsc=1,noretcomp=0/
211 So, to disable TSC packets use:
215 It is also possible to specify the config value explicitly:
217 -e intel_pt/config=0x400/
219 Note that, as with all events, the event is suffixed with event modifiers:
228 'h', 'G' and 'H' are for virtualization which is not supported by Intel PT.
229 'p' is also not relevant to Intel PT. So only options 'u' and 'k' are
230 meaningful for Intel PT.
232 perf_event_attr is displayed if the -vv option is used e.g.
234 ------------------------------------------------------------
239 { sample_period, sample_freq } 1
240 sample_type IP|TID|TIME|CPU|IDENTIFIER
248 ------------------------------------------------------------
249 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
250 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
251 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
252 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
253 ------------------------------------------------------------
259 The June 2015 version of Intel 64 and IA-32 Architectures Software Developer
260 Manuals, Chapter 36 Intel Processor Trace, defined new Intel PT features.
261 Some of the features are reflect in new config terms. All the config terms are
264 tsc Always supported. Produces TSC timestamp packets to provide
265 timing information. In some cases it is possible to decode
266 without timing information, for example a per-thread context
267 that does not overlap executable memory maps.
269 The default config selects tsc (i.e. tsc=1).
271 noretcomp Always supported. Disables "return compression" so a TIP packet
272 is produced when a function returns. Causes more packets to be
273 produced but might make decoding more reliable.
275 The default config does not select noretcomp (i.e. noretcomp=0).
277 psb_period Allows the frequency of PSB packets to be specified.
279 The PSB packet is a synchronization packet that provides a
280 starting point for decoding or recovery from errors.
282 Support for psb_period is indicated by:
284 /sys/bus/event_source/devices/intel_pt/caps/psb_cyc
286 which contains "1" if the feature is supported and "0"
289 Valid values are given by:
291 /sys/bus/event_source/devices/intel_pt/caps/psb_periods
293 which contains a hexadecimal value, the bits of which represent
294 valid values e.g. bit 2 set means value 2 is valid.
296 The psb_period value is converted to the approximate number of
297 trace bytes between PSB packets as:
301 e.g. value 3 means 16KiB bytes between PSBs
303 If an invalid value is entered, the error message
304 will give a list of valid values e.g.
306 $ perf record -e intel_pt/psb_period=15/u uname
307 Invalid psb_period for intel_pt. Valid values are: 0-5
309 If MTC packets are selected, the default config selects a value
310 of 3 (i.e. psb_period=3) or the nearest lower value that is
311 supported (0 is always supported). Otherwise the default is 0.
313 If decoding is expected to be reliable and the buffer is large
314 then a large PSB period can be used.
316 Because a TSC packet is produced with PSB, the PSB period can
317 also affect the granularity to timing information in the absence
320 mtc Produces MTC timing packets.
322 MTC packets provide finer grain timestamp information than TSC
323 packets. MTC packets record time using the hardware crystal
324 clock (CTC) which is related to TSC packets using a TMA packet.
326 Support for this feature is indicated by:
328 /sys/bus/event_source/devices/intel_pt/caps/mtc
330 which contains "1" if the feature is supported and
333 The frequency of MTC packets can also be specified - see
336 mtc_period Specifies how frequently MTC packets are produced - see mtc
337 above for how to determine if MTC packets are supported.
339 Valid values are given by:
341 /sys/bus/event_source/devices/intel_pt/caps/mtc_periods
343 which contains a hexadecimal value, the bits of which represent
344 valid values e.g. bit 2 set means value 2 is valid.
346 The mtc_period value is converted to the MTC frequency as:
348 CTC-frequency / (2 ^ value)
350 e.g. value 3 means one eighth of CTC-frequency
352 Where CTC is the hardware crystal clock, the frequency of which
353 can be related to TSC via values provided in cpuid leaf 0x15.
355 If an invalid value is entered, the error message
356 will give a list of valid values e.g.
358 $ perf record -e intel_pt/mtc_period=15/u uname
359 Invalid mtc_period for intel_pt. Valid values are: 0,3,6,9
361 The default value is 3 or the nearest lower value
362 that is supported (0 is always supported).
364 cyc Produces CYC timing packets.
366 CYC packets provide even finer grain timestamp information than
367 MTC and TSC packets. A CYC packet contains the number of CPU
368 cycles since the last CYC packet. Unlike MTC and TSC packets,
369 CYC packets are only sent when another packet is also sent.
371 Support for this feature is indicated by:
373 /sys/bus/event_source/devices/intel_pt/caps/psb_cyc
375 which contains "1" if the feature is supported and
378 The number of CYC packets produced can be reduced by specifying
379 a threshold - see cyc_thresh below.
381 cyc_thresh Specifies how frequently CYC packets are produced - see cyc
382 above for how to determine if CYC packets are supported.
384 Valid cyc_thresh values are given by:
386 /sys/bus/event_source/devices/intel_pt/caps/cycle_thresholds
388 which contains a hexadecimal value, the bits of which represent
389 valid values e.g. bit 2 set means value 2 is valid.
391 The cyc_thresh value represents the minimum number of CPU cycles
392 that must have passed before a CYC packet can be sent. The
393 number of CPU cycles is:
397 e.g. value 4 means 8 CPU cycles must pass before a CYC packet
398 can be sent. Note a CYC packet is still only sent when another
399 packet is sent, not at, e.g. every 8 CPU cycles.
401 If an invalid value is entered, the error message
402 will give a list of valid values e.g.
404 $ perf record -e intel_pt/cyc,cyc_thresh=15/u uname
405 Invalid cyc_thresh for intel_pt. Valid values are: 0-12
407 CYC packets are not requested by default.
409 pt Specifies pass-through which enables the 'branch' config term.
411 The default config selects 'pt' if it is available, so a user will
412 never need to specify this term.
414 branch Enable branch tracing. Branch tracing is enabled by default so to
415 disable branch tracing use 'branch=0'.
417 The default config selects 'branch' if it is available.
419 ptw Enable PTWRITE packets which are produced when a ptwrite instruction
422 Support for this feature is indicated by:
424 /sys/bus/event_source/devices/intel_pt/caps/ptwrite
426 which contains "1" if the feature is supported and
429 fup_on_ptw Enable a FUP packet to follow the PTWRITE packet. The FUP packet
430 provides the address of the ptwrite instruction. In the absence of
431 fup_on_ptw, the decoder will use the address of the previous branch
432 if branch tracing is enabled, otherwise the address will be zero.
433 Note that fup_on_ptw will work even when branch tracing is disabled.
435 pwr_evt Enable power events. The power events provide information about
436 changes to the CPU C-state.
438 Support for this feature is indicated by:
440 /sys/bus/event_source/devices/intel_pt/caps/power_event_trace
442 which contains "1" if the feature is supported and
446 AUX area sampling option
447 ~~~~~~~~~~~~~~~~~~~~~~~~
449 To select Intel PT "sampling" the AUX area sampling option can be used:
453 Optionally it can be followed by the sample size in bytes e.g.
457 In addition, the Intel PT event to sample must be defined e.g.
461 Samples on other events will be created containing Intel PT data e.g. the
462 following will create Intel PT samples on the branch-misses event, note the
463 events must be grouped using {}:
465 perf record --aux-sample -e '{intel_pt//u,branch-misses:u}'
467 An alternative to '--aux-sample' is to add the config term 'aux-sample-size' to
468 events. In this case, the grouping is implied e.g.
470 perf record -e intel_pt//u -e branch-misses/aux-sample-size=8192/u
474 perf record -e '{intel_pt//u,branch-misses/aux-sample-size=8192/u}'
476 but allows for also using an address filter e.g.:
478 perf record -e intel_pt//u --filter 'filter * @/bin/ls' -e branch-misses/aux-sample-size=8192/u -- ls
480 It is important to select a sample size that is big enough to contain at least
481 one PSB packet. If not a warning will be displayed:
483 Intel PT sample size (%zu) may be too small for PSB period (%zu)
485 The calculation used for that is: if sample_size <= psb_period + 256 display the
486 warning. When sampling is used, psb_period defaults to 0 (2KiB).
488 The default sample size is 4KiB.
490 The sample size is passed in aux_sample_size in struct perf_event_attr. The
491 sample size is limited by the maximum event size which is 64KiB. It is
492 difficult to know how big the event might be without the trace sample attached,
493 but the tool validates that the sample size is not greater than 60KiB.
499 The difference between full trace and snapshot from the kernel's perspective is
500 that in full trace we don't overwrite trace data that the user hasn't collected
501 yet (and indicated that by advancing aux_tail), whereas in snapshot mode we let
502 the trace run and overwrite older data in the buffer so that whenever something
503 interesting happens, we can stop it and grab a snapshot of what was going on
504 around that interesting moment.
506 To select snapshot mode a new option has been added:
510 Optionally it can be followed by the snapshot size e.g.
514 The default snapshot size is the auxtrace mmap size. If neither auxtrace mmap size
515 nor snapshot size is specified, then the default is 4MiB for privileged users
516 (or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users.
517 If an unprivileged user does not specify mmap pages, the mmap pages will be
518 reduced as described in the 'new auxtrace mmap size option' section below.
520 The snapshot size is displayed if the option -vv is used e.g.
522 Intel PT snapshot size: %zu
525 new auxtrace mmap size option
526 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
528 Intel PT buffer size is specified by an addition to the -m option e.g.
532 selects a buffer size of 16 pages i.e. 64KiB.
534 Note that the existing functionality of -m is unchanged. The auxtrace mmap size
535 is specified by the optional addition of a comma and the value.
537 The default auxtrace mmap size for Intel PT is 4MiB/page_size for privileged users
538 (or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users.
539 If an unprivileged user does not specify mmap pages, the mmap pages will be
540 reduced from the default 512KiB/page_size to 256KiB/page_size, otherwise the
541 user is likely to get an error as they exceed their mlock limit (Max locked
542 memory as shown in /proc/self/limits). Note that perf does not count the first
543 512KiB (actually /proc/sys/kernel/perf_event_mlock_kb minus 1 page) per cpu
544 against the mlock limit so an unprivileged user is allowed 512KiB per cpu plus
545 their mlock limit (which defaults to 64KiB but is not multiplied by the number
548 In full-trace mode, powers of two are allowed for buffer size, with a minimum
549 size of 2 pages. In snapshot mode or sampling mode, it is the same but the
550 minimum size is 1 page.
552 The mmap size and auxtrace mmap size are displayed if the -vv option is used e.g.
555 auxtrace mmap length 4198400
558 Intel PT modes of operation
559 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
561 Intel PT can be used in 3 modes:
566 Full-trace mode traces continuously e.g.
568 perf record -e intel_pt//u uname
570 Sample mode attaches a Intel PT sample to other events e.g.
572 perf record --aux-sample -e intel_pt//u -e branch-misses:u
574 Snapshot mode captures the available data when a signal is sent or "snapshot"
575 control command is issued. e.g. using a signal
577 perf record -v -e intel_pt//u -S ./loopy 1000000000 &
580 Recording AUX area tracing snapshot
582 Note that the signal sent is SIGUSR2.
583 Note that "Recording AUX area tracing snapshot" is displayed because the -v
586 The advantage of using "snapshot" control command is that the access is
587 controlled by access to a FIFO e.g.
589 $ mkfifo perf.control
593 $ sudo ~/bin/perf record --control fifo:perf.control,perf.ack -S -e intel_pt//u -- sleep 60 &
596 15244 pts/1 00:00:00 perf
598 bash: kill: (15244) - Operation not permitted
599 $ echo snapshot > perf.control
602 The 3 Intel PT modes of operation cannot be used together.
608 There may be buffer limitations (i.e. single ToPa entry) which means that actual
609 buffer sizes are limited to powers of 2 up to 4MiB (MAX_ORDER). In order to
610 provide other sizes, and in particular an arbitrarily large size, multiple
611 buffers are logically concatenated. However an interrupt must be used to switch
612 between buffers. That has two potential problems:
613 a) the interrupt may not be handled in time so that the current buffer
614 becomes full and some trace data is lost.
615 b) the interrupts may slow the system and affect the performance
618 If trace data is lost, the driver sets 'truncated' in the PERF_RECORD_AUX event
619 which the tools report as an error.
621 In full-trace mode, the driver waits for data to be copied out before allowing
622 the (logical) buffer to wrap-around. If data is not copied out quickly enough,
623 again 'truncated' is set in the PERF_RECORD_AUX event. If the driver has to
624 wait, the intel_pt event gets disabled. Because it is difficult to know when
625 that happens, perf tools always re-enable the intel_pt event after copying out
629 Intel PT and build ids
630 ~~~~~~~~~~~~~~~~~~~~~~
632 By default "perf record" post-processes the event stream to find all build ids
633 for executables for all addresses sampled. Deliberately, Intel PT is not
634 decoded for that purpose (it would take too long). Instead the build ids for
635 all executables encountered (due to mmap, comm or task events) are included
636 in the perf.data file.
638 To see buildids included in the perf.data file use the command:
642 If the perf.data file contains Intel PT data, that is the same as:
644 perf buildid-list --with-hits
647 Snapshot mode and event disabling
648 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
650 In order to make a snapshot, the intel_pt event is disabled using an IOCTL,
651 namely PERF_EVENT_IOC_DISABLE. However doing that can also disable the
652 collection of side-band information. In order to prevent that, a dummy
653 software event has been introduced that permits tracking events (like mmaps) to
654 continue to be recorded while intel_pt is disabled. That is important to ensure
655 there is complete side-band information to allow the decoding of subsequent
658 A test has been created for that. To find the test:
662 23: Test using a dummy software event to keep tracking
667 23: Test using a dummy software event to keep tracking : Ok
670 perf record modes (nothing new here)
671 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
673 perf record essentially operates in one of three modes:
678 "per thread" mode is selected by -t or by --per-thread (with -p or -u or just a
680 "per cpu" is selected by -C or -a.
681 "workload only" mode is selected by not using the other options but providing a
682 command to run (i.e. the workload).
684 In per-thread mode an exact list of threads is traced. There is no inheritance.
685 Each thread has its own event buffer.
687 In per-cpu mode all processes (or processes from the selected cgroup i.e. -G
688 option, or processes selected with -p or -u) are traced. Each cpu has its own
689 buffer. Inheritance is allowed.
691 In workload-only mode, the workload is traced but with per-cpu buffers.
692 Inheritance is allowed. Note that you can now trace a workload in per-thread
693 mode by using the --per-thread option.
696 Privileged vs non-privileged users
697 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
699 Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users
700 have memory limits imposed upon them. That affects what buffer sizes they can
701 have as outlined above.
703 The v4.2 kernel introduced support for a context switch metadata event,
704 PERF_RECORD_SWITCH, which allows unprivileged users to see when their processes
705 are scheduled out and in, just not by whom, which is left for the
706 PERF_RECORD_SWITCH_CPU_WIDE, that is only accessible in system wide context,
707 which in turn requires CAP_PERFMON or CAP_SYS_ADMIN.
709 Please see the 45ac1403f564 ("perf: Add PERF_RECORD_SWITCH to indicate context
710 switches") commit, that introduces these metadata events for further info.
712 When working with kernels < v4.2, the following considerations must be taken,
713 as the sched:sched_switch tracepoints will be used to receive such information:
715 Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users are
716 not permitted to use tracepoints which means there is insufficient side-band
717 information to decode Intel PT in per-cpu mode, and potentially workload-only
718 mode too if the workload creates new processes.
720 Note also, that to use tracepoints, read-access to debugfs is required. So if
721 debugfs is not mounted or the user does not have read-access, it will again not
722 be possible to decode Intel PT in per-cpu mode.
725 sched_switch tracepoint
726 ~~~~~~~~~~~~~~~~~~~~~~~
728 The sched_switch tracepoint is used to provide side-band data for Intel PT
729 decoding in kernels where the PERF_RECORD_SWITCH metadata event isn't
732 The sched_switch events are automatically added. e.g. the second event shown
735 $ perf record -vv -e intel_pt//u uname
736 ------------------------------------------------------------
741 { sample_period, sample_freq } 1
742 sample_type IP|TID|TIME|CPU|IDENTIFIER
750 ------------------------------------------------------------
751 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
752 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
753 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
754 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
755 ------------------------------------------------------------
760 { sample_period, sample_freq } 1
761 sample_type IP|TID|TIME|CPU|PERIOD|RAW|IDENTIFIER
766 ------------------------------------------------------------
767 sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8
768 sys_perf_event_open: pid -1 cpu 1 group_fd -1 flags 0x8
769 sys_perf_event_open: pid -1 cpu 2 group_fd -1 flags 0x8
770 sys_perf_event_open: pid -1 cpu 3 group_fd -1 flags 0x8
771 ------------------------------------------------------------
776 { sample_period, sample_freq } 1
777 sample_type IP|TID|TIME|IDENTIFIER
790 ------------------------------------------------------------
791 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8
792 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8
793 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8
794 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8
796 AUX area mmap length 4194304
797 perf event ring buffer mmapped per cpu
798 Synthesizing auxtrace information
800 [ perf record: Woken up 1 times to write data ]
801 [ perf record: Captured and wrote 0.042 MB perf.data ]
803 Note, the sched_switch event is only added if the user is permitted to use it
804 and only in per-cpu mode.
806 Note also, the sched_switch event is only added if TSC packets are requested.
807 That is because, in the absence of timing information, the sched_switch events
808 cannot be matched against the Intel PT trace.
814 By default, perf script will decode trace data found in the perf.data file.
815 This can be further controlled by new option --itrace.
821 Having no option is the same as
825 which, in turn, is the same as
831 i synthesize "instructions" events
832 b synthesize "branches" events
833 x synthesize "transactions" events
834 w synthesize "ptwrite" events
835 p synthesize "power" events
836 c synthesize branches events (calls only)
837 r synthesize branches events (returns only)
838 e synthesize tracing error events
840 g synthesize a call chain (use with i or x)
841 G synthesize a call chain on existing event records
842 l synthesize last branch entries (use with i or x)
843 L synthesize last branch entries on existing event records
844 s skip initial number of events
845 q quicker (less detailed) decoding
847 "Instructions" events look like they were recorded by "perf record -e
850 "Branches" events look like they were recorded by "perf record -e branches". "c"
851 and "r" can be combined to get calls and returns.
853 "Transactions" events correspond to the start or end of transactions. The
854 'flags' field can be used in perf script to determine whether the event is a
855 tranasaction start, commit or abort.
857 Note that "instructions", "branches" and "transactions" events depend on code
858 flow packets which can be disabled by using the config term "branch=0". Refer
859 to the config terms section above.
861 "ptwrite" events record the payload of the ptwrite instruction and whether
862 "fup_on_ptw" was used. "ptwrite" events depend on PTWRITE packets which are
863 recorded only if the "ptw" config term was used. Refer to the config terms
864 section above. perf script "synth" field displays "ptwrite" information like
865 this: "ip: 0 payload: 0x123456789abcdef0" where "ip" is 1 if "fup_on_ptw" was
868 "Power" events correspond to power event packets and CBR (core-to-bus ratio)
869 packets. While CBR packets are always recorded when tracing is enabled, power
870 event packets are recorded only if the "pwr_evt" config term was used. Refer to
871 the config terms section above. The power events record information about
872 C-state changes, whereas CBR is indicative of CPU frequency. perf script
873 "event,synth" fields display information like this:
874 cbr: cbr: 22 freq: 2189 MHz (200%)
875 mwait: hints: 0x60 extensions: 0x1
876 pwre: hw: 0 cstate: 2 sub-cstate: 0
878 pwrx: deepest cstate: 2 last cstate: 2 wake reason: 0x4
880 "cbr" includes the frequency and the percentage of maximum non-turbo
881 "mwait" shows mwait hints and extensions
882 "pwre" shows C-state transitions (to a C-state deeper than C0) and
883 whether initiated by hardware
884 "exstop" indicates execution stopped and whether the IP was recorded
886 "pwrx" indicates return to C0
887 For more details refer to the Intel 64 and IA-32 Architectures Software
890 Error events show where the decoder lost the trace. Error events
891 are quite important. Users must know if what they are seeing is a complete
892 picture or not. The "e" option may be followed by flags which affect what errors
893 will or will not be reported. Each flag must be preceded by either '+' or '-'.
894 The flags supported by Intel PT are:
895 -o Suppress overflow errors
896 -l Suppress trace data lost errors
897 For example, for errors but not overflow or data lost errors:
901 The "d" option will cause the creation of a file "intel_pt.log" containing all
902 decoded packets and instructions. Note that this option slows down the decoder
903 and that the resulting file may be very large. The "d" option may be followed
904 by flags which affect what debug messages will or will not be logged. Each flag
905 must be preceded by either '+' or '-'. The flags support by Intel PT are:
906 -a Suppress logging of perf events
907 +a Log all perf events
908 By default, logged perf events are filtered by any specified time ranges, but
909 flag +a overrides that.
911 In addition, the period of the "instructions" event can be specified. e.g.
915 sets the period to 10us i.e. one instruction sample is synthesized for each 10
916 microseconds of trace. Alternatives to "us" are "ms" (milliseconds),
917 "ns" (nanoseconds), "t" (TSC ticks) or "i" (instructions).
919 "ms", "us" and "ns" are converted to TSC ticks.
921 The timing information included with Intel PT does not give the time of every
922 instruction. Consequently, for the purpose of sampling, the decoder estimates
923 the time since the last timing packet based on 1 tick per instruction. The time
924 on the sample is *not* adjusted and reflects the last known value of TSC.
926 For Intel PT, the default period is 100us.
928 Setting it to a zero period means "as often as possible".
930 In the case of Intel PT that is the same as a period of 1 and a unit of
931 'instructions' (i.e. --itrace=i1i).
933 Also the call chain size (default 16, max. 1024) for instructions or
934 transactions events can be specified. e.g.
939 Also the number of last branch entries (default 64, max. 1024) for instructions or
940 transactions events can be specified. e.g.
945 Note that last branch entries are cleared for each sample, so there is no overlap
946 from one sample to the next.
948 The G and L options are designed in particular for sample mode, and work much
949 like g and l but add call chain and branch stack to the other selected events
950 instead of synthesized events. For example, to record branch-misses events for
951 'ls' and then add a call chain derived from the Intel PT trace:
953 perf record --aux-sample -e '{intel_pt//u,branch-misses:u}' -- ls
954 perf report --itrace=Ge
956 Although in fact G is a default for perf report, so that is the same as just:
960 One caveat with the G and L options is that they work poorly with "Large PEBS".
961 Large PEBS means PEBS records will be accumulated by hardware and the written
962 into the event buffer in one go. That reduces interrupts, but can give very
963 late timestamps. Because the Intel PT trace is synchronized by timestamps,
964 the PEBS events do not match the trace. Currently, Large PEBS is used only in
965 certain circumstances:
966 - hardware supports it
968 - event period is specified, instead of frequency
969 - the sample type is limited to the following flags:
970 PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR |
971 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID |
972 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER |
973 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR |
974 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER |
975 PERF_SAMPLE_PERIOD (and sometimes) | PERF_SAMPLE_TIME
976 Because Intel PT sample mode uses a different sample type to the list above,
977 Large PEBS is not used with Intel PT sample mode. To avoid Large PEBS in other
978 cases, avoid specifying the event period i.e. avoid the 'perf record' -c option,
979 --count option, or 'period' config term.
981 To disable trace decoding entirely, use the option --no-itrace.
983 It is also possible to skip events generated (instructions, branches, transactions)
984 at the beginning. This is useful to ignore initialization code.
986 --itrace=i0nss1000000
988 skips the first million instructions.
990 The q option changes the way the trace is decoded. The decoding is much faster
991 but much less detailed. Specifically, with the q option, the decoder does not
992 decode TNT packets, and does not walk object code, but gets the ip from FUP and
993 TIP packets. The q option can be used with the b and i options but the period
994 is not used. The q option decodes more quickly, but is useful only if the
995 control flow of interest is represented or indicated by FUP, TIP, TIP.PGE, or
996 TIP.PGD packets (refer below). However the q option could be used to find time
997 ranges that could then be decoded fully using the --time option.
999 What will *not* be decoded with the (single) q option:
1001 - direct calls and jmps
1002 - conditional branches
1003 - non-branch instructions
1005 What *will* be decoded with the (single) q option:
1007 - asynchronous branches such as interrupts
1009 - function return target address *if* the noretcomp config term (refer
1010 config terms section) was used
1011 - start of (control-flow) tracing
1012 - end of (control-flow) tracing, if it is not out of context
1013 - power events, ptwrite, transaction start and abort
1014 - instruction pointer associated with PSB packets
1016 Note the q option does not specify what events will be synthesized e.g. the p
1017 option must be used also to show power events.
1019 Repeating the q option (double-q i.e. qq) results in even faster decoding and even
1020 less detail. The decoder decodes only extended PSB (PSB+) packets, getting the
1021 instruction pointer if there is a FUP packet within PSB+ (i.e. between PSB and
1022 PSBEND). Note PSB packets occur regularly in the trace based on the psb_period
1023 config term (refer config terms section). There will be a FUP packet if the
1024 PSB+ occurs while control flow is being traced.
1026 What will *not* be decoded with the qq option:
1028 - everything except instruction pointer associated with PSB packets
1030 What *will* be decoded with the qq option:
1032 - instruction pointer associated with PSB packets
1038 perf script has an option (-D) to "dump" the events i.e. display the binary
1041 When -D is used, Intel PT packets are displayed. The packet decoder does not
1042 pay attention to PSB packets, but just decodes the bytes - so the packets seen
1043 by the actual decoder may not be identical in places where the data is corrupt.
1044 One example of that would be when the buffer-switching interrupt has been too
1045 slow, and the buffer has been filled completely. In that case, the last packet
1046 in the buffer might be truncated and immediately followed by a PSB as the trace
1047 continues in the next buffer.
1049 To disable the display of Intel PT packets, combine the -D option with
1056 By default, perf report will decode trace data found in the perf.data file.
1057 This can be further controlled by new option --itrace exactly the same as
1058 perf script, with the exception that the default is --itrace=igxe.
1064 perf inject also accepts the --itrace option in which case tracing data is
1065 removed and replaced with the synthesized events. e.g.
1067 perf inject --itrace -i perf.data -o perf.data.new
1069 Below is an example of using Intel PT with autofdo. It requires autofdo
1070 (https://github.com/google/autofdo) and gcc version 5. The bubble
1071 sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial)
1072 amended to take the number of elements as a parameter.
1074 $ gcc-5 -O3 sort.c -o sort_optimized
1075 $ ./sort_optimized 30000
1076 Bubble sorting array of 30000 elements
1083 $ perf record -e intel_pt//u ./sort 3000
1084 Bubble sorting array of 3000 elements
1086 [ perf record: Woken up 2 times to write data ]
1087 [ perf record: Captured and wrote 3.939 MB perf.data ]
1088 $ perf inject -i perf.data -o inj --itrace=i100usle --strip
1089 $ ./create_gcov --binary=./sort --profile=inj --gcov=sort.gcov -gcov_version=1
1090 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
1091 $ ./sort_autofdo 30000
1092 Bubble sorting array of 30000 elements
1095 Note there is currently no advantage to using Intel PT instead of LBR, but
1096 that may change in the future if greater use is made of the data.
1102 Some hardware has the feature to redirect PEBS records to the Intel PT trace.
1103 Recording is selected by using the aux-output config term e.g.
1105 perf record -c 10000 -e '{intel_pt/branch=0/,cycles/aux-output/ppp}' uname
1107 Note that currently, software only supports redirecting at most one PEBS event.
1109 To display PEBS events from the Intel PT trace, use the itrace 'o' option e.g.
1111 perf script --itrace=oe
1117 linkperf:perf-record[1], linkperf:perf-script[1], linkperf:perf-report[1],
1118 linkperf:perf-inject[1]