1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_das.c - Tegra20 DAS driver
5 * Author: Stephen Warren <swarren@nvidia.com>
6 * Copyright (C) 2010 - NVIDIA, Inc.
9 #include <linux/device.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <sound/soc.h>
17 #define DRV_NAME "tegra20-das"
19 /* Register TEGRA20_DAS_DAP_CTRL_SEL */
20 #define TEGRA20_DAS_DAP_CTRL_SEL 0x00
21 #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
22 #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
23 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
24 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
25 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
26 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
27 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
28 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
29 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
30 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
32 /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
33 #define TEGRA20_DAS_DAP_SEL_DAC1 0
34 #define TEGRA20_DAS_DAP_SEL_DAC2 1
35 #define TEGRA20_DAS_DAP_SEL_DAC3 2
36 #define TEGRA20_DAS_DAP_SEL_DAP1 16
37 #define TEGRA20_DAS_DAP_SEL_DAP2 17
38 #define TEGRA20_DAS_DAP_SEL_DAP3 18
39 #define TEGRA20_DAS_DAP_SEL_DAP4 19
40 #define TEGRA20_DAS_DAP_SEL_DAP5 20
42 /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
43 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
44 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
45 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
46 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
47 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
48 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
49 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
50 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
51 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
55 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
56 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
57 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
59 #define TEGRA20_DAS_DAC_SEL_DAP1 0
60 #define TEGRA20_DAS_DAC_SEL_DAP2 1
61 #define TEGRA20_DAS_DAC_SEL_DAP3 2
62 #define TEGRA20_DAS_DAC_SEL_DAP4 3
63 #define TEGRA20_DAS_DAC_SEL_DAP5 4
66 * Names/IDs of the DACs/DAPs.
69 #define TEGRA20_DAS_DAP_ID_1 0
70 #define TEGRA20_DAS_DAP_ID_2 1
71 #define TEGRA20_DAS_DAP_ID_3 2
72 #define TEGRA20_DAS_DAP_ID_4 3
73 #define TEGRA20_DAS_DAP_ID_5 4
75 #define TEGRA20_DAS_DAC_ID_1 0
76 #define TEGRA20_DAS_DAC_ID_2 1
77 #define TEGRA20_DAS_DAC_ID_3 2
81 struct regmap *regmap;
86 * DAS: Digital audio switch (HW module controlled by this driver)
87 * DAP: Digital audio port (port/pins on Tegra device)
88 * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
90 * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
91 * DAC, or another DAP. When DAPs are connected, one must be the master and
92 * one the slave. Each DAC allows selection of a specific DAP for input, to
93 * cater for the case where N DAPs are connected to 1 DAC for broadcast
96 * This driver is dumb; no attempt is made to ensure that a valid routing
97 * configuration is programmed.
100 static struct tegra20_das *das;
102 static inline void tegra20_das_write(u32 reg, u32 val)
104 regmap_write(das->regmap, reg, val);
107 static inline u32 tegra20_das_read(u32 reg)
111 regmap_read(das->regmap, reg, &val);
115 static int tegra20_das_connect_dap_to_dac(int dap, int dac)
123 addr = TEGRA20_DAS_DAP_CTRL_SEL +
124 (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
125 reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
127 tegra20_das_write(addr, reg);
132 static int tegra20_das_connect_dac_to_dap(int dac, int dap)
140 addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
141 (dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
142 reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
143 dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
144 dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
146 tegra20_das_write(addr, reg);
151 #define LAST_REG(name) \
152 (TEGRA20_DAS_##name + \
153 (TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
155 static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
157 if (reg <= LAST_REG(DAP_CTRL_SEL))
159 if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
160 (reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
166 static const struct regmap_config tegra20_das_regmap_config = {
170 .max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
171 .writeable_reg = tegra20_das_wr_rd_reg,
172 .readable_reg = tegra20_das_wr_rd_reg,
173 .cache_type = REGCACHE_FLAT,
176 static int tegra20_das_probe(struct platform_device *pdev)
184 das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
189 das->dev = &pdev->dev;
191 regs = devm_platform_ioremap_resource(pdev, 0);
197 das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
198 &tegra20_das_regmap_config);
199 if (IS_ERR(das->regmap)) {
200 dev_err(&pdev->dev, "regmap init failed\n");
201 ret = PTR_ERR(das->regmap);
205 ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
206 TEGRA20_DAS_DAP_SEL_DAC1);
208 dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
211 ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1,
212 TEGRA20_DAS_DAC_SEL_DAP1);
214 dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
218 ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_3,
219 TEGRA20_DAS_DAP_SEL_DAC3);
221 dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
224 ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_3,
225 TEGRA20_DAS_DAC_SEL_DAP3);
227 dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
231 platform_set_drvdata(pdev, das);
240 static int tegra20_das_remove(struct platform_device *pdev)
250 static const struct of_device_id tegra20_das_of_match[] = {
251 { .compatible = "nvidia,tegra20-das", },
255 static struct platform_driver tegra20_das_driver = {
256 .probe = tegra20_das_probe,
257 .remove = tegra20_das_remove,
260 .of_match_table = tegra20_das_of_match,
263 module_platform_driver(tegra20_das_driver);
265 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
266 MODULE_DESCRIPTION("Tegra20 DAS driver");
267 MODULE_LICENSE("GPL");
268 MODULE_ALIAS("platform:" DRV_NAME);
269 MODULE_DEVICE_TABLE(of, tegra20_das_of_match);