sound/soc/sunxi/sun4i-i2s.c

   1 /*
   2  * Copyright (C) 2015 Andrea Venturi
   3  * Andrea Venturi <be17068@iperbole.bo.it>
   4  *
   5  * Copyright (C) 2016 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 #include <sound/dmaengine_pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dai.h>
  27
  28 #define SUN4I_I2S_CTRL_REG              0x00
  29 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  30 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  31 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  32 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  33 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  34 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  35 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  36 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  37
  38 #define SUN4I_I2S_FMT0_REG              0x04
  39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  40 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  41 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  43 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  44 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  45 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  46 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  47 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  48 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  49 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  50 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  51 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  52 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  53 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  54 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  55
  56 #define SUN4I_I2S_FMT1_REG              0x08
  57 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  58 #define SUN4I_I2S_FIFO_RX_REG           0x10
  59
  60 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  61 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  62 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  63 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  64 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  65 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  66 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  67
  68 #define SUN4I_I2S_FIFO_STA_REG          0x18
  69
  70 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  71 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  72 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  73
  74 #define SUN4I_I2S_INT_STA_REG           0x20
  75
  76 #define SUN4I_I2S_CLK_DIV_REG           0x24
  77 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  78 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  79 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  80 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  81 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  82
  83 #define SUN4I_I2S_RX_CNT_REG            0x28
  84 #define SUN4I_I2S_TX_CNT_REG            0x2c
  85
  86 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  87 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  88
  89 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  90 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  91
  92 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  93 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  94
  95 /* Defines required for sun8i-h3 support */
  96 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  97 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  98
  99 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
 100 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
 101
 102 #define SUN8I_I2S_INT_STA_REG           0x0c
 103 #define SUN8I_I2S_FIFO_TX_REG           0x20
 104
 105 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 106 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 107 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 108 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 109 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 110
 111 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 112 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 113 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 12)
 114 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 115 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 116 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 117
 118 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 119 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 120
 121 struct sun4i_i2s;
 122
 123 /**
 124  * struct sun4i_i2s_quirks - Differences between SoC variants.
 125  *
 126  * @has_reset: SoC needs reset deasserted.
 127  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 128  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 129  * @has_chcfg: tx and rx slot number need to be set.
 130  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 131  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 132  * @reg_offset_txdata: offset of the tx fifo.
 133  * @sun4i_i2s_regmap: regmap config to use.
 134  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 135  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 136  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 137  * @field_fmt_wss: regmap field to set word select size.
 138  * @field_fmt_sr: regmap field to set sample resolution.
 139  * @field_fmt_bclk: regmap field to set clk polarity.
 140  * @field_fmt_lrclk: regmap field to set frame polarity.
 141  * @field_fmt_mode: regmap field to set the operational mode.
 142  * @field_txchanmap: location of the tx channel mapping register.
 143  * @field_rxchanmap: location of the rx channel mapping register.
 144  * @field_txchansel: location of the tx channel select bit fields.
 145  * @field_rxchansel: location of the rx channel select bit fields.
 146  */
 147 struct sun4i_i2s_quirks {
 148         bool                            has_reset;
 149         bool                            has_slave_select_bit;
 150         bool                            has_fmt_set_lrck_period;
 151         bool                            has_chcfg;
 152         bool                            has_chsel_tx_chen;
 153         bool                            has_chsel_offset;
 154         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 155         const struct regmap_config      *sun4i_i2s_regmap;
 156         unsigned int                    mclk_offset;
 157         unsigned int                    bclk_offset;
 158
 159         /* Register fields for i2s */
 160         struct reg_field                field_clkdiv_mclk_en;
 161         struct reg_field                field_fmt_wss;
 162         struct reg_field                field_fmt_sr;
 163         struct reg_field                field_fmt_bclk;
 164         struct reg_field                field_fmt_lrclk;
 165         struct reg_field                field_fmt_mode;
 166         struct reg_field                field_txchanmap;
 167         struct reg_field                field_rxchanmap;
 168         struct reg_field                field_txchansel;
 169         struct reg_field                field_rxchansel;
 170
 171         s8      (*get_sr)(const struct sun4i_i2s *, int);
 172         s8      (*get_wss)(const struct sun4i_i2s *, int);
 173 };
 174
 175 struct sun4i_i2s {
 176         struct clk      *bus_clk;
 177         struct clk      *mod_clk;
 178         struct regmap   *regmap;
 179         struct reset_control *rst;
 180
 181         unsigned int    mclk_freq;
 182
 183         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 184         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 185
 186         /* Register fields for i2s */
 187         struct regmap_field     *field_clkdiv_mclk_en;
 188         struct regmap_field     *field_fmt_wss;
 189         struct regmap_field     *field_fmt_sr;
 190         struct regmap_field     *field_fmt_bclk;
 191         struct regmap_field     *field_fmt_lrclk;
 192         struct regmap_field     *field_fmt_mode;
 193         struct regmap_field     *field_txchanmap;
 194         struct regmap_field     *field_rxchanmap;
 195         struct regmap_field     *field_txchansel;
 196         struct regmap_field     *field_rxchansel;
 197
 198         const struct sun4i_i2s_quirks   *variant;
 199 };
 200
 201 struct sun4i_i2s_clk_div {
 202         u8      div;
 203         u8      val;
 204 };
 205
 206 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 207         { .div = 2, .val = 0 },
 208         { .div = 4, .val = 1 },
 209         { .div = 6, .val = 2 },
 210         { .div = 8, .val = 3 },
 211         { .div = 12, .val = 4 },
 212         { .div = 16, .val = 5 },
 213         /* TODO - extend divide ratio supported by newer SoCs */
 214 };
 215
 216 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 217         { .div = 1, .val = 0 },
 218         { .div = 2, .val = 1 },
 219         { .div = 4, .val = 2 },
 220         { .div = 6, .val = 3 },
 221         { .div = 8, .val = 4 },
 222         { .div = 12, .val = 5 },
 223         { .div = 16, .val = 6 },
 224         { .div = 24, .val = 7 },
 225         /* TODO - extend divide ratio supported by newer SoCs */
 226 };
 227
 228 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 229                                   unsigned int oversample_rate,
 230                                   unsigned int word_size)
 231 {
 232         int div = oversample_rate / word_size / 2;
 233         int i;
 234
 235         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 236                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 237
 238                 if (bdiv->div == div)
 239                         return bdiv->val;
 240         }
 241
 242         return -EINVAL;
 243 }
 244
 245 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 246                                   unsigned int oversample_rate,
 247                                   unsigned int module_rate,
 248                                   unsigned int sampling_rate)
 249 {
 250         int div = module_rate / sampling_rate / oversample_rate;
 251         int i;
 252
 253         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 254                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 255
 256                 if (mdiv->div == div)
 257                         return mdiv->val;
 258         }
 259
 260         return -EINVAL;
 261 }
 262
 263 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 264 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 265 {
 266         int i;
 267
 268         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 269                 if (sun4i_i2s_oversample_rates[i] == oversample)
 270                         return true;
 271
 272         return false;
 273 }
 274
 275 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
 276                                   unsigned int rate,
 277                                   unsigned int word_size)
 278 {
 279         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 280         unsigned int oversample_rate, clk_rate;
 281         int bclk_div, mclk_div;
 282         int ret;
 283
 284         switch (rate) {
 285         case 176400:
 286         case 88200:
 287         case 44100:
 288         case 22050:
 289         case 11025:
 290                 clk_rate = 22579200;
 291                 break;
 292
 293         case 192000:
 294         case 128000:
 295         case 96000:
 296         case 64000:
 297         case 48000:
 298         case 32000:
 299         case 24000:
 300         case 16000:
 301         case 12000:
 302         case 8000:
 303                 clk_rate = 24576000;
 304                 break;
 305
 306         default:
 307                 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
 308                 return -EINVAL;
 309         }
 310
 311         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 312         if (ret)
 313                 return ret;
 314
 315         oversample_rate = i2s->mclk_freq / rate;
 316         if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
 317                 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
 318                         oversample_rate);
 319                 return -EINVAL;
 320         }
 321
 322         bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
 323                                           word_size);
 324         if (bclk_div < 0) {
 325                 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
 326                 return -EINVAL;
 327         }
 328
 329         mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
 330                                           clk_rate, rate);
 331         if (mclk_div < 0) {
 332                 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
 333                 return -EINVAL;
 334         }
 335
 336         /* Adjust the clock division values if needed */
 337         bclk_div += i2s->variant->bclk_offset;
 338         mclk_div += i2s->variant->mclk_offset;
 339
 340         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 341                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 342                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 343
 344         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 345
 346         /* Set sync period */
 347         if (i2s->variant->has_fmt_set_lrck_period)
 348                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 349                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 350                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 351
 352         return 0;
 353 }
 354
 355 static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
 356 {
 357         if (width < 16 || width > 24)
 358                 return -EINVAL;
 359
 360         if (width % 4)
 361                 return -EINVAL;
 362
 363         return (width - 16) / 4;
 364 }
 365
 366 static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
 367 {
 368         if (width < 16 || width > 32)
 369                 return -EINVAL;
 370
 371         if (width % 4)
 372                 return -EINVAL;
 373
 374         return (width - 16) / 4;
 375 }
 376
 377 static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
 378 {
 379         if (width % 4)
 380                 return -EINVAL;
 381
 382         if (width < 8 || width > 32)
 383                 return -EINVAL;
 384
 385         return (width - 8) / 4 + 1;
 386 }
 387
 388 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 389                                struct snd_pcm_hw_params *params,
 390                                struct snd_soc_dai *dai)
 391 {
 392         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 393         int sr, wss, channels;
 394         u32 width;
 395
 396         channels = params_channels(params);
 397         if (channels != 2) {
 398                 dev_err(dai->dev, "Unsupported number of channels: %d\n",
 399                         channels);
 400                 return -EINVAL;
 401         }
 402
 403         if (i2s->variant->has_chcfg) {
 404                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 405                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 406                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 407                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 408                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 409                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 410         }
 411
 412         /* Map the channels for playback and capture */
 413         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 414         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 415
 416         /* Configure the channels */
 417         regmap_field_write(i2s->field_txchansel,
 418                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 419
 420         regmap_field_write(i2s->field_rxchansel,
 421                            SUN4I_I2S_CHAN_SEL(params_channels(params)));
 422
 423         if (i2s->variant->has_chsel_tx_chen)
 424                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 425                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 426                                    SUN8I_I2S_TX_CHAN_EN(channels));
 427
 428         switch (params_physical_width(params)) {
 429         case 16:
 430                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 431                 break;
 432         default:
 433                 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
 434                         params_physical_width(params));
 435                 return -EINVAL;
 436         }
 437         i2s->playback_dma_data.addr_width = width;
 438
 439         sr = i2s->variant->get_sr(i2s, params_width(params));
 440         if (sr < 0)
 441                 return -EINVAL;
 442
 443         wss = i2s->variant->get_wss(i2s, params_width(params));
 444         if (wss < 0)
 445                 return -EINVAL;
 446
 447         regmap_field_write(i2s->field_fmt_wss, wss);
 448         regmap_field_write(i2s->field_fmt_sr, sr);
 449
 450         return sun4i_i2s_set_clk_rate(dai, params_rate(params),
 451                                       params_width(params));
 452 }
 453
 454 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 455 {
 456         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 457         u32 val;
 458         u32 offset = 0;
 459         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 460         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 461
 462         /* DAI Mode */
 463         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 464         case SND_SOC_DAIFMT_I2S:
 465                 val = SUN4I_I2S_FMT0_FMT_I2S;
 466                 offset = 1;
 467                 break;
 468         case SND_SOC_DAIFMT_LEFT_J:
 469                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 470                 break;
 471         case SND_SOC_DAIFMT_RIGHT_J:
 472                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 473                 break;
 474         default:
 475                 dev_err(dai->dev, "Unsupported format: %d\n",
 476                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 477                 return -EINVAL;
 478         }
 479
 480         if (i2s->variant->has_chsel_offset) {
 481                 /*
 482                  * offset being set indicates that we're connected to an i2s
 483                  * device, however offset is only used on the sun8i block and
 484                  * i2s shares the same setting with the LJ format. Increment
 485                  * val so that the bit to value to write is correct.
 486                  */
 487                 if (offset > 0)
 488                         val++;
 489                 /* blck offset determines whether i2s or LJ */
 490                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 491                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 492                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 493
 494                 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
 495                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 496                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 497         }
 498
 499         regmap_field_write(i2s->field_fmt_mode, val);
 500
 501         /* DAI clock polarity */
 502         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 503         case SND_SOC_DAIFMT_IB_IF:
 504                 /* Invert both clocks */
 505                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 506                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 507                 break;
 508         case SND_SOC_DAIFMT_IB_NF:
 509                 /* Invert bit clock */
 510                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 511                 break;
 512         case SND_SOC_DAIFMT_NB_IF:
 513                 /* Invert frame clock */
 514                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 515                 break;
 516         case SND_SOC_DAIFMT_NB_NF:
 517                 break;
 518         default:
 519                 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
 520                         fmt & SND_SOC_DAIFMT_INV_MASK);
 521                 return -EINVAL;
 522         }
 523
 524         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 525         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 526
 527         if (i2s->variant->has_slave_select_bit) {
 528                 /* DAI clock master masks */
 529                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 530                 case SND_SOC_DAIFMT_CBS_CFS:
 531                         /* BCLK and LRCLK master */
 532                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 533                         break;
 534                 case SND_SOC_DAIFMT_CBM_CFM:
 535                         /* BCLK and LRCLK slave */
 536                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 537                         break;
 538                 default:
 539                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 540                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 541                         return -EINVAL;
 542                 }
 543                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 544                                    SUN4I_I2S_CTRL_MODE_MASK,
 545                                    val);
 546         } else {
 547                 /*
 548                  * The newer i2s block does not have a slave select bit,
 549                  * instead the clk pins are configured as inputs.
 550                  */
 551                 /* DAI clock master masks */
 552                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 553                 case SND_SOC_DAIFMT_CBS_CFS:
 554                         /* BCLK and LRCLK master */
 555                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 556                                 SUN8I_I2S_CTRL_LRCK_OUT;
 557                         break;
 558                 case SND_SOC_DAIFMT_CBM_CFM:
 559                         /* BCLK and LRCLK slave */
 560                         val = 0;
 561                         break;
 562                 default:
 563                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 564                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 565                         return -EINVAL;
 566                 }
 567                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 568                                    SUN8I_I2S_CTRL_BCLK_OUT |
 569                                    SUN8I_I2S_CTRL_LRCK_OUT,
 570                                    val);
 571         }
 572
 573         /* Set significant bits in our FIFOs */
 574         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 575                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 576                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 577                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 578                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 579         return 0;
 580 }
 581
 582 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 583 {
 584         /* Flush RX FIFO */
 585         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 586                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 587                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 588
 589         /* Clear RX counter */
 590         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 591
 592         /* Enable RX Block */
 593         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 594                            SUN4I_I2S_CTRL_RX_EN,
 595                            SUN4I_I2S_CTRL_RX_EN);
 596
 597         /* Enable RX DRQ */
 598         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 599                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 600                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 601 }
 602
 603 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 604 {
 605         /* Flush TX FIFO */
 606         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 607                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 608                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 609
 610         /* Clear TX counter */
 611         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 612
 613         /* Enable TX Block */
 614         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 615                            SUN4I_I2S_CTRL_TX_EN,
 616                            SUN4I_I2S_CTRL_TX_EN);
 617
 618         /* Enable TX DRQ */
 619         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 620                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 621                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 622 }
 623
 624 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 625 {
 626         /* Disable RX Block */
 627         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 628                            SUN4I_I2S_CTRL_RX_EN,
 629                            0);
 630
 631         /* Disable RX DRQ */
 632         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 633                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 634                            0);
 635 }
 636
 637 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 638 {
 639         /* Disable TX Block */
 640         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 641                            SUN4I_I2S_CTRL_TX_EN,
 642                            0);
 643
 644         /* Disable TX DRQ */
 645         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 646                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 647                            0);
 648 }
 649
 650 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 651                              struct snd_soc_dai *dai)
 652 {
 653         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 654
 655         switch (cmd) {
 656         case SNDRV_PCM_TRIGGER_START:
 657         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 658         case SNDRV_PCM_TRIGGER_RESUME:
 659                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 660                         sun4i_i2s_start_playback(i2s);
 661                 else
 662                         sun4i_i2s_start_capture(i2s);
 663                 break;
 664
 665         case SNDRV_PCM_TRIGGER_STOP:
 666         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 667         case SNDRV_PCM_TRIGGER_SUSPEND:
 668                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 669                         sun4i_i2s_stop_playback(i2s);
 670                 else
 671                         sun4i_i2s_stop_capture(i2s);
 672                 break;
 673
 674         default:
 675                 return -EINVAL;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 682                                 unsigned int freq, int dir)
 683 {
 684         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 685
 686         if (clk_id != 0)
 687                 return -EINVAL;
 688
 689         i2s->mclk_freq = freq;
 690
 691         return 0;
 692 }
 693
 694 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 695         .hw_params      = sun4i_i2s_hw_params,
 696         .set_fmt        = sun4i_i2s_set_fmt,
 697         .set_sysclk     = sun4i_i2s_set_sysclk,
 698         .trigger        = sun4i_i2s_trigger,
 699 };
 700
 701 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 702 {
 703         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 704
 705         snd_soc_dai_init_dma_data(dai,
 706                                   &i2s->playback_dma_data,
 707                                   &i2s->capture_dma_data);
 708
 709         snd_soc_dai_set_drvdata(dai, i2s);
 710
 711         return 0;
 712 }
 713
 714 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 715         .probe = sun4i_i2s_dai_probe,
 716         .capture = {
 717                 .stream_name = "Capture",
 718                 .channels_min = 2,
 719                 .channels_max = 2,
 720                 .rates = SNDRV_PCM_RATE_8000_192000,
 721                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 722         },
 723         .playback = {
 724                 .stream_name = "Playback",
 725                 .channels_min = 2,
 726                 .channels_max = 2,
 727                 .rates = SNDRV_PCM_RATE_8000_192000,
 728                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 729         },
 730         .ops = &sun4i_i2s_dai_ops,
 731         .symmetric_rates = 1,
 732 };
 733
 734 static const struct snd_soc_component_driver sun4i_i2s_component = {
 735         .name   = "sun4i-dai",
 736 };
 737
 738 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 739 {
 740         switch (reg) {
 741         case SUN4I_I2S_FIFO_TX_REG:
 742                 return false;
 743
 744         default:
 745                 return true;
 746         }
 747 }
 748
 749 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 750 {
 751         switch (reg) {
 752         case SUN4I_I2S_FIFO_RX_REG:
 753         case SUN4I_I2S_FIFO_STA_REG:
 754                 return false;
 755
 756         default:
 757                 return true;
 758         }
 759 }
 760
 761 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 762 {
 763         switch (reg) {
 764         case SUN4I_I2S_FIFO_RX_REG:
 765         case SUN4I_I2S_INT_STA_REG:
 766         case SUN4I_I2S_RX_CNT_REG:
 767         case SUN4I_I2S_TX_CNT_REG:
 768                 return true;
 769
 770         default:
 771                 return false;
 772         }
 773 }
 774
 775 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 776 {
 777         switch (reg) {
 778         case SUN8I_I2S_FIFO_TX_REG:
 779                 return false;
 780
 781         default:
 782                 return true;
 783         }
 784 }
 785
 786 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 787 {
 788         if (reg == SUN8I_I2S_INT_STA_REG)
 789                 return true;
 790         if (reg == SUN8I_I2S_FIFO_TX_REG)
 791                 return false;
 792
 793         return sun4i_i2s_volatile_reg(dev, reg);
 794 }
 795
 796 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 797         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 798         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 799         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 800         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 801         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 802         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 803         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 804         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 805         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 806         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 807 };
 808
 809 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 810         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 811         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 812         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 813         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 814         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 815         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 816         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 817         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 818         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 819         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 820         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 821 };
 822
 823 static const struct regmap_config sun4i_i2s_regmap_config = {
 824         .reg_bits       = 32,
 825         .reg_stride     = 4,
 826         .val_bits       = 32,
 827         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 828
 829         .cache_type     = REGCACHE_FLAT,
 830         .reg_defaults   = sun4i_i2s_reg_defaults,
 831         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 832         .writeable_reg  = sun4i_i2s_wr_reg,
 833         .readable_reg   = sun4i_i2s_rd_reg,
 834         .volatile_reg   = sun4i_i2s_volatile_reg,
 835 };
 836
 837 static const struct regmap_config sun8i_i2s_regmap_config = {
 838         .reg_bits       = 32,
 839         .reg_stride     = 4,
 840         .val_bits       = 32,
 841         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 842         .cache_type     = REGCACHE_FLAT,
 843         .reg_defaults   = sun8i_i2s_reg_defaults,
 844         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 845         .writeable_reg  = sun4i_i2s_wr_reg,
 846         .readable_reg   = sun8i_i2s_rd_reg,
 847         .volatile_reg   = sun8i_i2s_volatile_reg,
 848 };
 849
 850 static int sun4i_i2s_runtime_resume(struct device *dev)
 851 {
 852         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 853         int ret;
 854
 855         ret = clk_prepare_enable(i2s->bus_clk);
 856         if (ret) {
 857                 dev_err(dev, "Failed to enable bus clock\n");
 858                 return ret;
 859         }
 860
 861         regcache_cache_only(i2s->regmap, false);
 862         regcache_mark_dirty(i2s->regmap);
 863
 864         ret = regcache_sync(i2s->regmap);
 865         if (ret) {
 866                 dev_err(dev, "Failed to sync regmap cache\n");
 867                 goto err_disable_clk;
 868         }
 869
 870         /* Enable the whole hardware block */
 871         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 872                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 873
 874         /* Enable the first output line */
 875         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 876                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 877                            SUN4I_I2S_CTRL_SDO_EN(0));
 878
 879         ret = clk_prepare_enable(i2s->mod_clk);
 880         if (ret) {
 881                 dev_err(dev, "Failed to enable module clock\n");
 882                 goto err_disable_clk;
 883         }
 884
 885         return 0;
 886
 887 err_disable_clk:
 888         clk_disable_unprepare(i2s->bus_clk);
 889         return ret;
 890 }
 891
 892 static int sun4i_i2s_runtime_suspend(struct device *dev)
 893 {
 894         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 895
 896         clk_disable_unprepare(i2s->mod_clk);
 897
 898         /* Disable our output lines */
 899         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 900                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 901
 902         /* Disable the whole hardware block */
 903         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 904                            SUN4I_I2S_CTRL_GL_EN, 0);
 905
 906         regcache_cache_only(i2s->regmap, true);
 907
 908         clk_disable_unprepare(i2s->bus_clk);
 909
 910         return 0;
 911 }
 912
 913 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 914         .has_reset              = false,
 915         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 916         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 917         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 918         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 919         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 920         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 921         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 922         .has_slave_select_bit   = true,
 923         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 924         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 925         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 926         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 927         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 928         .get_sr                 = sun4i_i2s_get_sr,
 929         .get_wss                = sun4i_i2s_get_wss,
 930 };
 931
 932 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 933         .has_reset              = true,
 934         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 935         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 936         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 937         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 938         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 939         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 940         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 941         .has_slave_select_bit   = true,
 942         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 943         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 944         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 945         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 946         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 947         .get_sr                 = sun4i_i2s_get_sr,
 948         .get_wss                = sun4i_i2s_get_wss,
 949 };
 950
 951 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
 952         .has_reset              = true,
 953         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 954         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 955         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 956         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 957         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 958         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 959         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 960         .has_slave_select_bit   = true,
 961         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 962         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 963         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 964         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 965         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 966         .get_sr                 = sun8i_i2s_get_sr_wss,
 967         .get_wss                = sun8i_i2s_get_sr_wss,
 968 };
 969
 970 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 971         .has_reset              = true,
 972         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 973         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 974         .mclk_offset            = 1,
 975         .bclk_offset            = 2,
 976         .has_fmt_set_lrck_period = true,
 977         .has_chcfg              = true,
 978         .has_chsel_tx_chen      = true,
 979         .has_chsel_offset       = true,
 980         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 981         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 982         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 983         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 984         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 985         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 986         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 987         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 988         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 989         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 990         .get_sr                 = sun8i_i2s_get_sr_wss,
 991         .get_wss                = sun8i_i2s_get_sr_wss,
 992 };
 993
 994 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
 995         .has_reset              = true,
 996         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 997         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 998         .has_slave_select_bit   = true,
 999         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
1000         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
1001         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
1002         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
1003         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
1004         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
1005         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
1006         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
1007         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
1008         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
1009         .get_sr                 = sun8i_i2s_get_sr_wss,
1010         .get_wss                = sun8i_i2s_get_sr_wss,
1011 };
1012
1013 static int sun4i_i2s_init_regmap_fields(struct device *dev,
1014                                         struct sun4i_i2s *i2s)
1015 {
1016         i2s->field_clkdiv_mclk_en =
1017                 devm_regmap_field_alloc(dev, i2s->regmap,
1018                                         i2s->variant->field_clkdiv_mclk_en);
1019         if (IS_ERR(i2s->field_clkdiv_mclk_en))
1020                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
1021
1022         i2s->field_fmt_wss =
1023                         devm_regmap_field_alloc(dev, i2s->regmap,
1024                                                 i2s->variant->field_fmt_wss);
1025         if (IS_ERR(i2s->field_fmt_wss))
1026                 return PTR_ERR(i2s->field_fmt_wss);
1027
1028         i2s->field_fmt_sr =
1029                         devm_regmap_field_alloc(dev, i2s->regmap,
1030                                                 i2s->variant->field_fmt_sr);
1031         if (IS_ERR(i2s->field_fmt_sr))
1032                 return PTR_ERR(i2s->field_fmt_sr);
1033
1034         i2s->field_fmt_bclk =
1035                         devm_regmap_field_alloc(dev, i2s->regmap,
1036                                                 i2s->variant->field_fmt_bclk);
1037         if (IS_ERR(i2s->field_fmt_bclk))
1038                 return PTR_ERR(i2s->field_fmt_bclk);
1039
1040         i2s->field_fmt_lrclk =
1041                         devm_regmap_field_alloc(dev, i2s->regmap,
1042                                                 i2s->variant->field_fmt_lrclk);
1043         if (IS_ERR(i2s->field_fmt_lrclk))
1044                 return PTR_ERR(i2s->field_fmt_lrclk);
1045
1046         i2s->field_fmt_mode =
1047                         devm_regmap_field_alloc(dev, i2s->regmap,
1048                                                 i2s->variant->field_fmt_mode);
1049         if (IS_ERR(i2s->field_fmt_mode))
1050                 return PTR_ERR(i2s->field_fmt_mode);
1051
1052         i2s->field_txchanmap =
1053                         devm_regmap_field_alloc(dev, i2s->regmap,
1054                                                 i2s->variant->field_txchanmap);
1055         if (IS_ERR(i2s->field_txchanmap))
1056                 return PTR_ERR(i2s->field_txchanmap);
1057
1058         i2s->field_rxchanmap =
1059                         devm_regmap_field_alloc(dev, i2s->regmap,
1060                                                 i2s->variant->field_rxchanmap);
1061         if (IS_ERR(i2s->field_rxchanmap))
1062                 return PTR_ERR(i2s->field_rxchanmap);
1063
1064         i2s->field_txchansel =
1065                         devm_regmap_field_alloc(dev, i2s->regmap,
1066                                                 i2s->variant->field_txchansel);
1067         if (IS_ERR(i2s->field_txchansel))
1068                 return PTR_ERR(i2s->field_txchansel);
1069
1070         i2s->field_rxchansel =
1071                         devm_regmap_field_alloc(dev, i2s->regmap,
1072                                                 i2s->variant->field_rxchansel);
1073         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1074 }
1075
1076 static int sun4i_i2s_probe(struct platform_device *pdev)
1077 {
1078         struct sun4i_i2s *i2s;
1079         struct resource *res;
1080         void __iomem *regs;
1081         int irq, ret;
1082
1083         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1084         if (!i2s)
1085                 return -ENOMEM;
1086         platform_set_drvdata(pdev, i2s);
1087
1088         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089         regs = devm_ioremap_resource(&pdev->dev, res);
1090         if (IS_ERR(regs))
1091                 return PTR_ERR(regs);
1092
1093         irq = platform_get_irq(pdev, 0);
1094         if (irq < 0) {
1095                 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1096                 return irq;
1097         }
1098
1099         i2s->variant = of_device_get_match_data(&pdev->dev);
1100         if (!i2s->variant) {
1101                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1102                 return -ENODEV;
1103         }
1104
1105         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1106         if (IS_ERR(i2s->bus_clk)) {
1107                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1108                 return PTR_ERR(i2s->bus_clk);
1109         }
1110
1111         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1112                                             i2s->variant->sun4i_i2s_regmap);
1113         if (IS_ERR(i2s->regmap)) {
1114                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1115                 return PTR_ERR(i2s->regmap);
1116         }
1117
1118         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1119         if (IS_ERR(i2s->mod_clk)) {
1120                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1121                 return PTR_ERR(i2s->mod_clk);
1122         }
1123
1124         if (i2s->variant->has_reset) {
1125                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1126                 if (IS_ERR(i2s->rst)) {
1127                         dev_err(&pdev->dev, "Failed to get reset control\n");
1128                         return PTR_ERR(i2s->rst);
1129                 }
1130         }
1131
1132         if (!IS_ERR(i2s->rst)) {
1133                 ret = reset_control_deassert(i2s->rst);
1134                 if (ret) {
1135                         dev_err(&pdev->dev,
1136                                 "Failed to deassert the reset control\n");
1137                         return -EINVAL;
1138                 }
1139         }
1140
1141         i2s->playback_dma_data.addr = res->start +
1142                                         i2s->variant->reg_offset_txdata;
1143         i2s->playback_dma_data.maxburst = 8;
1144
1145         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1146         i2s->capture_dma_data.maxburst = 8;
1147
1148         pm_runtime_enable(&pdev->dev);
1149         if (!pm_runtime_enabled(&pdev->dev)) {
1150                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1151                 if (ret)
1152                         goto err_pm_disable;
1153         }
1154
1155         ret = devm_snd_soc_register_component(&pdev->dev,
1156                                               &sun4i_i2s_component,
1157                                               &sun4i_i2s_dai, 1);
1158         if (ret) {
1159                 dev_err(&pdev->dev, "Could not register DAI\n");
1160                 goto err_suspend;
1161         }
1162
1163         ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1164         if (ret) {
1165                 dev_err(&pdev->dev, "Could not register PCM\n");
1166                 goto err_suspend;
1167         }
1168
1169         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1170         if (ret) {
1171                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1172                 goto err_suspend;
1173         }
1174
1175         return 0;
1176
1177 err_suspend:
1178         if (!pm_runtime_status_suspended(&pdev->dev))
1179                 sun4i_i2s_runtime_suspend(&pdev->dev);
1180 err_pm_disable:
1181         pm_runtime_disable(&pdev->dev);
1182         if (!IS_ERR(i2s->rst))
1183                 reset_control_assert(i2s->rst);
1184
1185         return ret;
1186 }
1187
1188 static int sun4i_i2s_remove(struct platform_device *pdev)
1189 {
1190         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1191
1192         snd_dmaengine_pcm_unregister(&pdev->dev);
1193
1194         pm_runtime_disable(&pdev->dev);
1195         if (!pm_runtime_status_suspended(&pdev->dev))
1196                 sun4i_i2s_runtime_suspend(&pdev->dev);
1197
1198         if (!IS_ERR(i2s->rst))
1199                 reset_control_assert(i2s->rst);
1200
1201         return 0;
1202 }
1203
1204 static const struct of_device_id sun4i_i2s_match[] = {
1205         {
1206                 .compatible = "allwinner,sun4i-a10-i2s",
1207                 .data = &sun4i_a10_i2s_quirks,
1208         },
1209         {
1210                 .compatible = "allwinner,sun6i-a31-i2s",
1211                 .data = &sun6i_a31_i2s_quirks,
1212         },
1213         {
1214                 .compatible = "allwinner,sun8i-a83t-i2s",
1215                 .data = &sun8i_a83t_i2s_quirks,
1216         },
1217         {
1218                 .compatible = "allwinner,sun8i-h3-i2s",
1219                 .data = &sun8i_h3_i2s_quirks,
1220         },
1221         {
1222                 .compatible = "allwinner,sun50i-a64-codec-i2s",
1223                 .data = &sun50i_a64_codec_i2s_quirks,
1224         },
1225         {}
1226 };
1227 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1228
1229 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1230         .runtime_resume         = sun4i_i2s_runtime_resume,
1231         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1232 };
1233
1234 static struct platform_driver sun4i_i2s_driver = {
1235         .probe  = sun4i_i2s_probe,
1236         .remove = sun4i_i2s_remove,
1237         .driver = {
1238                 .name           = "sun4i-i2s",
1239                 .of_match_table = sun4i_i2s_match,
1240                 .pm             = &sun4i_i2s_pm_ops,
1241         },
1242 };
1243 module_platform_driver(sun4i_i2s_driver);
1244
1245 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1246 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1247 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1248 MODULE_LICENSE("GPL");