1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <sound/pcm_params.h>
19 #include <sound/dmaengine_pcm.h>
21 #include "rockchip_i2s.h"
22 #include "rockchip_pcm.h"
24 #define DRV_NAME "rockchip-i2s"
37 struct snd_dmaengine_dai_dma_data capture_dma_data;
38 struct snd_dmaengine_dai_dma_data playback_dma_data;
40 struct regmap *regmap;
47 * Used to indicate the tx/rx status.
48 * I2S controller hopes to start the tx and rx together,
49 * also to stop them when they are both try to stop.
54 const struct rk_i2s_pins *pins;
55 unsigned int bclk_ratio;
58 static int i2s_runtime_suspend(struct device *dev)
60 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
62 regcache_cache_only(i2s->regmap, true);
63 clk_disable_unprepare(i2s->mclk);
68 static int i2s_runtime_resume(struct device *dev)
70 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
73 ret = clk_prepare_enable(i2s->mclk);
75 dev_err(i2s->dev, "clock enable failed %d\n", ret);
79 regcache_cache_only(i2s->regmap, false);
80 regcache_mark_dirty(i2s->regmap);
82 ret = regcache_sync(i2s->regmap);
84 clk_disable_unprepare(i2s->mclk);
89 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
91 return snd_soc_dai_get_drvdata(dai);
94 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
100 regmap_update_bits(i2s->regmap, I2S_DMACR,
101 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
103 regmap_update_bits(i2s->regmap, I2S_XFER,
104 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
105 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
107 i2s->tx_start = true;
109 i2s->tx_start = false;
111 regmap_update_bits(i2s->regmap, I2S_DMACR,
112 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
114 if (!i2s->rx_start) {
115 regmap_update_bits(i2s->regmap, I2S_XFER,
122 regmap_update_bits(i2s->regmap, I2S_CLR,
123 I2S_CLR_TXC | I2S_CLR_RXC,
124 I2S_CLR_TXC | I2S_CLR_RXC);
126 regmap_read(i2s->regmap, I2S_CLR, &val);
128 /* Should wait for clear operation to finish */
130 regmap_read(i2s->regmap, I2S_CLR, &val);
133 dev_warn(i2s->dev, "fail to clear\n");
141 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
143 unsigned int val = 0;
147 regmap_update_bits(i2s->regmap, I2S_DMACR,
148 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
150 regmap_update_bits(i2s->regmap, I2S_XFER,
151 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
152 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
154 i2s->rx_start = true;
156 i2s->rx_start = false;
158 regmap_update_bits(i2s->regmap, I2S_DMACR,
159 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
161 if (!i2s->tx_start) {
162 regmap_update_bits(i2s->regmap, I2S_XFER,
169 regmap_update_bits(i2s->regmap, I2S_CLR,
170 I2S_CLR_TXC | I2S_CLR_RXC,
171 I2S_CLR_TXC | I2S_CLR_RXC);
173 regmap_read(i2s->regmap, I2S_CLR, &val);
175 /* Should wait for clear operation to finish */
177 regmap_read(i2s->regmap, I2S_CLR, &val);
180 dev_warn(i2s->dev, "fail to clear\n");
188 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
191 struct rk_i2s_dev *i2s = to_info(cpu_dai);
192 unsigned int mask = 0, val = 0;
195 pm_runtime_get_sync(cpu_dai->dev);
196 mask = I2S_CKR_MSS_MASK;
197 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
198 case SND_SOC_DAIFMT_CBS_CFS:
199 /* Set source clock in Master mode */
200 val = I2S_CKR_MSS_MASTER;
201 i2s->is_master_mode = true;
203 case SND_SOC_DAIFMT_CBM_CFM:
204 val = I2S_CKR_MSS_SLAVE;
205 i2s->is_master_mode = false;
212 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
214 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
215 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
216 case SND_SOC_DAIFMT_NB_NF:
217 val = I2S_CKR_CKP_NORMAL |
221 case SND_SOC_DAIFMT_NB_IF:
222 val = I2S_CKR_CKP_NORMAL |
223 I2S_CKR_TLP_INVERTED |
224 I2S_CKR_RLP_INVERTED;
226 case SND_SOC_DAIFMT_IB_NF:
227 val = I2S_CKR_CKP_INVERTED |
231 case SND_SOC_DAIFMT_IB_IF:
232 val = I2S_CKR_CKP_INVERTED |
233 I2S_CKR_TLP_INVERTED |
234 I2S_CKR_RLP_INVERTED;
241 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
243 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
245 case SND_SOC_DAIFMT_RIGHT_J:
246 val = I2S_TXCR_IBM_RSJM;
248 case SND_SOC_DAIFMT_LEFT_J:
249 val = I2S_TXCR_IBM_LSJM;
251 case SND_SOC_DAIFMT_I2S:
252 val = I2S_TXCR_IBM_NORMAL;
254 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
255 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
257 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
258 val = I2S_TXCR_TFS_PCM;
265 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
267 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
268 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
269 case SND_SOC_DAIFMT_RIGHT_J:
270 val = I2S_RXCR_IBM_RSJM;
272 case SND_SOC_DAIFMT_LEFT_J:
273 val = I2S_RXCR_IBM_LSJM;
275 case SND_SOC_DAIFMT_I2S:
276 val = I2S_RXCR_IBM_NORMAL;
278 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
279 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
281 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
282 val = I2S_RXCR_TFS_PCM;
289 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
292 pm_runtime_put(cpu_dai->dev);
297 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
298 struct snd_pcm_hw_params *params,
299 struct snd_soc_dai *dai)
301 struct rk_i2s_dev *i2s = to_info(dai);
302 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
303 unsigned int val = 0;
304 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
306 if (i2s->is_master_mode) {
307 mclk_rate = clk_get_rate(i2s->mclk);
308 bclk_rate = i2s->bclk_ratio * params_rate(params);
312 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
313 div_lrck = bclk_rate / params_rate(params);
314 regmap_update_bits(i2s->regmap, I2S_CKR,
316 I2S_CKR_MDIV(div_bclk));
318 regmap_update_bits(i2s->regmap, I2S_CKR,
321 I2S_CKR_TSD(div_lrck) |
322 I2S_CKR_RSD(div_lrck));
325 switch (params_format(params)) {
326 case SNDRV_PCM_FORMAT_S8:
327 val |= I2S_TXCR_VDW(8);
329 case SNDRV_PCM_FORMAT_S16_LE:
330 val |= I2S_TXCR_VDW(16);
332 case SNDRV_PCM_FORMAT_S20_3LE:
333 val |= I2S_TXCR_VDW(20);
335 case SNDRV_PCM_FORMAT_S24_LE:
336 val |= I2S_TXCR_VDW(24);
338 case SNDRV_PCM_FORMAT_S32_LE:
339 val |= I2S_TXCR_VDW(32);
345 switch (params_channels(params)) {
359 dev_err(i2s->dev, "invalid channel: %d\n",
360 params_channels(params));
364 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
365 regmap_update_bits(i2s->regmap, I2S_RXCR,
366 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
369 regmap_update_bits(i2s->regmap, I2S_TXCR,
370 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
373 if (!IS_ERR(i2s->grf) && i2s->pins) {
374 regmap_read(i2s->regmap, I2S_TXCR, &val);
375 val &= I2S_TXCR_CSR_MASK;
379 val = I2S_IO_4CH_OUT_6CH_IN;
382 val = I2S_IO_6CH_OUT_4CH_IN;
385 val = I2S_IO_8CH_OUT_2CH_IN;
388 val = I2S_IO_2CH_OUT_8CH_IN;
392 val <<= i2s->pins->shift;
393 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
394 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
397 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
399 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
402 val = I2S_CKR_TRCM_TXRX;
403 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
404 val = I2S_CKR_TRCM_TXONLY;
406 regmap_update_bits(i2s->regmap, I2S_CKR,
412 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
413 int cmd, struct snd_soc_dai *dai)
415 struct rk_i2s_dev *i2s = to_info(dai);
419 case SNDRV_PCM_TRIGGER_START:
420 case SNDRV_PCM_TRIGGER_RESUME:
421 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
422 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
423 rockchip_snd_rxctrl(i2s, 1);
425 rockchip_snd_txctrl(i2s, 1);
427 case SNDRV_PCM_TRIGGER_SUSPEND:
428 case SNDRV_PCM_TRIGGER_STOP:
429 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
430 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
431 rockchip_snd_rxctrl(i2s, 0);
433 rockchip_snd_txctrl(i2s, 0);
443 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
446 struct rk_i2s_dev *i2s = to_info(dai);
448 i2s->bclk_ratio = ratio;
453 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
454 unsigned int freq, int dir)
456 struct rk_i2s_dev *i2s = to_info(cpu_dai);
462 ret = clk_set_rate(i2s->mclk, freq);
464 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
469 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
471 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
473 snd_soc_dai_init_dma_data(dai,
474 i2s->has_playback ? &i2s->playback_dma_data : NULL,
475 i2s->has_capture ? &i2s->capture_dma_data : NULL);
480 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
481 .hw_params = rockchip_i2s_hw_params,
482 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
483 .set_sysclk = rockchip_i2s_set_sysclk,
484 .set_fmt = rockchip_i2s_set_fmt,
485 .trigger = rockchip_i2s_trigger,
488 static struct snd_soc_dai_driver rockchip_i2s_dai = {
489 .probe = rockchip_i2s_dai_probe,
490 .ops = &rockchip_i2s_dai_ops,
494 static const struct snd_soc_component_driver rockchip_i2s_component = {
498 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
515 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
535 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
549 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
559 static const struct reg_default rockchip_i2s_reg_defaults[] = {
567 static const struct regmap_config rockchip_i2s_regmap_config = {
571 .max_register = I2S_RXDR,
572 .reg_defaults = rockchip_i2s_reg_defaults,
573 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
574 .writeable_reg = rockchip_i2s_wr_reg,
575 .readable_reg = rockchip_i2s_rd_reg,
576 .volatile_reg = rockchip_i2s_volatile_reg,
577 .precious_reg = rockchip_i2s_precious_reg,
578 .cache_type = REGCACHE_FLAT,
581 static const struct rk_i2s_pins rk3399_i2s_pins = {
582 .reg_offset = 0xe220,
586 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
587 { .compatible = "rockchip,px30-i2s", },
588 { .compatible = "rockchip,rk1808-i2s", },
589 { .compatible = "rockchip,rk3036-i2s", },
590 { .compatible = "rockchip,rk3066-i2s", },
591 { .compatible = "rockchip,rk3128-i2s", },
592 { .compatible = "rockchip,rk3188-i2s", },
593 { .compatible = "rockchip,rk3228-i2s", },
594 { .compatible = "rockchip,rk3288-i2s", },
595 { .compatible = "rockchip,rk3308-i2s", },
596 { .compatible = "rockchip,rk3328-i2s", },
597 { .compatible = "rockchip,rk3366-i2s", },
598 { .compatible = "rockchip,rk3368-i2s", },
599 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
600 { .compatible = "rockchip,rv1126-i2s", },
604 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
605 struct snd_soc_dai_driver **dp)
607 struct device_node *node = i2s->dev->of_node;
608 struct snd_soc_dai_driver *dai;
609 struct property *dma_names;
610 const char *dma_name;
613 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
614 if (!strcmp(dma_name, "tx"))
615 i2s->has_playback = true;
616 if (!strcmp(dma_name, "rx"))
617 i2s->has_capture = true;
620 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
621 sizeof(*dai), GFP_KERNEL);
625 if (i2s->has_playback) {
626 dai->playback.stream_name = "Playback";
627 dai->playback.channels_min = 2;
628 dai->playback.channels_max = 8;
629 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
630 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
631 SNDRV_PCM_FMTBIT_S16_LE |
632 SNDRV_PCM_FMTBIT_S20_3LE |
633 SNDRV_PCM_FMTBIT_S24_LE |
634 SNDRV_PCM_FMTBIT_S32_LE;
636 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
637 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
638 i2s->playback_dma_data.maxburst = 8;
640 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
641 if (val >= 2 && val <= 8)
642 dai->playback.channels_max = val;
646 if (i2s->has_capture) {
647 dai->capture.stream_name = "Capture";
648 dai->capture.channels_min = 2;
649 dai->capture.channels_max = 8;
650 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
651 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
652 SNDRV_PCM_FMTBIT_S16_LE |
653 SNDRV_PCM_FMTBIT_S20_3LE |
654 SNDRV_PCM_FMTBIT_S24_LE |
655 SNDRV_PCM_FMTBIT_S32_LE;
657 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
658 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
659 i2s->capture_dma_data.maxburst = 8;
661 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
662 if (val >= 2 && val <= 8)
663 dai->capture.channels_max = val;
673 static int rockchip_i2s_probe(struct platform_device *pdev)
675 struct device_node *node = pdev->dev.of_node;
676 const struct of_device_id *of_id;
677 struct rk_i2s_dev *i2s;
678 struct snd_soc_dai_driver *dai;
679 struct resource *res;
683 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
687 i2s->dev = &pdev->dev;
689 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
690 if (!IS_ERR(i2s->grf)) {
691 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
692 if (!of_id || !of_id->data)
695 i2s->pins = of_id->data;
698 /* try to prepare related clocks */
699 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
700 if (IS_ERR(i2s->hclk)) {
701 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
702 return PTR_ERR(i2s->hclk);
704 ret = clk_prepare_enable(i2s->hclk);
706 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
710 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
711 if (IS_ERR(i2s->mclk)) {
712 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
713 return PTR_ERR(i2s->mclk);
716 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
718 return PTR_ERR(regs);
720 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
721 &rockchip_i2s_regmap_config);
722 if (IS_ERR(i2s->regmap)) {
724 "Failed to initialise managed register map\n");
725 return PTR_ERR(i2s->regmap);
728 i2s->bclk_ratio = 64;
730 dev_set_drvdata(&pdev->dev, i2s);
732 pm_runtime_enable(&pdev->dev);
733 if (!pm_runtime_enabled(&pdev->dev)) {
734 ret = i2s_runtime_resume(&pdev->dev);
739 ret = rockchip_i2s_init_dai(i2s, res, &dai);
743 ret = devm_snd_soc_register_component(&pdev->dev,
744 &rockchip_i2s_component,
748 dev_err(&pdev->dev, "Could not register DAI\n");
752 ret = rockchip_pcm_platform_register(&pdev->dev);
754 dev_err(&pdev->dev, "Could not register PCM\n");
761 if (!pm_runtime_status_suspended(&pdev->dev))
762 i2s_runtime_suspend(&pdev->dev);
764 pm_runtime_disable(&pdev->dev);
769 static int rockchip_i2s_remove(struct platform_device *pdev)
771 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
773 pm_runtime_disable(&pdev->dev);
774 if (!pm_runtime_status_suspended(&pdev->dev))
775 i2s_runtime_suspend(&pdev->dev);
777 clk_disable_unprepare(i2s->hclk);
782 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
783 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
787 static struct platform_driver rockchip_i2s_driver = {
788 .probe = rockchip_i2s_probe,
789 .remove = rockchip_i2s_remove,
792 .of_match_table = of_match_ptr(rockchip_i2s_match),
793 .pm = &rockchip_i2s_pm_ops,
796 module_platform_driver(rockchip_i2s_driver);
798 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
799 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
800 MODULE_LICENSE("GPL v2");
801 MODULE_ALIAS("platform:" DRV_NAME);
802 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);