sound/soc/codecs/wcd938x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/slab.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/device.h>
   8 #include <linux/delay.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/component.h>
  12 #include <sound/soc.h>
  13 #include <sound/tlv.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/of.h>
  16 #include <sound/jack.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_params.h>
  19 #include <linux/regmap.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include "wcd-clsh-v2.h"
  25 #include "wcd938x.h"
  26
  27 #define WCD938X_MAX_MICBIAS             (4)
  28 #define WCD938X_MAX_SUPPLY              (4)
  29 #define WCD938X_MBHC_MAX_BUTTONS        (8)
  30 #define TX_ADC_MAX                      (4)
  31 #define WCD938X_TX_MAX_SWR_PORTS        (5)
  32
  33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  34                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  35                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  36 /* Fractional Rates */
  37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  38                                  SNDRV_PCM_RATE_176400)
  39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  40                                     SNDRV_PCM_FMTBIT_S24_LE)
  41 /* Convert from vout ctl to micbias voltage in mV */
  42 #define  WCD_VOUT_CTL_TO_MICB(v)        (1000 + v * 50)
  43 #define SWR_CLK_RATE_0P6MHZ             (600000)
  44 #define SWR_CLK_RATE_1P2MHZ             (1200000)
  45 #define SWR_CLK_RATE_2P4MHZ             (2400000)
  46 #define SWR_CLK_RATE_4P8MHZ             (4800000)
  47 #define SWR_CLK_RATE_9P6MHZ             (9600000)
  48 #define SWR_CLK_RATE_11P2896MHZ         (1128960)
  49
  50 #define WCD938X_DRV_NAME "wcd938x_codec"
  51 #define WCD938X_VERSION_1_0             (1)
  52 #define EAR_RX_PATH_AUX                 (1)
  53
  54 #define ADC_MODE_VAL_HIFI               0x01
  55 #define ADC_MODE_VAL_LO_HIF             0x02
  56 #define ADC_MODE_VAL_NORMAL             0x03
  57 #define ADC_MODE_VAL_LP                 0x05
  58 #define ADC_MODE_VAL_ULP1               0x09
  59 #define ADC_MODE_VAL_ULP2               0x0B
  60
  61 /* Z value defined in milliohm */
  62 #define WCD938X_ZDET_VAL_32             (32000)
  63 #define WCD938X_ZDET_VAL_400            (400000)
  64 #define WCD938X_ZDET_VAL_1200           (1200000)
  65 #define WCD938X_ZDET_VAL_100K           (100000000)
  66 /* Z floating defined in ohms */
  67 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
  68 #define WCD938X_ZDET_NUM_MEASUREMENTS   (900)
  69 #define WCD938X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
  70 #define WCD938X_MBHC_GET_X1(x)          (x & 0x3FFF)
  71 /* Z value compared in milliOhm */
  72 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
  73 #define WCD938X_MBHC_ZDET_CONST         (86 * 16384)
  74 #define WCD938X_MBHC_MOISTURE_RREF      R_24_KOHM
  75 #define WCD_MBHC_HS_V_MAX           1600
  76
  77 enum {
  78         WCD9380 = 0,
  79         WCD9385 = 5,
  80 };
  81
  82 enum {
  83         TX_HDR12 = 0,
  84         TX_HDR34,
  85         TX_HDR_MAX,
  86 };
  87
  88 enum {
  89         WCD_RX1,
  90         WCD_RX2,
  91         WCD_RX3
  92 };
  93
  94 enum {
  95         /* INTR_CTRL_INT_MASK_0 */
  96         WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  97         WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
  98         WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
  99         WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 100         WCD938X_IRQ_MBHC_SW_DET,
 101         WCD938X_IRQ_HPHR_OCP_INT,
 102         WCD938X_IRQ_HPHR_CNP_INT,
 103         WCD938X_IRQ_HPHL_OCP_INT,
 104
 105         /* INTR_CTRL_INT_MASK_1 */
 106         WCD938X_IRQ_HPHL_CNP_INT,
 107         WCD938X_IRQ_EAR_CNP_INT,
 108         WCD938X_IRQ_EAR_SCD_INT,
 109         WCD938X_IRQ_AUX_CNP_INT,
 110         WCD938X_IRQ_AUX_SCD_INT,
 111         WCD938X_IRQ_HPHL_PDM_WD_INT,
 112         WCD938X_IRQ_HPHR_PDM_WD_INT,
 113         WCD938X_IRQ_AUX_PDM_WD_INT,
 114
 115         /* INTR_CTRL_INT_MASK_2 */
 116         WCD938X_IRQ_LDORT_SCD_INT,
 117         WCD938X_IRQ_MBHC_MOISTURE_INT,
 118         WCD938X_IRQ_HPHL_SURGE_DET_INT,
 119         WCD938X_IRQ_HPHR_SURGE_DET_INT,
 120         WCD938X_NUM_IRQS,
 121 };
 122
 123 enum {
 124         WCD_ADC1 = 0,
 125         WCD_ADC2,
 126         WCD_ADC3,
 127         WCD_ADC4,
 128         ALLOW_BUCK_DISABLE,
 129         HPH_COMP_DELAY,
 130         HPH_PA_DELAY,
 131         AMIC2_BCS_ENABLE,
 132         WCD_SUPPLIES_LPM_MODE,
 133 };
 134
 135 enum {
 136         ADC_MODE_INVALID = 0,
 137         ADC_MODE_HIFI,
 138         ADC_MODE_LO_HIF,
 139         ADC_MODE_NORMAL,
 140         ADC_MODE_LP,
 141         ADC_MODE_ULP1,
 142         ADC_MODE_ULP2,
 143 };
 144
 145 enum {
 146         AIF1_PB = 0,
 147         AIF1_CAP,
 148         NUM_CODEC_DAIS,
 149 };
 150
 151 struct wcd938x_priv {
 152         struct sdw_slave *tx_sdw_dev;
 153         struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
 154         struct device *txdev;
 155         struct device *rxdev;
 156         struct device_node *rxnode, *txnode;
 157         struct regmap *regmap;
 158         struct wcd_clsh_ctrl *clsh_info;
 159         struct irq_domain *virq;
 160         struct regmap_irq_chip *wcd_regmap_irq_chip;
 161         struct regmap_irq_chip_data *irq_chip;
 162         struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
 163         struct snd_soc_jack *jack;
 164         unsigned long status_mask;
 165         s32 micb_ref[WCD938X_MAX_MICBIAS];
 166         s32 pullup_ref[WCD938X_MAX_MICBIAS];
 167         u32 hph_mode;
 168         u32 tx_mode[TX_ADC_MAX];
 169         int flyback_cur_det_disable;
 170         int ear_rx_path;
 171         int variant;
 172         int reset_gpio;
 173         u32 micb1_mv;
 174         u32 micb2_mv;
 175         u32 micb3_mv;
 176         u32 micb4_mv;
 177         int hphr_pdm_wd_int;
 178         int hphl_pdm_wd_int;
 179         int aux_pdm_wd_int;
 180         bool comp1_enable;
 181         bool comp2_enable;
 182         bool ldoh;
 183         bool bcs_dis;
 184 };
 185
 186 enum {
 187         MIC_BIAS_1 = 1,
 188         MIC_BIAS_2,
 189         MIC_BIAS_3,
 190         MIC_BIAS_4
 191 };
 192
 193 enum {
 194         MICB_PULLUP_ENABLE,
 195         MICB_PULLUP_DISABLE,
 196         MICB_ENABLE,
 197         MICB_DISABLE,
 198 };
 199
 200 static const struct reg_default wcd938x_defaults[] = {
 201         {WCD938X_ANA_PAGE_REGISTER,                            0x00},
 202         {WCD938X_ANA_BIAS,                                     0x00},
 203         {WCD938X_ANA_RX_SUPPLIES,                              0x00},
 204         {WCD938X_ANA_HPH,                                      0x0C},
 205         {WCD938X_ANA_EAR,                                      0x00},
 206         {WCD938X_ANA_EAR_COMPANDER_CTL,                        0x02},
 207         {WCD938X_ANA_TX_CH1,                                   0x20},
 208         {WCD938X_ANA_TX_CH2,                                   0x00},
 209         {WCD938X_ANA_TX_CH3,                                   0x20},
 210         {WCD938X_ANA_TX_CH4,                                   0x00},
 211         {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC,                 0x00},
 212         {WCD938X_ANA_MICB3_DSP_EN_LOGIC,                       0x00},
 213         {WCD938X_ANA_MBHC_MECH,                                0x39},
 214         {WCD938X_ANA_MBHC_ELECT,                               0x08},
 215         {WCD938X_ANA_MBHC_ZDET,                                0x00},
 216         {WCD938X_ANA_MBHC_RESULT_1,                            0x00},
 217         {WCD938X_ANA_MBHC_RESULT_2,                            0x00},
 218         {WCD938X_ANA_MBHC_RESULT_3,                            0x00},
 219         {WCD938X_ANA_MBHC_BTN0,                                0x00},
 220         {WCD938X_ANA_MBHC_BTN1,                                0x10},
 221         {WCD938X_ANA_MBHC_BTN2,                                0x20},
 222         {WCD938X_ANA_MBHC_BTN3,                                0x30},
 223         {WCD938X_ANA_MBHC_BTN4,                                0x40},
 224         {WCD938X_ANA_MBHC_BTN5,                                0x50},
 225         {WCD938X_ANA_MBHC_BTN6,                                0x60},
 226         {WCD938X_ANA_MBHC_BTN7,                                0x70},
 227         {WCD938X_ANA_MICB1,                                    0x10},
 228         {WCD938X_ANA_MICB2,                                    0x10},
 229         {WCD938X_ANA_MICB2_RAMP,                               0x00},
 230         {WCD938X_ANA_MICB3,                                    0x10},
 231         {WCD938X_ANA_MICB4,                                    0x10},
 232         {WCD938X_BIAS_CTL,                                     0x2A},
 233         {WCD938X_BIAS_VBG_FINE_ADJ,                            0x55},
 234         {WCD938X_LDOL_VDDCX_ADJUST,                            0x01},
 235         {WCD938X_LDOL_DISABLE_LDOL,                            0x00},
 236         {WCD938X_MBHC_CTL_CLK,                                 0x00},
 237         {WCD938X_MBHC_CTL_ANA,                                 0x00},
 238         {WCD938X_MBHC_CTL_SPARE_1,                             0x00},
 239         {WCD938X_MBHC_CTL_SPARE_2,                             0x00},
 240         {WCD938X_MBHC_CTL_BCS,                                 0x00},
 241         {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS,                 0x00},
 242         {WCD938X_MBHC_TEST_CTL,                                0x00},
 243         {WCD938X_LDOH_MODE,                                    0x2B},
 244         {WCD938X_LDOH_BIAS,                                    0x68},
 245         {WCD938X_LDOH_STB_LOADS,                               0x00},
 246         {WCD938X_LDOH_SLOWRAMP,                                0x50},
 247         {WCD938X_MICB1_TEST_CTL_1,                             0x1A},
 248         {WCD938X_MICB1_TEST_CTL_2,                             0x00},
 249         {WCD938X_MICB1_TEST_CTL_3,                             0xA4},
 250         {WCD938X_MICB2_TEST_CTL_1,                             0x1A},
 251         {WCD938X_MICB2_TEST_CTL_2,                             0x00},
 252         {WCD938X_MICB2_TEST_CTL_3,                             0x24},
 253         {WCD938X_MICB3_TEST_CTL_1,                             0x1A},
 254         {WCD938X_MICB3_TEST_CTL_2,                             0x00},
 255         {WCD938X_MICB3_TEST_CTL_3,                             0xA4},
 256         {WCD938X_MICB4_TEST_CTL_1,                             0x1A},
 257         {WCD938X_MICB4_TEST_CTL_2,                             0x00},
 258         {WCD938X_MICB4_TEST_CTL_3,                             0xA4},
 259         {WCD938X_TX_COM_ADC_VCM,                               0x39},
 260         {WCD938X_TX_COM_BIAS_ATEST,                            0xE0},
 261         {WCD938X_TX_COM_SPARE1,                                0x00},
 262         {WCD938X_TX_COM_SPARE2,                                0x00},
 263         {WCD938X_TX_COM_TXFE_DIV_CTL,                          0x22},
 264         {WCD938X_TX_COM_TXFE_DIV_START,                        0x00},
 265         {WCD938X_TX_COM_SPARE3,                                0x00},
 266         {WCD938X_TX_COM_SPARE4,                                0x00},
 267         {WCD938X_TX_1_2_TEST_EN,                               0xCC},
 268         {WCD938X_TX_1_2_ADC_IB,                                0xE9},
 269         {WCD938X_TX_1_2_ATEST_REFCTL,                          0x0A},
 270         {WCD938X_TX_1_2_TEST_CTL,                              0x38},
 271         {WCD938X_TX_1_2_TEST_BLK_EN1,                          0xFF},
 272         {WCD938X_TX_1_2_TXFE1_CLKDIV,                          0x00},
 273         {WCD938X_TX_1_2_SAR2_ERR,                              0x00},
 274         {WCD938X_TX_1_2_SAR1_ERR,                              0x00},
 275         {WCD938X_TX_3_4_TEST_EN,                               0xCC},
 276         {WCD938X_TX_3_4_ADC_IB,                                0xE9},
 277         {WCD938X_TX_3_4_ATEST_REFCTL,                          0x0A},
 278         {WCD938X_TX_3_4_TEST_CTL,                              0x38},
 279         {WCD938X_TX_3_4_TEST_BLK_EN3,                          0xFF},
 280         {WCD938X_TX_3_4_TXFE3_CLKDIV,                          0x00},
 281         {WCD938X_TX_3_4_SAR4_ERR,                              0x00},
 282         {WCD938X_TX_3_4_SAR3_ERR,                              0x00},
 283         {WCD938X_TX_3_4_TEST_BLK_EN2,                          0xFB},
 284         {WCD938X_TX_3_4_TXFE2_CLKDIV,                          0x00},
 285         {WCD938X_TX_3_4_SPARE1,                                0x00},
 286         {WCD938X_TX_3_4_TEST_BLK_EN4,                          0xFB},
 287         {WCD938X_TX_3_4_TXFE4_CLKDIV,                          0x00},
 288         {WCD938X_TX_3_4_SPARE2,                                0x00},
 289         {WCD938X_CLASSH_MODE_1,                                0x40},
 290         {WCD938X_CLASSH_MODE_2,                                0x3A},
 291         {WCD938X_CLASSH_MODE_3,                                0x00},
 292         {WCD938X_CLASSH_CTRL_VCL_1,                            0x70},
 293         {WCD938X_CLASSH_CTRL_VCL_2,                            0x82},
 294         {WCD938X_CLASSH_CTRL_CCL_1,                            0x31},
 295         {WCD938X_CLASSH_CTRL_CCL_2,                            0x80},
 296         {WCD938X_CLASSH_CTRL_CCL_3,                            0x80},
 297         {WCD938X_CLASSH_CTRL_CCL_4,                            0x51},
 298         {WCD938X_CLASSH_CTRL_CCL_5,                            0x00},
 299         {WCD938X_CLASSH_BUCK_TMUX_A_D,                         0x00},
 300         {WCD938X_CLASSH_BUCK_SW_DRV_CNTL,                      0x77},
 301         {WCD938X_CLASSH_SPARE,                                 0x00},
 302         {WCD938X_FLYBACK_EN,                                   0x4E},
 303         {WCD938X_FLYBACK_VNEG_CTRL_1,                          0x0B},
 304         {WCD938X_FLYBACK_VNEG_CTRL_2,                          0x45},
 305         {WCD938X_FLYBACK_VNEG_CTRL_3,                          0x74},
 306         {WCD938X_FLYBACK_VNEG_CTRL_4,                          0x7F},
 307         {WCD938X_FLYBACK_VNEG_CTRL_5,                          0x83},
 308         {WCD938X_FLYBACK_VNEG_CTRL_6,                          0x98},
 309         {WCD938X_FLYBACK_VNEG_CTRL_7,                          0xA9},
 310         {WCD938X_FLYBACK_VNEG_CTRL_8,                          0x68},
 311         {WCD938X_FLYBACK_VNEG_CTRL_9,                          0x64},
 312         {WCD938X_FLYBACK_VNEGDAC_CTRL_1,                       0xED},
 313         {WCD938X_FLYBACK_VNEGDAC_CTRL_2,                       0xF0},
 314         {WCD938X_FLYBACK_VNEGDAC_CTRL_3,                       0xA6},
 315         {WCD938X_FLYBACK_CTRL_1,                               0x65},
 316         {WCD938X_FLYBACK_TEST_CTL,                             0x00},
 317         {WCD938X_RX_AUX_SW_CTL,                                0x00},
 318         {WCD938X_RX_PA_AUX_IN_CONN,                            0x01},
 319         {WCD938X_RX_TIMER_DIV,                                 0x32},
 320         {WCD938X_RX_OCP_CTL,                                   0x1F},
 321         {WCD938X_RX_OCP_COUNT,                                 0x77},
 322         {WCD938X_RX_BIAS_EAR_DAC,                              0xA0},
 323         {WCD938X_RX_BIAS_EAR_AMP,                              0xAA},
 324         {WCD938X_RX_BIAS_HPH_LDO,                              0xA9},
 325         {WCD938X_RX_BIAS_HPH_PA,                               0xAA},
 326         {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2,                    0x8A},
 327         {WCD938X_RX_BIAS_HPH_RDAC_LDO,                         0x88},
 328         {WCD938X_RX_BIAS_HPH_CNP1,                             0x82},
 329         {WCD938X_RX_BIAS_HPH_LOWPOWER,                         0x82},
 330         {WCD938X_RX_BIAS_AUX_DAC,                              0xA0},
 331         {WCD938X_RX_BIAS_AUX_AMP,                              0xAA},
 332         {WCD938X_RX_BIAS_VNEGDAC_BLEEDER,                      0x50},
 333         {WCD938X_RX_BIAS_MISC,                                 0x00},
 334         {WCD938X_RX_BIAS_BUCK_RST,                             0x08},
 335         {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP,                     0x44},
 336         {WCD938X_RX_BIAS_FLYB_ERRAMP,                          0x40},
 337         {WCD938X_RX_BIAS_FLYB_BUFF,                            0xAA},
 338         {WCD938X_RX_BIAS_FLYB_MID_RST,                         0x14},
 339         {WCD938X_HPH_L_STATUS,                                 0x04},
 340         {WCD938X_HPH_R_STATUS,                                 0x04},
 341         {WCD938X_HPH_CNP_EN,                                   0x80},
 342         {WCD938X_HPH_CNP_WG_CTL,                               0x9A},
 343         {WCD938X_HPH_CNP_WG_TIME,                              0x14},
 344         {WCD938X_HPH_OCP_CTL,                                  0x28},
 345         {WCD938X_HPH_AUTO_CHOP,                                0x16},
 346         {WCD938X_HPH_CHOP_CTL,                                 0x83},
 347         {WCD938X_HPH_PA_CTL1,                                  0x46},
 348         {WCD938X_HPH_PA_CTL2,                                  0x50},
 349         {WCD938X_HPH_L_EN,                                     0x80},
 350         {WCD938X_HPH_L_TEST,                                   0xE0},
 351         {WCD938X_HPH_L_ATEST,                                  0x50},
 352         {WCD938X_HPH_R_EN,                                     0x80},
 353         {WCD938X_HPH_R_TEST,                                   0xE0},
 354         {WCD938X_HPH_R_ATEST,                                  0x54},
 355         {WCD938X_HPH_RDAC_CLK_CTL1,                            0x99},
 356         {WCD938X_HPH_RDAC_CLK_CTL2,                            0x9B},
 357         {WCD938X_HPH_RDAC_LDO_CTL,                             0x33},
 358         {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL,                     0x00},
 359         {WCD938X_HPH_REFBUFF_UHQA_CTL,                         0x68},
 360         {WCD938X_HPH_REFBUFF_LP_CTL,                           0x0E},
 361         {WCD938X_HPH_L_DAC_CTL,                                0x20},
 362         {WCD938X_HPH_R_DAC_CTL,                                0x20},
 363         {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL,               0x55},
 364         {WCD938X_HPH_SURGE_HPHLR_SURGE_EN,                     0x19},
 365         {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1,                  0xA0},
 366         {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS,                 0x00},
 367         {WCD938X_EAR_EAR_EN_REG,                               0x22},
 368         {WCD938X_EAR_EAR_PA_CON,                               0x44},
 369         {WCD938X_EAR_EAR_SP_CON,                               0xDB},
 370         {WCD938X_EAR_EAR_DAC_CON,                              0x80},
 371         {WCD938X_EAR_EAR_CNP_FSM_CON,                          0xB2},
 372         {WCD938X_EAR_TEST_CTL,                                 0x00},
 373         {WCD938X_EAR_STATUS_REG_1,                             0x00},
 374         {WCD938X_EAR_STATUS_REG_2,                             0x08},
 375         {WCD938X_ANA_NEW_PAGE_REGISTER,                        0x00},
 376         {WCD938X_HPH_NEW_ANA_HPH2,                             0x00},
 377         {WCD938X_HPH_NEW_ANA_HPH3,                             0x00},
 378         {WCD938X_SLEEP_CTL,                                    0x16},
 379         {WCD938X_SLEEP_WATCHDOG_CTL,                           0x00},
 380         {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL,                 0x00},
 381         {WCD938X_MBHC_NEW_CTL_1,                               0x02},
 382         {WCD938X_MBHC_NEW_CTL_2,                               0x05},
 383         {WCD938X_MBHC_NEW_PLUG_DETECT_CTL,                     0xE9},
 384         {WCD938X_MBHC_NEW_ZDET_ANA_CTL,                        0x0F},
 385         {WCD938X_MBHC_NEW_ZDET_RAMP_CTL,                       0x00},
 386         {WCD938X_MBHC_NEW_FSM_STATUS,                          0x00},
 387         {WCD938X_MBHC_NEW_ADC_RESULT,                          0x00},
 388         {WCD938X_TX_NEW_AMIC_MUX_CFG,                          0x00},
 389         {WCD938X_AUX_AUXPA,                                    0x00},
 390         {WCD938X_LDORXTX_MODE,                                 0x0C},
 391         {WCD938X_LDORXTX_CONFIG,                               0x10},
 392         {WCD938X_DIE_CRACK_DIE_CRK_DET_EN,                     0x00},
 393         {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT,                    0x00},
 394         {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,                    0x40},
 395         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,                   0x81},
 396         {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL,                    0x10},
 397         {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL,                0x00},
 398         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,                   0x81},
 399         {WCD938X_HPH_NEW_INT_PA_MISC1,                         0x22},
 400         {WCD938X_HPH_NEW_INT_PA_MISC2,                         0x00},
 401         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC,                     0x00},
 402         {WCD938X_HPH_NEW_INT_HPH_TIMER1,                       0xFE},
 403         {WCD938X_HPH_NEW_INT_HPH_TIMER2,                       0x02},
 404         {WCD938X_HPH_NEW_INT_HPH_TIMER3,                       0x4E},
 405         {WCD938X_HPH_NEW_INT_HPH_TIMER4,                       0x54},
 406         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2,                    0x00},
 407         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3,                    0x00},
 408         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,               0x90},
 409         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,               0x90},
 410         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI,              0x62},
 411         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,                 0x01},
 412         {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP,                   0x11},
 413         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL,            0x57},
 414         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,       0x01},
 415         {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,                0x00},
 416         {WCD938X_MBHC_NEW_INT_SPARE_2,                         0x00},
 417         {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON,                  0xA8},
 418         {WCD938X_EAR_INT_NEW_CNP_VCM_CON1,                     0x42},
 419         {WCD938X_EAR_INT_NEW_CNP_VCM_CON2,                     0x22},
 420         {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS,                 0x00},
 421         {WCD938X_AUX_INT_EN_REG,                               0x00},
 422         {WCD938X_AUX_INT_PA_CTRL,                              0x06},
 423         {WCD938X_AUX_INT_SP_CTRL,                              0xD2},
 424         {WCD938X_AUX_INT_DAC_CTRL,                             0x80},
 425         {WCD938X_AUX_INT_CLK_CTRL,                             0x50},
 426         {WCD938X_AUX_INT_TEST_CTRL,                            0x00},
 427         {WCD938X_AUX_INT_STATUS_REG,                           0x00},
 428         {WCD938X_AUX_INT_MISC,                                 0x00},
 429         {WCD938X_LDORXTX_INT_BIAS,                             0x6E},
 430         {WCD938X_LDORXTX_INT_STB_LOADS_DTEST,                  0x50},
 431         {WCD938X_LDORXTX_INT_TEST0,                            0x1C},
 432         {WCD938X_LDORXTX_INT_STARTUP_TIMER,                    0xFF},
 433         {WCD938X_LDORXTX_INT_TEST1,                            0x1F},
 434         {WCD938X_LDORXTX_INT_STATUS,                           0x00},
 435         {WCD938X_SLEEP_INT_WATCHDOG_CTL_1,                     0x0A},
 436         {WCD938X_SLEEP_INT_WATCHDOG_CTL_2,                     0x0A},
 437         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1,               0x02},
 438         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2,               0x60},
 439         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2,               0xFF},
 440         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1,               0x7F},
 441         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0,               0x3F},
 442         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M,          0x1F},
 443         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M,          0x0F},
 444         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1,          0xD7},
 445         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0,            0xC8},
 446         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP,           0xC6},
 447         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1,      0xD5},
 448         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0,        0xCA},
 449         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,       0x05},
 450         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0,    0xA5},
 451         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,       0x13},
 452         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1,             0x88},
 453         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP,            0x42},
 454         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2,                  0xFF},
 455         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1,                  0x64},
 456         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0,                  0x64},
 457         {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP,                 0x77},
 458         {WCD938X_DIGITAL_PAGE_REGISTER,                        0x00},
 459         {WCD938X_DIGITAL_CHIP_ID0,                             0x00},
 460         {WCD938X_DIGITAL_CHIP_ID1,                             0x00},
 461         {WCD938X_DIGITAL_CHIP_ID2,                             0x0D},
 462         {WCD938X_DIGITAL_CHIP_ID3,                             0x01},
 463         {WCD938X_DIGITAL_SWR_TX_CLK_RATE,                      0x00},
 464         {WCD938X_DIGITAL_CDC_RST_CTL,                          0x03},
 465         {WCD938X_DIGITAL_TOP_CLK_CFG,                          0x00},
 466         {WCD938X_DIGITAL_CDC_ANA_CLK_CTL,                      0x00},
 467         {WCD938X_DIGITAL_CDC_DIG_CLK_CTL,                      0xF0},
 468         {WCD938X_DIGITAL_SWR_RST_EN,                           0x00},
 469         {WCD938X_DIGITAL_CDC_PATH_MODE,                        0x55},
 470         {WCD938X_DIGITAL_CDC_RX_RST,                           0x00},
 471         {WCD938X_DIGITAL_CDC_RX0_CTL,                          0xFC},
 472         {WCD938X_DIGITAL_CDC_RX1_CTL,                          0xFC},
 473         {WCD938X_DIGITAL_CDC_RX2_CTL,                          0xFC},
 474         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,                  0x00},
 475         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,                  0x00},
 476         {WCD938X_DIGITAL_CDC_COMP_CTL_0,                       0x00},
 477         {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,                   0x1E},
 478         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0,                     0x00},
 479         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1,                     0x01},
 480         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0,                     0x63},
 481         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1,                     0x04},
 482         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0,                     0xAC},
 483         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1,                     0x04},
 484         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0,                     0x1A},
 485         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1,                     0x03},
 486         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0,                     0xBC},
 487         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1,                     0x02},
 488         {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0,                     0xC7},
 489         {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0,                     0xF8},
 490         {WCD938X_DIGITAL_CDC_HPH_DSM_C_0,                      0x47},
 491         {WCD938X_DIGITAL_CDC_HPH_DSM_C_1,                      0x43},
 492         {WCD938X_DIGITAL_CDC_HPH_DSM_C_2,                      0xB1},
 493         {WCD938X_DIGITAL_CDC_HPH_DSM_C_3,                      0x17},
 494         {WCD938X_DIGITAL_CDC_HPH_DSM_R1,                       0x4D},
 495         {WCD938X_DIGITAL_CDC_HPH_DSM_R2,                       0x29},
 496         {WCD938X_DIGITAL_CDC_HPH_DSM_R3,                       0x34},
 497         {WCD938X_DIGITAL_CDC_HPH_DSM_R4,                       0x59},
 498         {WCD938X_DIGITAL_CDC_HPH_DSM_R5,                       0x66},
 499         {WCD938X_DIGITAL_CDC_HPH_DSM_R6,                       0x87},
 500         {WCD938X_DIGITAL_CDC_HPH_DSM_R7,                       0x64},
 501         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0,                     0x00},
 502         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1,                     0x01},
 503         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0,                     0x96},
 504         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1,                     0x09},
 505         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0,                     0xAB},
 506         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1,                     0x05},
 507         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0,                     0x1C},
 508         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1,                     0x02},
 509         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0,                     0x17},
 510         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1,                     0x02},
 511         {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0,                     0xAA},
 512         {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0,                     0xE3},
 513         {WCD938X_DIGITAL_CDC_AUX_DSM_C_0,                      0x69},
 514         {WCD938X_DIGITAL_CDC_AUX_DSM_C_1,                      0x54},
 515         {WCD938X_DIGITAL_CDC_AUX_DSM_C_2,                      0x02},
 516         {WCD938X_DIGITAL_CDC_AUX_DSM_C_3,                      0x15},
 517         {WCD938X_DIGITAL_CDC_AUX_DSM_R1,                       0xA4},
 518         {WCD938X_DIGITAL_CDC_AUX_DSM_R2,                       0xB5},
 519         {WCD938X_DIGITAL_CDC_AUX_DSM_R3,                       0x86},
 520         {WCD938X_DIGITAL_CDC_AUX_DSM_R4,                       0x85},
 521         {WCD938X_DIGITAL_CDC_AUX_DSM_R5,                       0xAA},
 522         {WCD938X_DIGITAL_CDC_AUX_DSM_R6,                       0xE2},
 523         {WCD938X_DIGITAL_CDC_AUX_DSM_R7,                       0x62},
 524         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0,                    0x55},
 525         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1,                    0xA9},
 526         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0,                   0x3D},
 527         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1,                   0x2E},
 528         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2,                   0x01},
 529         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0,                   0x00},
 530         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1,                   0xFC},
 531         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2,                   0x01},
 532         {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,                     0x00},
 533         {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,                     0x00},
 534         {WCD938X_DIGITAL_CDC_EAR_PATH_CTL,                     0x00},
 535         {WCD938X_DIGITAL_CDC_SWR_CLH,                          0x00},
 536         {WCD938X_DIGITAL_SWR_CLH_BYP,                          0x00},
 537         {WCD938X_DIGITAL_CDC_TX0_CTL,                          0x68},
 538         {WCD938X_DIGITAL_CDC_TX1_CTL,                          0x68},
 539         {WCD938X_DIGITAL_CDC_TX2_CTL,                          0x68},
 540         {WCD938X_DIGITAL_CDC_TX_RST,                           0x00},
 541         {WCD938X_DIGITAL_CDC_REQ_CTL,                          0x01},
 542         {WCD938X_DIGITAL_CDC_RST,                              0x00},
 543         {WCD938X_DIGITAL_CDC_AMIC_CTL,                         0x0F},
 544         {WCD938X_DIGITAL_CDC_DMIC_CTL,                         0x04},
 545         {WCD938X_DIGITAL_CDC_DMIC1_CTL,                        0x01},
 546         {WCD938X_DIGITAL_CDC_DMIC2_CTL,                        0x01},
 547         {WCD938X_DIGITAL_CDC_DMIC3_CTL,                        0x01},
 548         {WCD938X_DIGITAL_CDC_DMIC4_CTL,                        0x01},
 549         {WCD938X_DIGITAL_EFUSE_PRG_CTL,                        0x00},
 550         {WCD938X_DIGITAL_EFUSE_CTL,                            0x2B},
 551         {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2,                    0x11},
 552         {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4,                    0x11},
 553         {WCD938X_DIGITAL_PDM_WD_CTL0,                          0x00},
 554         {WCD938X_DIGITAL_PDM_WD_CTL1,                          0x00},
 555         {WCD938X_DIGITAL_PDM_WD_CTL2,                          0x00},
 556         {WCD938X_DIGITAL_INTR_MODE,                            0x00},
 557         {WCD938X_DIGITAL_INTR_MASK_0,                          0xFF},
 558         {WCD938X_DIGITAL_INTR_MASK_1,                          0xFF},
 559         {WCD938X_DIGITAL_INTR_MASK_2,                          0x3F},
 560         {WCD938X_DIGITAL_INTR_STATUS_0,                        0x00},
 561         {WCD938X_DIGITAL_INTR_STATUS_1,                        0x00},
 562         {WCD938X_DIGITAL_INTR_STATUS_2,                        0x00},
 563         {WCD938X_DIGITAL_INTR_CLEAR_0,                         0x00},
 564         {WCD938X_DIGITAL_INTR_CLEAR_1,                         0x00},
 565         {WCD938X_DIGITAL_INTR_CLEAR_2,                         0x00},
 566         {WCD938X_DIGITAL_INTR_LEVEL_0,                         0x00},
 567         {WCD938X_DIGITAL_INTR_LEVEL_1,                         0x00},
 568         {WCD938X_DIGITAL_INTR_LEVEL_2,                         0x00},
 569         {WCD938X_DIGITAL_INTR_SET_0,                           0x00},
 570         {WCD938X_DIGITAL_INTR_SET_1,                           0x00},
 571         {WCD938X_DIGITAL_INTR_SET_2,                           0x00},
 572         {WCD938X_DIGITAL_INTR_TEST_0,                          0x00},
 573         {WCD938X_DIGITAL_INTR_TEST_1,                          0x00},
 574         {WCD938X_DIGITAL_INTR_TEST_2,                          0x00},
 575         {WCD938X_DIGITAL_TX_MODE_DBG_EN,                       0x00},
 576         {WCD938X_DIGITAL_TX_MODE_DBG_0_1,                      0x00},
 577         {WCD938X_DIGITAL_TX_MODE_DBG_2_3,                      0x00},
 578         {WCD938X_DIGITAL_LB_IN_SEL_CTL,                        0x00},
 579         {WCD938X_DIGITAL_LOOP_BACK_MODE,                       0x00},
 580         {WCD938X_DIGITAL_SWR_DAC_TEST,                         0x00},
 581         {WCD938X_DIGITAL_SWR_HM_TEST_RX_0,                     0x40},
 582         {WCD938X_DIGITAL_SWR_HM_TEST_TX_0,                     0x40},
 583         {WCD938X_DIGITAL_SWR_HM_TEST_RX_1,                     0x00},
 584         {WCD938X_DIGITAL_SWR_HM_TEST_TX_1,                     0x00},
 585         {WCD938X_DIGITAL_SWR_HM_TEST_TX_2,                     0x00},
 586         {WCD938X_DIGITAL_SWR_HM_TEST_0,                        0x00},
 587         {WCD938X_DIGITAL_SWR_HM_TEST_1,                        0x00},
 588         {WCD938X_DIGITAL_PAD_CTL_SWR_0,                        0x8F},
 589         {WCD938X_DIGITAL_PAD_CTL_SWR_1,                        0x06},
 590         {WCD938X_DIGITAL_I2C_CTL,                              0x00},
 591         {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE,                0x00},
 592         {WCD938X_DIGITAL_EFUSE_TEST_CTL_0,                     0x00},
 593         {WCD938X_DIGITAL_EFUSE_TEST_CTL_1,                     0x00},
 594         {WCD938X_DIGITAL_EFUSE_T_DATA_0,                       0x00},
 595         {WCD938X_DIGITAL_EFUSE_T_DATA_1,                       0x00},
 596         {WCD938X_DIGITAL_PAD_CTL_PDM_RX0,                      0xF1},
 597         {WCD938X_DIGITAL_PAD_CTL_PDM_RX1,                      0xF1},
 598         {WCD938X_DIGITAL_PAD_CTL_PDM_TX0,                      0xF1},
 599         {WCD938X_DIGITAL_PAD_CTL_PDM_TX1,                      0xF1},
 600         {WCD938X_DIGITAL_PAD_CTL_PDM_TX2,                      0xF1},
 601         {WCD938X_DIGITAL_PAD_INP_DIS_0,                        0x00},
 602         {WCD938X_DIGITAL_PAD_INP_DIS_1,                        0x00},
 603         {WCD938X_DIGITAL_DRIVE_STRENGTH_0,                     0x00},
 604         {WCD938X_DIGITAL_DRIVE_STRENGTH_1,                     0x00},
 605         {WCD938X_DIGITAL_DRIVE_STRENGTH_2,                     0x00},
 606         {WCD938X_DIGITAL_RX_DATA_EDGE_CTL,                     0x1F},
 607         {WCD938X_DIGITAL_TX_DATA_EDGE_CTL,                     0x80},
 608         {WCD938X_DIGITAL_GPIO_MODE,                            0x00},
 609         {WCD938X_DIGITAL_PIN_CTL_OE,                           0x00},
 610         {WCD938X_DIGITAL_PIN_CTL_DATA_0,                       0x00},
 611         {WCD938X_DIGITAL_PIN_CTL_DATA_1,                       0x00},
 612         {WCD938X_DIGITAL_PIN_STATUS_0,                         0x00},
 613         {WCD938X_DIGITAL_PIN_STATUS_1,                         0x00},
 614         {WCD938X_DIGITAL_DIG_DEBUG_CTL,                        0x00},
 615         {WCD938X_DIGITAL_DIG_DEBUG_EN,                         0x00},
 616         {WCD938X_DIGITAL_ANA_CSR_DBG_ADD,                      0x00},
 617         {WCD938X_DIGITAL_ANA_CSR_DBG_CTL,                      0x48},
 618         {WCD938X_DIGITAL_SSP_DBG,                              0x00},
 619         {WCD938X_DIGITAL_MODE_STATUS_0,                        0x00},
 620         {WCD938X_DIGITAL_MODE_STATUS_1,                        0x00},
 621         {WCD938X_DIGITAL_SPARE_0,                              0x00},
 622         {WCD938X_DIGITAL_SPARE_1,                              0x00},
 623         {WCD938X_DIGITAL_SPARE_2,                              0x00},
 624         {WCD938X_DIGITAL_EFUSE_REG_0,                          0x00},
 625         {WCD938X_DIGITAL_EFUSE_REG_1,                          0xFF},
 626         {WCD938X_DIGITAL_EFUSE_REG_2,                          0xFF},
 627         {WCD938X_DIGITAL_EFUSE_REG_3,                          0xFF},
 628         {WCD938X_DIGITAL_EFUSE_REG_4,                          0xFF},
 629         {WCD938X_DIGITAL_EFUSE_REG_5,                          0xFF},
 630         {WCD938X_DIGITAL_EFUSE_REG_6,                          0xFF},
 631         {WCD938X_DIGITAL_EFUSE_REG_7,                          0xFF},
 632         {WCD938X_DIGITAL_EFUSE_REG_8,                          0xFF},
 633         {WCD938X_DIGITAL_EFUSE_REG_9,                          0xFF},
 634         {WCD938X_DIGITAL_EFUSE_REG_10,                         0xFF},
 635         {WCD938X_DIGITAL_EFUSE_REG_11,                         0xFF},
 636         {WCD938X_DIGITAL_EFUSE_REG_12,                         0xFF},
 637         {WCD938X_DIGITAL_EFUSE_REG_13,                         0xFF},
 638         {WCD938X_DIGITAL_EFUSE_REG_14,                         0xFF},
 639         {WCD938X_DIGITAL_EFUSE_REG_15,                         0xFF},
 640         {WCD938X_DIGITAL_EFUSE_REG_16,                         0xFF},
 641         {WCD938X_DIGITAL_EFUSE_REG_17,                         0xFF},
 642         {WCD938X_DIGITAL_EFUSE_REG_18,                         0xFF},
 643         {WCD938X_DIGITAL_EFUSE_REG_19,                         0xFF},
 644         {WCD938X_DIGITAL_EFUSE_REG_20,                         0x0E},
 645         {WCD938X_DIGITAL_EFUSE_REG_21,                         0x00},
 646         {WCD938X_DIGITAL_EFUSE_REG_22,                         0x00},
 647         {WCD938X_DIGITAL_EFUSE_REG_23,                         0xF8},
 648         {WCD938X_DIGITAL_EFUSE_REG_24,                         0x16},
 649         {WCD938X_DIGITAL_EFUSE_REG_25,                         0x00},
 650         {WCD938X_DIGITAL_EFUSE_REG_26,                         0x00},
 651         {WCD938X_DIGITAL_EFUSE_REG_27,                         0x00},
 652         {WCD938X_DIGITAL_EFUSE_REG_28,                         0x00},
 653         {WCD938X_DIGITAL_EFUSE_REG_29,                         0x00},
 654         {WCD938X_DIGITAL_EFUSE_REG_30,                         0x00},
 655         {WCD938X_DIGITAL_EFUSE_REG_31,                         0x00},
 656         {WCD938X_DIGITAL_TX_REQ_FB_CTL_0,                      0x88},
 657         {WCD938X_DIGITAL_TX_REQ_FB_CTL_1,                      0x88},
 658         {WCD938X_DIGITAL_TX_REQ_FB_CTL_2,                      0x88},
 659         {WCD938X_DIGITAL_TX_REQ_FB_CTL_3,                      0x88},
 660         {WCD938X_DIGITAL_TX_REQ_FB_CTL_4,                      0x88},
 661         {WCD938X_DIGITAL_DEM_BYPASS_DATA0,                     0x55},
 662         {WCD938X_DIGITAL_DEM_BYPASS_DATA1,                     0x55},
 663         {WCD938X_DIGITAL_DEM_BYPASS_DATA2,                     0x55},
 664         {WCD938X_DIGITAL_DEM_BYPASS_DATA3,                     0x01},
 665 };
 666
 667 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
 668 {
 669         switch (reg) {
 670         case WCD938X_ANA_PAGE_REGISTER:
 671         case WCD938X_ANA_BIAS:
 672         case WCD938X_ANA_RX_SUPPLIES:
 673         case WCD938X_ANA_HPH:
 674         case WCD938X_ANA_EAR:
 675         case WCD938X_ANA_EAR_COMPANDER_CTL:
 676         case WCD938X_ANA_TX_CH1:
 677         case WCD938X_ANA_TX_CH2:
 678         case WCD938X_ANA_TX_CH3:
 679         case WCD938X_ANA_TX_CH4:
 680         case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
 681         case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
 682         case WCD938X_ANA_MBHC_MECH:
 683         case WCD938X_ANA_MBHC_ELECT:
 684         case WCD938X_ANA_MBHC_ZDET:
 685         case WCD938X_ANA_MBHC_BTN0:
 686         case WCD938X_ANA_MBHC_BTN1:
 687         case WCD938X_ANA_MBHC_BTN2:
 688         case WCD938X_ANA_MBHC_BTN3:
 689         case WCD938X_ANA_MBHC_BTN4:
 690         case WCD938X_ANA_MBHC_BTN5:
 691         case WCD938X_ANA_MBHC_BTN6:
 692         case WCD938X_ANA_MBHC_BTN7:
 693         case WCD938X_ANA_MICB1:
 694         case WCD938X_ANA_MICB2:
 695         case WCD938X_ANA_MICB2_RAMP:
 696         case WCD938X_ANA_MICB3:
 697         case WCD938X_ANA_MICB4:
 698         case WCD938X_BIAS_CTL:
 699         case WCD938X_BIAS_VBG_FINE_ADJ:
 700         case WCD938X_LDOL_VDDCX_ADJUST:
 701         case WCD938X_LDOL_DISABLE_LDOL:
 702         case WCD938X_MBHC_CTL_CLK:
 703         case WCD938X_MBHC_CTL_ANA:
 704         case WCD938X_MBHC_CTL_SPARE_1:
 705         case WCD938X_MBHC_CTL_SPARE_2:
 706         case WCD938X_MBHC_CTL_BCS:
 707         case WCD938X_MBHC_TEST_CTL:
 708         case WCD938X_LDOH_MODE:
 709         case WCD938X_LDOH_BIAS:
 710         case WCD938X_LDOH_STB_LOADS:
 711         case WCD938X_LDOH_SLOWRAMP:
 712         case WCD938X_MICB1_TEST_CTL_1:
 713         case WCD938X_MICB1_TEST_CTL_2:
 714         case WCD938X_MICB1_TEST_CTL_3:
 715         case WCD938X_MICB2_TEST_CTL_1:
 716         case WCD938X_MICB2_TEST_CTL_2:
 717         case WCD938X_MICB2_TEST_CTL_3:
 718         case WCD938X_MICB3_TEST_CTL_1:
 719         case WCD938X_MICB3_TEST_CTL_2:
 720         case WCD938X_MICB3_TEST_CTL_3:
 721         case WCD938X_MICB4_TEST_CTL_1:
 722         case WCD938X_MICB4_TEST_CTL_2:
 723         case WCD938X_MICB4_TEST_CTL_3:
 724         case WCD938X_TX_COM_ADC_VCM:
 725         case WCD938X_TX_COM_BIAS_ATEST:
 726         case WCD938X_TX_COM_SPARE1:
 727         case WCD938X_TX_COM_SPARE2:
 728         case WCD938X_TX_COM_TXFE_DIV_CTL:
 729         case WCD938X_TX_COM_TXFE_DIV_START:
 730         case WCD938X_TX_COM_SPARE3:
 731         case WCD938X_TX_COM_SPARE4:
 732         case WCD938X_TX_1_2_TEST_EN:
 733         case WCD938X_TX_1_2_ADC_IB:
 734         case WCD938X_TX_1_2_ATEST_REFCTL:
 735         case WCD938X_TX_1_2_TEST_CTL:
 736         case WCD938X_TX_1_2_TEST_BLK_EN1:
 737         case WCD938X_TX_1_2_TXFE1_CLKDIV:
 738         case WCD938X_TX_3_4_TEST_EN:
 739         case WCD938X_TX_3_4_ADC_IB:
 740         case WCD938X_TX_3_4_ATEST_REFCTL:
 741         case WCD938X_TX_3_4_TEST_CTL:
 742         case WCD938X_TX_3_4_TEST_BLK_EN3:
 743         case WCD938X_TX_3_4_TXFE3_CLKDIV:
 744         case WCD938X_TX_3_4_TEST_BLK_EN2:
 745         case WCD938X_TX_3_4_TXFE2_CLKDIV:
 746         case WCD938X_TX_3_4_SPARE1:
 747         case WCD938X_TX_3_4_TEST_BLK_EN4:
 748         case WCD938X_TX_3_4_TXFE4_CLKDIV:
 749         case WCD938X_TX_3_4_SPARE2:
 750         case WCD938X_CLASSH_MODE_1:
 751         case WCD938X_CLASSH_MODE_2:
 752         case WCD938X_CLASSH_MODE_3:
 753         case WCD938X_CLASSH_CTRL_VCL_1:
 754         case WCD938X_CLASSH_CTRL_VCL_2:
 755         case WCD938X_CLASSH_CTRL_CCL_1:
 756         case WCD938X_CLASSH_CTRL_CCL_2:
 757         case WCD938X_CLASSH_CTRL_CCL_3:
 758         case WCD938X_CLASSH_CTRL_CCL_4:
 759         case WCD938X_CLASSH_CTRL_CCL_5:
 760         case WCD938X_CLASSH_BUCK_TMUX_A_D:
 761         case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
 762         case WCD938X_CLASSH_SPARE:
 763         case WCD938X_FLYBACK_EN:
 764         case WCD938X_FLYBACK_VNEG_CTRL_1:
 765         case WCD938X_FLYBACK_VNEG_CTRL_2:
 766         case WCD938X_FLYBACK_VNEG_CTRL_3:
 767         case WCD938X_FLYBACK_VNEG_CTRL_4:
 768         case WCD938X_FLYBACK_VNEG_CTRL_5:
 769         case WCD938X_FLYBACK_VNEG_CTRL_6:
 770         case WCD938X_FLYBACK_VNEG_CTRL_7:
 771         case WCD938X_FLYBACK_VNEG_CTRL_8:
 772         case WCD938X_FLYBACK_VNEG_CTRL_9:
 773         case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
 774         case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
 775         case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
 776         case WCD938X_FLYBACK_CTRL_1:
 777         case WCD938X_FLYBACK_TEST_CTL:
 778         case WCD938X_RX_AUX_SW_CTL:
 779         case WCD938X_RX_PA_AUX_IN_CONN:
 780         case WCD938X_RX_TIMER_DIV:
 781         case WCD938X_RX_OCP_CTL:
 782         case WCD938X_RX_OCP_COUNT:
 783         case WCD938X_RX_BIAS_EAR_DAC:
 784         case WCD938X_RX_BIAS_EAR_AMP:
 785         case WCD938X_RX_BIAS_HPH_LDO:
 786         case WCD938X_RX_BIAS_HPH_PA:
 787         case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
 788         case WCD938X_RX_BIAS_HPH_RDAC_LDO:
 789         case WCD938X_RX_BIAS_HPH_CNP1:
 790         case WCD938X_RX_BIAS_HPH_LOWPOWER:
 791         case WCD938X_RX_BIAS_AUX_DAC:
 792         case WCD938X_RX_BIAS_AUX_AMP:
 793         case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
 794         case WCD938X_RX_BIAS_MISC:
 795         case WCD938X_RX_BIAS_BUCK_RST:
 796         case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
 797         case WCD938X_RX_BIAS_FLYB_ERRAMP:
 798         case WCD938X_RX_BIAS_FLYB_BUFF:
 799         case WCD938X_RX_BIAS_FLYB_MID_RST:
 800         case WCD938X_HPH_CNP_EN:
 801         case WCD938X_HPH_CNP_WG_CTL:
 802         case WCD938X_HPH_CNP_WG_TIME:
 803         case WCD938X_HPH_OCP_CTL:
 804         case WCD938X_HPH_AUTO_CHOP:
 805         case WCD938X_HPH_CHOP_CTL:
 806         case WCD938X_HPH_PA_CTL1:
 807         case WCD938X_HPH_PA_CTL2:
 808         case WCD938X_HPH_L_EN:
 809         case WCD938X_HPH_L_TEST:
 810         case WCD938X_HPH_L_ATEST:
 811         case WCD938X_HPH_R_EN:
 812         case WCD938X_HPH_R_TEST:
 813         case WCD938X_HPH_R_ATEST:
 814         case WCD938X_HPH_RDAC_CLK_CTL1:
 815         case WCD938X_HPH_RDAC_CLK_CTL2:
 816         case WCD938X_HPH_RDAC_LDO_CTL:
 817         case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
 818         case WCD938X_HPH_REFBUFF_UHQA_CTL:
 819         case WCD938X_HPH_REFBUFF_LP_CTL:
 820         case WCD938X_HPH_L_DAC_CTL:
 821         case WCD938X_HPH_R_DAC_CTL:
 822         case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
 823         case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
 824         case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
 825         case WCD938X_EAR_EAR_EN_REG:
 826         case WCD938X_EAR_EAR_PA_CON:
 827         case WCD938X_EAR_EAR_SP_CON:
 828         case WCD938X_EAR_EAR_DAC_CON:
 829         case WCD938X_EAR_EAR_CNP_FSM_CON:
 830         case WCD938X_EAR_TEST_CTL:
 831         case WCD938X_ANA_NEW_PAGE_REGISTER:
 832         case WCD938X_HPH_NEW_ANA_HPH2:
 833         case WCD938X_HPH_NEW_ANA_HPH3:
 834         case WCD938X_SLEEP_CTL:
 835         case WCD938X_SLEEP_WATCHDOG_CTL:
 836         case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
 837         case WCD938X_MBHC_NEW_CTL_1:
 838         case WCD938X_MBHC_NEW_CTL_2:
 839         case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
 840         case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
 841         case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
 842         case WCD938X_TX_NEW_AMIC_MUX_CFG:
 843         case WCD938X_AUX_AUXPA:
 844         case WCD938X_LDORXTX_MODE:
 845         case WCD938X_LDORXTX_CONFIG:
 846         case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
 847         case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
 848         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
 849         case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
 850         case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
 851         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
 852         case WCD938X_HPH_NEW_INT_PA_MISC1:
 853         case WCD938X_HPH_NEW_INT_PA_MISC2:
 854         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
 855         case WCD938X_HPH_NEW_INT_HPH_TIMER1:
 856         case WCD938X_HPH_NEW_INT_HPH_TIMER2:
 857         case WCD938X_HPH_NEW_INT_HPH_TIMER3:
 858         case WCD938X_HPH_NEW_INT_HPH_TIMER4:
 859         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
 860         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
 861         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
 862         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
 863         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
 864         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
 865         case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
 866         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
 867         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
 868         case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
 869         case WCD938X_MBHC_NEW_INT_SPARE_2:
 870         case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
 871         case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
 872         case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
 873         case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
 874         case WCD938X_AUX_INT_EN_REG:
 875         case WCD938X_AUX_INT_PA_CTRL:
 876         case WCD938X_AUX_INT_SP_CTRL:
 877         case WCD938X_AUX_INT_DAC_CTRL:
 878         case WCD938X_AUX_INT_CLK_CTRL:
 879         case WCD938X_AUX_INT_TEST_CTRL:
 880         case WCD938X_AUX_INT_MISC:
 881         case WCD938X_LDORXTX_INT_BIAS:
 882         case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
 883         case WCD938X_LDORXTX_INT_TEST0:
 884         case WCD938X_LDORXTX_INT_STARTUP_TIMER:
 885         case WCD938X_LDORXTX_INT_TEST1:
 886         case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
 887         case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
 888         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
 889         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
 890         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
 891         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
 892         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
 893         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
 894         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
 895         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
 896         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
 897         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
 898         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
 899         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
 900         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
 901         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
 902         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
 903         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
 904         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
 905         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
 906         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
 907         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
 908         case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
 909         case WCD938X_DIGITAL_PAGE_REGISTER:
 910         case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
 911         case WCD938X_DIGITAL_CDC_RST_CTL:
 912         case WCD938X_DIGITAL_TOP_CLK_CFG:
 913         case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
 914         case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
 915         case WCD938X_DIGITAL_SWR_RST_EN:
 916         case WCD938X_DIGITAL_CDC_PATH_MODE:
 917         case WCD938X_DIGITAL_CDC_RX_RST:
 918         case WCD938X_DIGITAL_CDC_RX0_CTL:
 919         case WCD938X_DIGITAL_CDC_RX1_CTL:
 920         case WCD938X_DIGITAL_CDC_RX2_CTL:
 921         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
 922         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
 923         case WCD938X_DIGITAL_CDC_COMP_CTL_0:
 924         case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
 925         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
 926         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
 927         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
 928         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
 929         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
 930         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
 931         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
 932         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
 933         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
 934         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
 935         case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
 936         case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
 937         case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
 938         case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
 939         case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
 940         case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
 941         case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
 942         case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
 943         case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
 944         case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
 945         case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
 946         case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
 947         case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
 948         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
 949         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
 950         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
 951         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
 952         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
 953         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
 954         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
 955         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
 956         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
 957         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
 958         case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
 959         case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
 960         case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
 961         case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
 962         case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
 963         case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
 964         case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
 965         case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
 966         case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
 967         case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
 968         case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
 969         case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
 970         case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
 971         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
 972         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
 973         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
 974         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
 975         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
 976         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
 977         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
 978         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
 979         case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
 980         case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
 981         case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
 982         case WCD938X_DIGITAL_CDC_SWR_CLH:
 983         case WCD938X_DIGITAL_SWR_CLH_BYP:
 984         case WCD938X_DIGITAL_CDC_TX0_CTL:
 985         case WCD938X_DIGITAL_CDC_TX1_CTL:
 986         case WCD938X_DIGITAL_CDC_TX2_CTL:
 987         case WCD938X_DIGITAL_CDC_TX_RST:
 988         case WCD938X_DIGITAL_CDC_REQ_CTL:
 989         case WCD938X_DIGITAL_CDC_RST:
 990         case WCD938X_DIGITAL_CDC_AMIC_CTL:
 991         case WCD938X_DIGITAL_CDC_DMIC_CTL:
 992         case WCD938X_DIGITAL_CDC_DMIC1_CTL:
 993         case WCD938X_DIGITAL_CDC_DMIC2_CTL:
 994         case WCD938X_DIGITAL_CDC_DMIC3_CTL:
 995         case WCD938X_DIGITAL_CDC_DMIC4_CTL:
 996         case WCD938X_DIGITAL_EFUSE_PRG_CTL:
 997         case WCD938X_DIGITAL_EFUSE_CTL:
 998         case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
 999         case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1000         case WCD938X_DIGITAL_PDM_WD_CTL0:
1001         case WCD938X_DIGITAL_PDM_WD_CTL1:
1002         case WCD938X_DIGITAL_PDM_WD_CTL2:
1003         case WCD938X_DIGITAL_INTR_MODE:
1004         case WCD938X_DIGITAL_INTR_MASK_0:
1005         case WCD938X_DIGITAL_INTR_MASK_1:
1006         case WCD938X_DIGITAL_INTR_MASK_2:
1007         case WCD938X_DIGITAL_INTR_CLEAR_0:
1008         case WCD938X_DIGITAL_INTR_CLEAR_1:
1009         case WCD938X_DIGITAL_INTR_CLEAR_2:
1010         case WCD938X_DIGITAL_INTR_LEVEL_0:
1011         case WCD938X_DIGITAL_INTR_LEVEL_1:
1012         case WCD938X_DIGITAL_INTR_LEVEL_2:
1013         case WCD938X_DIGITAL_INTR_SET_0:
1014         case WCD938X_DIGITAL_INTR_SET_1:
1015         case WCD938X_DIGITAL_INTR_SET_2:
1016         case WCD938X_DIGITAL_INTR_TEST_0:
1017         case WCD938X_DIGITAL_INTR_TEST_1:
1018         case WCD938X_DIGITAL_INTR_TEST_2:
1019         case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1020         case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1021         case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1022         case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1023         case WCD938X_DIGITAL_LOOP_BACK_MODE:
1024         case WCD938X_DIGITAL_SWR_DAC_TEST:
1025         case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1026         case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1027         case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1028         case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1029         case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1030         case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1031         case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1032         case WCD938X_DIGITAL_I2C_CTL:
1033         case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1034         case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1035         case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1036         case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1037         case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1038         case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1039         case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1040         case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1041         case WCD938X_DIGITAL_PAD_INP_DIS_0:
1042         case WCD938X_DIGITAL_PAD_INP_DIS_1:
1043         case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1044         case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1045         case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1046         case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1047         case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1048         case WCD938X_DIGITAL_GPIO_MODE:
1049         case WCD938X_DIGITAL_PIN_CTL_OE:
1050         case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1051         case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1052         case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1053         case WCD938X_DIGITAL_DIG_DEBUG_EN:
1054         case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1055         case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1056         case WCD938X_DIGITAL_SSP_DBG:
1057         case WCD938X_DIGITAL_SPARE_0:
1058         case WCD938X_DIGITAL_SPARE_1:
1059         case WCD938X_DIGITAL_SPARE_2:
1060         case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1061         case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1062         case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1063         case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1064         case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1065         case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1066         case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1067         case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1068         case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1069                 return true;
1070         }
1071
1072         return false;
1073 }
1074
1075 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1076 {
1077         switch (reg) {
1078         case WCD938X_ANA_MBHC_RESULT_1:
1079         case WCD938X_ANA_MBHC_RESULT_2:
1080         case WCD938X_ANA_MBHC_RESULT_3:
1081         case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1082         case WCD938X_TX_1_2_SAR2_ERR:
1083         case WCD938X_TX_1_2_SAR1_ERR:
1084         case WCD938X_TX_3_4_SAR4_ERR:
1085         case WCD938X_TX_3_4_SAR3_ERR:
1086         case WCD938X_HPH_L_STATUS:
1087         case WCD938X_HPH_R_STATUS:
1088         case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1089         case WCD938X_EAR_STATUS_REG_1:
1090         case WCD938X_EAR_STATUS_REG_2:
1091         case WCD938X_MBHC_NEW_FSM_STATUS:
1092         case WCD938X_MBHC_NEW_ADC_RESULT:
1093         case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1094         case WCD938X_AUX_INT_STATUS_REG:
1095         case WCD938X_LDORXTX_INT_STATUS:
1096         case WCD938X_DIGITAL_CHIP_ID0:
1097         case WCD938X_DIGITAL_CHIP_ID1:
1098         case WCD938X_DIGITAL_CHIP_ID2:
1099         case WCD938X_DIGITAL_CHIP_ID3:
1100         case WCD938X_DIGITAL_INTR_STATUS_0:
1101         case WCD938X_DIGITAL_INTR_STATUS_1:
1102         case WCD938X_DIGITAL_INTR_STATUS_2:
1103         case WCD938X_DIGITAL_SWR_HM_TEST_0:
1104         case WCD938X_DIGITAL_SWR_HM_TEST_1:
1105         case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1106         case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1107         case WCD938X_DIGITAL_PIN_STATUS_0:
1108         case WCD938X_DIGITAL_PIN_STATUS_1:
1109         case WCD938X_DIGITAL_MODE_STATUS_0:
1110         case WCD938X_DIGITAL_MODE_STATUS_1:
1111         case WCD938X_DIGITAL_EFUSE_REG_0:
1112         case WCD938X_DIGITAL_EFUSE_REG_1:
1113         case WCD938X_DIGITAL_EFUSE_REG_2:
1114         case WCD938X_DIGITAL_EFUSE_REG_3:
1115         case WCD938X_DIGITAL_EFUSE_REG_4:
1116         case WCD938X_DIGITAL_EFUSE_REG_5:
1117         case WCD938X_DIGITAL_EFUSE_REG_6:
1118         case WCD938X_DIGITAL_EFUSE_REG_7:
1119         case WCD938X_DIGITAL_EFUSE_REG_8:
1120         case WCD938X_DIGITAL_EFUSE_REG_9:
1121         case WCD938X_DIGITAL_EFUSE_REG_10:
1122         case WCD938X_DIGITAL_EFUSE_REG_11:
1123         case WCD938X_DIGITAL_EFUSE_REG_12:
1124         case WCD938X_DIGITAL_EFUSE_REG_13:
1125         case WCD938X_DIGITAL_EFUSE_REG_14:
1126         case WCD938X_DIGITAL_EFUSE_REG_15:
1127         case WCD938X_DIGITAL_EFUSE_REG_16:
1128         case WCD938X_DIGITAL_EFUSE_REG_17:
1129         case WCD938X_DIGITAL_EFUSE_REG_18:
1130         case WCD938X_DIGITAL_EFUSE_REG_19:
1131         case WCD938X_DIGITAL_EFUSE_REG_20:
1132         case WCD938X_DIGITAL_EFUSE_REG_21:
1133         case WCD938X_DIGITAL_EFUSE_REG_22:
1134         case WCD938X_DIGITAL_EFUSE_REG_23:
1135         case WCD938X_DIGITAL_EFUSE_REG_24:
1136         case WCD938X_DIGITAL_EFUSE_REG_25:
1137         case WCD938X_DIGITAL_EFUSE_REG_26:
1138         case WCD938X_DIGITAL_EFUSE_REG_27:
1139         case WCD938X_DIGITAL_EFUSE_REG_28:
1140         case WCD938X_DIGITAL_EFUSE_REG_29:
1141         case WCD938X_DIGITAL_EFUSE_REG_30:
1142         case WCD938X_DIGITAL_EFUSE_REG_31:
1143                 return true;
1144         }
1145         return false;
1146 }
1147
1148 static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1149 {
1150         bool ret;
1151
1152         ret = wcd938x_readonly_register(dev, reg);
1153         if (!ret)
1154                 return wcd938x_rdwr_register(dev, reg);
1155
1156         return ret;
1157 }
1158
1159 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1160 {
1161         return wcd938x_rdwr_register(dev, reg);
1162 }
1163
1164 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1165 {
1166         if (reg <= WCD938X_BASE_ADDRESS)
1167                 return 0;
1168
1169         if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1170                 return true;
1171
1172         if (wcd938x_readonly_register(dev, reg))
1173                 return true;
1174
1175         return false;
1176 }
1177
1178 struct regmap_config wcd938x_regmap_config = {
1179         .name = "wcd938x_csr",
1180         .reg_bits = 32,
1181         .val_bits = 8,
1182         .cache_type = REGCACHE_RBTREE,
1183         .reg_defaults = wcd938x_defaults,
1184         .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1185         .max_register = WCD938X_MAX_REGISTER,
1186         .readable_reg = wcd938x_readable_register,
1187         .writeable_reg = wcd938x_writeable_register,
1188         .volatile_reg = wcd938x_volatile_register,
1189         .can_multi_write = true,
1190 };
1191 EXPORT_SYMBOL_GPL(wcd938x_regmap_config);
1192
1193 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1194         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1195         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1196         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1197         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1198         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1199         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1200         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1201         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1202         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1203         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1204         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1205         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1206         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1207         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1208         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1209         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1210         REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1211         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1212         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1213         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1214 };
1215
1216 static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1217         .name = "wcd938x",
1218         .irqs = wcd938x_irqs,
1219         .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1220         .num_regs = 3,
1221         .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1222         .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1223         .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1224         .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1225         .use_ack = 1,
1226         .runtime_pm = true,
1227         .irq_drv_data = NULL,
1228 };
1229
1230 static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1231 {
1232         struct regmap *rm = wcd938x->regmap;
1233
1234         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1235         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1236         /* 1 msec delay as per HW requirement */
1237         usleep_range(1000, 1010);
1238         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1239         /* 1 msec delay as per HW requirement */
1240         usleep_range(1000, 1010);
1241         regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1242         regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1243                                                                 0xF0, 0x80);
1244         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1245         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1246         /* 10 msec delay as per HW requirement */
1247         usleep_range(10000, 10010);
1248
1249         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1250         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1251                                       0xF0, 0x00);
1252         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1253                                       0x1F, 0x15);
1254         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1255                                       0x1F, 0x15);
1256         regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1257                                       0xC0, 0x80);
1258         regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1259                                       0x02, 0x02);
1260
1261         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1262                            0xFF, 0x14);
1263         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1264                            0x1F, 0x08);
1265
1266         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1267         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1268         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1269         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1270         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1271
1272         /* Set Noise Filter Resistor value */
1273         regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1274         regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1275         regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1276         regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1277
1278         regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1279         regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1280
1281         return 0;
1282
1283 }
1284
1285 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
1286 {
1287         /* min micbias voltage is 1V and maximum is 2.85V */
1288         if (micb_mv < 1000 || micb_mv > 2850)
1289                 return -EINVAL;
1290
1291         return (micb_mv - 1000) / 50;
1292 }
1293
1294 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
1295 {
1296         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
1297
1298         /* set micbias voltage */
1299         vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
1300         vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
1301         vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
1302         vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
1303         if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
1304                 return -EINVAL;
1305
1306         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
1307                            WCD938X_MICB_VOUT_MASK, vout_ctl_1);
1308         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
1309                            WCD938X_MICB_VOUT_MASK, vout_ctl_2);
1310         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
1311                            WCD938X_MICB_VOUT_MASK, vout_ctl_3);
1312         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
1313                            WCD938X_MICB_VOUT_MASK, vout_ctl_4);
1314
1315         return 0;
1316 }
1317
1318 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
1319 {
1320         return IRQ_HANDLED;
1321 }
1322
1323 static struct irq_chip wcd_irq_chip = {
1324         .name = "WCD938x",
1325 };
1326
1327 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
1328                         irq_hw_number_t hw)
1329 {
1330         irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
1331         irq_set_nested_thread(virq, 1);
1332         irq_set_noprobe(virq);
1333
1334         return 0;
1335 }
1336
1337 static const struct irq_domain_ops wcd_domain_ops = {
1338         .map = wcd_irq_chip_map,
1339 };
1340
1341 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
1342 {
1343
1344         wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
1345         if (!(wcd->virq)) {
1346                 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
1347                 return -EINVAL;
1348         }
1349
1350         return devm_regmap_add_irq_chip(dev, wcd->regmap,
1351                                         irq_create_mapping(wcd->virq, 0),
1352                                         IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
1353                                         &wcd->irq_chip);
1354 }
1355
1356 static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
1357 {
1358         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1359         struct device *dev = component->dev;
1360         int ret, i;
1361
1362         snd_soc_component_init_regmap(component, wcd938x->regmap);
1363
1364         wcd938x->variant = snd_soc_component_read_field(component,
1365                                                  WCD938X_DIGITAL_EFUSE_REG_0,
1366                                                  WCD938X_ID_MASK);
1367
1368         wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
1369
1370         wcd938x_io_init(wcd938x);
1371         /* Set all interrupts as edge triggered */
1372         for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
1373                 regmap_write(wcd938x->regmap,
1374                              (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
1375         }
1376
1377         ret = wcd938x_irq_init(wcd938x, component->dev);
1378         if (ret) {
1379                 dev_err(component->dev, "%s: IRQ init failed: %d\n",
1380                         __func__, ret);
1381                 return ret;
1382         }
1383
1384         wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
1385                                                        WCD938X_IRQ_HPHR_PDM_WD_INT);
1386         wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
1387                                                        WCD938X_IRQ_HPHL_PDM_WD_INT);
1388         wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
1389                                                        WCD938X_IRQ_AUX_PDM_WD_INT);
1390
1391         /* Request for watchdog interrupt */
1392         ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
1393                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
1394                                    "HPHR PDM WD INT", wcd938x);
1395         if (ret)
1396                 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
1397
1398         ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
1399                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
1400                                    "HPHL PDM WD INT", wcd938x);
1401         if (ret)
1402                 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
1403
1404         ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
1405                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
1406                                    "AUX PDM WD INT", wcd938x);
1407         if (ret)
1408                 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
1409
1410         /* Disable watchdog interrupt for HPH and AUX */
1411         disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1412         disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1413         disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1414
1415         return ret;
1416 }
1417
1418 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
1419         .name = "wcd938x_codec",
1420         .probe = wcd938x_soc_codec_probe,
1421 };
1422
1423 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
1424 {
1425         struct device_node *np = dev->of_node;
1426         u32 prop_val = 0;
1427         int rc = 0;
1428
1429         rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
1430         if (!rc)
1431                 wcd->micb1_mv = prop_val/1000;
1432         else
1433                 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
1434
1435         rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
1436         if (!rc)
1437                 wcd->micb2_mv = prop_val/1000;
1438         else
1439                 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
1440
1441         rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
1442         if (!rc)
1443                 wcd->micb3_mv = prop_val/1000;
1444         else
1445                 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
1446
1447         rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
1448         if (!rc)
1449                 wcd->micb4_mv = prop_val/1000;
1450         else
1451                 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
1452 }
1453
1454 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
1455 {
1456         int ret;
1457
1458         wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
1459         if (wcd938x->reset_gpio < 0) {
1460                 dev_err(dev, "Failed to get reset gpio: err = %d\n",
1461                         wcd938x->reset_gpio);
1462                 return wcd938x->reset_gpio;
1463         }
1464
1465         wcd938x->supplies[0].supply = "vdd-rxtx";
1466         wcd938x->supplies[1].supply = "vdd-io";
1467         wcd938x->supplies[2].supply = "vdd-buck";
1468         wcd938x->supplies[3].supply = "vdd-mic-bias";
1469
1470         ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
1471         if (ret) {
1472                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
1473                 return ret;
1474         }
1475
1476         ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
1477         if (ret) {
1478                 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
1479                 return ret;
1480         }
1481
1482         wcd938x_dt_parse_micbias_info(dev, wcd938x);
1483
1484         return 0;
1485 }
1486
1487 static int wcd938x_reset(struct wcd938x_priv *wcd938x)
1488 {
1489         gpio_direction_output(wcd938x->reset_gpio, 0);
1490         /* 20us sleep required after pulling the reset gpio to LOW */
1491         usleep_range(20, 30);
1492         gpio_set_value(wcd938x->reset_gpio, 1);
1493         /* 20us sleep required after pulling the reset gpio to HIGH */
1494         usleep_range(20, 30);
1495
1496         return 0;
1497 }
1498
1499 int wcd938x_handle_sdw_irq(struct wcd938x_sdw_priv *wcd)
1500 {
1501         struct wcd938x_priv *wcd938x = wcd->wcd938x;
1502         struct irq_domain *slave_irq = wcd938x->virq;
1503         u32 sts1, sts2, sts3;
1504
1505         do {
1506                 handle_nested_irq(irq_find_mapping(slave_irq, 0));
1507                 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
1508                 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
1509                 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
1510
1511         } while (sts1 || sts2 || sts3);
1512
1513         return IRQ_HANDLED;
1514 }
1515 EXPORT_SYMBOL_GPL(wcd938x_handle_sdw_irq);
1516
1517 static struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
1518 };
1519
1520 static struct snd_soc_dai_driver wcd938x_dais[] = {
1521         [0] = {
1522                 .name = "wcd938x-sdw-rx",
1523                 .playback = {
1524                         .stream_name = "WCD AIF1 Playback",
1525                         .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
1526                         .formats = WCD938X_FORMATS_S16_S24_LE,
1527                         .rate_max = 192000,
1528                         .rate_min = 8000,
1529                         .channels_min = 1,
1530                         .channels_max = 2,
1531                 },
1532                 .ops = &wcd938x_sdw_dai_ops,
1533         },
1534         [1] = {
1535                 .name = "wcd938x-sdw-tx",
1536                 .capture = {
1537                         .stream_name = "WCD AIF1 Capture",
1538                         .rates = WCD938X_RATES_MASK,
1539                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1540                         .rate_min = 8000,
1541                         .rate_max = 192000,
1542                         .channels_min = 1,
1543                         .channels_max = 4,
1544                 },
1545                 .ops = &wcd938x_sdw_dai_ops,
1546         },
1547 };
1548
1549 static int wcd938x_bind(struct device *dev)
1550 {
1551         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
1552         int ret;
1553
1554         ret = component_bind_all(dev, wcd938x);
1555         if (ret) {
1556                 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
1557                         __func__, ret);
1558                 return ret;
1559         }
1560
1561         ret = wcd938x_set_micbias_data(wcd938x);
1562         if (ret < 0) {
1563                 dev_err(dev, "%s: bad micbias pdata\n", __func__);
1564                 return ret;
1565         }
1566
1567         ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
1568                                          wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
1569         if (ret)
1570                 dev_err(dev, "%s: Codec registration failed\n",
1571                                 __func__);
1572
1573         return ret;
1574
1575 }
1576
1577 static void wcd938x_unbind(struct device *dev)
1578 {
1579         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
1580
1581         snd_soc_unregister_component(dev);
1582         component_unbind_all(dev, wcd938x);
1583 }
1584
1585 static const struct component_master_ops wcd938x_comp_ops = {
1586         .bind   = wcd938x_bind,
1587         .unbind = wcd938x_unbind,
1588 };
1589
1590 static int wcd938x_compare_of(struct device *dev, void *data)
1591 {
1592         return dev->of_node == data;
1593 }
1594
1595 static void wcd938x_release_of(struct device *dev, void *data)
1596 {
1597         of_node_put(data);
1598 }
1599
1600 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
1601                                         struct device *dev,
1602                                         struct component_match **matchptr)
1603 {
1604         struct device_node *np;
1605
1606         np = dev->of_node;
1607
1608         wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
1609         if (!wcd938x->rxnode) {
1610                 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
1611                 return -ENODEV;
1612         }
1613
1614         of_node_get(wcd938x->rxnode);
1615         component_match_add_release(dev, matchptr, wcd938x_release_of,
1616                                     wcd938x_compare_of, wcd938x->rxnode);
1617
1618         wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
1619         if (!wcd938x->txnode) {
1620                 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
1621                 return -ENODEV;
1622         }
1623         of_node_get(wcd938x->txnode);
1624         component_match_add_release(dev, matchptr, wcd938x_release_of,
1625                                     wcd938x_compare_of, wcd938x->txnode);
1626         return 0;
1627 }
1628
1629 static int wcd938x_probe(struct platform_device *pdev)
1630 {
1631         struct component_match *match = NULL;
1632         struct wcd938x_priv *wcd938x = NULL;
1633         struct device *dev = &pdev->dev;
1634         int ret;
1635
1636         wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
1637                                 GFP_KERNEL);
1638         if (!wcd938x)
1639                 return -ENOMEM;
1640
1641         dev_set_drvdata(dev, wcd938x);
1642
1643         ret = wcd938x_populate_dt_data(wcd938x, dev);
1644         if (ret) {
1645                 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
1646                 return -EINVAL;
1647         }
1648
1649         ret = wcd938x_add_slave_components(wcd938x, dev, &match);
1650         if (ret)
1651                 return ret;
1652
1653         wcd938x_reset(wcd938x);
1654
1655         ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
1656         if (ret)
1657                 return ret;
1658
1659         pm_runtime_set_autosuspend_delay(dev, 1000);
1660         pm_runtime_use_autosuspend(dev);
1661         pm_runtime_mark_last_busy(dev);
1662         pm_runtime_set_active(dev);
1663         pm_runtime_enable(dev);
1664         pm_runtime_idle(dev);
1665
1666         return ret;
1667 }
1668
1669 static int wcd938x_remove(struct platform_device *pdev)
1670 {
1671         component_master_del(&pdev->dev, &wcd938x_comp_ops);
1672
1673         return 0;
1674 }
1675
1676 static const struct of_device_id wcd938x_dt_match[] = {
1677         { .compatible = "qcom,wcd9380-codec" },
1678         { .compatible = "qcom,wcd9385-codec" },
1679         {}
1680 };
1681 MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
1682
1683 static struct platform_driver wcd938x_codec_driver = {
1684         .probe = wcd938x_probe,
1685         .remove = wcd938x_remove,
1686         .driver = {
1687                 .name = "wcd938x_codec",
1688                 .of_match_table = of_match_ptr(wcd938x_dt_match),
1689                 .suppress_bind_attrs = true,
1690         },
1691 };
1692
1693 module_platform_driver(wcd938x_codec_driver);
1694 MODULE_DESCRIPTION("WCD938X Codec driver");
1695 MODULE_LICENSE("GPL");