sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2018 Realtek Semiconductor Corp.
   6 // Author: Bard Liao <bardliao@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/mutex.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/rt5682.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5682.h"
  33
  34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  35         "AVDD",
  36         "MICVDD",
  37         "VBAT",
  38 };
  39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
  40
  41 static const struct reg_sequence patch_list[] = {
  42         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  43         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  44         {RT5682_I2C_CTRL, 0x000f},
  45         {RT5682_PLL2_INTERNAL, 0x8266},
  46         {RT5682_SAR_IL_CMD_1, 0x22b7},
  47         {RT5682_SAR_IL_CMD_3, 0x0365},
  48         {RT5682_SAR_IL_CMD_6, 0x0110},
  49         {RT5682_CHARGE_PUMP_1, 0x0210},
  50         {RT5682_HP_LOGIC_CTRL_2, 0x0007},
  51         {RT5682_SAR_IL_CMD_2, 0xac00},
  52         {RT5682_CBJ_CTRL_7, 0x0104},
  53 };
  54
  55 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  56 {
  57         int ret;
  58
  59         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  60                                      ARRAY_SIZE(patch_list));
  61         if (ret)
  62                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  63 }
  64 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  65
  66 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  67         {0x0002, 0x8080},
  68         {0x0003, 0x8000},
  69         {0x0005, 0x0000},
  70         {0x0006, 0x0000},
  71         {0x0008, 0x800f},
  72         {0x000b, 0x0000},
  73         {0x0010, 0x4040},
  74         {0x0011, 0x0000},
  75         {0x0012, 0x1404},
  76         {0x0013, 0x1000},
  77         {0x0014, 0xa00a},
  78         {0x0015, 0x0404},
  79         {0x0016, 0x0404},
  80         {0x0019, 0xafaf},
  81         {0x001c, 0x2f2f},
  82         {0x001f, 0x0000},
  83         {0x0022, 0x5757},
  84         {0x0023, 0x0039},
  85         {0x0024, 0x000b},
  86         {0x0026, 0xc0c4},
  87         {0x0029, 0x8080},
  88         {0x002a, 0xa0a0},
  89         {0x002b, 0x0300},
  90         {0x0030, 0x0000},
  91         {0x003c, 0x0080},
  92         {0x0044, 0x0c0c},
  93         {0x0049, 0x0000},
  94         {0x0061, 0x0000},
  95         {0x0062, 0x0000},
  96         {0x0063, 0x003f},
  97         {0x0064, 0x0000},
  98         {0x0065, 0x0000},
  99         {0x0066, 0x0030},
 100         {0x0067, 0x0000},
 101         {0x006b, 0x0000},
 102         {0x006c, 0x0000},
 103         {0x006d, 0x2200},
 104         {0x006e, 0x0a10},
 105         {0x0070, 0x8000},
 106         {0x0071, 0x8000},
 107         {0x0073, 0x0000},
 108         {0x0074, 0x0000},
 109         {0x0075, 0x0002},
 110         {0x0076, 0x0001},
 111         {0x0079, 0x0000},
 112         {0x007a, 0x0000},
 113         {0x007b, 0x0000},
 114         {0x007c, 0x0100},
 115         {0x007e, 0x0000},
 116         {0x0080, 0x0000},
 117         {0x0081, 0x0000},
 118         {0x0082, 0x0000},
 119         {0x0083, 0x0000},
 120         {0x0084, 0x0000},
 121         {0x0085, 0x0000},
 122         {0x0086, 0x0005},
 123         {0x0087, 0x0000},
 124         {0x0088, 0x0000},
 125         {0x008c, 0x0003},
 126         {0x008d, 0x0000},
 127         {0x008e, 0x0060},
 128         {0x008f, 0x1000},
 129         {0x0091, 0x0c26},
 130         {0x0092, 0x0073},
 131         {0x0093, 0x0000},
 132         {0x0094, 0x0080},
 133         {0x0098, 0x0000},
 134         {0x009a, 0x0000},
 135         {0x009b, 0x0000},
 136         {0x009c, 0x0000},
 137         {0x009d, 0x0000},
 138         {0x009e, 0x100c},
 139         {0x009f, 0x0000},
 140         {0x00a0, 0x0000},
 141         {0x00a3, 0x0002},
 142         {0x00a4, 0x0001},
 143         {0x00ae, 0x2040},
 144         {0x00af, 0x0000},
 145         {0x00b6, 0x0000},
 146         {0x00b7, 0x0000},
 147         {0x00b8, 0x0000},
 148         {0x00b9, 0x0002},
 149         {0x00be, 0x0000},
 150         {0x00c0, 0x0160},
 151         {0x00c1, 0x82a0},
 152         {0x00c2, 0x0000},
 153         {0x00d0, 0x0000},
 154         {0x00d1, 0x2244},
 155         {0x00d2, 0x3300},
 156         {0x00d3, 0x2200},
 157         {0x00d4, 0x0000},
 158         {0x00d9, 0x0009},
 159         {0x00da, 0x0000},
 160         {0x00db, 0x0000},
 161         {0x00dc, 0x00c0},
 162         {0x00dd, 0x2220},
 163         {0x00de, 0x3131},
 164         {0x00df, 0x3131},
 165         {0x00e0, 0x3131},
 166         {0x00e2, 0x0000},
 167         {0x00e3, 0x4000},
 168         {0x00e4, 0x0aa0},
 169         {0x00e5, 0x3131},
 170         {0x00e6, 0x3131},
 171         {0x00e7, 0x3131},
 172         {0x00e8, 0x3131},
 173         {0x00ea, 0xb320},
 174         {0x00eb, 0x0000},
 175         {0x00f0, 0x0000},
 176         {0x00f1, 0x00d0},
 177         {0x00f2, 0x00d0},
 178         {0x00f6, 0x0000},
 179         {0x00fa, 0x0000},
 180         {0x00fb, 0x0000},
 181         {0x00fc, 0x0000},
 182         {0x00fd, 0x0000},
 183         {0x00fe, 0x10ec},
 184         {0x00ff, 0x6530},
 185         {0x0100, 0xa0a0},
 186         {0x010b, 0x0000},
 187         {0x010c, 0xae00},
 188         {0x010d, 0xaaa0},
 189         {0x010e, 0x8aa2},
 190         {0x010f, 0x02a2},
 191         {0x0110, 0xc000},
 192         {0x0111, 0x04a2},
 193         {0x0112, 0x2800},
 194         {0x0113, 0x0000},
 195         {0x0117, 0x0100},
 196         {0x0125, 0x0410},
 197         {0x0132, 0x6026},
 198         {0x0136, 0x5555},
 199         {0x0138, 0x3700},
 200         {0x013a, 0x2000},
 201         {0x013b, 0x2000},
 202         {0x013c, 0x2005},
 203         {0x013f, 0x0000},
 204         {0x0142, 0x0000},
 205         {0x0145, 0x0002},
 206         {0x0146, 0x0000},
 207         {0x0147, 0x0000},
 208         {0x0148, 0x0000},
 209         {0x0149, 0x0000},
 210         {0x0150, 0x79a1},
 211         {0x0156, 0xaaaa},
 212         {0x0160, 0x4ec0},
 213         {0x0161, 0x0080},
 214         {0x0162, 0x0200},
 215         {0x0163, 0x0800},
 216         {0x0164, 0x0000},
 217         {0x0165, 0x0000},
 218         {0x0166, 0x0000},
 219         {0x0167, 0x000f},
 220         {0x0168, 0x000f},
 221         {0x0169, 0x0021},
 222         {0x0190, 0x413d},
 223         {0x0194, 0x0000},
 224         {0x0195, 0x0000},
 225         {0x0197, 0x0022},
 226         {0x0198, 0x0000},
 227         {0x0199, 0x0000},
 228         {0x01af, 0x0000},
 229         {0x01b0, 0x0400},
 230         {0x01b1, 0x0000},
 231         {0x01b2, 0x0000},
 232         {0x01b3, 0x0000},
 233         {0x01b4, 0x0000},
 234         {0x01b5, 0x0000},
 235         {0x01b6, 0x01c3},
 236         {0x01b7, 0x02a0},
 237         {0x01b8, 0x03e9},
 238         {0x01b9, 0x1389},
 239         {0x01ba, 0xc351},
 240         {0x01bb, 0x0009},
 241         {0x01bc, 0x0018},
 242         {0x01bd, 0x002a},
 243         {0x01be, 0x004c},
 244         {0x01bf, 0x0097},
 245         {0x01c0, 0x433d},
 246         {0x01c2, 0x0000},
 247         {0x01c3, 0x0000},
 248         {0x01c4, 0x0000},
 249         {0x01c5, 0x0000},
 250         {0x01c6, 0x0000},
 251         {0x01c7, 0x0000},
 252         {0x01c8, 0x40af},
 253         {0x01c9, 0x0702},
 254         {0x01ca, 0x0000},
 255         {0x01cb, 0x0000},
 256         {0x01cc, 0x5757},
 257         {0x01cd, 0x5757},
 258         {0x01ce, 0x5757},
 259         {0x01cf, 0x5757},
 260         {0x01d0, 0x5757},
 261         {0x01d1, 0x5757},
 262         {0x01d2, 0x5757},
 263         {0x01d3, 0x5757},
 264         {0x01d4, 0x5757},
 265         {0x01d5, 0x5757},
 266         {0x01d6, 0x0000},
 267         {0x01d7, 0x0008},
 268         {0x01d8, 0x0029},
 269         {0x01d9, 0x3333},
 270         {0x01da, 0x0000},
 271         {0x01db, 0x0004},
 272         {0x01dc, 0x0000},
 273         {0x01de, 0x7c00},
 274         {0x01df, 0x0320},
 275         {0x01e0, 0x06a1},
 276         {0x01e1, 0x0000},
 277         {0x01e2, 0x0000},
 278         {0x01e3, 0x0000},
 279         {0x01e4, 0x0000},
 280         {0x01e6, 0x0001},
 281         {0x01e7, 0x0000},
 282         {0x01e8, 0x0000},
 283         {0x01ea, 0x0000},
 284         {0x01eb, 0x0000},
 285         {0x01ec, 0x0000},
 286         {0x01ed, 0x0000},
 287         {0x01ee, 0x0000},
 288         {0x01ef, 0x0000},
 289         {0x01f0, 0x0000},
 290         {0x01f1, 0x0000},
 291         {0x01f2, 0x0000},
 292         {0x01f3, 0x0000},
 293         {0x01f4, 0x0000},
 294         {0x0210, 0x6297},
 295         {0x0211, 0xa005},
 296         {0x0212, 0x824c},
 297         {0x0213, 0xf7ff},
 298         {0x0214, 0xf24c},
 299         {0x0215, 0x0102},
 300         {0x0216, 0x00a3},
 301         {0x0217, 0x0048},
 302         {0x0218, 0xa2c0},
 303         {0x0219, 0x0400},
 304         {0x021a, 0x00c8},
 305         {0x021b, 0x00c0},
 306         {0x021c, 0x0000},
 307         {0x0250, 0x4500},
 308         {0x0251, 0x40b3},
 309         {0x0252, 0x0000},
 310         {0x0253, 0x0000},
 311         {0x0254, 0x0000},
 312         {0x0255, 0x0000},
 313         {0x0256, 0x0000},
 314         {0x0257, 0x0000},
 315         {0x0258, 0x0000},
 316         {0x0259, 0x0000},
 317         {0x025a, 0x0005},
 318         {0x0270, 0x0000},
 319         {0x02ff, 0x0110},
 320         {0x0300, 0x001f},
 321         {0x0301, 0x032c},
 322         {0x0302, 0x5f21},
 323         {0x0303, 0x4000},
 324         {0x0304, 0x4000},
 325         {0x0305, 0x06d5},
 326         {0x0306, 0x8000},
 327         {0x0307, 0x0700},
 328         {0x0310, 0x4560},
 329         {0x0311, 0xa4a8},
 330         {0x0312, 0x7418},
 331         {0x0313, 0x0000},
 332         {0x0314, 0x0006},
 333         {0x0315, 0xffff},
 334         {0x0316, 0xc400},
 335         {0x0317, 0x0000},
 336         {0x03c0, 0x7e00},
 337         {0x03c1, 0x8000},
 338         {0x03c2, 0x8000},
 339         {0x03c3, 0x8000},
 340         {0x03c4, 0x8000},
 341         {0x03c5, 0x8000},
 342         {0x03c6, 0x8000},
 343         {0x03c7, 0x8000},
 344         {0x03c8, 0x8000},
 345         {0x03c9, 0x8000},
 346         {0x03ca, 0x8000},
 347         {0x03cb, 0x8000},
 348         {0x03cc, 0x8000},
 349         {0x03d0, 0x0000},
 350         {0x03d1, 0x0000},
 351         {0x03d2, 0x0000},
 352         {0x03d3, 0x0000},
 353         {0x03d4, 0x2000},
 354         {0x03d5, 0x2000},
 355         {0x03d6, 0x0000},
 356         {0x03d7, 0x0000},
 357         {0x03d8, 0x2000},
 358         {0x03d9, 0x2000},
 359         {0x03da, 0x2000},
 360         {0x03db, 0x2000},
 361         {0x03dc, 0x0000},
 362         {0x03dd, 0x0000},
 363         {0x03de, 0x0000},
 364         {0x03df, 0x2000},
 365         {0x03e0, 0x0000},
 366         {0x03e1, 0x0000},
 367         {0x03e2, 0x0000},
 368         {0x03e3, 0x0000},
 369         {0x03e4, 0x0000},
 370         {0x03e5, 0x0000},
 371         {0x03e6, 0x0000},
 372         {0x03e7, 0x0000},
 373         {0x03e8, 0x0000},
 374         {0x03e9, 0x0000},
 375         {0x03ea, 0x0000},
 376         {0x03eb, 0x0000},
 377         {0x03ec, 0x0000},
 378         {0x03ed, 0x0000},
 379         {0x03ee, 0x0000},
 380         {0x03ef, 0x0000},
 381         {0x03f0, 0x0800},
 382         {0x03f1, 0x0800},
 383         {0x03f2, 0x0800},
 384         {0x03f3, 0x0800},
 385 };
 386 EXPORT_SYMBOL_GPL(rt5682_reg);
 387
 388 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 389 {
 390         switch (reg) {
 391         case RT5682_RESET:
 392         case RT5682_CBJ_CTRL_2:
 393         case RT5682_INT_ST_1:
 394         case RT5682_4BTN_IL_CMD_1:
 395         case RT5682_AJD1_CTRL:
 396         case RT5682_HP_CALIB_CTRL_1:
 397         case RT5682_DEVICE_ID:
 398         case RT5682_I2C_MODE:
 399         case RT5682_HP_CALIB_CTRL_10:
 400         case RT5682_EFUSE_CTRL_2:
 401         case RT5682_JD_TOP_VC_VTRL:
 402         case RT5682_HP_IMP_SENS_CTRL_19:
 403         case RT5682_IL_CMD_1:
 404         case RT5682_SAR_IL_CMD_2:
 405         case RT5682_SAR_IL_CMD_4:
 406         case RT5682_SAR_IL_CMD_10:
 407         case RT5682_SAR_IL_CMD_11:
 408         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 409         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 410                 return true;
 411         default:
 412                 return false;
 413         }
 414 }
 415 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
 416
 417 bool rt5682_readable_register(struct device *dev, unsigned int reg)
 418 {
 419         switch (reg) {
 420         case RT5682_RESET:
 421         case RT5682_VERSION_ID:
 422         case RT5682_VENDOR_ID:
 423         case RT5682_DEVICE_ID:
 424         case RT5682_HP_CTRL_1:
 425         case RT5682_HP_CTRL_2:
 426         case RT5682_HPL_GAIN:
 427         case RT5682_HPR_GAIN:
 428         case RT5682_I2C_CTRL:
 429         case RT5682_CBJ_BST_CTRL:
 430         case RT5682_CBJ_CTRL_1:
 431         case RT5682_CBJ_CTRL_2:
 432         case RT5682_CBJ_CTRL_3:
 433         case RT5682_CBJ_CTRL_4:
 434         case RT5682_CBJ_CTRL_5:
 435         case RT5682_CBJ_CTRL_6:
 436         case RT5682_CBJ_CTRL_7:
 437         case RT5682_DAC1_DIG_VOL:
 438         case RT5682_STO1_ADC_DIG_VOL:
 439         case RT5682_STO1_ADC_BOOST:
 440         case RT5682_HP_IMP_GAIN_1:
 441         case RT5682_HP_IMP_GAIN_2:
 442         case RT5682_SIDETONE_CTRL:
 443         case RT5682_STO1_ADC_MIXER:
 444         case RT5682_AD_DA_MIXER:
 445         case RT5682_STO1_DAC_MIXER:
 446         case RT5682_A_DAC1_MUX:
 447         case RT5682_DIG_INF2_DATA:
 448         case RT5682_REC_MIXER:
 449         case RT5682_CAL_REC:
 450         case RT5682_ALC_BACK_GAIN:
 451         case RT5682_PWR_DIG_1:
 452         case RT5682_PWR_DIG_2:
 453         case RT5682_PWR_ANLG_1:
 454         case RT5682_PWR_ANLG_2:
 455         case RT5682_PWR_ANLG_3:
 456         case RT5682_PWR_MIXER:
 457         case RT5682_PWR_VOL:
 458         case RT5682_CLK_DET:
 459         case RT5682_RESET_LPF_CTRL:
 460         case RT5682_RESET_HPF_CTRL:
 461         case RT5682_DMIC_CTRL_1:
 462         case RT5682_I2S1_SDP:
 463         case RT5682_I2S2_SDP:
 464         case RT5682_ADDA_CLK_1:
 465         case RT5682_ADDA_CLK_2:
 466         case RT5682_I2S1_F_DIV_CTRL_1:
 467         case RT5682_I2S1_F_DIV_CTRL_2:
 468         case RT5682_TDM_CTRL:
 469         case RT5682_TDM_ADDA_CTRL_1:
 470         case RT5682_TDM_ADDA_CTRL_2:
 471         case RT5682_DATA_SEL_CTRL_1:
 472         case RT5682_TDM_TCON_CTRL:
 473         case RT5682_GLB_CLK:
 474         case RT5682_PLL_CTRL_1:
 475         case RT5682_PLL_CTRL_2:
 476         case RT5682_PLL_TRACK_1:
 477         case RT5682_PLL_TRACK_2:
 478         case RT5682_PLL_TRACK_3:
 479         case RT5682_PLL_TRACK_4:
 480         case RT5682_PLL_TRACK_5:
 481         case RT5682_PLL_TRACK_6:
 482         case RT5682_PLL_TRACK_11:
 483         case RT5682_SDW_REF_CLK:
 484         case RT5682_DEPOP_1:
 485         case RT5682_DEPOP_2:
 486         case RT5682_HP_CHARGE_PUMP_1:
 487         case RT5682_HP_CHARGE_PUMP_2:
 488         case RT5682_MICBIAS_1:
 489         case RT5682_MICBIAS_2:
 490         case RT5682_PLL_TRACK_12:
 491         case RT5682_PLL_TRACK_14:
 492         case RT5682_PLL2_CTRL_1:
 493         case RT5682_PLL2_CTRL_2:
 494         case RT5682_PLL2_CTRL_3:
 495         case RT5682_PLL2_CTRL_4:
 496         case RT5682_RC_CLK_CTRL:
 497         case RT5682_I2S_M_CLK_CTRL_1:
 498         case RT5682_I2S2_F_DIV_CTRL_1:
 499         case RT5682_I2S2_F_DIV_CTRL_2:
 500         case RT5682_EQ_CTRL_1:
 501         case RT5682_EQ_CTRL_2:
 502         case RT5682_IRQ_CTRL_1:
 503         case RT5682_IRQ_CTRL_2:
 504         case RT5682_IRQ_CTRL_3:
 505         case RT5682_IRQ_CTRL_4:
 506         case RT5682_INT_ST_1:
 507         case RT5682_GPIO_CTRL_1:
 508         case RT5682_GPIO_CTRL_2:
 509         case RT5682_GPIO_CTRL_3:
 510         case RT5682_HP_AMP_DET_CTRL_1:
 511         case RT5682_HP_AMP_DET_CTRL_2:
 512         case RT5682_MID_HP_AMP_DET:
 513         case RT5682_LOW_HP_AMP_DET:
 514         case RT5682_DELAY_BUF_CTRL:
 515         case RT5682_SV_ZCD_1:
 516         case RT5682_SV_ZCD_2:
 517         case RT5682_IL_CMD_1:
 518         case RT5682_IL_CMD_2:
 519         case RT5682_IL_CMD_3:
 520         case RT5682_IL_CMD_4:
 521         case RT5682_IL_CMD_5:
 522         case RT5682_IL_CMD_6:
 523         case RT5682_4BTN_IL_CMD_1:
 524         case RT5682_4BTN_IL_CMD_2:
 525         case RT5682_4BTN_IL_CMD_3:
 526         case RT5682_4BTN_IL_CMD_4:
 527         case RT5682_4BTN_IL_CMD_5:
 528         case RT5682_4BTN_IL_CMD_6:
 529         case RT5682_4BTN_IL_CMD_7:
 530         case RT5682_ADC_STO1_HP_CTRL_1:
 531         case RT5682_ADC_STO1_HP_CTRL_2:
 532         case RT5682_AJD1_CTRL:
 533         case RT5682_JD1_THD:
 534         case RT5682_JD2_THD:
 535         case RT5682_JD_CTRL_1:
 536         case RT5682_DUMMY_1:
 537         case RT5682_DUMMY_2:
 538         case RT5682_DUMMY_3:
 539         case RT5682_DAC_ADC_DIG_VOL1:
 540         case RT5682_BIAS_CUR_CTRL_2:
 541         case RT5682_BIAS_CUR_CTRL_3:
 542         case RT5682_BIAS_CUR_CTRL_4:
 543         case RT5682_BIAS_CUR_CTRL_5:
 544         case RT5682_BIAS_CUR_CTRL_6:
 545         case RT5682_BIAS_CUR_CTRL_7:
 546         case RT5682_BIAS_CUR_CTRL_8:
 547         case RT5682_BIAS_CUR_CTRL_9:
 548         case RT5682_BIAS_CUR_CTRL_10:
 549         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 550         case RT5682_CHARGE_PUMP_1:
 551         case RT5682_DIG_IN_CTRL_1:
 552         case RT5682_PAD_DRIVING_CTRL:
 553         case RT5682_SOFT_RAMP_DEPOP:
 554         case RT5682_CHOP_DAC:
 555         case RT5682_CHOP_ADC:
 556         case RT5682_CALIB_ADC_CTRL:
 557         case RT5682_VOL_TEST:
 558         case RT5682_SPKVDD_DET_STA:
 559         case RT5682_TEST_MODE_CTRL_1:
 560         case RT5682_TEST_MODE_CTRL_2:
 561         case RT5682_TEST_MODE_CTRL_3:
 562         case RT5682_TEST_MODE_CTRL_4:
 563         case RT5682_TEST_MODE_CTRL_5:
 564         case RT5682_PLL1_INTERNAL:
 565         case RT5682_PLL2_INTERNAL:
 566         case RT5682_STO_NG2_CTRL_1:
 567         case RT5682_STO_NG2_CTRL_2:
 568         case RT5682_STO_NG2_CTRL_3:
 569         case RT5682_STO_NG2_CTRL_4:
 570         case RT5682_STO_NG2_CTRL_5:
 571         case RT5682_STO_NG2_CTRL_6:
 572         case RT5682_STO_NG2_CTRL_7:
 573         case RT5682_STO_NG2_CTRL_8:
 574         case RT5682_STO_NG2_CTRL_9:
 575         case RT5682_STO_NG2_CTRL_10:
 576         case RT5682_STO1_DAC_SIL_DET:
 577         case RT5682_SIL_PSV_CTRL1:
 578         case RT5682_SIL_PSV_CTRL2:
 579         case RT5682_SIL_PSV_CTRL3:
 580         case RT5682_SIL_PSV_CTRL4:
 581         case RT5682_SIL_PSV_CTRL5:
 582         case RT5682_HP_IMP_SENS_CTRL_01:
 583         case RT5682_HP_IMP_SENS_CTRL_02:
 584         case RT5682_HP_IMP_SENS_CTRL_03:
 585         case RT5682_HP_IMP_SENS_CTRL_04:
 586         case RT5682_HP_IMP_SENS_CTRL_05:
 587         case RT5682_HP_IMP_SENS_CTRL_06:
 588         case RT5682_HP_IMP_SENS_CTRL_07:
 589         case RT5682_HP_IMP_SENS_CTRL_08:
 590         case RT5682_HP_IMP_SENS_CTRL_09:
 591         case RT5682_HP_IMP_SENS_CTRL_10:
 592         case RT5682_HP_IMP_SENS_CTRL_11:
 593         case RT5682_HP_IMP_SENS_CTRL_12:
 594         case RT5682_HP_IMP_SENS_CTRL_13:
 595         case RT5682_HP_IMP_SENS_CTRL_14:
 596         case RT5682_HP_IMP_SENS_CTRL_15:
 597         case RT5682_HP_IMP_SENS_CTRL_16:
 598         case RT5682_HP_IMP_SENS_CTRL_17:
 599         case RT5682_HP_IMP_SENS_CTRL_18:
 600         case RT5682_HP_IMP_SENS_CTRL_19:
 601         case RT5682_HP_IMP_SENS_CTRL_20:
 602         case RT5682_HP_IMP_SENS_CTRL_21:
 603         case RT5682_HP_IMP_SENS_CTRL_22:
 604         case RT5682_HP_IMP_SENS_CTRL_23:
 605         case RT5682_HP_IMP_SENS_CTRL_24:
 606         case RT5682_HP_IMP_SENS_CTRL_25:
 607         case RT5682_HP_IMP_SENS_CTRL_26:
 608         case RT5682_HP_IMP_SENS_CTRL_27:
 609         case RT5682_HP_IMP_SENS_CTRL_28:
 610         case RT5682_HP_IMP_SENS_CTRL_29:
 611         case RT5682_HP_IMP_SENS_CTRL_30:
 612         case RT5682_HP_IMP_SENS_CTRL_31:
 613         case RT5682_HP_IMP_SENS_CTRL_32:
 614         case RT5682_HP_IMP_SENS_CTRL_33:
 615         case RT5682_HP_IMP_SENS_CTRL_34:
 616         case RT5682_HP_IMP_SENS_CTRL_35:
 617         case RT5682_HP_IMP_SENS_CTRL_36:
 618         case RT5682_HP_IMP_SENS_CTRL_37:
 619         case RT5682_HP_IMP_SENS_CTRL_38:
 620         case RT5682_HP_IMP_SENS_CTRL_39:
 621         case RT5682_HP_IMP_SENS_CTRL_40:
 622         case RT5682_HP_IMP_SENS_CTRL_41:
 623         case RT5682_HP_IMP_SENS_CTRL_42:
 624         case RT5682_HP_IMP_SENS_CTRL_43:
 625         case RT5682_HP_LOGIC_CTRL_1:
 626         case RT5682_HP_LOGIC_CTRL_2:
 627         case RT5682_HP_LOGIC_CTRL_3:
 628         case RT5682_HP_CALIB_CTRL_1:
 629         case RT5682_HP_CALIB_CTRL_2:
 630         case RT5682_HP_CALIB_CTRL_3:
 631         case RT5682_HP_CALIB_CTRL_4:
 632         case RT5682_HP_CALIB_CTRL_5:
 633         case RT5682_HP_CALIB_CTRL_6:
 634         case RT5682_HP_CALIB_CTRL_7:
 635         case RT5682_HP_CALIB_CTRL_9:
 636         case RT5682_HP_CALIB_CTRL_10:
 637         case RT5682_HP_CALIB_CTRL_11:
 638         case RT5682_HP_CALIB_STA_1:
 639         case RT5682_HP_CALIB_STA_2:
 640         case RT5682_HP_CALIB_STA_3:
 641         case RT5682_HP_CALIB_STA_4:
 642         case RT5682_HP_CALIB_STA_5:
 643         case RT5682_HP_CALIB_STA_6:
 644         case RT5682_HP_CALIB_STA_7:
 645         case RT5682_HP_CALIB_STA_8:
 646         case RT5682_HP_CALIB_STA_9:
 647         case RT5682_HP_CALIB_STA_10:
 648         case RT5682_HP_CALIB_STA_11:
 649         case RT5682_SAR_IL_CMD_1:
 650         case RT5682_SAR_IL_CMD_2:
 651         case RT5682_SAR_IL_CMD_3:
 652         case RT5682_SAR_IL_CMD_4:
 653         case RT5682_SAR_IL_CMD_5:
 654         case RT5682_SAR_IL_CMD_6:
 655         case RT5682_SAR_IL_CMD_7:
 656         case RT5682_SAR_IL_CMD_8:
 657         case RT5682_SAR_IL_CMD_9:
 658         case RT5682_SAR_IL_CMD_10:
 659         case RT5682_SAR_IL_CMD_11:
 660         case RT5682_SAR_IL_CMD_12:
 661         case RT5682_SAR_IL_CMD_13:
 662         case RT5682_EFUSE_CTRL_1:
 663         case RT5682_EFUSE_CTRL_2:
 664         case RT5682_EFUSE_CTRL_3:
 665         case RT5682_EFUSE_CTRL_4:
 666         case RT5682_EFUSE_CTRL_5:
 667         case RT5682_EFUSE_CTRL_6:
 668         case RT5682_EFUSE_CTRL_7:
 669         case RT5682_EFUSE_CTRL_8:
 670         case RT5682_EFUSE_CTRL_9:
 671         case RT5682_EFUSE_CTRL_10:
 672         case RT5682_EFUSE_CTRL_11:
 673         case RT5682_JD_TOP_VC_VTRL:
 674         case RT5682_DRC1_CTRL_0:
 675         case RT5682_DRC1_CTRL_1:
 676         case RT5682_DRC1_CTRL_2:
 677         case RT5682_DRC1_CTRL_3:
 678         case RT5682_DRC1_CTRL_4:
 679         case RT5682_DRC1_CTRL_5:
 680         case RT5682_DRC1_CTRL_6:
 681         case RT5682_DRC1_HARD_LMT_CTRL_1:
 682         case RT5682_DRC1_HARD_LMT_CTRL_2:
 683         case RT5682_DRC1_PRIV_1:
 684         case RT5682_DRC1_PRIV_2:
 685         case RT5682_DRC1_PRIV_3:
 686         case RT5682_DRC1_PRIV_4:
 687         case RT5682_DRC1_PRIV_5:
 688         case RT5682_DRC1_PRIV_6:
 689         case RT5682_DRC1_PRIV_7:
 690         case RT5682_DRC1_PRIV_8:
 691         case RT5682_EQ_AUTO_RCV_CTRL1:
 692         case RT5682_EQ_AUTO_RCV_CTRL2:
 693         case RT5682_EQ_AUTO_RCV_CTRL3:
 694         case RT5682_EQ_AUTO_RCV_CTRL4:
 695         case RT5682_EQ_AUTO_RCV_CTRL5:
 696         case RT5682_EQ_AUTO_RCV_CTRL6:
 697         case RT5682_EQ_AUTO_RCV_CTRL7:
 698         case RT5682_EQ_AUTO_RCV_CTRL8:
 699         case RT5682_EQ_AUTO_RCV_CTRL9:
 700         case RT5682_EQ_AUTO_RCV_CTRL10:
 701         case RT5682_EQ_AUTO_RCV_CTRL11:
 702         case RT5682_EQ_AUTO_RCV_CTRL12:
 703         case RT5682_EQ_AUTO_RCV_CTRL13:
 704         case RT5682_ADC_L_EQ_LPF1_A1:
 705         case RT5682_R_EQ_LPF1_A1:
 706         case RT5682_L_EQ_LPF1_H0:
 707         case RT5682_R_EQ_LPF1_H0:
 708         case RT5682_L_EQ_BPF1_A1:
 709         case RT5682_R_EQ_BPF1_A1:
 710         case RT5682_L_EQ_BPF1_A2:
 711         case RT5682_R_EQ_BPF1_A2:
 712         case RT5682_L_EQ_BPF1_H0:
 713         case RT5682_R_EQ_BPF1_H0:
 714         case RT5682_L_EQ_BPF2_A1:
 715         case RT5682_R_EQ_BPF2_A1:
 716         case RT5682_L_EQ_BPF2_A2:
 717         case RT5682_R_EQ_BPF2_A2:
 718         case RT5682_L_EQ_BPF2_H0:
 719         case RT5682_R_EQ_BPF2_H0:
 720         case RT5682_L_EQ_BPF3_A1:
 721         case RT5682_R_EQ_BPF3_A1:
 722         case RT5682_L_EQ_BPF3_A2:
 723         case RT5682_R_EQ_BPF3_A2:
 724         case RT5682_L_EQ_BPF3_H0:
 725         case RT5682_R_EQ_BPF3_H0:
 726         case RT5682_L_EQ_BPF4_A1:
 727         case RT5682_R_EQ_BPF4_A1:
 728         case RT5682_L_EQ_BPF4_A2:
 729         case RT5682_R_EQ_BPF4_A2:
 730         case RT5682_L_EQ_BPF4_H0:
 731         case RT5682_R_EQ_BPF4_H0:
 732         case RT5682_L_EQ_HPF1_A1:
 733         case RT5682_R_EQ_HPF1_A1:
 734         case RT5682_L_EQ_HPF1_H0:
 735         case RT5682_R_EQ_HPF1_H0:
 736         case RT5682_L_EQ_PRE_VOL:
 737         case RT5682_R_EQ_PRE_VOL:
 738         case RT5682_L_EQ_POST_VOL:
 739         case RT5682_R_EQ_POST_VOL:
 740         case RT5682_I2C_MODE:
 741                 return true;
 742         default:
 743                 return false;
 744         }
 745 }
 746 EXPORT_SYMBOL_GPL(rt5682_readable_register);
 747
 748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 751
 752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 753 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 754         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 755         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 756         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 757         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 758         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 759         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 760         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 761 );
 762
 763 /* Interface data select */
 764 static const char * const rt5682_data_select[] = {
 765         "L/R", "R/L", "L/L", "R/R"
 766 };
 767
 768 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 769         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 770
 771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 772         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 773
 774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 775         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 776
 777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 778         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 779
 780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 781         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 782
 783 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 784         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 785
 786 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 787         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 788
 789 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 790         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 791
 792 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 793         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 794
 795 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 796         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 797
 798 static const char * const rt5682_dac_select[] = {
 799         "IF1", "SOUND"
 800 };
 801
 802 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
 803         RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
 804
 805 static const struct snd_kcontrol_new rt5682_dac_l_mux =
 806         SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
 807
 808 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
 809         RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
 810
 811 static const struct snd_kcontrol_new rt5682_dac_r_mux =
 812         SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
 813
 814 void rt5682_reset(struct rt5682_priv *rt5682)
 815 {
 816         regmap_write(rt5682->regmap, RT5682_RESET, 0);
 817         if (!rt5682->is_sdw)
 818                 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
 819 }
 820 EXPORT_SYMBOL_GPL(rt5682_reset);
 821
 822 /**
 823  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 824  * @component: SoC audio component device.
 825  * @filter_mask: mask of filters.
 826  * @clk_src: clock source
 827  *
 828  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 829  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 830  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 831  * ASRC function will track i2s clock and generate a corresponding system clock
 832  * for codec. This function provides an API to select the clock source for a
 833  * set of filters specified by the mask. And the component driver will turn on
 834  * ASRC for these filters if ASRC is selected as their clock source.
 835  */
 836 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 837                 unsigned int filter_mask, unsigned int clk_src)
 838 {
 839         switch (clk_src) {
 840         case RT5682_CLK_SEL_SYS:
 841         case RT5682_CLK_SEL_I2S1_ASRC:
 842         case RT5682_CLK_SEL_I2S2_ASRC:
 843                 break;
 844
 845         default:
 846                 return -EINVAL;
 847         }
 848
 849         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 850                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 851                         RT5682_FILTER_CLK_SEL_MASK,
 852                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 853         }
 854
 855         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 856                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 857                         RT5682_FILTER_CLK_SEL_MASK,
 858                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 859         }
 860
 861         return 0;
 862 }
 863 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 864
 865 static int rt5682_button_detect(struct snd_soc_component *component)
 866 {
 867         int btn_type, val;
 868
 869         val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
 870         btn_type = val & 0xfff0;
 871         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 872         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 873         snd_soc_component_update_bits(component,
 874                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 875
 876         return btn_type;
 877 }
 878
 879 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 880                 bool enable)
 881 {
 882         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 883
 884         if (enable) {
 885                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 886                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 887                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 888                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 889                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 890                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 891                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 892                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 893                 if (rt5682->is_sdw)
 894                         snd_soc_component_update_bits(component,
 895                                 RT5682_IRQ_CTRL_3,
 896                                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
 897                                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
 898                 else
 899                         snd_soc_component_update_bits(component,
 900                                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
 901                                 RT5682_IL_IRQ_EN);
 902         } else {
 903                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 904                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 905                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 906                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 907                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 908                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 909                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 910                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 911                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 912                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 913         }
 914 }
 915
 916 /**
 917  * rt5682_headset_detect - Detect headset.
 918  * @component: SoC audio component device.
 919  * @jack_insert: Jack insert or not.
 920  *
 921  * Detect whether is headset or not when jack inserted.
 922  *
 923  * Returns detect status.
 924  */
 925 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
 926 {
 927         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 928         struct snd_soc_dapm_context *dapm = &component->dapm;
 929         unsigned int val, count;
 930
 931         if (jack_insert) {
 932                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 933                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 934                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 935                 snd_soc_component_update_bits(component,
 936                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 937                 usleep_range(15000, 20000);
 938                 snd_soc_component_update_bits(component,
 939                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 940                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 941                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 942                 snd_soc_component_update_bits(component,
 943                         RT5682_HP_CHARGE_PUMP_1,
 944                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
 945                 rt5682_enable_push_button_irq(component, false);
 946                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 947                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 948                 usleep_range(55000, 60000);
 949                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 950                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 951
 952                 count = 0;
 953                 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
 954                         & RT5682_JACK_TYPE_MASK;
 955                 while (val == 0 && count < 50) {
 956                         usleep_range(10000, 15000);
 957                         val = snd_soc_component_read(component,
 958                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 959                         count++;
 960                 }
 961
 962                 switch (val) {
 963                 case 0x1:
 964                 case 0x2:
 965                         rt5682->jack_type = SND_JACK_HEADSET;
 966                         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 967                                 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
 968                         rt5682_enable_push_button_irq(component, true);
 969                         break;
 970                 default:
 971                         rt5682->jack_type = SND_JACK_HEADPHONE;
 972                         break;
 973                 }
 974
 975                 snd_soc_component_update_bits(component,
 976                         RT5682_HP_CHARGE_PUMP_1,
 977                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
 978                         RT5682_OSW_L_EN | RT5682_OSW_R_EN);
 979                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 980                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 981                         RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
 982         } else {
 983                 rt5682_enable_push_button_irq(component, false);
 984                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 985                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 986                 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
 987                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 988                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 989                         snd_soc_component_update_bits(component,
 990                                 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
 991                 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
 992                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 993                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 994                         snd_soc_component_update_bits(component,
 995                                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
 996                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 997                         RT5682_PWR_CBJ, 0);
 998                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 999                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1000                         RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1001                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1002                         RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1003
1004                 rt5682->jack_type = 0;
1005         }
1006
1007         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1008         return rt5682->jack_type;
1009 }
1010
1011 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1012                 struct snd_soc_jack *hs_jack, void *data)
1013 {
1014         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1015
1016         rt5682->hs_jack = hs_jack;
1017
1018         if (!hs_jack) {
1019                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1020                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1021                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1022                         RT5682_POW_JDH | RT5682_POW_JDL, 0);
1023                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1024
1025                 return 0;
1026         }
1027
1028         if (!rt5682->is_sdw) {
1029                 switch (rt5682->pdata.jd_src) {
1030                 case RT5682_JD1:
1031                         snd_soc_component_update_bits(component,
1032                                 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1033                         snd_soc_component_update_bits(component,
1034                                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1035                                 RT5682_EXT_JD_SRC_MANUAL);
1036                         snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1037                                 0xd142);
1038                         snd_soc_component_update_bits(component,
1039                                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1040                                 RT5682_CBJ_IN_BUF_EN);
1041                         snd_soc_component_update_bits(component,
1042                                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1043                                 RT5682_SAR_POW_EN);
1044                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1045                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1046                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1047                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1048                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1049                                 RT5682_POW_JDH | RT5682_POW_ANA);
1050                         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1051                                 RT5682_PWR_JDH, RT5682_PWR_JDH);
1052                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1053                                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1054                                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1055                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1056                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1057                                 rt5682->pdata.btndet_delay));
1058                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1059                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1060                                 rt5682->pdata.btndet_delay));
1061                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1062                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1063                                 rt5682->pdata.btndet_delay));
1064                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1065                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1066                                 rt5682->pdata.btndet_delay));
1067                         mod_delayed_work(system_power_efficient_wq,
1068                                 &rt5682->jack_detect_work,
1069                                 msecs_to_jiffies(250));
1070                         break;
1071
1072                 case RT5682_JD_NULL:
1073                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1074                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1075                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1076                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1077                         break;
1078
1079                 default:
1080                         dev_warn(component->dev, "Wrong JD source\n");
1081                         break;
1082                 }
1083         }
1084
1085         return 0;
1086 }
1087
1088 void rt5682_jack_detect_handler(struct work_struct *work)
1089 {
1090         struct rt5682_priv *rt5682 =
1091                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1092         struct snd_soc_dapm_context *dapm;
1093         int val, btn_type;
1094
1095         if (!rt5682->component || !rt5682->component->card ||
1096             !rt5682->component->card->instantiated) {
1097                 /* card not yet ready, try later */
1098                 mod_delayed_work(system_power_efficient_wq,
1099                                  &rt5682->jack_detect_work, msecs_to_jiffies(15));
1100                 return;
1101         }
1102
1103         dapm = snd_soc_component_get_dapm(rt5682->component);
1104
1105         snd_soc_dapm_mutex_lock(dapm);
1106         mutex_lock(&rt5682->calibrate_mutex);
1107
1108         val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1109                 & RT5682_JDH_RS_MASK;
1110         if (!val) {
1111                 /* jack in */
1112                 if (rt5682->jack_type == 0) {
1113                         /* jack was out, report jack type */
1114                         rt5682->jack_type =
1115                                 rt5682_headset_detect(rt5682->component, 1);
1116                         rt5682->irq_work_delay_time = 0;
1117                 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1118                         SND_JACK_HEADSET) {
1119                         /* jack is already in, report button event */
1120                         rt5682->jack_type = SND_JACK_HEADSET;
1121                         btn_type = rt5682_button_detect(rt5682->component);
1122                         /**
1123                          * rt5682 can report three kinds of button behavior,
1124                          * one click, double click and hold. However,
1125                          * currently we will report button pressed/released
1126                          * event. So all the three button behaviors are
1127                          * treated as button pressed.
1128                          */
1129                         switch (btn_type) {
1130                         case 0x8000:
1131                         case 0x4000:
1132                         case 0x2000:
1133                                 rt5682->jack_type |= SND_JACK_BTN_0;
1134                                 break;
1135                         case 0x1000:
1136                         case 0x0800:
1137                         case 0x0400:
1138                                 rt5682->jack_type |= SND_JACK_BTN_1;
1139                                 break;
1140                         case 0x0200:
1141                         case 0x0100:
1142                         case 0x0080:
1143                                 rt5682->jack_type |= SND_JACK_BTN_2;
1144                                 break;
1145                         case 0x0040:
1146                         case 0x0020:
1147                         case 0x0010:
1148                                 rt5682->jack_type |= SND_JACK_BTN_3;
1149                                 break;
1150                         case 0x0000: /* unpressed */
1151                                 break;
1152                         default:
1153                                 dev_err(rt5682->component->dev,
1154                                         "Unexpected button code 0x%04x\n",
1155                                         btn_type);
1156                                 break;
1157                         }
1158                 }
1159         } else {
1160                 /* jack out */
1161                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1162                 rt5682->irq_work_delay_time = 50;
1163         }
1164
1165         mutex_unlock(&rt5682->calibrate_mutex);
1166         snd_soc_dapm_mutex_unlock(dapm);
1167
1168         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1169                 SND_JACK_HEADSET |
1170                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1171                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1172
1173         if (!rt5682->is_sdw) {
1174                 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1175                         SND_JACK_BTN_2 | SND_JACK_BTN_3))
1176                         schedule_delayed_work(&rt5682->jd_check_work, 0);
1177                 else
1178                         cancel_delayed_work_sync(&rt5682->jd_check_work);
1179         }
1180 }
1181 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1182
1183 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1184         /* DAC Digital Volume */
1185         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1186                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1187
1188         /* IN Boost Volume */
1189         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1190                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1191
1192         /* ADC Digital Volume Control */
1193         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1194                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1195         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1196                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1197
1198         /* ADC Boost Volume Control */
1199         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1200                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1201                 3, 0, adc_bst_tlv),
1202 };
1203
1204 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1205                 int target, const int div[], int size)
1206 {
1207         int i;
1208
1209         if (rt5682->sysclk < target) {
1210                 dev_err(rt5682->component->dev,
1211                         "sysclk rate %d is too low\n", rt5682->sysclk);
1212                 return 0;
1213         }
1214
1215         for (i = 0; i < size - 1; i++) {
1216                 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1217                 if (target * div[i] == rt5682->sysclk)
1218                         return i;
1219                 if (target * div[i + 1] > rt5682->sysclk) {
1220                         dev_dbg(rt5682->component->dev,
1221                                 "can't find div for sysclk %d\n",
1222                                 rt5682->sysclk);
1223                         return i;
1224                 }
1225         }
1226
1227         if (target * div[i] < rt5682->sysclk)
1228                 dev_err(rt5682->component->dev,
1229                         "sysclk rate %d is too high\n", rt5682->sysclk);
1230
1231         return size - 1;
1232 }
1233
1234 /**
1235  * set_dmic_clk - Set parameter of dmic.
1236  *
1237  * @w: DAPM widget.
1238  * @kcontrol: The kcontrol of this widget.
1239  * @event: Event id.
1240  *
1241  * Choose dmic clock between 1MHz and 3MHz.
1242  * It is better for clock to approximate 3MHz.
1243  */
1244 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1245                 struct snd_kcontrol *kcontrol, int event)
1246 {
1247         struct snd_soc_component *component =
1248                 snd_soc_dapm_to_component(w->dapm);
1249         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1250         int idx, dmic_clk_rate = 3072000;
1251         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1252
1253         if (rt5682->pdata.dmic_clk_rate)
1254                 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1255
1256         idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1257
1258         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1259                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1260
1261         return 0;
1262 }
1263
1264 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1265                 struct snd_kcontrol *kcontrol, int event)
1266 {
1267         struct snd_soc_component *component =
1268                 snd_soc_dapm_to_component(w->dapm);
1269         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1270         int ref, val, reg, idx;
1271         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1272         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1273
1274         if (rt5682->is_sdw)
1275                 return 0;
1276
1277         val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1278                 RT5682_GP4_PIN_MASK;
1279         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1280                 val == RT5682_GP4_PIN_ADCDAT2)
1281                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1282         else
1283                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1284
1285         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1286
1287         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1288                 reg = RT5682_PLL_TRACK_3;
1289         else
1290                 reg = RT5682_PLL_TRACK_2;
1291
1292         snd_soc_component_update_bits(component, reg,
1293                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1294
1295         /* select over sample rate */
1296         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1297                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1298                         break;
1299         }
1300
1301         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1302                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1303                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1304
1305         return 0;
1306 }
1307
1308 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1309                 struct snd_soc_dapm_widget *sink)
1310 {
1311         unsigned int val;
1312         struct snd_soc_component *component =
1313                 snd_soc_dapm_to_component(w->dapm);
1314
1315         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1316         val &= RT5682_SCLK_SRC_MASK;
1317         if (val == RT5682_SCLK_SRC_PLL1)
1318                 return 1;
1319         else
1320                 return 0;
1321 }
1322
1323 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1324                 struct snd_soc_dapm_widget *sink)
1325 {
1326         unsigned int val;
1327         struct snd_soc_component *component =
1328                 snd_soc_dapm_to_component(w->dapm);
1329
1330         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1331         val &= RT5682_SCLK_SRC_MASK;
1332         if (val == RT5682_SCLK_SRC_PLL2)
1333                 return 1;
1334         else
1335                 return 0;
1336 }
1337
1338 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1339                 struct snd_soc_dapm_widget *sink)
1340 {
1341         unsigned int reg, shift, val;
1342         struct snd_soc_component *component =
1343                 snd_soc_dapm_to_component(w->dapm);
1344
1345         switch (w->shift) {
1346         case RT5682_ADC_STO1_ASRC_SFT:
1347                 reg = RT5682_PLL_TRACK_3;
1348                 shift = RT5682_FILTER_CLK_SEL_SFT;
1349                 break;
1350         case RT5682_DAC_STO1_ASRC_SFT:
1351                 reg = RT5682_PLL_TRACK_2;
1352                 shift = RT5682_FILTER_CLK_SEL_SFT;
1353                 break;
1354         default:
1355                 return 0;
1356         }
1357
1358         val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1359         switch (val) {
1360         case RT5682_CLK_SEL_I2S1_ASRC:
1361         case RT5682_CLK_SEL_I2S2_ASRC:
1362                 return 1;
1363         default:
1364                 return 0;
1365         }
1366 }
1367
1368 /* Digital Mixer */
1369 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1370         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1371                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1372         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1373                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1374 };
1375
1376 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1377         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1378                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1379         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1380                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1381 };
1382
1383 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1384         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1385                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1386         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1387                         RT5682_M_DAC1_L_SFT, 1, 1),
1388 };
1389
1390 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1391         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1392                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1393         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1394                         RT5682_M_DAC1_R_SFT, 1, 1),
1395 };
1396
1397 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1398         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1399                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1400         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1401                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1402 };
1403
1404 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1405         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1406                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1407         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1408                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1409 };
1410
1411 /* Analog Input Mixer */
1412 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1413         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1414                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1415 };
1416
1417 /* STO1 ADC1 Source */
1418 /* MX-26 [13] [5] */
1419 static const char * const rt5682_sto1_adc1_src[] = {
1420         "DAC MIX", "ADC"
1421 };
1422
1423 static SOC_ENUM_SINGLE_DECL(
1424         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1425         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1426
1427 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1428         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1429
1430 static SOC_ENUM_SINGLE_DECL(
1431         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1432         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1433
1434 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1435         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1436
1437 /* STO1 ADC Source */
1438 /* MX-26 [11:10] [3:2] */
1439 static const char * const rt5682_sto1_adc_src[] = {
1440         "ADC1 L", "ADC1 R"
1441 };
1442
1443 static SOC_ENUM_SINGLE_DECL(
1444         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1445         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1446
1447 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1448         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1449
1450 static SOC_ENUM_SINGLE_DECL(
1451         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1452         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1453
1454 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1455         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1456
1457 /* STO1 ADC2 Source */
1458 /* MX-26 [12] [4] */
1459 static const char * const rt5682_sto1_adc2_src[] = {
1460         "DAC MIX", "DMIC"
1461 };
1462
1463 static SOC_ENUM_SINGLE_DECL(
1464         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1465         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1466
1467 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1468         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1469
1470 static SOC_ENUM_SINGLE_DECL(
1471         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1472         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1473
1474 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1475         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1476
1477 /* MX-79 [6:4] I2S1 ADC data location */
1478 static const unsigned int rt5682_if1_adc_slot_values[] = {
1479         0,
1480         2,
1481         4,
1482         6,
1483 };
1484
1485 static const char * const rt5682_if1_adc_slot_src[] = {
1486         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1487 };
1488
1489 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1490         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1491         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1492
1493 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1494         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1495
1496 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1497 /* MX-2B [4], MX-2B [0]*/
1498 static const char * const rt5682_alg_dac1_src[] = {
1499         "Stereo1 DAC Mixer", "DAC1"
1500 };
1501
1502 static SOC_ENUM_SINGLE_DECL(
1503         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1504         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1505
1506 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1507         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1508
1509 static SOC_ENUM_SINGLE_DECL(
1510         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1511         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1512
1513 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1514         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1515
1516 /* Out Switch */
1517 static const struct snd_kcontrol_new hpol_switch =
1518         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1519                 RT5682_L_MUTE_SFT, 1, 1);
1520 static const struct snd_kcontrol_new hpor_switch =
1521         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1522                 RT5682_R_MUTE_SFT, 1, 1);
1523
1524 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1525                 struct snd_kcontrol *kcontrol, int event)
1526 {
1527         struct snd_soc_component *component =
1528                 snd_soc_dapm_to_component(w->dapm);
1529
1530         switch (event) {
1531         case SND_SOC_DAPM_PRE_PMU:
1532                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1533                         RT5682_HP_C2_DAC_AMP_MUTE, 0);
1534                 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1535                         RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1536                 snd_soc_component_update_bits(component,
1537                         RT5682_DEPOP_1, 0x60, 0x60);
1538                 snd_soc_component_update_bits(component,
1539                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1540                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1541                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1542                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1543                 usleep_range(5000, 10000);
1544                 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1545                         RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1546                 break;
1547
1548         case SND_SOC_DAPM_POST_PMD:
1549                 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1550                         RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
1551                 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1552                         RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1553                 snd_soc_component_update_bits(component,
1554                         RT5682_DEPOP_1, 0x60, 0x0);
1555                 snd_soc_component_update_bits(component,
1556                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1557                 break;
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1564                 struct snd_kcontrol *kcontrol, int event)
1565 {
1566         struct snd_soc_component *component =
1567                 snd_soc_dapm_to_component(w->dapm);
1568         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1569         unsigned int delay = 50, val;
1570
1571         if (rt5682->pdata.dmic_delay)
1572                 delay = rt5682->pdata.dmic_delay;
1573
1574         switch (event) {
1575         case SND_SOC_DAPM_POST_PMU:
1576                 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1577                 val &= RT5682_SCLK_SRC_MASK;
1578                 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1579                         snd_soc_component_update_bits(component,
1580                                 RT5682_PWR_ANLG_1,
1581                                 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1582                                 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1583
1584                 /*Add delay to avoid pop noise*/
1585                 msleep(delay);
1586                 break;
1587
1588         case SND_SOC_DAPM_POST_PMD:
1589                 if (!rt5682->jack_type) {
1590                         if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1591                                 snd_soc_component_update_bits(component,
1592                                         RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1593                         if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1594                                 snd_soc_component_update_bits(component,
1595                                         RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1596                 }
1597                 break;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1604                 struct snd_kcontrol *kcontrol, int event)
1605 {
1606         struct snd_soc_component *component =
1607                 snd_soc_dapm_to_component(w->dapm);
1608
1609         switch (event) {
1610         case SND_SOC_DAPM_PRE_PMU:
1611                 switch (w->shift) {
1612                 case RT5682_PWR_VREF1_BIT:
1613                         snd_soc_component_update_bits(component,
1614                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1615                         break;
1616
1617                 case RT5682_PWR_VREF2_BIT:
1618                         snd_soc_component_update_bits(component,
1619                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1620                         break;
1621                 }
1622                 break;
1623
1624         case SND_SOC_DAPM_POST_PMU:
1625                 usleep_range(15000, 20000);
1626                 switch (w->shift) {
1627                 case RT5682_PWR_VREF1_BIT:
1628                         snd_soc_component_update_bits(component,
1629                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1630                                 RT5682_PWR_FV1);
1631                         break;
1632
1633                 case RT5682_PWR_VREF2_BIT:
1634                         snd_soc_component_update_bits(component,
1635                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1636                                 RT5682_PWR_FV2);
1637                         break;
1638                 }
1639                 break;
1640         }
1641
1642         return 0;
1643 }
1644
1645 static const unsigned int rt5682_adcdat_pin_values[] = {
1646         1,
1647         3,
1648 };
1649
1650 static const char * const rt5682_adcdat_pin_select[] = {
1651         "ADCDAT1",
1652         "ADCDAT2",
1653 };
1654
1655 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1656         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1657         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1658
1659 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1660         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1661
1662 static const unsigned int rt5682_hpo_sig_out_values[] = {
1663         2,
1664         7,
1665 };
1666
1667 static const char * const rt5682_hpo_sig_out_mode[] = {
1668         "Legacy",
1669         "OneBit",
1670 };
1671
1672 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1673         RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1674         rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1675
1676 static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1677         SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1678
1679 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1680         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1681                 0, NULL, 0),
1682         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1683                 0, NULL, 0),
1684         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1685                 0, NULL, 0),
1686         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1687                 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1688         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1689                 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1690         SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1691         SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1692
1693         /* ASRC */
1694         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1695                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1696         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1697                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1698         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1699                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1700         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1701                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1702         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1703                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1704
1705         /* Input Side */
1706         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1707                 0, NULL, 0),
1708         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1709                 0, NULL, 0),
1710
1711         /* Input Lines */
1712         SND_SOC_DAPM_INPUT("DMIC L1"),
1713         SND_SOC_DAPM_INPUT("DMIC R1"),
1714
1715         SND_SOC_DAPM_INPUT("IN1P"),
1716
1717         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1718                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1719         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1720                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1721                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1722
1723         /* Boost */
1724         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1725                 0, 0, NULL, 0),
1726
1727         /* REC Mixer */
1728         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1729                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1730         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1731                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1732
1733         /* ADCs */
1734         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1735         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1736
1737         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1738                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1739         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1740                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1741         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1742                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1743
1744         /* ADC Mux */
1745         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1746                 &rt5682_sto1_adc1l_mux),
1747         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1748                 &rt5682_sto1_adc1r_mux),
1749         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1750                 &rt5682_sto1_adc2l_mux),
1751         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1752                 &rt5682_sto1_adc2r_mux),
1753         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1754                 &rt5682_sto1_adcl_mux),
1755         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1756                 &rt5682_sto1_adcr_mux),
1757         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1758                 &rt5682_if1_adc_slot_mux),
1759
1760         /* ADC Mixer */
1761         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1762                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1763                 SND_SOC_DAPM_PRE_PMU),
1764         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1765                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1766                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1767         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1768                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1769                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1770
1771         /* ADC PGA */
1772         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1773
1774         /* Digital Interface */
1775         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1776                 0, NULL, 0),
1777         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1778                 0, NULL, 0),
1779         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1780         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1781         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1782         SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1783         SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1784
1785         /* Digital Interface Select */
1786         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1787                 &rt5682_if1_01_adc_swap_mux),
1788         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1789                 &rt5682_if1_23_adc_swap_mux),
1790         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1791                 &rt5682_if1_45_adc_swap_mux),
1792         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1793                 &rt5682_if1_67_adc_swap_mux),
1794         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1795                 &rt5682_if2_adc_swap_mux),
1796
1797         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1798                 &rt5682_adcdat_pin_ctrl),
1799
1800         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1801                 &rt5682_dac_l_mux),
1802         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1803                 &rt5682_dac_r_mux),
1804
1805         /* Audio Interface */
1806         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1807                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1808         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1809                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1810         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1811         SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1812         SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1813
1814         /* Output Side */
1815         /* DAC mixer before sound effect  */
1816         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1817                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1818         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1819                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1820
1821         /* DAC channel Mux */
1822         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1823                 &rt5682_alg_dac_l1_mux),
1824         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1825                 &rt5682_alg_dac_r1_mux),
1826
1827         /* DAC Mixer */
1828         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1829                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1830                 SND_SOC_DAPM_PRE_PMU),
1831         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1832                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1833         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1834                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1835
1836         /* DACs */
1837         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1838                 RT5682_PWR_DAC_L1_BIT, 0),
1839         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1840                 RT5682_PWR_DAC_R1_BIT, 0),
1841         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1842                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1843
1844         /* HPO */
1845         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1846                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1847
1848         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1849                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1850         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1851                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1852         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1853                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1854         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1855                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1856
1857         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1858                 &hpol_switch),
1859         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1860                 &hpor_switch),
1861
1862         SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1863         SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1864         SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1865
1866         /* CLK DET */
1867         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1868                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1869         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1870                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1871         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1872                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1873         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1874                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1875
1876         /* Output Lines */
1877         SND_SOC_DAPM_OUTPUT("HPOL"),
1878         SND_SOC_DAPM_OUTPUT("HPOR"),
1879 };
1880
1881 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1882         /*PLL*/
1883         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1884         {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1885         {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1886         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1887         {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1888         {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1889
1890         /*ASRC*/
1891         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1892         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1893         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1894         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1895         {"ADC STO1 ASRC", NULL, "CLKDET"},
1896         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1897         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1898         {"DAC STO1 ASRC", NULL, "CLKDET"},
1899
1900         /*Vref*/
1901         {"MICBIAS1", NULL, "Vref1"},
1902         {"MICBIAS2", NULL, "Vref1"},
1903
1904         {"CLKDET SYS", NULL, "CLKDET"},
1905
1906         {"BST1 CBJ", NULL, "IN1P"},
1907
1908         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1909         {"RECMIX1L", NULL, "RECMIX1L Power"},
1910
1911         {"ADC1 L", NULL, "RECMIX1L"},
1912         {"ADC1 L", NULL, "ADC1 L Power"},
1913         {"ADC1 L", NULL, "ADC1 clock"},
1914
1915         {"DMIC L1", NULL, "DMIC CLK"},
1916         {"DMIC L1", NULL, "DMIC1 Power"},
1917         {"DMIC R1", NULL, "DMIC CLK"},
1918         {"DMIC R1", NULL, "DMIC1 Power"},
1919         {"DMIC CLK", NULL, "DMIC ASRC"},
1920
1921         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1922         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1923         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1924         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1925
1926         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1927         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1928         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1929         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1930
1931         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1932         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1933         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1934         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1935
1936         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1937         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1938         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1939
1940         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1941         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1942         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1943
1944         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1945         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1946
1947         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1948         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1949         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1950         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1951         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1952         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1953         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1954         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1955         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1956         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1957         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1958         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1959         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1960         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1961         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1962         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1963
1964         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1965         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1966         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1967         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1968         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1969         {"AIF1TX", NULL, "I2S1"},
1970         {"AIF1TX", NULL, "ADCDAT Mux"},
1971         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1972         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1973         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1974         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1975         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1976         {"AIF2TX", NULL, "ADCDAT Mux"},
1977
1978         {"SDWTX", NULL, "PLL2B"},
1979         {"SDWTX", NULL, "PLL2F"},
1980         {"SDWTX", NULL, "ADCDAT Mux"},
1981
1982         {"IF1 DAC1 L", NULL, "AIF1RX"},
1983         {"IF1 DAC1 L", NULL, "I2S1"},
1984         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1985         {"IF1 DAC1 R", NULL, "AIF1RX"},
1986         {"IF1 DAC1 R", NULL, "I2S1"},
1987         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1988
1989         {"SOUND DAC L", NULL, "SDWRX"},
1990         {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1991         {"SOUND DAC L", NULL, "PLL2B"},
1992         {"SOUND DAC L", NULL, "PLL2F"},
1993         {"SOUND DAC R", NULL, "SDWRX"},
1994         {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1995         {"SOUND DAC R", NULL, "PLL2B"},
1996         {"SOUND DAC R", NULL, "PLL2F"},
1997
1998         {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1999         {"DAC L Mux", "SOUND", "SOUND DAC L"},
2000         {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2001         {"DAC R Mux", "SOUND", "SOUND DAC R"},
2002
2003         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2004         {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2005         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2006         {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2007
2008         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2009         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2010
2011         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2012         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2013
2014         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2015         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2016         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2017         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2018
2019         {"DAC L1", NULL, "DAC L1 Source"},
2020         {"DAC R1", NULL, "DAC R1 Source"},
2021
2022         {"DAC L1", NULL, "DAC 1 Clock"},
2023         {"DAC R1", NULL, "DAC 1 Clock"},
2024
2025         {"HP Amp", NULL, "DAC L1"},
2026         {"HP Amp", NULL, "DAC R1"},
2027         {"HP Amp", NULL, "HP Amp L"},
2028         {"HP Amp", NULL, "HP Amp R"},
2029         {"HP Amp", NULL, "Capless"},
2030         {"HP Amp", NULL, "Charge Pump"},
2031         {"HP Amp", NULL, "CLKDET SYS"},
2032         {"HP Amp", NULL, "Vref1"},
2033
2034         {"HPO Signal Demux", NULL, "HP Amp"},
2035
2036         {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2037         {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2038
2039         {"HPOL Playback", "Switch", "HPO Legacy"},
2040         {"HPOR Playback", "Switch", "HPO Legacy"},
2041
2042         {"HPOL", NULL, "HPOL Playback"},
2043         {"HPOR", NULL, "HPOR Playback"},
2044         {"HPOL", NULL, "HPO OneBit"},
2045         {"HPOR", NULL, "HPO OneBit"},
2046 };
2047
2048 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2049                 unsigned int rx_mask, int slots, int slot_width)
2050 {
2051         struct snd_soc_component *component = dai->component;
2052         unsigned int cl, val = 0;
2053
2054         if (tx_mask || rx_mask)
2055                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2056                         RT5682_TDM_EN, RT5682_TDM_EN);
2057         else
2058                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2059                         RT5682_TDM_EN, 0);
2060
2061         switch (slots) {
2062         case 4:
2063                 val |= RT5682_TDM_TX_CH_4;
2064                 val |= RT5682_TDM_RX_CH_4;
2065                 break;
2066         case 6:
2067                 val |= RT5682_TDM_TX_CH_6;
2068                 val |= RT5682_TDM_RX_CH_6;
2069                 break;
2070         case 8:
2071                 val |= RT5682_TDM_TX_CH_8;
2072                 val |= RT5682_TDM_RX_CH_8;
2073                 break;
2074         case 2:
2075                 break;
2076         default:
2077                 return -EINVAL;
2078         }
2079
2080         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2081                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2082
2083         switch (slot_width) {
2084         case 8:
2085                 if (tx_mask || rx_mask)
2086                         return -EINVAL;
2087                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2088                 break;
2089         case 16:
2090                 val = RT5682_TDM_CL_16;
2091                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2092                 break;
2093         case 20:
2094                 val = RT5682_TDM_CL_20;
2095                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2096                 break;
2097         case 24:
2098                 val = RT5682_TDM_CL_24;
2099                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2100                 break;
2101         case 32:
2102                 val = RT5682_TDM_CL_32;
2103                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2104                 break;
2105         default:
2106                 return -EINVAL;
2107         }
2108
2109         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2110                 RT5682_TDM_CL_MASK, val);
2111         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2112                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2113
2114         return 0;
2115 }
2116
2117 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2118                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2119 {
2120         struct snd_soc_component *component = dai->component;
2121         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2122         unsigned int len_1 = 0, len_2 = 0;
2123         int pre_div, frame_size;
2124
2125         rt5682->lrck[dai->id] = params_rate(params);
2126         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2127
2128         frame_size = snd_soc_params_to_frame_size(params);
2129         if (frame_size < 0) {
2130                 dev_err(component->dev, "Unsupported frame size: %d\n",
2131                         frame_size);
2132                 return -EINVAL;
2133         }
2134
2135         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2136                 rt5682->lrck[dai->id], pre_div, dai->id);
2137
2138         switch (params_width(params)) {
2139         case 16:
2140                 break;
2141         case 20:
2142                 len_1 |= RT5682_I2S1_DL_20;
2143                 len_2 |= RT5682_I2S2_DL_20;
2144                 break;
2145         case 24:
2146                 len_1 |= RT5682_I2S1_DL_24;
2147                 len_2 |= RT5682_I2S2_DL_24;
2148                 break;
2149         case 32:
2150                 len_1 |= RT5682_I2S1_DL_32;
2151                 len_2 |= RT5682_I2S2_DL_24;
2152                 break;
2153         case 8:
2154                 len_1 |= RT5682_I2S2_DL_8;
2155                 len_2 |= RT5682_I2S2_DL_8;
2156                 break;
2157         default:
2158                 return -EINVAL;
2159         }
2160
2161         switch (dai->id) {
2162         case RT5682_AIF1:
2163                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2164                         RT5682_I2S1_DL_MASK, len_1);
2165                 if (rt5682->master[RT5682_AIF1]) {
2166                         snd_soc_component_update_bits(component,
2167                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2168                                 RT5682_I2S_CLK_SRC_MASK,
2169                                 pre_div << RT5682_I2S_M_DIV_SFT |
2170                                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2171                 }
2172                 if (params_channels(params) == 1) /* mono mode */
2173                         snd_soc_component_update_bits(component,
2174                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2175                                 RT5682_I2S1_MONO_EN);
2176                 else
2177                         snd_soc_component_update_bits(component,
2178                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2179                                 RT5682_I2S1_MONO_DIS);
2180                 break;
2181         case RT5682_AIF2:
2182                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2183                         RT5682_I2S2_DL_MASK, len_2);
2184                 if (rt5682->master[RT5682_AIF2]) {
2185                         snd_soc_component_update_bits(component,
2186                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2187                                 pre_div << RT5682_I2S2_M_PD_SFT);
2188                 }
2189                 if (params_channels(params) == 1) /* mono mode */
2190                         snd_soc_component_update_bits(component,
2191                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2192                                 RT5682_I2S2_MONO_EN);
2193                 else
2194                         snd_soc_component_update_bits(component,
2195                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2196                                 RT5682_I2S2_MONO_DIS);
2197                 break;
2198         default:
2199                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2200                 return -EINVAL;
2201         }
2202
2203         return 0;
2204 }
2205
2206 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2207 {
2208         struct snd_soc_component *component = dai->component;
2209         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2210         unsigned int reg_val = 0, tdm_ctrl = 0;
2211
2212         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2213         case SND_SOC_DAIFMT_CBM_CFM:
2214                 rt5682->master[dai->id] = 1;
2215                 break;
2216         case SND_SOC_DAIFMT_CBS_CFS:
2217                 rt5682->master[dai->id] = 0;
2218                 break;
2219         default:
2220                 return -EINVAL;
2221         }
2222
2223         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2224         case SND_SOC_DAIFMT_NB_NF:
2225                 break;
2226         case SND_SOC_DAIFMT_IB_NF:
2227                 reg_val |= RT5682_I2S_BP_INV;
2228                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2229                 break;
2230         case SND_SOC_DAIFMT_NB_IF:
2231                 if (dai->id == RT5682_AIF1)
2232                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2233                 else
2234                         return -EINVAL;
2235                 break;
2236         case SND_SOC_DAIFMT_IB_IF:
2237                 if (dai->id == RT5682_AIF1)
2238                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2239                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2240                 else
2241                         return -EINVAL;
2242                 break;
2243         default:
2244                 return -EINVAL;
2245         }
2246
2247         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2248         case SND_SOC_DAIFMT_I2S:
2249                 break;
2250         case SND_SOC_DAIFMT_LEFT_J:
2251                 reg_val |= RT5682_I2S_DF_LEFT;
2252                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2253                 break;
2254         case SND_SOC_DAIFMT_DSP_A:
2255                 reg_val |= RT5682_I2S_DF_PCM_A;
2256                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2257                 break;
2258         case SND_SOC_DAIFMT_DSP_B:
2259                 reg_val |= RT5682_I2S_DF_PCM_B;
2260                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2261                 break;
2262         default:
2263                 return -EINVAL;
2264         }
2265
2266         switch (dai->id) {
2267         case RT5682_AIF1:
2268                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2269                         RT5682_I2S_DF_MASK, reg_val);
2270                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2271                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2272                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2273                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2274                         tdm_ctrl | rt5682->master[dai->id]);
2275                 break;
2276         case RT5682_AIF2:
2277                 if (rt5682->master[dai->id] == 0)
2278                         reg_val |= RT5682_I2S2_MS_S;
2279                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2280                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2281                         RT5682_I2S_DF_MASK, reg_val);
2282                 break;
2283         default:
2284                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2285                 return -EINVAL;
2286         }
2287         return 0;
2288 }
2289
2290 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2291                 int clk_id, int source, unsigned int freq, int dir)
2292 {
2293         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2294         unsigned int reg_val = 0, src = 0;
2295
2296         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2297                 return 0;
2298
2299         switch (clk_id) {
2300         case RT5682_SCLK_S_MCLK:
2301                 reg_val |= RT5682_SCLK_SRC_MCLK;
2302                 src = RT5682_CLK_SRC_MCLK;
2303                 break;
2304         case RT5682_SCLK_S_PLL1:
2305                 reg_val |= RT5682_SCLK_SRC_PLL1;
2306                 src = RT5682_CLK_SRC_PLL1;
2307                 break;
2308         case RT5682_SCLK_S_PLL2:
2309                 reg_val |= RT5682_SCLK_SRC_PLL2;
2310                 src = RT5682_CLK_SRC_PLL2;
2311                 break;
2312         case RT5682_SCLK_S_RCCLK:
2313                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2314                 src = RT5682_CLK_SRC_RCCLK;
2315                 break;
2316         default:
2317                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2318                 return -EINVAL;
2319         }
2320         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2321                 RT5682_SCLK_SRC_MASK, reg_val);
2322
2323         if (rt5682->master[RT5682_AIF2]) {
2324                 snd_soc_component_update_bits(component,
2325                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2326                         src << RT5682_I2S2_SRC_SFT);
2327         }
2328
2329         rt5682->sysclk = freq;
2330         rt5682->sysclk_src = clk_id;
2331
2332         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2333                 freq, clk_id);
2334
2335         return 0;
2336 }
2337
2338 static int rt5682_set_component_pll(struct snd_soc_component *component,
2339                 int pll_id, int source, unsigned int freq_in,
2340                 unsigned int freq_out)
2341 {
2342         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2343         struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2344         unsigned int pll2_fout1, pll2_ps_val;
2345         int ret;
2346
2347         if (source == rt5682->pll_src[pll_id] &&
2348             freq_in == rt5682->pll_in[pll_id] &&
2349             freq_out == rt5682->pll_out[pll_id])
2350                 return 0;
2351
2352         if (!freq_in || !freq_out) {
2353                 dev_dbg(component->dev, "PLL disabled\n");
2354
2355                 rt5682->pll_in[pll_id] = 0;
2356                 rt5682->pll_out[pll_id] = 0;
2357                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2358                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2359                 return 0;
2360         }
2361
2362         if (pll_id == RT5682_PLL2) {
2363                 switch (source) {
2364                 case RT5682_PLL2_S_MCLK:
2365                         snd_soc_component_update_bits(component,
2366                                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2367                                 RT5682_PLL2_SRC_MCLK);
2368                         break;
2369                 default:
2370                         dev_err(component->dev, "Unknown PLL2 Source %d\n",
2371                                 source);
2372                         return -EINVAL;
2373                 }
2374
2375                 /**
2376                  * PLL2 concatenates 2 PLL units.
2377                  * We suggest the Fout of the front PLL is 3.84MHz.
2378                  */
2379                 pll2_fout1 = 3840000;
2380                 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2381                 if (ret < 0) {
2382                         dev_err(component->dev, "Unsupported input clock %d\n",
2383                                 freq_in);
2384                         return ret;
2385                 }
2386                 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2387                         freq_in, pll2_fout1,
2388                         pll2f_code.m_bp,
2389                         (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2390                         pll2f_code.n_code, pll2f_code.k_code);
2391
2392                 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2393                 if (ret < 0) {
2394                         dev_err(component->dev, "Unsupported input clock %d\n",
2395                                 pll2_fout1);
2396                         return ret;
2397                 }
2398                 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2399                         pll2_fout1, freq_out,
2400                         pll2b_code.m_bp,
2401                         (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2402                         pll2b_code.n_code, pll2b_code.k_code);
2403
2404                 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2405                         pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2406                         pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2407                         pll2b_code.m_code);
2408                 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2409                         pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2410                         pll2b_code.n_code);
2411                 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2412                         pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2413
2414                 if (freq_out == 22579200)
2415                         pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2416                 else
2417                         pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2418                 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2419                         RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2420                         RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2421                         pll2_ps_val |
2422                         (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2423                         (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2424                         0xf);
2425         } else {
2426                 switch (source) {
2427                 case RT5682_PLL1_S_MCLK:
2428                         snd_soc_component_update_bits(component,
2429                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2430                                 RT5682_PLL1_SRC_MCLK);
2431                         break;
2432                 case RT5682_PLL1_S_BCLK1:
2433                         snd_soc_component_update_bits(component,
2434                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2435                                 RT5682_PLL1_SRC_BCLK1);
2436                         break;
2437                 default:
2438                         dev_err(component->dev, "Unknown PLL1 Source %d\n",
2439                                 source);
2440                         return -EINVAL;
2441                 }
2442
2443                 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2444                 if (ret < 0) {
2445                         dev_err(component->dev, "Unsupported input clock %d\n",
2446                                 freq_in);
2447                         return ret;
2448                 }
2449
2450                 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2451                         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2452                         pll_code.n_code, pll_code.k_code);
2453
2454                 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2455                         (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2456                 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2457                         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2458                         ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2459         }
2460
2461         rt5682->pll_in[pll_id] = freq_in;
2462         rt5682->pll_out[pll_id] = freq_out;
2463         rt5682->pll_src[pll_id] = source;
2464
2465         return 0;
2466 }
2467
2468 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2469 {
2470         struct snd_soc_component *component = dai->component;
2471         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2472
2473         rt5682->bclk[dai->id] = ratio;
2474
2475         switch (ratio) {
2476         case 256:
2477                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2478                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2479                 break;
2480         case 128:
2481                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2482                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2483                 break;
2484         case 64:
2485                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2486                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2487                 break;
2488         case 32:
2489                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2490                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2491                 break;
2492         default:
2493                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2494                 return -EINVAL;
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2501 {
2502         struct snd_soc_component *component = dai->component;
2503         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2504
2505         rt5682->bclk[dai->id] = ratio;
2506
2507         switch (ratio) {
2508         case 64:
2509                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2510                         RT5682_I2S2_BCLK_MS2_MASK,
2511                         RT5682_I2S2_BCLK_MS2_64);
2512                 break;
2513         case 32:
2514                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2515                         RT5682_I2S2_BCLK_MS2_MASK,
2516                         RT5682_I2S2_BCLK_MS2_32);
2517                 break;
2518         default:
2519                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2520                 return -EINVAL;
2521         }
2522
2523         return 0;
2524 }
2525
2526 static int rt5682_set_bias_level(struct snd_soc_component *component,
2527                 enum snd_soc_bias_level level)
2528 {
2529         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2530
2531         switch (level) {
2532         case SND_SOC_BIAS_PREPARE:
2533                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2534                         RT5682_PWR_BG, RT5682_PWR_BG);
2535                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2536                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2537                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2538                 break;
2539
2540         case SND_SOC_BIAS_STANDBY:
2541                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2542                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2543                 break;
2544         case SND_SOC_BIAS_OFF:
2545                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2546                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2547                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2548                         RT5682_PWR_BG, 0);
2549                 break;
2550         case SND_SOC_BIAS_ON:
2551                 break;
2552         }
2553
2554         return 0;
2555 }
2556
2557 #ifdef CONFIG_COMMON_CLK
2558 #define CLK_PLL2_FIN 48000000
2559 #define CLK_48 48000
2560 #define CLK_44 44100
2561
2562 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2563 {
2564         if (!rt5682->master[RT5682_AIF1]) {
2565                 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2566                 return false;
2567         }
2568         return true;
2569 }
2570
2571 static int rt5682_wclk_prepare(struct clk_hw *hw)
2572 {
2573         struct rt5682_priv *rt5682 =
2574                 container_of(hw, struct rt5682_priv,
2575                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2576         struct snd_soc_component *component;
2577         struct snd_soc_dapm_context *dapm;
2578
2579         if (!rt5682_clk_check(rt5682))
2580                 return -EINVAL;
2581
2582         component = rt5682->component;
2583         dapm = snd_soc_component_get_dapm(component);
2584
2585         snd_soc_dapm_mutex_lock(dapm);
2586
2587         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2588         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2589                                 RT5682_PWR_MB, RT5682_PWR_MB);
2590
2591         snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2592         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2593                         RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2594                         RT5682_PWR_VREF2);
2595         usleep_range(55000, 60000);
2596         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2597                         RT5682_PWR_FV2, RT5682_PWR_FV2);
2598
2599         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2600         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2601         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2602         snd_soc_dapm_sync_unlocked(dapm);
2603
2604         snd_soc_dapm_mutex_unlock(dapm);
2605
2606         return 0;
2607 }
2608
2609 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2610 {
2611         struct rt5682_priv *rt5682 =
2612                 container_of(hw, struct rt5682_priv,
2613                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2614         struct snd_soc_component *component;
2615         struct snd_soc_dapm_context *dapm;
2616
2617         if (!rt5682_clk_check(rt5682))
2618                 return;
2619
2620         component = rt5682->component;
2621         dapm = snd_soc_component_get_dapm(component);
2622
2623         snd_soc_dapm_mutex_lock(dapm);
2624
2625         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2626         snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2627         if (!rt5682->jack_type)
2628                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2629                                 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2630                                 RT5682_PWR_MB, 0);
2631
2632         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2633         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2634         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2635         snd_soc_dapm_sync_unlocked(dapm);
2636
2637         snd_soc_dapm_mutex_unlock(dapm);
2638 }
2639
2640 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2641                                              unsigned long parent_rate)
2642 {
2643         struct rt5682_priv *rt5682 =
2644                 container_of(hw, struct rt5682_priv,
2645                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2646         const char * const clk_name = clk_hw_get_name(hw);
2647
2648         if (!rt5682_clk_check(rt5682))
2649                 return 0;
2650         /*
2651          * Only accept to set wclk rate to 44.1k or 48kHz.
2652          */
2653         if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2654             rt5682->lrck[RT5682_AIF1] != CLK_44) {
2655                 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2656                         __func__, clk_name, CLK_44, CLK_48);
2657                 return 0;
2658         }
2659
2660         return rt5682->lrck[RT5682_AIF1];
2661 }
2662
2663 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2664                                    unsigned long *parent_rate)
2665 {
2666         struct rt5682_priv *rt5682 =
2667                 container_of(hw, struct rt5682_priv,
2668                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2669         const char * const clk_name = clk_hw_get_name(hw);
2670
2671         if (!rt5682_clk_check(rt5682))
2672                 return -EINVAL;
2673         /*
2674          * Only accept to set wclk rate to 44.1k or 48kHz.
2675          * It will force to 48kHz if not both.
2676          */
2677         if (rate != CLK_48 && rate != CLK_44) {
2678                 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2679                         __func__, clk_name, CLK_44, CLK_48);
2680                 rate = CLK_48;
2681         }
2682
2683         return rate;
2684 }
2685
2686 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2687                                 unsigned long parent_rate)
2688 {
2689         struct rt5682_priv *rt5682 =
2690                 container_of(hw, struct rt5682_priv,
2691                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2692         struct snd_soc_component *component;
2693         struct clk_hw *parent_hw;
2694         const char * const clk_name = clk_hw_get_name(hw);
2695         int pre_div;
2696         unsigned int clk_pll2_out;
2697
2698         if (!rt5682_clk_check(rt5682))
2699                 return -EINVAL;
2700
2701         component = rt5682->component;
2702
2703         /*
2704          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2705          * it is fixed or set to 48MHz before setting wclk rate. It's a
2706          * temporary limitation. Only accept 48MHz clk as the clk provider.
2707          *
2708          * It will set the codec anyway by assuming mclk is 48MHz.
2709          */
2710         parent_hw = clk_hw_get_parent(hw);
2711         if (!parent_hw)
2712                 dev_warn(rt5682->i2c_dev,
2713                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2714                         CLK_PLL2_FIN);
2715
2716         if (parent_rate != CLK_PLL2_FIN)
2717                 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2718                         clk_name, CLK_PLL2_FIN);
2719
2720         /*
2721          * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2722          * PLL2 is needed.
2723          */
2724         clk_pll2_out = rate * 512;
2725         rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2726                 CLK_PLL2_FIN, clk_pll2_out);
2727
2728         rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2729                 clk_pll2_out, SND_SOC_CLOCK_IN);
2730
2731         rt5682->lrck[RT5682_AIF1] = rate;
2732
2733         pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2734
2735         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2736                 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2737                 pre_div << RT5682_I2S_M_DIV_SFT |
2738                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2739
2740         return 0;
2741 }
2742
2743 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2744                                              unsigned long parent_rate)
2745 {
2746         struct rt5682_priv *rt5682 =
2747                 container_of(hw, struct rt5682_priv,
2748                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2749         unsigned int bclks_per_wclk;
2750
2751         regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
2752
2753         switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2754         case RT5682_TDM_BCLK_MS1_256:
2755                 return parent_rate * 256;
2756         case RT5682_TDM_BCLK_MS1_128:
2757                 return parent_rate * 128;
2758         case RT5682_TDM_BCLK_MS1_64:
2759                 return parent_rate * 64;
2760         case RT5682_TDM_BCLK_MS1_32:
2761                 return parent_rate * 32;
2762         default:
2763                 return 0;
2764         }
2765 }
2766
2767 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2768                                             unsigned long parent_rate)
2769 {
2770         unsigned long factor;
2771
2772         factor = rate / parent_rate;
2773         if (factor < 64)
2774                 return 32;
2775         else if (factor < 128)
2776                 return 64;
2777         else if (factor < 256)
2778                 return 128;
2779         else
2780                 return 256;
2781 }
2782
2783 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2784                                    unsigned long *parent_rate)
2785 {
2786         struct rt5682_priv *rt5682 =
2787                 container_of(hw, struct rt5682_priv,
2788                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2789         unsigned long factor;
2790
2791         if (!*parent_rate || !rt5682_clk_check(rt5682))
2792                 return -EINVAL;
2793
2794         /*
2795          * BCLK rates are set as a multiplier of WCLK in HW.
2796          * We don't allow changing the parent WCLK. We just do
2797          * some rounding down based on the parent WCLK rate
2798          * and find the appropriate multiplier of BCLK to
2799          * get the rounded down BCLK value.
2800          */
2801         factor = rt5682_bclk_get_factor(rate, *parent_rate);
2802
2803         return *parent_rate * factor;
2804 }
2805
2806 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2807                                 unsigned long parent_rate)
2808 {
2809         struct rt5682_priv *rt5682 =
2810                 container_of(hw, struct rt5682_priv,
2811                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2812         struct snd_soc_component *component;
2813         struct snd_soc_dai *dai;
2814         unsigned long factor;
2815
2816         if (!rt5682_clk_check(rt5682))
2817                 return -EINVAL;
2818
2819         component = rt5682->component;
2820
2821         factor = rt5682_bclk_get_factor(rate, parent_rate);
2822
2823         for_each_component_dais(component, dai)
2824                 if (dai->id == RT5682_AIF1)
2825                         break;
2826         if (!dai) {
2827                 dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2828                         RT5682_AIF1);
2829                 return -ENODEV;
2830         }
2831
2832         return rt5682_set_bclk1_ratio(dai, factor);
2833 }
2834
2835 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2836         [RT5682_DAI_WCLK_IDX] = {
2837                 .prepare = rt5682_wclk_prepare,
2838                 .unprepare = rt5682_wclk_unprepare,
2839                 .recalc_rate = rt5682_wclk_recalc_rate,
2840                 .round_rate = rt5682_wclk_round_rate,
2841                 .set_rate = rt5682_wclk_set_rate,
2842         },
2843         [RT5682_DAI_BCLK_IDX] = {
2844                 .recalc_rate = rt5682_bclk_recalc_rate,
2845                 .round_rate = rt5682_bclk_round_rate,
2846                 .set_rate = rt5682_bclk_set_rate,
2847         },
2848 };
2849
2850 int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2851 {
2852         struct device *dev = rt5682->i2c_dev;
2853         struct rt5682_platform_data *pdata = &rt5682->pdata;
2854         struct clk_hw *dai_clk_hw;
2855         int i, ret;
2856
2857         for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2858                 struct clk_init_data init = { };
2859                 const struct clk_hw *parent;
2860
2861                 dai_clk_hw = &rt5682->dai_clks_hw[i];
2862
2863                 switch (i) {
2864                 case RT5682_DAI_WCLK_IDX:
2865                         /* Make MCLK the parent of WCLK */
2866                         if (rt5682->mclk) {
2867                                 parent = __clk_get_hw(rt5682->mclk);
2868                                 init.parent_hws = &parent;
2869                                 init.num_parents = 1;
2870                         }
2871                         break;
2872                 case RT5682_DAI_BCLK_IDX:
2873                         /* Make WCLK the parent of BCLK */
2874                         parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2875                         init.parent_hws = &parent;
2876                         init.num_parents = 1;
2877                         break;
2878                 default:
2879                         dev_err(dev, "Invalid clock index\n");
2880                         return -EINVAL;
2881                 }
2882
2883                 init.name = pdata->dai_clk_names[i];
2884                 init.ops = &rt5682_dai_clk_ops[i];
2885                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2886                 dai_clk_hw->init = &init;
2887
2888                 ret = devm_clk_hw_register(dev, dai_clk_hw);
2889                 if (ret) {
2890                         dev_warn(dev, "Failed to register %s: %d\n",
2891                                  init.name, ret);
2892                         return ret;
2893                 }
2894
2895                 if (dev->of_node) {
2896                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2897                                                     dai_clk_hw);
2898                 } else {
2899                         ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2900                                                           init.name,
2901                                                           dev_name(dev));
2902                         if (ret)
2903                                 return ret;
2904                 }
2905         }
2906
2907         return 0;
2908 }
2909 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2910 #endif /* CONFIG_COMMON_CLK */
2911
2912 static int rt5682_probe(struct snd_soc_component *component)
2913 {
2914         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2915         struct sdw_slave *slave;
2916         unsigned long time;
2917         struct snd_soc_dapm_context *dapm = &component->dapm;
2918
2919         rt5682->component = component;
2920
2921         if (rt5682->is_sdw) {
2922                 slave = rt5682->slave;
2923                 time = wait_for_completion_timeout(
2924                         &slave->initialization_complete,
2925                         msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2926                 if (!time) {
2927                         dev_err(&slave->dev, "Initialization not complete, timed out\n");
2928                         return -ETIMEDOUT;
2929                 }
2930         }
2931
2932         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2933         snd_soc_dapm_disable_pin(dapm, "Vref2");
2934         snd_soc_dapm_sync(dapm);
2935         return 0;
2936 }
2937
2938 static void rt5682_remove(struct snd_soc_component *component)
2939 {
2940         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2941
2942         rt5682_reset(rt5682);
2943 }
2944
2945 #ifdef CONFIG_PM
2946 static int rt5682_suspend(struct snd_soc_component *component)
2947 {
2948         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2949         unsigned int val;
2950
2951         if (rt5682->is_sdw)
2952                 return 0;
2953
2954         cancel_delayed_work_sync(&rt5682->jack_detect_work);
2955         cancel_delayed_work_sync(&rt5682->jd_check_work);
2956         if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2957                 val = snd_soc_component_read(component,
2958                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2959
2960                 switch (val) {
2961                 case 0x1:
2962                         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2963                                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2964                                 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2965                         break;
2966                 case 0x2:
2967                         snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2968                                 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2969                                 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2970                         break;
2971                 default:
2972                         break;
2973                 }
2974
2975                 /* enter SAR ADC power saving mode */
2976                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2977                         RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2978                         RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2979                 usleep_range(5000, 6000);
2980                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2981                         RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2982                         RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
2983                 usleep_range(10000, 12000);
2984                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2985                         RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
2986                         RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
2987                 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
2988                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
2989         }
2990
2991         regcache_cache_only(rt5682->regmap, true);
2992         regcache_mark_dirty(rt5682->regmap);
2993         return 0;
2994 }
2995
2996 static int rt5682_resume(struct snd_soc_component *component)
2997 {
2998         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2999
3000         if (rt5682->is_sdw)
3001                 return 0;
3002
3003         regcache_cache_only(rt5682->regmap, false);
3004         regcache_sync(rt5682->regmap);
3005
3006         if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3007                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3008                         RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3009                         RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3010                 usleep_range(5000, 6000);
3011                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3012                         RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3013                         RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3014                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3015                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3016         }
3017
3018         rt5682->jack_type = 0;
3019         mod_delayed_work(system_power_efficient_wq,
3020                 &rt5682->jack_detect_work, msecs_to_jiffies(0));
3021
3022         return 0;
3023 }
3024 #else
3025 #define rt5682_suspend NULL
3026 #define rt5682_resume NULL
3027 #endif
3028
3029 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3030         .hw_params = rt5682_hw_params,
3031         .set_fmt = rt5682_set_dai_fmt,
3032         .set_tdm_slot = rt5682_set_tdm_slot,
3033         .set_bclk_ratio = rt5682_set_bclk1_ratio,
3034 };
3035 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3036
3037 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3038         .hw_params = rt5682_hw_params,
3039         .set_fmt = rt5682_set_dai_fmt,
3040         .set_bclk_ratio = rt5682_set_bclk2_ratio,
3041 };
3042 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3043
3044 const struct snd_soc_component_driver rt5682_soc_component_dev = {
3045         .probe = rt5682_probe,
3046         .remove = rt5682_remove,
3047         .suspend = rt5682_suspend,
3048         .resume = rt5682_resume,
3049         .set_bias_level = rt5682_set_bias_level,
3050         .controls = rt5682_snd_controls,
3051         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3052         .dapm_widgets = rt5682_dapm_widgets,
3053         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3054         .dapm_routes = rt5682_dapm_routes,
3055         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3056         .set_sysclk = rt5682_set_component_sysclk,
3057         .set_pll = rt5682_set_component_pll,
3058         .set_jack = rt5682_set_jack_detect,
3059         .use_pmdown_time        = 1,
3060         .endianness             = 1,
3061         .non_legacy_dai_naming  = 1,
3062 };
3063 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3064
3065 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3066 {
3067
3068         device_property_read_u32(dev, "realtek,dmic1-data-pin",
3069                 &rt5682->pdata.dmic1_data_pin);
3070         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3071                 &rt5682->pdata.dmic1_clk_pin);
3072         device_property_read_u32(dev, "realtek,jd-src",
3073                 &rt5682->pdata.jd_src);
3074         device_property_read_u32(dev, "realtek,btndet-delay",
3075                 &rt5682->pdata.btndet_delay);
3076         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3077                 &rt5682->pdata.dmic_clk_rate);
3078         device_property_read_u32(dev, "realtek,dmic-delay-ms",
3079                 &rt5682->pdata.dmic_delay);
3080
3081         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3082                 "realtek,ldo1-en-gpios", 0);
3083
3084         if (device_property_read_string_array(dev, "clock-output-names",
3085                                               rt5682->pdata.dai_clk_names,
3086                                               RT5682_DAI_NUM_CLKS) < 0)
3087                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3088                          rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3089                          rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3090
3091         rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3092                 "realtek,dmic-clk-driving-high");
3093
3094         return 0;
3095 }
3096 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3097
3098 void rt5682_calibrate(struct rt5682_priv *rt5682)
3099 {
3100         int value, count;
3101
3102         mutex_lock(&rt5682->calibrate_mutex);
3103
3104         rt5682_reset(rt5682);
3105         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3106         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3107         usleep_range(15000, 20000);
3108         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3109         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3110         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3111         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3112         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3113         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3114         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3115         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3116         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3117         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3118         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3119         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3120         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3121         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3122         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3123
3124         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3125
3126         for (count = 0; count < 60; count++) {
3127                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3128                 if (!(value & 0x8000))
3129                         break;
3130
3131                 usleep_range(10000, 10005);
3132         }
3133
3134         if (count >= 60)
3135                 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3136
3137         /* restore settings */
3138         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3139         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3140         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3141         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3142         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3143         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3144         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3145         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3146
3147         mutex_unlock(&rt5682->calibrate_mutex);
3148 }
3149 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3150
3151 MODULE_DESCRIPTION("ASoC RT5682 driver");
3152 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3153 MODULE_LICENSE("GPL v2");