1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
5 // Copyright 2018 Realtek Semiconductor Corp.
6 // Author: Bard Liao <bardliao@realtek.com>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5682.h>
34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
41 static const struct reg_sequence patch_list[] = {
42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44 {RT5682_I2C_CTRL, 0x000f},
45 {RT5682_PLL2_INTERNAL, 0x8266},
46 {RT5682_SAR_IL_CMD_3, 0x8365},
49 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
53 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
54 ARRAY_SIZE(patch_list));
56 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
58 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
60 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
380 EXPORT_SYMBOL_GPL(rt5682_reg);
382 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
386 case RT5682_CBJ_CTRL_2:
387 case RT5682_INT_ST_1:
388 case RT5682_4BTN_IL_CMD_1:
389 case RT5682_AJD1_CTRL:
390 case RT5682_HP_CALIB_CTRL_1:
391 case RT5682_DEVICE_ID:
392 case RT5682_I2C_MODE:
393 case RT5682_HP_CALIB_CTRL_10:
394 case RT5682_EFUSE_CTRL_2:
395 case RT5682_JD_TOP_VC_VTRL:
396 case RT5682_HP_IMP_SENS_CTRL_19:
397 case RT5682_IL_CMD_1:
398 case RT5682_SAR_IL_CMD_2:
399 case RT5682_SAR_IL_CMD_4:
400 case RT5682_SAR_IL_CMD_10:
401 case RT5682_SAR_IL_CMD_11:
402 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
403 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
409 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
411 bool rt5682_readable_register(struct device *dev, unsigned int reg)
415 case RT5682_VERSION_ID:
416 case RT5682_VENDOR_ID:
417 case RT5682_DEVICE_ID:
418 case RT5682_HP_CTRL_1:
419 case RT5682_HP_CTRL_2:
420 case RT5682_HPL_GAIN:
421 case RT5682_HPR_GAIN:
422 case RT5682_I2C_CTRL:
423 case RT5682_CBJ_BST_CTRL:
424 case RT5682_CBJ_CTRL_1:
425 case RT5682_CBJ_CTRL_2:
426 case RT5682_CBJ_CTRL_3:
427 case RT5682_CBJ_CTRL_4:
428 case RT5682_CBJ_CTRL_5:
429 case RT5682_CBJ_CTRL_6:
430 case RT5682_CBJ_CTRL_7:
431 case RT5682_DAC1_DIG_VOL:
432 case RT5682_STO1_ADC_DIG_VOL:
433 case RT5682_STO1_ADC_BOOST:
434 case RT5682_HP_IMP_GAIN_1:
435 case RT5682_HP_IMP_GAIN_2:
436 case RT5682_SIDETONE_CTRL:
437 case RT5682_STO1_ADC_MIXER:
438 case RT5682_AD_DA_MIXER:
439 case RT5682_STO1_DAC_MIXER:
440 case RT5682_A_DAC1_MUX:
441 case RT5682_DIG_INF2_DATA:
442 case RT5682_REC_MIXER:
444 case RT5682_ALC_BACK_GAIN:
445 case RT5682_PWR_DIG_1:
446 case RT5682_PWR_DIG_2:
447 case RT5682_PWR_ANLG_1:
448 case RT5682_PWR_ANLG_2:
449 case RT5682_PWR_ANLG_3:
450 case RT5682_PWR_MIXER:
453 case RT5682_RESET_LPF_CTRL:
454 case RT5682_RESET_HPF_CTRL:
455 case RT5682_DMIC_CTRL_1:
456 case RT5682_I2S1_SDP:
457 case RT5682_I2S2_SDP:
458 case RT5682_ADDA_CLK_1:
459 case RT5682_ADDA_CLK_2:
460 case RT5682_I2S1_F_DIV_CTRL_1:
461 case RT5682_I2S1_F_DIV_CTRL_2:
462 case RT5682_TDM_CTRL:
463 case RT5682_TDM_ADDA_CTRL_1:
464 case RT5682_TDM_ADDA_CTRL_2:
465 case RT5682_DATA_SEL_CTRL_1:
466 case RT5682_TDM_TCON_CTRL:
468 case RT5682_PLL_CTRL_1:
469 case RT5682_PLL_CTRL_2:
470 case RT5682_PLL_TRACK_1:
471 case RT5682_PLL_TRACK_2:
472 case RT5682_PLL_TRACK_3:
473 case RT5682_PLL_TRACK_4:
474 case RT5682_PLL_TRACK_5:
475 case RT5682_PLL_TRACK_6:
476 case RT5682_PLL_TRACK_11:
477 case RT5682_SDW_REF_CLK:
480 case RT5682_HP_CHARGE_PUMP_1:
481 case RT5682_HP_CHARGE_PUMP_2:
482 case RT5682_MICBIAS_1:
483 case RT5682_MICBIAS_2:
484 case RT5682_PLL_TRACK_12:
485 case RT5682_PLL_TRACK_14:
486 case RT5682_PLL2_CTRL_1:
487 case RT5682_PLL2_CTRL_2:
488 case RT5682_PLL2_CTRL_3:
489 case RT5682_PLL2_CTRL_4:
490 case RT5682_RC_CLK_CTRL:
491 case RT5682_I2S_M_CLK_CTRL_1:
492 case RT5682_I2S2_F_DIV_CTRL_1:
493 case RT5682_I2S2_F_DIV_CTRL_2:
494 case RT5682_EQ_CTRL_1:
495 case RT5682_EQ_CTRL_2:
496 case RT5682_IRQ_CTRL_1:
497 case RT5682_IRQ_CTRL_2:
498 case RT5682_IRQ_CTRL_3:
499 case RT5682_IRQ_CTRL_4:
500 case RT5682_INT_ST_1:
501 case RT5682_GPIO_CTRL_1:
502 case RT5682_GPIO_CTRL_2:
503 case RT5682_GPIO_CTRL_3:
504 case RT5682_HP_AMP_DET_CTRL_1:
505 case RT5682_HP_AMP_DET_CTRL_2:
506 case RT5682_MID_HP_AMP_DET:
507 case RT5682_LOW_HP_AMP_DET:
508 case RT5682_DELAY_BUF_CTRL:
509 case RT5682_SV_ZCD_1:
510 case RT5682_SV_ZCD_2:
511 case RT5682_IL_CMD_1:
512 case RT5682_IL_CMD_2:
513 case RT5682_IL_CMD_3:
514 case RT5682_IL_CMD_4:
515 case RT5682_IL_CMD_5:
516 case RT5682_IL_CMD_6:
517 case RT5682_4BTN_IL_CMD_1:
518 case RT5682_4BTN_IL_CMD_2:
519 case RT5682_4BTN_IL_CMD_3:
520 case RT5682_4BTN_IL_CMD_4:
521 case RT5682_4BTN_IL_CMD_5:
522 case RT5682_4BTN_IL_CMD_6:
523 case RT5682_4BTN_IL_CMD_7:
524 case RT5682_ADC_STO1_HP_CTRL_1:
525 case RT5682_ADC_STO1_HP_CTRL_2:
526 case RT5682_AJD1_CTRL:
529 case RT5682_JD_CTRL_1:
533 case RT5682_DAC_ADC_DIG_VOL1:
534 case RT5682_BIAS_CUR_CTRL_2:
535 case RT5682_BIAS_CUR_CTRL_3:
536 case RT5682_BIAS_CUR_CTRL_4:
537 case RT5682_BIAS_CUR_CTRL_5:
538 case RT5682_BIAS_CUR_CTRL_6:
539 case RT5682_BIAS_CUR_CTRL_7:
540 case RT5682_BIAS_CUR_CTRL_8:
541 case RT5682_BIAS_CUR_CTRL_9:
542 case RT5682_BIAS_CUR_CTRL_10:
543 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
544 case RT5682_CHARGE_PUMP_1:
545 case RT5682_DIG_IN_CTRL_1:
546 case RT5682_PAD_DRIVING_CTRL:
547 case RT5682_SOFT_RAMP_DEPOP:
548 case RT5682_CHOP_DAC:
549 case RT5682_CHOP_ADC:
550 case RT5682_CALIB_ADC_CTRL:
551 case RT5682_VOL_TEST:
552 case RT5682_SPKVDD_DET_STA:
553 case RT5682_TEST_MODE_CTRL_1:
554 case RT5682_TEST_MODE_CTRL_2:
555 case RT5682_TEST_MODE_CTRL_3:
556 case RT5682_TEST_MODE_CTRL_4:
557 case RT5682_TEST_MODE_CTRL_5:
558 case RT5682_PLL1_INTERNAL:
559 case RT5682_PLL2_INTERNAL:
560 case RT5682_STO_NG2_CTRL_1:
561 case RT5682_STO_NG2_CTRL_2:
562 case RT5682_STO_NG2_CTRL_3:
563 case RT5682_STO_NG2_CTRL_4:
564 case RT5682_STO_NG2_CTRL_5:
565 case RT5682_STO_NG2_CTRL_6:
566 case RT5682_STO_NG2_CTRL_7:
567 case RT5682_STO_NG2_CTRL_8:
568 case RT5682_STO_NG2_CTRL_9:
569 case RT5682_STO_NG2_CTRL_10:
570 case RT5682_STO1_DAC_SIL_DET:
571 case RT5682_SIL_PSV_CTRL1:
572 case RT5682_SIL_PSV_CTRL2:
573 case RT5682_SIL_PSV_CTRL3:
574 case RT5682_SIL_PSV_CTRL4:
575 case RT5682_SIL_PSV_CTRL5:
576 case RT5682_HP_IMP_SENS_CTRL_01:
577 case RT5682_HP_IMP_SENS_CTRL_02:
578 case RT5682_HP_IMP_SENS_CTRL_03:
579 case RT5682_HP_IMP_SENS_CTRL_04:
580 case RT5682_HP_IMP_SENS_CTRL_05:
581 case RT5682_HP_IMP_SENS_CTRL_06:
582 case RT5682_HP_IMP_SENS_CTRL_07:
583 case RT5682_HP_IMP_SENS_CTRL_08:
584 case RT5682_HP_IMP_SENS_CTRL_09:
585 case RT5682_HP_IMP_SENS_CTRL_10:
586 case RT5682_HP_IMP_SENS_CTRL_11:
587 case RT5682_HP_IMP_SENS_CTRL_12:
588 case RT5682_HP_IMP_SENS_CTRL_13:
589 case RT5682_HP_IMP_SENS_CTRL_14:
590 case RT5682_HP_IMP_SENS_CTRL_15:
591 case RT5682_HP_IMP_SENS_CTRL_16:
592 case RT5682_HP_IMP_SENS_CTRL_17:
593 case RT5682_HP_IMP_SENS_CTRL_18:
594 case RT5682_HP_IMP_SENS_CTRL_19:
595 case RT5682_HP_IMP_SENS_CTRL_20:
596 case RT5682_HP_IMP_SENS_CTRL_21:
597 case RT5682_HP_IMP_SENS_CTRL_22:
598 case RT5682_HP_IMP_SENS_CTRL_23:
599 case RT5682_HP_IMP_SENS_CTRL_24:
600 case RT5682_HP_IMP_SENS_CTRL_25:
601 case RT5682_HP_IMP_SENS_CTRL_26:
602 case RT5682_HP_IMP_SENS_CTRL_27:
603 case RT5682_HP_IMP_SENS_CTRL_28:
604 case RT5682_HP_IMP_SENS_CTRL_29:
605 case RT5682_HP_IMP_SENS_CTRL_30:
606 case RT5682_HP_IMP_SENS_CTRL_31:
607 case RT5682_HP_IMP_SENS_CTRL_32:
608 case RT5682_HP_IMP_SENS_CTRL_33:
609 case RT5682_HP_IMP_SENS_CTRL_34:
610 case RT5682_HP_IMP_SENS_CTRL_35:
611 case RT5682_HP_IMP_SENS_CTRL_36:
612 case RT5682_HP_IMP_SENS_CTRL_37:
613 case RT5682_HP_IMP_SENS_CTRL_38:
614 case RT5682_HP_IMP_SENS_CTRL_39:
615 case RT5682_HP_IMP_SENS_CTRL_40:
616 case RT5682_HP_IMP_SENS_CTRL_41:
617 case RT5682_HP_IMP_SENS_CTRL_42:
618 case RT5682_HP_IMP_SENS_CTRL_43:
619 case RT5682_HP_LOGIC_CTRL_1:
620 case RT5682_HP_LOGIC_CTRL_2:
621 case RT5682_HP_LOGIC_CTRL_3:
622 case RT5682_HP_CALIB_CTRL_1:
623 case RT5682_HP_CALIB_CTRL_2:
624 case RT5682_HP_CALIB_CTRL_3:
625 case RT5682_HP_CALIB_CTRL_4:
626 case RT5682_HP_CALIB_CTRL_5:
627 case RT5682_HP_CALIB_CTRL_6:
628 case RT5682_HP_CALIB_CTRL_7:
629 case RT5682_HP_CALIB_CTRL_9:
630 case RT5682_HP_CALIB_CTRL_10:
631 case RT5682_HP_CALIB_CTRL_11:
632 case RT5682_HP_CALIB_STA_1:
633 case RT5682_HP_CALIB_STA_2:
634 case RT5682_HP_CALIB_STA_3:
635 case RT5682_HP_CALIB_STA_4:
636 case RT5682_HP_CALIB_STA_5:
637 case RT5682_HP_CALIB_STA_6:
638 case RT5682_HP_CALIB_STA_7:
639 case RT5682_HP_CALIB_STA_8:
640 case RT5682_HP_CALIB_STA_9:
641 case RT5682_HP_CALIB_STA_10:
642 case RT5682_HP_CALIB_STA_11:
643 case RT5682_SAR_IL_CMD_1:
644 case RT5682_SAR_IL_CMD_2:
645 case RT5682_SAR_IL_CMD_3:
646 case RT5682_SAR_IL_CMD_4:
647 case RT5682_SAR_IL_CMD_5:
648 case RT5682_SAR_IL_CMD_6:
649 case RT5682_SAR_IL_CMD_7:
650 case RT5682_SAR_IL_CMD_8:
651 case RT5682_SAR_IL_CMD_9:
652 case RT5682_SAR_IL_CMD_10:
653 case RT5682_SAR_IL_CMD_11:
654 case RT5682_SAR_IL_CMD_12:
655 case RT5682_SAR_IL_CMD_13:
656 case RT5682_EFUSE_CTRL_1:
657 case RT5682_EFUSE_CTRL_2:
658 case RT5682_EFUSE_CTRL_3:
659 case RT5682_EFUSE_CTRL_4:
660 case RT5682_EFUSE_CTRL_5:
661 case RT5682_EFUSE_CTRL_6:
662 case RT5682_EFUSE_CTRL_7:
663 case RT5682_EFUSE_CTRL_8:
664 case RT5682_EFUSE_CTRL_9:
665 case RT5682_EFUSE_CTRL_10:
666 case RT5682_EFUSE_CTRL_11:
667 case RT5682_JD_TOP_VC_VTRL:
668 case RT5682_DRC1_CTRL_0:
669 case RT5682_DRC1_CTRL_1:
670 case RT5682_DRC1_CTRL_2:
671 case RT5682_DRC1_CTRL_3:
672 case RT5682_DRC1_CTRL_4:
673 case RT5682_DRC1_CTRL_5:
674 case RT5682_DRC1_CTRL_6:
675 case RT5682_DRC1_HARD_LMT_CTRL_1:
676 case RT5682_DRC1_HARD_LMT_CTRL_2:
677 case RT5682_DRC1_PRIV_1:
678 case RT5682_DRC1_PRIV_2:
679 case RT5682_DRC1_PRIV_3:
680 case RT5682_DRC1_PRIV_4:
681 case RT5682_DRC1_PRIV_5:
682 case RT5682_DRC1_PRIV_6:
683 case RT5682_DRC1_PRIV_7:
684 case RT5682_DRC1_PRIV_8:
685 case RT5682_EQ_AUTO_RCV_CTRL1:
686 case RT5682_EQ_AUTO_RCV_CTRL2:
687 case RT5682_EQ_AUTO_RCV_CTRL3:
688 case RT5682_EQ_AUTO_RCV_CTRL4:
689 case RT5682_EQ_AUTO_RCV_CTRL5:
690 case RT5682_EQ_AUTO_RCV_CTRL6:
691 case RT5682_EQ_AUTO_RCV_CTRL7:
692 case RT5682_EQ_AUTO_RCV_CTRL8:
693 case RT5682_EQ_AUTO_RCV_CTRL9:
694 case RT5682_EQ_AUTO_RCV_CTRL10:
695 case RT5682_EQ_AUTO_RCV_CTRL11:
696 case RT5682_EQ_AUTO_RCV_CTRL12:
697 case RT5682_EQ_AUTO_RCV_CTRL13:
698 case RT5682_ADC_L_EQ_LPF1_A1:
699 case RT5682_R_EQ_LPF1_A1:
700 case RT5682_L_EQ_LPF1_H0:
701 case RT5682_R_EQ_LPF1_H0:
702 case RT5682_L_EQ_BPF1_A1:
703 case RT5682_R_EQ_BPF1_A1:
704 case RT5682_L_EQ_BPF1_A2:
705 case RT5682_R_EQ_BPF1_A2:
706 case RT5682_L_EQ_BPF1_H0:
707 case RT5682_R_EQ_BPF1_H0:
708 case RT5682_L_EQ_BPF2_A1:
709 case RT5682_R_EQ_BPF2_A1:
710 case RT5682_L_EQ_BPF2_A2:
711 case RT5682_R_EQ_BPF2_A2:
712 case RT5682_L_EQ_BPF2_H0:
713 case RT5682_R_EQ_BPF2_H0:
714 case RT5682_L_EQ_BPF3_A1:
715 case RT5682_R_EQ_BPF3_A1:
716 case RT5682_L_EQ_BPF3_A2:
717 case RT5682_R_EQ_BPF3_A2:
718 case RT5682_L_EQ_BPF3_H0:
719 case RT5682_R_EQ_BPF3_H0:
720 case RT5682_L_EQ_BPF4_A1:
721 case RT5682_R_EQ_BPF4_A1:
722 case RT5682_L_EQ_BPF4_A2:
723 case RT5682_R_EQ_BPF4_A2:
724 case RT5682_L_EQ_BPF4_H0:
725 case RT5682_R_EQ_BPF4_H0:
726 case RT5682_L_EQ_HPF1_A1:
727 case RT5682_R_EQ_HPF1_A1:
728 case RT5682_L_EQ_HPF1_H0:
729 case RT5682_R_EQ_HPF1_H0:
730 case RT5682_L_EQ_PRE_VOL:
731 case RT5682_R_EQ_PRE_VOL:
732 case RT5682_L_EQ_POST_VOL:
733 case RT5682_R_EQ_POST_VOL:
734 case RT5682_I2C_MODE:
740 EXPORT_SYMBOL_GPL(rt5682_readable_register);
742 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
743 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
744 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
746 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
747 static const DECLARE_TLV_DB_RANGE(bst_tlv,
748 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
749 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
750 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
751 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
752 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
753 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
754 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
757 /* Interface data select */
758 static const char * const rt5682_data_select[] = {
759 "L/R", "R/L", "L/L", "R/R"
762 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
763 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
765 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
766 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
768 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
769 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
772 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
777 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
778 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
780 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
781 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
783 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
784 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
786 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
787 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
789 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
790 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
792 static const char * const rt5682_dac_select[] = {
796 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
797 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
799 static const struct snd_kcontrol_new rt5682_dac_l_mux =
800 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
802 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
803 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
805 static const struct snd_kcontrol_new rt5682_dac_r_mux =
806 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
808 void rt5682_reset(struct rt5682_priv *rt5682)
810 regmap_write(rt5682->regmap, RT5682_RESET, 0);
812 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
814 EXPORT_SYMBOL_GPL(rt5682_reset);
817 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
818 * @component: SoC audio component device.
819 * @filter_mask: mask of filters.
820 * @clk_src: clock source
822 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
823 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
824 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
825 * ASRC function will track i2s clock and generate a corresponding system clock
826 * for codec. This function provides an API to select the clock source for a
827 * set of filters specified by the mask. And the component driver will turn on
828 * ASRC for these filters if ASRC is selected as their clock source.
830 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
831 unsigned int filter_mask, unsigned int clk_src)
834 case RT5682_CLK_SEL_SYS:
835 case RT5682_CLK_SEL_I2S1_ASRC:
836 case RT5682_CLK_SEL_I2S2_ASRC:
843 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
844 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
845 RT5682_FILTER_CLK_SEL_MASK,
846 clk_src << RT5682_FILTER_CLK_SEL_SFT);
849 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
850 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
851 RT5682_FILTER_CLK_SEL_MASK,
852 clk_src << RT5682_FILTER_CLK_SEL_SFT);
857 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
859 static int rt5682_button_detect(struct snd_soc_component *component)
863 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
864 btn_type = val & 0xfff0;
865 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
866 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
867 snd_soc_component_update_bits(component,
868 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
873 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
876 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
879 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
880 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
881 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
882 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
883 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
884 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
885 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
886 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
888 snd_soc_component_update_bits(component,
890 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
891 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
893 snd_soc_component_update_bits(component,
894 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
897 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
898 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
899 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
900 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
901 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
902 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
903 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
904 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
905 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
906 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
911 * rt5682_headset_detect - Detect headset.
912 * @component: SoC audio component device.
913 * @jack_insert: Jack insert or not.
915 * Detect whether is headset or not when jack inserted.
917 * Returns detect status.
919 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
921 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
922 struct snd_soc_dapm_context *dapm = &component->dapm;
923 unsigned int val, count;
926 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
927 RT5682_PWR_VREF2 | RT5682_PWR_MB,
928 RT5682_PWR_VREF2 | RT5682_PWR_MB);
929 snd_soc_component_update_bits(component,
930 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
931 usleep_range(15000, 20000);
932 snd_soc_component_update_bits(component,
933 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
934 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
935 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
936 snd_soc_component_update_bits(component,
937 RT5682_HP_CHARGE_PUMP_1,
938 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
943 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
944 & RT5682_JACK_TYPE_MASK;
945 while (val == 0 && count < 50) {
946 usleep_range(10000, 15000);
947 val = snd_soc_component_read(component,
948 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
955 rt5682->jack_type = SND_JACK_HEADSET;
956 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
957 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
958 rt5682_enable_push_button_irq(component, true);
961 rt5682->jack_type = SND_JACK_HEADPHONE;
965 snd_soc_component_update_bits(component,
966 RT5682_HP_CHARGE_PUMP_1,
967 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
968 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
969 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
970 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
971 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
973 rt5682_enable_push_button_irq(component, false);
974 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
975 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
976 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
977 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
978 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
979 snd_soc_component_update_bits(component,
980 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
981 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
982 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
983 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
984 snd_soc_component_update_bits(component,
985 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
986 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
988 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
989 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
990 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
991 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
992 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
994 rt5682->jack_type = 0;
997 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
998 return rt5682->jack_type;
1000 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
1002 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1003 struct snd_soc_jack *hs_jack, void *data)
1005 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1007 rt5682->hs_jack = hs_jack;
1010 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1011 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1012 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1013 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1014 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1019 if (!rt5682->is_sdw) {
1020 switch (rt5682->pdata.jd_src) {
1022 snd_soc_component_update_bits(component,
1023 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1024 snd_soc_component_update_bits(component,
1025 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1026 RT5682_EXT_JD_SRC_MANUAL);
1027 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1029 snd_soc_component_update_bits(component,
1030 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1031 RT5682_CBJ_IN_BUF_EN);
1032 snd_soc_component_update_bits(component,
1033 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1035 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1036 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1037 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1038 RT5682_POW_IRQ | RT5682_POW_JDH |
1039 RT5682_POW_ANA, RT5682_POW_IRQ |
1040 RT5682_POW_JDH | RT5682_POW_ANA);
1041 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1042 RT5682_PWR_JDH, RT5682_PWR_JDH);
1043 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1044 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1045 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1046 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1047 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1048 rt5682->pdata.btndet_delay));
1049 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1050 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1051 rt5682->pdata.btndet_delay));
1052 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1053 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1054 rt5682->pdata.btndet_delay));
1055 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1056 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1057 rt5682->pdata.btndet_delay));
1058 mod_delayed_work(system_power_efficient_wq,
1059 &rt5682->jack_detect_work,
1060 msecs_to_jiffies(250));
1063 case RT5682_JD_NULL:
1064 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1065 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1066 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1067 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1071 dev_warn(component->dev, "Wrong JD source\n");
1079 void rt5682_jack_detect_handler(struct work_struct *work)
1081 struct rt5682_priv *rt5682 =
1082 container_of(work, struct rt5682_priv, jack_detect_work.work);
1085 while (!rt5682->component)
1086 usleep_range(10000, 15000);
1088 while (!rt5682->component->card->instantiated)
1089 usleep_range(10000, 15000);
1091 mutex_lock(&rt5682->calibrate_mutex);
1093 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1094 & RT5682_JDH_RS_MASK;
1097 if (rt5682->jack_type == 0) {
1098 /* jack was out, report jack type */
1100 rt5682_headset_detect(rt5682->component, 1);
1101 rt5682->irq_work_delay_time = 0;
1102 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1104 /* jack is already in, report button event */
1105 rt5682->jack_type = SND_JACK_HEADSET;
1106 btn_type = rt5682_button_detect(rt5682->component);
1108 * rt5682 can report three kinds of button behavior,
1109 * one click, double click and hold. However,
1110 * currently we will report button pressed/released
1111 * event. So all the three button behaviors are
1112 * treated as button pressed.
1118 rt5682->jack_type |= SND_JACK_BTN_0;
1123 rt5682->jack_type |= SND_JACK_BTN_1;
1128 rt5682->jack_type |= SND_JACK_BTN_2;
1133 rt5682->jack_type |= SND_JACK_BTN_3;
1135 case 0x0000: /* unpressed */
1138 dev_err(rt5682->component->dev,
1139 "Unexpected button code 0x%04x\n",
1146 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1147 rt5682->irq_work_delay_time = 50;
1150 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1152 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1153 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1155 if (!rt5682->is_sdw) {
1156 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1157 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1158 schedule_delayed_work(&rt5682->jd_check_work, 0);
1160 cancel_delayed_work_sync(&rt5682->jd_check_work);
1163 mutex_unlock(&rt5682->calibrate_mutex);
1165 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1167 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1168 /* DAC Digital Volume */
1169 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1170 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1172 /* IN Boost Volume */
1173 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1174 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1176 /* ADC Digital Volume Control */
1177 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1178 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1179 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1180 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1182 /* ADC Boost Volume Control */
1183 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1184 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1188 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1189 int target, const int div[], int size)
1193 if (rt5682->sysclk < target) {
1194 dev_err(rt5682->component->dev,
1195 "sysclk rate %d is too low\n", rt5682->sysclk);
1199 for (i = 0; i < size - 1; i++) {
1200 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1201 if (target * div[i] == rt5682->sysclk)
1203 if (target * div[i + 1] > rt5682->sysclk) {
1204 dev_dbg(rt5682->component->dev,
1205 "can't find div for sysclk %d\n",
1211 if (target * div[i] < rt5682->sysclk)
1212 dev_err(rt5682->component->dev,
1213 "sysclk rate %d is too high\n", rt5682->sysclk);
1219 * set_dmic_clk - Set parameter of dmic.
1222 * @kcontrol: The kcontrol of this widget.
1225 * Choose dmic clock between 1MHz and 3MHz.
1226 * It is better for clock to approximate 3MHz.
1228 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1229 struct snd_kcontrol *kcontrol, int event)
1231 struct snd_soc_component *component =
1232 snd_soc_dapm_to_component(w->dapm);
1233 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1234 int idx, dmic_clk_rate = 3072000;
1235 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1237 if (rt5682->pdata.dmic_clk_rate)
1238 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1240 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1242 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1243 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1248 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1249 struct snd_kcontrol *kcontrol, int event)
1251 struct snd_soc_component *component =
1252 snd_soc_dapm_to_component(w->dapm);
1253 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1254 int ref, val, reg, idx;
1255 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1256 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1261 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1262 RT5682_GP4_PIN_MASK;
1263 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1264 val == RT5682_GP4_PIN_ADCDAT2)
1265 ref = 256 * rt5682->lrck[RT5682_AIF2];
1267 ref = 256 * rt5682->lrck[RT5682_AIF1];
1269 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1271 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1272 reg = RT5682_PLL_TRACK_3;
1274 reg = RT5682_PLL_TRACK_2;
1276 snd_soc_component_update_bits(component, reg,
1277 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1279 /* select over sample rate */
1280 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1281 if (rt5682->sysclk <= 12288000 * div_o[idx])
1285 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1286 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1287 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1292 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1293 struct snd_soc_dapm_widget *sink)
1296 struct snd_soc_component *component =
1297 snd_soc_dapm_to_component(w->dapm);
1299 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1300 val &= RT5682_SCLK_SRC_MASK;
1301 if (val == RT5682_SCLK_SRC_PLL1)
1307 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1308 struct snd_soc_dapm_widget *sink)
1311 struct snd_soc_component *component =
1312 snd_soc_dapm_to_component(w->dapm);
1314 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1315 val &= RT5682_SCLK_SRC_MASK;
1316 if (val == RT5682_SCLK_SRC_PLL2)
1322 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1323 struct snd_soc_dapm_widget *sink)
1325 unsigned int reg, shift, val;
1326 struct snd_soc_component *component =
1327 snd_soc_dapm_to_component(w->dapm);
1330 case RT5682_ADC_STO1_ASRC_SFT:
1331 reg = RT5682_PLL_TRACK_3;
1332 shift = RT5682_FILTER_CLK_SEL_SFT;
1334 case RT5682_DAC_STO1_ASRC_SFT:
1335 reg = RT5682_PLL_TRACK_2;
1336 shift = RT5682_FILTER_CLK_SEL_SFT;
1342 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1344 case RT5682_CLK_SEL_I2S1_ASRC:
1345 case RT5682_CLK_SEL_I2S2_ASRC:
1353 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1354 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1355 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1356 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1357 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1360 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1361 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1362 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1363 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1364 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1367 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1368 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1369 RT5682_M_ADCMIX_L_SFT, 1, 1),
1370 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1371 RT5682_M_DAC1_L_SFT, 1, 1),
1374 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1375 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1376 RT5682_M_ADCMIX_R_SFT, 1, 1),
1377 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1378 RT5682_M_DAC1_R_SFT, 1, 1),
1381 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1382 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1383 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1384 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1385 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1388 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1389 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1390 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1391 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1392 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1395 /* Analog Input Mixer */
1396 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1397 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1398 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1401 /* STO1 ADC1 Source */
1402 /* MX-26 [13] [5] */
1403 static const char * const rt5682_sto1_adc1_src[] = {
1407 static SOC_ENUM_SINGLE_DECL(
1408 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1409 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1411 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1412 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1414 static SOC_ENUM_SINGLE_DECL(
1415 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1416 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1418 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1419 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1421 /* STO1 ADC Source */
1422 /* MX-26 [11:10] [3:2] */
1423 static const char * const rt5682_sto1_adc_src[] = {
1427 static SOC_ENUM_SINGLE_DECL(
1428 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1429 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1431 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1432 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1434 static SOC_ENUM_SINGLE_DECL(
1435 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1436 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1438 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1439 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1441 /* STO1 ADC2 Source */
1442 /* MX-26 [12] [4] */
1443 static const char * const rt5682_sto1_adc2_src[] = {
1447 static SOC_ENUM_SINGLE_DECL(
1448 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1449 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1451 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1452 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1454 static SOC_ENUM_SINGLE_DECL(
1455 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1456 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1458 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1459 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1461 /* MX-79 [6:4] I2S1 ADC data location */
1462 static const unsigned int rt5682_if1_adc_slot_values[] = {
1469 static const char * const rt5682_if1_adc_slot_src[] = {
1470 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1473 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1474 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1475 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1477 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1478 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1480 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1481 /* MX-2B [4], MX-2B [0]*/
1482 static const char * const rt5682_alg_dac1_src[] = {
1483 "Stereo1 DAC Mixer", "DAC1"
1486 static SOC_ENUM_SINGLE_DECL(
1487 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1488 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1490 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1491 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1493 static SOC_ENUM_SINGLE_DECL(
1494 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1495 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1497 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1498 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1501 static const struct snd_kcontrol_new hpol_switch =
1502 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1503 RT5682_L_MUTE_SFT, 1, 1);
1504 static const struct snd_kcontrol_new hpor_switch =
1505 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1506 RT5682_R_MUTE_SFT, 1, 1);
1508 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1509 struct snd_kcontrol *kcontrol, int event)
1511 struct snd_soc_component *component =
1512 snd_soc_dapm_to_component(w->dapm);
1515 case SND_SOC_DAPM_PRE_PMU:
1516 snd_soc_component_write(component,
1517 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1518 snd_soc_component_write(component,
1519 RT5682_HP_CTRL_2, 0x6000);
1520 snd_soc_component_update_bits(component,
1521 RT5682_DEPOP_1, 0x60, 0x60);
1522 snd_soc_component_update_bits(component,
1523 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1526 case SND_SOC_DAPM_POST_PMD:
1527 snd_soc_component_update_bits(component,
1528 RT5682_DEPOP_1, 0x60, 0x0);
1529 snd_soc_component_write(component,
1530 RT5682_HP_CTRL_2, 0x0000);
1531 snd_soc_component_update_bits(component,
1532 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1539 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1540 struct snd_kcontrol *kcontrol, int event)
1542 struct snd_soc_component *component =
1543 snd_soc_dapm_to_component(w->dapm);
1544 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1545 unsigned int delay = 50, val;
1547 if (rt5682->pdata.dmic_delay)
1548 delay = rt5682->pdata.dmic_delay;
1551 case SND_SOC_DAPM_POST_PMU:
1552 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1553 val &= RT5682_SCLK_SRC_MASK;
1554 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1555 snd_soc_component_update_bits(component,
1557 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1558 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1560 /*Add delay to avoid pop noise*/
1564 case SND_SOC_DAPM_POST_PMD:
1565 if (!rt5682->jack_type) {
1566 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1567 snd_soc_component_update_bits(component,
1568 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1569 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1570 snd_soc_component_update_bits(component,
1571 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1579 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1580 struct snd_kcontrol *kcontrol, int event)
1582 struct snd_soc_component *component =
1583 snd_soc_dapm_to_component(w->dapm);
1586 case SND_SOC_DAPM_PRE_PMU:
1588 case RT5682_PWR_VREF1_BIT:
1589 snd_soc_component_update_bits(component,
1590 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1593 case RT5682_PWR_VREF2_BIT:
1594 snd_soc_component_update_bits(component,
1595 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1600 case SND_SOC_DAPM_POST_PMU:
1601 usleep_range(15000, 20000);
1603 case RT5682_PWR_VREF1_BIT:
1604 snd_soc_component_update_bits(component,
1605 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1609 case RT5682_PWR_VREF2_BIT:
1610 snd_soc_component_update_bits(component,
1611 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1621 static const unsigned int rt5682_adcdat_pin_values[] = {
1626 static const char * const rt5682_adcdat_pin_select[] = {
1631 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1632 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1633 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1635 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1636 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1638 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1639 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1641 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1643 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1645 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1646 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1647 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1648 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1649 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1650 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1653 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1654 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1655 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1656 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1657 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1658 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1660 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1661 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1662 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1665 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1667 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1671 SND_SOC_DAPM_INPUT("DMIC L1"),
1672 SND_SOC_DAPM_INPUT("DMIC R1"),
1674 SND_SOC_DAPM_INPUT("IN1P"),
1676 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1677 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1678 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1679 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1680 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1683 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1687 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1688 ARRAY_SIZE(rt5682_rec1_l_mix)),
1689 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1690 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1693 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1694 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1696 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1697 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1698 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1699 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1700 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1701 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1704 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1705 &rt5682_sto1_adc1l_mux),
1706 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1707 &rt5682_sto1_adc1r_mux),
1708 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1709 &rt5682_sto1_adc2l_mux),
1710 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1711 &rt5682_sto1_adc2r_mux),
1712 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1713 &rt5682_sto1_adcl_mux),
1714 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1715 &rt5682_sto1_adcr_mux),
1716 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1717 &rt5682_if1_adc_slot_mux),
1720 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1721 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1722 SND_SOC_DAPM_PRE_PMU),
1723 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1724 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1725 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1726 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1727 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1728 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1729 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1733 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1735 /* Digital Interface */
1736 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1738 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1740 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1742 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1743 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1744 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1746 /* Digital Interface Select */
1747 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5682_if1_01_adc_swap_mux),
1749 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5682_if1_23_adc_swap_mux),
1751 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5682_if1_45_adc_swap_mux),
1753 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5682_if1_67_adc_swap_mux),
1755 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5682_if2_adc_swap_mux),
1758 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5682_adcdat_pin_ctrl),
1761 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1763 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1766 /* Audio Interface */
1767 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1768 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1769 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1770 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1771 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1772 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1773 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1776 /* DAC mixer before sound effect */
1777 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1778 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1779 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1780 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1782 /* DAC channel Mux */
1783 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1784 &rt5682_alg_dac_l1_mux),
1785 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1786 &rt5682_alg_dac_r1_mux),
1789 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1790 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1791 SND_SOC_DAPM_PRE_PMU),
1792 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1793 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1794 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1795 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1798 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1799 RT5682_PWR_DAC_L1_BIT, 0),
1800 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1801 RT5682_PWR_DAC_R1_BIT, 0),
1802 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1803 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1806 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1807 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1809 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1810 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1811 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1812 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1813 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1814 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1815 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1816 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1818 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1820 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1824 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1825 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1826 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1827 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1828 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1829 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1830 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1831 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1834 SND_SOC_DAPM_OUTPUT("HPOL"),
1835 SND_SOC_DAPM_OUTPUT("HPOR"),
1838 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1840 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1841 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1842 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1843 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1844 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1845 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1848 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1849 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1850 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1851 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1852 {"ADC STO1 ASRC", NULL, "CLKDET"},
1853 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1854 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1855 {"DAC STO1 ASRC", NULL, "CLKDET"},
1858 {"MICBIAS1", NULL, "Vref1"},
1859 {"MICBIAS2", NULL, "Vref1"},
1861 {"CLKDET SYS", NULL, "CLKDET"},
1863 {"BST1 CBJ", NULL, "IN1P"},
1865 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1866 {"RECMIX1L", NULL, "RECMIX1L Power"},
1868 {"ADC1 L", NULL, "RECMIX1L"},
1869 {"ADC1 L", NULL, "ADC1 L Power"},
1870 {"ADC1 L", NULL, "ADC1 clock"},
1872 {"DMIC L1", NULL, "DMIC CLK"},
1873 {"DMIC L1", NULL, "DMIC1 Power"},
1874 {"DMIC R1", NULL, "DMIC CLK"},
1875 {"DMIC R1", NULL, "DMIC1 Power"},
1876 {"DMIC CLK", NULL, "DMIC ASRC"},
1878 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1879 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1880 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1881 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1883 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1884 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1885 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1886 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1888 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1889 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1890 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1891 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1893 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1894 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1895 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1897 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1898 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1899 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1901 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1903 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1904 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1906 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1907 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1908 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1909 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1910 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1911 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1912 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1913 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1914 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1915 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1916 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1917 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1918 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1919 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1920 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1921 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1923 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1924 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1925 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1926 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1927 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1928 {"AIF1TX", NULL, "I2S1"},
1929 {"AIF1TX", NULL, "ADCDAT Mux"},
1930 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1931 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1932 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1933 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1934 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1935 {"AIF2TX", NULL, "ADCDAT Mux"},
1937 {"SDWTX", NULL, "PLL2B"},
1938 {"SDWTX", NULL, "PLL2F"},
1939 {"SDWTX", NULL, "ADCDAT Mux"},
1941 {"IF1 DAC1 L", NULL, "AIF1RX"},
1942 {"IF1 DAC1 L", NULL, "I2S1"},
1943 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1944 {"IF1 DAC1 R", NULL, "AIF1RX"},
1945 {"IF1 DAC1 R", NULL, "I2S1"},
1946 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1948 {"SOUND DAC L", NULL, "SDWRX"},
1949 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1950 {"SOUND DAC L", NULL, "PLL2B"},
1951 {"SOUND DAC L", NULL, "PLL2F"},
1952 {"SOUND DAC R", NULL, "SDWRX"},
1953 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1954 {"SOUND DAC R", NULL, "PLL2B"},
1955 {"SOUND DAC R", NULL, "PLL2F"},
1957 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1958 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1959 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1960 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1962 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1963 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1964 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1965 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1967 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1968 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1970 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1971 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1973 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1974 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1975 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1976 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1978 {"DAC L1", NULL, "DAC L1 Source"},
1979 {"DAC R1", NULL, "DAC R1 Source"},
1981 {"DAC L1", NULL, "DAC 1 Clock"},
1982 {"DAC R1", NULL, "DAC 1 Clock"},
1984 {"HP Amp", NULL, "DAC L1"},
1985 {"HP Amp", NULL, "DAC R1"},
1986 {"HP Amp", NULL, "HP Amp L"},
1987 {"HP Amp", NULL, "HP Amp R"},
1988 {"HP Amp", NULL, "Capless"},
1989 {"HP Amp", NULL, "Charge Pump"},
1990 {"HP Amp", NULL, "CLKDET SYS"},
1991 {"HP Amp", NULL, "Vref1"},
1992 {"HPOL Playback", "Switch", "HP Amp"},
1993 {"HPOR Playback", "Switch", "HP Amp"},
1994 {"HPOL", NULL, "HPOL Playback"},
1995 {"HPOR", NULL, "HPOR Playback"},
1998 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1999 unsigned int rx_mask, int slots, int slot_width)
2001 struct snd_soc_component *component = dai->component;
2002 unsigned int cl, val = 0;
2004 if (tx_mask || rx_mask)
2005 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2006 RT5682_TDM_EN, RT5682_TDM_EN);
2008 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2013 val |= RT5682_TDM_TX_CH_4;
2014 val |= RT5682_TDM_RX_CH_4;
2017 val |= RT5682_TDM_TX_CH_6;
2018 val |= RT5682_TDM_RX_CH_6;
2021 val |= RT5682_TDM_TX_CH_8;
2022 val |= RT5682_TDM_RX_CH_8;
2030 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2031 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2033 switch (slot_width) {
2035 if (tx_mask || rx_mask)
2037 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2040 val = RT5682_TDM_CL_16;
2041 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2044 val = RT5682_TDM_CL_20;
2045 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2048 val = RT5682_TDM_CL_24;
2049 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2052 val = RT5682_TDM_CL_32;
2053 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2059 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2060 RT5682_TDM_CL_MASK, val);
2061 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2062 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2067 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2068 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2070 struct snd_soc_component *component = dai->component;
2071 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2072 unsigned int len_1 = 0, len_2 = 0;
2073 int pre_div, frame_size;
2075 rt5682->lrck[dai->id] = params_rate(params);
2076 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2078 frame_size = snd_soc_params_to_frame_size(params);
2079 if (frame_size < 0) {
2080 dev_err(component->dev, "Unsupported frame size: %d\n",
2085 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2086 rt5682->lrck[dai->id], pre_div, dai->id);
2088 switch (params_width(params)) {
2092 len_1 |= RT5682_I2S1_DL_20;
2093 len_2 |= RT5682_I2S2_DL_20;
2096 len_1 |= RT5682_I2S1_DL_24;
2097 len_2 |= RT5682_I2S2_DL_24;
2100 len_1 |= RT5682_I2S1_DL_32;
2101 len_2 |= RT5682_I2S2_DL_24;
2104 len_1 |= RT5682_I2S2_DL_8;
2105 len_2 |= RT5682_I2S2_DL_8;
2113 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2114 RT5682_I2S1_DL_MASK, len_1);
2115 if (rt5682->master[RT5682_AIF1]) {
2116 snd_soc_component_update_bits(component,
2117 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2118 RT5682_I2S_CLK_SRC_MASK,
2119 pre_div << RT5682_I2S_M_DIV_SFT |
2120 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2122 if (params_channels(params) == 1) /* mono mode */
2123 snd_soc_component_update_bits(component,
2124 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2125 RT5682_I2S1_MONO_EN);
2127 snd_soc_component_update_bits(component,
2128 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2129 RT5682_I2S1_MONO_DIS);
2132 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2133 RT5682_I2S2_DL_MASK, len_2);
2134 if (rt5682->master[RT5682_AIF2]) {
2135 snd_soc_component_update_bits(component,
2136 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2137 pre_div << RT5682_I2S2_M_PD_SFT);
2139 if (params_channels(params) == 1) /* mono mode */
2140 snd_soc_component_update_bits(component,
2141 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2142 RT5682_I2S2_MONO_EN);
2144 snd_soc_component_update_bits(component,
2145 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2146 RT5682_I2S2_MONO_DIS);
2149 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2156 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2158 struct snd_soc_component *component = dai->component;
2159 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2160 unsigned int reg_val = 0, tdm_ctrl = 0;
2162 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2163 case SND_SOC_DAIFMT_CBM_CFM:
2164 rt5682->master[dai->id] = 1;
2166 case SND_SOC_DAIFMT_CBS_CFS:
2167 rt5682->master[dai->id] = 0;
2173 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2174 case SND_SOC_DAIFMT_NB_NF:
2176 case SND_SOC_DAIFMT_IB_NF:
2177 reg_val |= RT5682_I2S_BP_INV;
2178 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2180 case SND_SOC_DAIFMT_NB_IF:
2181 if (dai->id == RT5682_AIF1)
2182 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2186 case SND_SOC_DAIFMT_IB_IF:
2187 if (dai->id == RT5682_AIF1)
2188 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2189 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2197 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2198 case SND_SOC_DAIFMT_I2S:
2200 case SND_SOC_DAIFMT_LEFT_J:
2201 reg_val |= RT5682_I2S_DF_LEFT;
2202 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2204 case SND_SOC_DAIFMT_DSP_A:
2205 reg_val |= RT5682_I2S_DF_PCM_A;
2206 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2208 case SND_SOC_DAIFMT_DSP_B:
2209 reg_val |= RT5682_I2S_DF_PCM_B;
2210 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2218 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2219 RT5682_I2S_DF_MASK, reg_val);
2220 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2221 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2222 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2223 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2224 tdm_ctrl | rt5682->master[dai->id]);
2227 if (rt5682->master[dai->id] == 0)
2228 reg_val |= RT5682_I2S2_MS_S;
2229 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2230 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2231 RT5682_I2S_DF_MASK, reg_val);
2234 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2240 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2241 int clk_id, int source, unsigned int freq, int dir)
2243 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2244 unsigned int reg_val = 0, src = 0;
2246 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2250 case RT5682_SCLK_S_MCLK:
2251 reg_val |= RT5682_SCLK_SRC_MCLK;
2252 src = RT5682_CLK_SRC_MCLK;
2254 case RT5682_SCLK_S_PLL1:
2255 reg_val |= RT5682_SCLK_SRC_PLL1;
2256 src = RT5682_CLK_SRC_PLL1;
2258 case RT5682_SCLK_S_PLL2:
2259 reg_val |= RT5682_SCLK_SRC_PLL2;
2260 src = RT5682_CLK_SRC_PLL2;
2262 case RT5682_SCLK_S_RCCLK:
2263 reg_val |= RT5682_SCLK_SRC_RCCLK;
2264 src = RT5682_CLK_SRC_RCCLK;
2267 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2270 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2271 RT5682_SCLK_SRC_MASK, reg_val);
2273 if (rt5682->master[RT5682_AIF2]) {
2274 snd_soc_component_update_bits(component,
2275 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2276 src << RT5682_I2S2_SRC_SFT);
2279 rt5682->sysclk = freq;
2280 rt5682->sysclk_src = clk_id;
2282 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2288 static int rt5682_set_component_pll(struct snd_soc_component *component,
2289 int pll_id, int source, unsigned int freq_in,
2290 unsigned int freq_out)
2292 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2293 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2294 unsigned int pll2_fout1, pll2_ps_val;
2297 if (source == rt5682->pll_src[pll_id] &&
2298 freq_in == rt5682->pll_in[pll_id] &&
2299 freq_out == rt5682->pll_out[pll_id])
2302 if (!freq_in || !freq_out) {
2303 dev_dbg(component->dev, "PLL disabled\n");
2305 rt5682->pll_in[pll_id] = 0;
2306 rt5682->pll_out[pll_id] = 0;
2307 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2308 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2312 if (pll_id == RT5682_PLL2) {
2314 case RT5682_PLL2_S_MCLK:
2315 snd_soc_component_update_bits(component,
2316 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2317 RT5682_PLL2_SRC_MCLK);
2320 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2326 * PLL2 concatenates 2 PLL units.
2327 * We suggest the Fout of the front PLL is 3.84MHz.
2329 pll2_fout1 = 3840000;
2330 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2332 dev_err(component->dev, "Unsupport input clock %d\n",
2336 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2337 freq_in, pll2_fout1,
2339 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2340 pll2f_code.n_code, pll2f_code.k_code);
2342 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2344 dev_err(component->dev, "Unsupport input clock %d\n",
2348 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2349 pll2_fout1, freq_out,
2351 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2352 pll2b_code.n_code, pll2b_code.k_code);
2354 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2355 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2356 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2358 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2359 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2361 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2362 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2364 if (freq_out == 22579200)
2365 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2367 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2368 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2369 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2370 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2372 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2373 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2377 case RT5682_PLL1_S_MCLK:
2378 snd_soc_component_update_bits(component,
2379 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2380 RT5682_PLL1_SRC_MCLK);
2382 case RT5682_PLL1_S_BCLK1:
2383 snd_soc_component_update_bits(component,
2384 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2385 RT5682_PLL1_SRC_BCLK1);
2388 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2393 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2395 dev_err(component->dev, "Unsupport input clock %d\n",
2400 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2401 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2402 pll_code.n_code, pll_code.k_code);
2404 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2405 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2406 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2407 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2408 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2411 rt5682->pll_in[pll_id] = freq_in;
2412 rt5682->pll_out[pll_id] = freq_out;
2413 rt5682->pll_src[pll_id] = source;
2418 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2420 struct snd_soc_component *component = dai->component;
2421 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2423 rt5682->bclk[dai->id] = ratio;
2427 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2428 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2431 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2432 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2435 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2436 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2439 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2440 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2443 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2450 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2452 struct snd_soc_component *component = dai->component;
2453 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2455 rt5682->bclk[dai->id] = ratio;
2459 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2460 RT5682_I2S2_BCLK_MS2_MASK,
2461 RT5682_I2S2_BCLK_MS2_64);
2464 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2465 RT5682_I2S2_BCLK_MS2_MASK,
2466 RT5682_I2S2_BCLK_MS2_32);
2469 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2476 static int rt5682_set_bias_level(struct snd_soc_component *component,
2477 enum snd_soc_bias_level level)
2479 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2482 case SND_SOC_BIAS_PREPARE:
2483 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2484 RT5682_PWR_BG, RT5682_PWR_BG);
2485 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2486 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2487 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2490 case SND_SOC_BIAS_STANDBY:
2491 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2492 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2494 case SND_SOC_BIAS_OFF:
2495 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2496 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2497 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2500 case SND_SOC_BIAS_ON:
2507 #ifdef CONFIG_COMMON_CLK
2508 #define CLK_PLL2_FIN 48000000
2509 #define CLK_48 48000
2510 #define CLK_44 44100
2512 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2514 if (!rt5682->master[RT5682_AIF1]) {
2515 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2521 static int rt5682_wclk_prepare(struct clk_hw *hw)
2523 struct rt5682_priv *rt5682 =
2524 container_of(hw, struct rt5682_priv,
2525 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2526 struct snd_soc_component *component = rt5682->component;
2527 struct snd_soc_dapm_context *dapm =
2528 snd_soc_component_get_dapm(component);
2530 if (!rt5682_clk_check(rt5682))
2533 snd_soc_dapm_mutex_lock(dapm);
2535 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2536 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2537 RT5682_PWR_MB, RT5682_PWR_MB);
2539 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2540 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2541 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2543 usleep_range(55000, 60000);
2544 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2545 RT5682_PWR_FV2, RT5682_PWR_FV2);
2547 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2548 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2549 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2550 snd_soc_dapm_sync_unlocked(dapm);
2552 snd_soc_dapm_mutex_unlock(dapm);
2557 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2559 struct rt5682_priv *rt5682 =
2560 container_of(hw, struct rt5682_priv,
2561 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2562 struct snd_soc_component *component = rt5682->component;
2563 struct snd_soc_dapm_context *dapm =
2564 snd_soc_component_get_dapm(component);
2566 if (!rt5682_clk_check(rt5682))
2569 snd_soc_dapm_mutex_lock(dapm);
2571 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2572 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2573 if (!rt5682->jack_type)
2574 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2575 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2578 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2579 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2580 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2581 snd_soc_dapm_sync_unlocked(dapm);
2583 snd_soc_dapm_mutex_unlock(dapm);
2586 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2587 unsigned long parent_rate)
2589 struct rt5682_priv *rt5682 =
2590 container_of(hw, struct rt5682_priv,
2591 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2592 struct snd_soc_component *component = rt5682->component;
2593 const char * const clk_name = clk_hw_get_name(hw);
2595 if (!rt5682_clk_check(rt5682))
2598 * Only accept to set wclk rate to 44.1k or 48kHz.
2600 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2601 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2602 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2603 __func__, clk_name, CLK_44, CLK_48);
2607 return rt5682->lrck[RT5682_AIF1];
2610 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2611 unsigned long *parent_rate)
2613 struct rt5682_priv *rt5682 =
2614 container_of(hw, struct rt5682_priv,
2615 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2616 struct snd_soc_component *component = rt5682->component;
2617 const char * const clk_name = clk_hw_get_name(hw);
2619 if (!rt5682_clk_check(rt5682))
2622 * Only accept to set wclk rate to 44.1k or 48kHz.
2623 * It will force to 48kHz if not both.
2625 if (rate != CLK_48 && rate != CLK_44) {
2626 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2627 __func__, clk_name, CLK_44, CLK_48);
2634 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2635 unsigned long parent_rate)
2637 struct rt5682_priv *rt5682 =
2638 container_of(hw, struct rt5682_priv,
2639 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2640 struct snd_soc_component *component = rt5682->component;
2641 struct clk_hw *parent_hw;
2642 const char * const clk_name = clk_hw_get_name(hw);
2644 unsigned int clk_pll2_out;
2646 if (!rt5682_clk_check(rt5682))
2650 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2651 * it is fixed or set to 48MHz before setting wclk rate. It's a
2652 * temporary limitation. Only accept 48MHz clk as the clk provider.
2654 * It will set the codec anyway by assuming mclk is 48MHz.
2656 parent_hw = clk_hw_get_parent(hw);
2658 dev_warn(component->dev,
2659 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2662 if (parent_rate != CLK_PLL2_FIN)
2663 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2664 clk_name, CLK_PLL2_FIN);
2667 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2670 clk_pll2_out = rate * 512;
2671 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2672 CLK_PLL2_FIN, clk_pll2_out);
2674 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2675 clk_pll2_out, SND_SOC_CLOCK_IN);
2677 rt5682->lrck[RT5682_AIF1] = rate;
2679 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2681 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2682 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2683 pre_div << RT5682_I2S_M_DIV_SFT |
2684 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2689 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2690 unsigned long parent_rate)
2692 struct rt5682_priv *rt5682 =
2693 container_of(hw, struct rt5682_priv,
2694 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2695 struct snd_soc_component *component = rt5682->component;
2696 unsigned int bclks_per_wclk;
2698 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2700 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2701 case RT5682_TDM_BCLK_MS1_256:
2702 return parent_rate * 256;
2703 case RT5682_TDM_BCLK_MS1_128:
2704 return parent_rate * 128;
2705 case RT5682_TDM_BCLK_MS1_64:
2706 return parent_rate * 64;
2707 case RT5682_TDM_BCLK_MS1_32:
2708 return parent_rate * 32;
2714 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2715 unsigned long parent_rate)
2717 unsigned long factor;
2719 factor = rate / parent_rate;
2722 else if (factor < 128)
2724 else if (factor < 256)
2730 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2731 unsigned long *parent_rate)
2733 struct rt5682_priv *rt5682 =
2734 container_of(hw, struct rt5682_priv,
2735 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2736 unsigned long factor;
2738 if (!*parent_rate || !rt5682_clk_check(rt5682))
2742 * BCLK rates are set as a multiplier of WCLK in HW.
2743 * We don't allow changing the parent WCLK. We just do
2744 * some rounding down based on the parent WCLK rate
2745 * and find the appropriate multiplier of BCLK to
2746 * get the rounded down BCLK value.
2748 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2750 return *parent_rate * factor;
2753 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2754 unsigned long parent_rate)
2756 struct rt5682_priv *rt5682 =
2757 container_of(hw, struct rt5682_priv,
2758 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2759 struct snd_soc_component *component = rt5682->component;
2760 struct snd_soc_dai *dai;
2761 unsigned long factor;
2763 if (!rt5682_clk_check(rt5682))
2766 factor = rt5682_bclk_get_factor(rate, parent_rate);
2768 for_each_component_dais(component, dai)
2769 if (dai->id == RT5682_AIF1)
2772 dev_err(component->dev, "dai %d not found in component\n",
2777 return rt5682_set_bclk1_ratio(dai, factor);
2780 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2781 [RT5682_DAI_WCLK_IDX] = {
2782 .prepare = rt5682_wclk_prepare,
2783 .unprepare = rt5682_wclk_unprepare,
2784 .recalc_rate = rt5682_wclk_recalc_rate,
2785 .round_rate = rt5682_wclk_round_rate,
2786 .set_rate = rt5682_wclk_set_rate,
2788 [RT5682_DAI_BCLK_IDX] = {
2789 .recalc_rate = rt5682_bclk_recalc_rate,
2790 .round_rate = rt5682_bclk_round_rate,
2791 .set_rate = rt5682_bclk_set_rate,
2795 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2797 struct device *dev = component->dev;
2798 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2799 struct rt5682_platform_data *pdata = &rt5682->pdata;
2800 struct clk_hw *dai_clk_hw;
2803 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2804 struct clk_init_data init = { };
2806 dai_clk_hw = &rt5682->dai_clks_hw[i];
2809 case RT5682_DAI_WCLK_IDX:
2810 /* Make MCLK the parent of WCLK */
2812 init.parent_data = &(struct clk_parent_data){
2815 init.num_parents = 1;
2818 case RT5682_DAI_BCLK_IDX:
2819 /* Make WCLK the parent of BCLK */
2820 init.parent_hws = &(const struct clk_hw *){
2821 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]
2823 init.num_parents = 1;
2826 dev_err(dev, "Invalid clock index\n");
2830 init.name = pdata->dai_clk_names[i];
2831 init.ops = &rt5682_dai_clk_ops[i];
2832 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2833 dai_clk_hw->init = &init;
2835 ret = devm_clk_hw_register(dev, dai_clk_hw);
2837 dev_warn(dev, "Failed to register %s: %d\n",
2843 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2846 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2856 #endif /* CONFIG_COMMON_CLK */
2858 static int rt5682_probe(struct snd_soc_component *component)
2860 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2861 struct sdw_slave *slave;
2863 struct snd_soc_dapm_context *dapm = &component->dapm;
2865 #ifdef CONFIG_COMMON_CLK
2868 rt5682->component = component;
2870 if (rt5682->is_sdw) {
2871 slave = rt5682->slave;
2872 time = wait_for_completion_timeout(
2873 &slave->initialization_complete,
2874 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2876 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2880 #ifdef CONFIG_COMMON_CLK
2881 /* Check if MCLK provided */
2882 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2883 if (IS_ERR(rt5682->mclk)) {
2884 if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2885 ret = PTR_ERR(rt5682->mclk);
2888 rt5682->mclk = NULL;
2891 /* Register CCF DAI clock control */
2892 ret = rt5682_register_dai_clks(component);
2896 /* Initial setup for CCF */
2897 rt5682->lrck[RT5682_AIF1] = CLK_48;
2901 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2902 snd_soc_dapm_disable_pin(dapm, "Vref2");
2903 snd_soc_dapm_sync(dapm);
2907 static void rt5682_remove(struct snd_soc_component *component)
2909 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2911 rt5682_reset(rt5682);
2915 static int rt5682_suspend(struct snd_soc_component *component)
2917 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2922 regcache_cache_only(rt5682->regmap, true);
2923 regcache_mark_dirty(rt5682->regmap);
2927 static int rt5682_resume(struct snd_soc_component *component)
2929 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2934 regcache_cache_only(rt5682->regmap, false);
2935 regcache_sync(rt5682->regmap);
2937 mod_delayed_work(system_power_efficient_wq,
2938 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2943 #define rt5682_suspend NULL
2944 #define rt5682_resume NULL
2947 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2948 .hw_params = rt5682_hw_params,
2949 .set_fmt = rt5682_set_dai_fmt,
2950 .set_tdm_slot = rt5682_set_tdm_slot,
2951 .set_bclk_ratio = rt5682_set_bclk1_ratio,
2953 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2955 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2956 .hw_params = rt5682_hw_params,
2957 .set_fmt = rt5682_set_dai_fmt,
2958 .set_bclk_ratio = rt5682_set_bclk2_ratio,
2960 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2962 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2963 .probe = rt5682_probe,
2964 .remove = rt5682_remove,
2965 .suspend = rt5682_suspend,
2966 .resume = rt5682_resume,
2967 .set_bias_level = rt5682_set_bias_level,
2968 .controls = rt5682_snd_controls,
2969 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2970 .dapm_widgets = rt5682_dapm_widgets,
2971 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2972 .dapm_routes = rt5682_dapm_routes,
2973 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2974 .set_sysclk = rt5682_set_component_sysclk,
2975 .set_pll = rt5682_set_component_pll,
2976 .set_jack = rt5682_set_jack_detect,
2977 .use_pmdown_time = 1,
2979 .non_legacy_dai_naming = 1,
2981 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2983 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2986 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2987 &rt5682->pdata.dmic1_data_pin);
2988 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2989 &rt5682->pdata.dmic1_clk_pin);
2990 device_property_read_u32(dev, "realtek,jd-src",
2991 &rt5682->pdata.jd_src);
2992 device_property_read_u32(dev, "realtek,btndet-delay",
2993 &rt5682->pdata.btndet_delay);
2994 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2995 &rt5682->pdata.dmic_clk_rate);
2996 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2997 &rt5682->pdata.dmic_delay);
2999 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3000 "realtek,ldo1-en-gpios", 0);
3002 if (device_property_read_string_array(dev, "clock-output-names",
3003 rt5682->pdata.dai_clk_names,
3004 RT5682_DAI_NUM_CLKS) < 0)
3005 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3006 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3007 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3009 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3010 "realtek,dmic-clk-driving-high");
3014 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3016 void rt5682_calibrate(struct rt5682_priv *rt5682)
3020 mutex_lock(&rt5682->calibrate_mutex);
3022 rt5682_reset(rt5682);
3023 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3024 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3025 usleep_range(15000, 20000);
3026 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3027 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3028 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3029 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3030 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3031 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3032 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3033 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3034 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3035 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3036 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3037 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3038 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3039 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3040 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3042 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3044 for (count = 0; count < 60; count++) {
3045 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3046 if (!(value & 0x8000))
3049 usleep_range(10000, 10005);
3053 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3055 /* restore settings */
3056 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3057 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3058 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3059 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3060 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3061 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3062 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3063 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3065 mutex_unlock(&rt5682->calibrate_mutex);
3067 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3069 MODULE_DESCRIPTION("ASoC RT5682 driver");
3070 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3071 MODULE_LICENSE("GPL v2");
projects / linux-2.6-microblaze.git / blob