sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2018 Realtek Semiconductor Corp.
   6 // Author: Bard Liao <bardliao@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/mutex.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/rt5682.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5682.h"
  33
  34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  35         "AVDD",
  36         "MICVDD",
  37         "VBAT",
  38 };
  39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
  40
  41 static const struct reg_sequence patch_list[] = {
  42         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  43         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  44         {RT5682_I2C_CTRL, 0x000f},
  45         {RT5682_PLL2_INTERNAL, 0x8266},
  46         {RT5682_SAR_IL_CMD_3, 0x8365},
  47         {RT5682_SAR_IL_CMD_6, 0x0180},
  48 };
  49
  50 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  51 {
  52         int ret;
  53
  54         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  55                                      ARRAY_SIZE(patch_list));
  56         if (ret)
  57                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  58 }
  59 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  60
  61 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  62         {0x0002, 0x8080},
  63         {0x0003, 0x8000},
  64         {0x0005, 0x0000},
  65         {0x0006, 0x0000},
  66         {0x0008, 0x800f},
  67         {0x000b, 0x0000},
  68         {0x0010, 0x4040},
  69         {0x0011, 0x0000},
  70         {0x0012, 0x1404},
  71         {0x0013, 0x1000},
  72         {0x0014, 0xa00a},
  73         {0x0015, 0x0404},
  74         {0x0016, 0x0404},
  75         {0x0019, 0xafaf},
  76         {0x001c, 0x2f2f},
  77         {0x001f, 0x0000},
  78         {0x0022, 0x5757},
  79         {0x0023, 0x0039},
  80         {0x0024, 0x000b},
  81         {0x0026, 0xc0c4},
  82         {0x0029, 0x8080},
  83         {0x002a, 0xa0a0},
  84         {0x002b, 0x0300},
  85         {0x0030, 0x0000},
  86         {0x003c, 0x0080},
  87         {0x0044, 0x0c0c},
  88         {0x0049, 0x0000},
  89         {0x0061, 0x0000},
  90         {0x0062, 0x0000},
  91         {0x0063, 0x003f},
  92         {0x0064, 0x0000},
  93         {0x0065, 0x0000},
  94         {0x0066, 0x0030},
  95         {0x0067, 0x0000},
  96         {0x006b, 0x0000},
  97         {0x006c, 0x0000},
  98         {0x006d, 0x2200},
  99         {0x006e, 0x0a10},
 100         {0x0070, 0x8000},
 101         {0x0071, 0x8000},
 102         {0x0073, 0x0000},
 103         {0x0074, 0x0000},
 104         {0x0075, 0x0002},
 105         {0x0076, 0x0001},
 106         {0x0079, 0x0000},
 107         {0x007a, 0x0000},
 108         {0x007b, 0x0000},
 109         {0x007c, 0x0100},
 110         {0x007e, 0x0000},
 111         {0x0080, 0x0000},
 112         {0x0081, 0x0000},
 113         {0x0082, 0x0000},
 114         {0x0083, 0x0000},
 115         {0x0084, 0x0000},
 116         {0x0085, 0x0000},
 117         {0x0086, 0x0005},
 118         {0x0087, 0x0000},
 119         {0x0088, 0x0000},
 120         {0x008c, 0x0003},
 121         {0x008d, 0x0000},
 122         {0x008e, 0x0060},
 123         {0x008f, 0x1000},
 124         {0x0091, 0x0c26},
 125         {0x0092, 0x0073},
 126         {0x0093, 0x0000},
 127         {0x0094, 0x0080},
 128         {0x0098, 0x0000},
 129         {0x009a, 0x0000},
 130         {0x009b, 0x0000},
 131         {0x009c, 0x0000},
 132         {0x009d, 0x0000},
 133         {0x009e, 0x100c},
 134         {0x009f, 0x0000},
 135         {0x00a0, 0x0000},
 136         {0x00a3, 0x0002},
 137         {0x00a4, 0x0001},
 138         {0x00ae, 0x2040},
 139         {0x00af, 0x0000},
 140         {0x00b6, 0x0000},
 141         {0x00b7, 0x0000},
 142         {0x00b8, 0x0000},
 143         {0x00b9, 0x0002},
 144         {0x00be, 0x0000},
 145         {0x00c0, 0x0160},
 146         {0x00c1, 0x82a0},
 147         {0x00c2, 0x0000},
 148         {0x00d0, 0x0000},
 149         {0x00d1, 0x2244},
 150         {0x00d2, 0x3300},
 151         {0x00d3, 0x2200},
 152         {0x00d4, 0x0000},
 153         {0x00d9, 0x0009},
 154         {0x00da, 0x0000},
 155         {0x00db, 0x0000},
 156         {0x00dc, 0x00c0},
 157         {0x00dd, 0x2220},
 158         {0x00de, 0x3131},
 159         {0x00df, 0x3131},
 160         {0x00e0, 0x3131},
 161         {0x00e2, 0x0000},
 162         {0x00e3, 0x4000},
 163         {0x00e4, 0x0aa0},
 164         {0x00e5, 0x3131},
 165         {0x00e6, 0x3131},
 166         {0x00e7, 0x3131},
 167         {0x00e8, 0x3131},
 168         {0x00ea, 0xb320},
 169         {0x00eb, 0x0000},
 170         {0x00f0, 0x0000},
 171         {0x00f1, 0x00d0},
 172         {0x00f2, 0x00d0},
 173         {0x00f6, 0x0000},
 174         {0x00fa, 0x0000},
 175         {0x00fb, 0x0000},
 176         {0x00fc, 0x0000},
 177         {0x00fd, 0x0000},
 178         {0x00fe, 0x10ec},
 179         {0x00ff, 0x6530},
 180         {0x0100, 0xa0a0},
 181         {0x010b, 0x0000},
 182         {0x010c, 0xae00},
 183         {0x010d, 0xaaa0},
 184         {0x010e, 0x8aa2},
 185         {0x010f, 0x02a2},
 186         {0x0110, 0xc000},
 187         {0x0111, 0x04a2},
 188         {0x0112, 0x2800},
 189         {0x0113, 0x0000},
 190         {0x0117, 0x0100},
 191         {0x0125, 0x0410},
 192         {0x0132, 0x6026},
 193         {0x0136, 0x5555},
 194         {0x0138, 0x3700},
 195         {0x013a, 0x2000},
 196         {0x013b, 0x2000},
 197         {0x013c, 0x2005},
 198         {0x013f, 0x0000},
 199         {0x0142, 0x0000},
 200         {0x0145, 0x0002},
 201         {0x0146, 0x0000},
 202         {0x0147, 0x0000},
 203         {0x0148, 0x0000},
 204         {0x0149, 0x0000},
 205         {0x0150, 0x79a1},
 206         {0x0156, 0xaaaa},
 207         {0x0160, 0x4ec0},
 208         {0x0161, 0x0080},
 209         {0x0162, 0x0200},
 210         {0x0163, 0x0800},
 211         {0x0164, 0x0000},
 212         {0x0165, 0x0000},
 213         {0x0166, 0x0000},
 214         {0x0167, 0x000f},
 215         {0x0168, 0x000f},
 216         {0x0169, 0x0021},
 217         {0x0190, 0x413d},
 218         {0x0194, 0x0000},
 219         {0x0195, 0x0000},
 220         {0x0197, 0x0022},
 221         {0x0198, 0x0000},
 222         {0x0199, 0x0000},
 223         {0x01af, 0x0000},
 224         {0x01b0, 0x0400},
 225         {0x01b1, 0x0000},
 226         {0x01b2, 0x0000},
 227         {0x01b3, 0x0000},
 228         {0x01b4, 0x0000},
 229         {0x01b5, 0x0000},
 230         {0x01b6, 0x01c3},
 231         {0x01b7, 0x02a0},
 232         {0x01b8, 0x03e9},
 233         {0x01b9, 0x1389},
 234         {0x01ba, 0xc351},
 235         {0x01bb, 0x0009},
 236         {0x01bc, 0x0018},
 237         {0x01bd, 0x002a},
 238         {0x01be, 0x004c},
 239         {0x01bf, 0x0097},
 240         {0x01c0, 0x433d},
 241         {0x01c2, 0x0000},
 242         {0x01c3, 0x0000},
 243         {0x01c4, 0x0000},
 244         {0x01c5, 0x0000},
 245         {0x01c6, 0x0000},
 246         {0x01c7, 0x0000},
 247         {0x01c8, 0x40af},
 248         {0x01c9, 0x0702},
 249         {0x01ca, 0x0000},
 250         {0x01cb, 0x0000},
 251         {0x01cc, 0x5757},
 252         {0x01cd, 0x5757},
 253         {0x01ce, 0x5757},
 254         {0x01cf, 0x5757},
 255         {0x01d0, 0x5757},
 256         {0x01d1, 0x5757},
 257         {0x01d2, 0x5757},
 258         {0x01d3, 0x5757},
 259         {0x01d4, 0x5757},
 260         {0x01d5, 0x5757},
 261         {0x01d6, 0x0000},
 262         {0x01d7, 0x0008},
 263         {0x01d8, 0x0029},
 264         {0x01d9, 0x3333},
 265         {0x01da, 0x0000},
 266         {0x01db, 0x0004},
 267         {0x01dc, 0x0000},
 268         {0x01de, 0x7c00},
 269         {0x01df, 0x0320},
 270         {0x01e0, 0x06a1},
 271         {0x01e1, 0x0000},
 272         {0x01e2, 0x0000},
 273         {0x01e3, 0x0000},
 274         {0x01e4, 0x0000},
 275         {0x01e6, 0x0001},
 276         {0x01e7, 0x0000},
 277         {0x01e8, 0x0000},
 278         {0x01ea, 0x0000},
 279         {0x01eb, 0x0000},
 280         {0x01ec, 0x0000},
 281         {0x01ed, 0x0000},
 282         {0x01ee, 0x0000},
 283         {0x01ef, 0x0000},
 284         {0x01f0, 0x0000},
 285         {0x01f1, 0x0000},
 286         {0x01f2, 0x0000},
 287         {0x01f3, 0x0000},
 288         {0x01f4, 0x0000},
 289         {0x0210, 0x6297},
 290         {0x0211, 0xa005},
 291         {0x0212, 0x824c},
 292         {0x0213, 0xf7ff},
 293         {0x0214, 0xf24c},
 294         {0x0215, 0x0102},
 295         {0x0216, 0x00a3},
 296         {0x0217, 0x0048},
 297         {0x0218, 0xa2c0},
 298         {0x0219, 0x0400},
 299         {0x021a, 0x00c8},
 300         {0x021b, 0x00c0},
 301         {0x021c, 0x0000},
 302         {0x0250, 0x4500},
 303         {0x0251, 0x40b3},
 304         {0x0252, 0x0000},
 305         {0x0253, 0x0000},
 306         {0x0254, 0x0000},
 307         {0x0255, 0x0000},
 308         {0x0256, 0x0000},
 309         {0x0257, 0x0000},
 310         {0x0258, 0x0000},
 311         {0x0259, 0x0000},
 312         {0x025a, 0x0005},
 313         {0x0270, 0x0000},
 314         {0x02ff, 0x0110},
 315         {0x0300, 0x001f},
 316         {0x0301, 0x032c},
 317         {0x0302, 0x5f21},
 318         {0x0303, 0x4000},
 319         {0x0304, 0x4000},
 320         {0x0305, 0x06d5},
 321         {0x0306, 0x8000},
 322         {0x0307, 0x0700},
 323         {0x0310, 0x4560},
 324         {0x0311, 0xa4a8},
 325         {0x0312, 0x7418},
 326         {0x0313, 0x0000},
 327         {0x0314, 0x0006},
 328         {0x0315, 0xffff},
 329         {0x0316, 0xc400},
 330         {0x0317, 0x0000},
 331         {0x03c0, 0x7e00},
 332         {0x03c1, 0x8000},
 333         {0x03c2, 0x8000},
 334         {0x03c3, 0x8000},
 335         {0x03c4, 0x8000},
 336         {0x03c5, 0x8000},
 337         {0x03c6, 0x8000},
 338         {0x03c7, 0x8000},
 339         {0x03c8, 0x8000},
 340         {0x03c9, 0x8000},
 341         {0x03ca, 0x8000},
 342         {0x03cb, 0x8000},
 343         {0x03cc, 0x8000},
 344         {0x03d0, 0x0000},
 345         {0x03d1, 0x0000},
 346         {0x03d2, 0x0000},
 347         {0x03d3, 0x0000},
 348         {0x03d4, 0x2000},
 349         {0x03d5, 0x2000},
 350         {0x03d6, 0x0000},
 351         {0x03d7, 0x0000},
 352         {0x03d8, 0x2000},
 353         {0x03d9, 0x2000},
 354         {0x03da, 0x2000},
 355         {0x03db, 0x2000},
 356         {0x03dc, 0x0000},
 357         {0x03dd, 0x0000},
 358         {0x03de, 0x0000},
 359         {0x03df, 0x2000},
 360         {0x03e0, 0x0000},
 361         {0x03e1, 0x0000},
 362         {0x03e2, 0x0000},
 363         {0x03e3, 0x0000},
 364         {0x03e4, 0x0000},
 365         {0x03e5, 0x0000},
 366         {0x03e6, 0x0000},
 367         {0x03e7, 0x0000},
 368         {0x03e8, 0x0000},
 369         {0x03e9, 0x0000},
 370         {0x03ea, 0x0000},
 371         {0x03eb, 0x0000},
 372         {0x03ec, 0x0000},
 373         {0x03ed, 0x0000},
 374         {0x03ee, 0x0000},
 375         {0x03ef, 0x0000},
 376         {0x03f0, 0x0800},
 377         {0x03f1, 0x0800},
 378         {0x03f2, 0x0800},
 379         {0x03f3, 0x0800},
 380 };
 381 EXPORT_SYMBOL_GPL(rt5682_reg);
 382
 383 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 384 {
 385         switch (reg) {
 386         case RT5682_RESET:
 387         case RT5682_CBJ_CTRL_2:
 388         case RT5682_INT_ST_1:
 389         case RT5682_4BTN_IL_CMD_1:
 390         case RT5682_AJD1_CTRL:
 391         case RT5682_HP_CALIB_CTRL_1:
 392         case RT5682_DEVICE_ID:
 393         case RT5682_I2C_MODE:
 394         case RT5682_HP_CALIB_CTRL_10:
 395         case RT5682_EFUSE_CTRL_2:
 396         case RT5682_JD_TOP_VC_VTRL:
 397         case RT5682_HP_IMP_SENS_CTRL_19:
 398         case RT5682_IL_CMD_1:
 399         case RT5682_SAR_IL_CMD_2:
 400         case RT5682_SAR_IL_CMD_4:
 401         case RT5682_SAR_IL_CMD_10:
 402         case RT5682_SAR_IL_CMD_11:
 403         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 404         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
 411
 412 bool rt5682_readable_register(struct device *dev, unsigned int reg)
 413 {
 414         switch (reg) {
 415         case RT5682_RESET:
 416         case RT5682_VERSION_ID:
 417         case RT5682_VENDOR_ID:
 418         case RT5682_DEVICE_ID:
 419         case RT5682_HP_CTRL_1:
 420         case RT5682_HP_CTRL_2:
 421         case RT5682_HPL_GAIN:
 422         case RT5682_HPR_GAIN:
 423         case RT5682_I2C_CTRL:
 424         case RT5682_CBJ_BST_CTRL:
 425         case RT5682_CBJ_CTRL_1:
 426         case RT5682_CBJ_CTRL_2:
 427         case RT5682_CBJ_CTRL_3:
 428         case RT5682_CBJ_CTRL_4:
 429         case RT5682_CBJ_CTRL_5:
 430         case RT5682_CBJ_CTRL_6:
 431         case RT5682_CBJ_CTRL_7:
 432         case RT5682_DAC1_DIG_VOL:
 433         case RT5682_STO1_ADC_DIG_VOL:
 434         case RT5682_STO1_ADC_BOOST:
 435         case RT5682_HP_IMP_GAIN_1:
 436         case RT5682_HP_IMP_GAIN_2:
 437         case RT5682_SIDETONE_CTRL:
 438         case RT5682_STO1_ADC_MIXER:
 439         case RT5682_AD_DA_MIXER:
 440         case RT5682_STO1_DAC_MIXER:
 441         case RT5682_A_DAC1_MUX:
 442         case RT5682_DIG_INF2_DATA:
 443         case RT5682_REC_MIXER:
 444         case RT5682_CAL_REC:
 445         case RT5682_ALC_BACK_GAIN:
 446         case RT5682_PWR_DIG_1:
 447         case RT5682_PWR_DIG_2:
 448         case RT5682_PWR_ANLG_1:
 449         case RT5682_PWR_ANLG_2:
 450         case RT5682_PWR_ANLG_3:
 451         case RT5682_PWR_MIXER:
 452         case RT5682_PWR_VOL:
 453         case RT5682_CLK_DET:
 454         case RT5682_RESET_LPF_CTRL:
 455         case RT5682_RESET_HPF_CTRL:
 456         case RT5682_DMIC_CTRL_1:
 457         case RT5682_I2S1_SDP:
 458         case RT5682_I2S2_SDP:
 459         case RT5682_ADDA_CLK_1:
 460         case RT5682_ADDA_CLK_2:
 461         case RT5682_I2S1_F_DIV_CTRL_1:
 462         case RT5682_I2S1_F_DIV_CTRL_2:
 463         case RT5682_TDM_CTRL:
 464         case RT5682_TDM_ADDA_CTRL_1:
 465         case RT5682_TDM_ADDA_CTRL_2:
 466         case RT5682_DATA_SEL_CTRL_1:
 467         case RT5682_TDM_TCON_CTRL:
 468         case RT5682_GLB_CLK:
 469         case RT5682_PLL_CTRL_1:
 470         case RT5682_PLL_CTRL_2:
 471         case RT5682_PLL_TRACK_1:
 472         case RT5682_PLL_TRACK_2:
 473         case RT5682_PLL_TRACK_3:
 474         case RT5682_PLL_TRACK_4:
 475         case RT5682_PLL_TRACK_5:
 476         case RT5682_PLL_TRACK_6:
 477         case RT5682_PLL_TRACK_11:
 478         case RT5682_SDW_REF_CLK:
 479         case RT5682_DEPOP_1:
 480         case RT5682_DEPOP_2:
 481         case RT5682_HP_CHARGE_PUMP_1:
 482         case RT5682_HP_CHARGE_PUMP_2:
 483         case RT5682_MICBIAS_1:
 484         case RT5682_MICBIAS_2:
 485         case RT5682_PLL_TRACK_12:
 486         case RT5682_PLL_TRACK_14:
 487         case RT5682_PLL2_CTRL_1:
 488         case RT5682_PLL2_CTRL_2:
 489         case RT5682_PLL2_CTRL_3:
 490         case RT5682_PLL2_CTRL_4:
 491         case RT5682_RC_CLK_CTRL:
 492         case RT5682_I2S_M_CLK_CTRL_1:
 493         case RT5682_I2S2_F_DIV_CTRL_1:
 494         case RT5682_I2S2_F_DIV_CTRL_2:
 495         case RT5682_EQ_CTRL_1:
 496         case RT5682_EQ_CTRL_2:
 497         case RT5682_IRQ_CTRL_1:
 498         case RT5682_IRQ_CTRL_2:
 499         case RT5682_IRQ_CTRL_3:
 500         case RT5682_IRQ_CTRL_4:
 501         case RT5682_INT_ST_1:
 502         case RT5682_GPIO_CTRL_1:
 503         case RT5682_GPIO_CTRL_2:
 504         case RT5682_GPIO_CTRL_3:
 505         case RT5682_HP_AMP_DET_CTRL_1:
 506         case RT5682_HP_AMP_DET_CTRL_2:
 507         case RT5682_MID_HP_AMP_DET:
 508         case RT5682_LOW_HP_AMP_DET:
 509         case RT5682_DELAY_BUF_CTRL:
 510         case RT5682_SV_ZCD_1:
 511         case RT5682_SV_ZCD_2:
 512         case RT5682_IL_CMD_1:
 513         case RT5682_IL_CMD_2:
 514         case RT5682_IL_CMD_3:
 515         case RT5682_IL_CMD_4:
 516         case RT5682_IL_CMD_5:
 517         case RT5682_IL_CMD_6:
 518         case RT5682_4BTN_IL_CMD_1:
 519         case RT5682_4BTN_IL_CMD_2:
 520         case RT5682_4BTN_IL_CMD_3:
 521         case RT5682_4BTN_IL_CMD_4:
 522         case RT5682_4BTN_IL_CMD_5:
 523         case RT5682_4BTN_IL_CMD_6:
 524         case RT5682_4BTN_IL_CMD_7:
 525         case RT5682_ADC_STO1_HP_CTRL_1:
 526         case RT5682_ADC_STO1_HP_CTRL_2:
 527         case RT5682_AJD1_CTRL:
 528         case RT5682_JD1_THD:
 529         case RT5682_JD2_THD:
 530         case RT5682_JD_CTRL_1:
 531         case RT5682_DUMMY_1:
 532         case RT5682_DUMMY_2:
 533         case RT5682_DUMMY_3:
 534         case RT5682_DAC_ADC_DIG_VOL1:
 535         case RT5682_BIAS_CUR_CTRL_2:
 536         case RT5682_BIAS_CUR_CTRL_3:
 537         case RT5682_BIAS_CUR_CTRL_4:
 538         case RT5682_BIAS_CUR_CTRL_5:
 539         case RT5682_BIAS_CUR_CTRL_6:
 540         case RT5682_BIAS_CUR_CTRL_7:
 541         case RT5682_BIAS_CUR_CTRL_8:
 542         case RT5682_BIAS_CUR_CTRL_9:
 543         case RT5682_BIAS_CUR_CTRL_10:
 544         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 545         case RT5682_CHARGE_PUMP_1:
 546         case RT5682_DIG_IN_CTRL_1:
 547         case RT5682_PAD_DRIVING_CTRL:
 548         case RT5682_SOFT_RAMP_DEPOP:
 549         case RT5682_CHOP_DAC:
 550         case RT5682_CHOP_ADC:
 551         case RT5682_CALIB_ADC_CTRL:
 552         case RT5682_VOL_TEST:
 553         case RT5682_SPKVDD_DET_STA:
 554         case RT5682_TEST_MODE_CTRL_1:
 555         case RT5682_TEST_MODE_CTRL_2:
 556         case RT5682_TEST_MODE_CTRL_3:
 557         case RT5682_TEST_MODE_CTRL_4:
 558         case RT5682_TEST_MODE_CTRL_5:
 559         case RT5682_PLL1_INTERNAL:
 560         case RT5682_PLL2_INTERNAL:
 561         case RT5682_STO_NG2_CTRL_1:
 562         case RT5682_STO_NG2_CTRL_2:
 563         case RT5682_STO_NG2_CTRL_3:
 564         case RT5682_STO_NG2_CTRL_4:
 565         case RT5682_STO_NG2_CTRL_5:
 566         case RT5682_STO_NG2_CTRL_6:
 567         case RT5682_STO_NG2_CTRL_7:
 568         case RT5682_STO_NG2_CTRL_8:
 569         case RT5682_STO_NG2_CTRL_9:
 570         case RT5682_STO_NG2_CTRL_10:
 571         case RT5682_STO1_DAC_SIL_DET:
 572         case RT5682_SIL_PSV_CTRL1:
 573         case RT5682_SIL_PSV_CTRL2:
 574         case RT5682_SIL_PSV_CTRL3:
 575         case RT5682_SIL_PSV_CTRL4:
 576         case RT5682_SIL_PSV_CTRL5:
 577         case RT5682_HP_IMP_SENS_CTRL_01:
 578         case RT5682_HP_IMP_SENS_CTRL_02:
 579         case RT5682_HP_IMP_SENS_CTRL_03:
 580         case RT5682_HP_IMP_SENS_CTRL_04:
 581         case RT5682_HP_IMP_SENS_CTRL_05:
 582         case RT5682_HP_IMP_SENS_CTRL_06:
 583         case RT5682_HP_IMP_SENS_CTRL_07:
 584         case RT5682_HP_IMP_SENS_CTRL_08:
 585         case RT5682_HP_IMP_SENS_CTRL_09:
 586         case RT5682_HP_IMP_SENS_CTRL_10:
 587         case RT5682_HP_IMP_SENS_CTRL_11:
 588         case RT5682_HP_IMP_SENS_CTRL_12:
 589         case RT5682_HP_IMP_SENS_CTRL_13:
 590         case RT5682_HP_IMP_SENS_CTRL_14:
 591         case RT5682_HP_IMP_SENS_CTRL_15:
 592         case RT5682_HP_IMP_SENS_CTRL_16:
 593         case RT5682_HP_IMP_SENS_CTRL_17:
 594         case RT5682_HP_IMP_SENS_CTRL_18:
 595         case RT5682_HP_IMP_SENS_CTRL_19:
 596         case RT5682_HP_IMP_SENS_CTRL_20:
 597         case RT5682_HP_IMP_SENS_CTRL_21:
 598         case RT5682_HP_IMP_SENS_CTRL_22:
 599         case RT5682_HP_IMP_SENS_CTRL_23:
 600         case RT5682_HP_IMP_SENS_CTRL_24:
 601         case RT5682_HP_IMP_SENS_CTRL_25:
 602         case RT5682_HP_IMP_SENS_CTRL_26:
 603         case RT5682_HP_IMP_SENS_CTRL_27:
 604         case RT5682_HP_IMP_SENS_CTRL_28:
 605         case RT5682_HP_IMP_SENS_CTRL_29:
 606         case RT5682_HP_IMP_SENS_CTRL_30:
 607         case RT5682_HP_IMP_SENS_CTRL_31:
 608         case RT5682_HP_IMP_SENS_CTRL_32:
 609         case RT5682_HP_IMP_SENS_CTRL_33:
 610         case RT5682_HP_IMP_SENS_CTRL_34:
 611         case RT5682_HP_IMP_SENS_CTRL_35:
 612         case RT5682_HP_IMP_SENS_CTRL_36:
 613         case RT5682_HP_IMP_SENS_CTRL_37:
 614         case RT5682_HP_IMP_SENS_CTRL_38:
 615         case RT5682_HP_IMP_SENS_CTRL_39:
 616         case RT5682_HP_IMP_SENS_CTRL_40:
 617         case RT5682_HP_IMP_SENS_CTRL_41:
 618         case RT5682_HP_IMP_SENS_CTRL_42:
 619         case RT5682_HP_IMP_SENS_CTRL_43:
 620         case RT5682_HP_LOGIC_CTRL_1:
 621         case RT5682_HP_LOGIC_CTRL_2:
 622         case RT5682_HP_LOGIC_CTRL_3:
 623         case RT5682_HP_CALIB_CTRL_1:
 624         case RT5682_HP_CALIB_CTRL_2:
 625         case RT5682_HP_CALIB_CTRL_3:
 626         case RT5682_HP_CALIB_CTRL_4:
 627         case RT5682_HP_CALIB_CTRL_5:
 628         case RT5682_HP_CALIB_CTRL_6:
 629         case RT5682_HP_CALIB_CTRL_7:
 630         case RT5682_HP_CALIB_CTRL_9:
 631         case RT5682_HP_CALIB_CTRL_10:
 632         case RT5682_HP_CALIB_CTRL_11:
 633         case RT5682_HP_CALIB_STA_1:
 634         case RT5682_HP_CALIB_STA_2:
 635         case RT5682_HP_CALIB_STA_3:
 636         case RT5682_HP_CALIB_STA_4:
 637         case RT5682_HP_CALIB_STA_5:
 638         case RT5682_HP_CALIB_STA_6:
 639         case RT5682_HP_CALIB_STA_7:
 640         case RT5682_HP_CALIB_STA_8:
 641         case RT5682_HP_CALIB_STA_9:
 642         case RT5682_HP_CALIB_STA_10:
 643         case RT5682_HP_CALIB_STA_11:
 644         case RT5682_SAR_IL_CMD_1:
 645         case RT5682_SAR_IL_CMD_2:
 646         case RT5682_SAR_IL_CMD_3:
 647         case RT5682_SAR_IL_CMD_4:
 648         case RT5682_SAR_IL_CMD_5:
 649         case RT5682_SAR_IL_CMD_6:
 650         case RT5682_SAR_IL_CMD_7:
 651         case RT5682_SAR_IL_CMD_8:
 652         case RT5682_SAR_IL_CMD_9:
 653         case RT5682_SAR_IL_CMD_10:
 654         case RT5682_SAR_IL_CMD_11:
 655         case RT5682_SAR_IL_CMD_12:
 656         case RT5682_SAR_IL_CMD_13:
 657         case RT5682_EFUSE_CTRL_1:
 658         case RT5682_EFUSE_CTRL_2:
 659         case RT5682_EFUSE_CTRL_3:
 660         case RT5682_EFUSE_CTRL_4:
 661         case RT5682_EFUSE_CTRL_5:
 662         case RT5682_EFUSE_CTRL_6:
 663         case RT5682_EFUSE_CTRL_7:
 664         case RT5682_EFUSE_CTRL_8:
 665         case RT5682_EFUSE_CTRL_9:
 666         case RT5682_EFUSE_CTRL_10:
 667         case RT5682_EFUSE_CTRL_11:
 668         case RT5682_JD_TOP_VC_VTRL:
 669         case RT5682_DRC1_CTRL_0:
 670         case RT5682_DRC1_CTRL_1:
 671         case RT5682_DRC1_CTRL_2:
 672         case RT5682_DRC1_CTRL_3:
 673         case RT5682_DRC1_CTRL_4:
 674         case RT5682_DRC1_CTRL_5:
 675         case RT5682_DRC1_CTRL_6:
 676         case RT5682_DRC1_HARD_LMT_CTRL_1:
 677         case RT5682_DRC1_HARD_LMT_CTRL_2:
 678         case RT5682_DRC1_PRIV_1:
 679         case RT5682_DRC1_PRIV_2:
 680         case RT5682_DRC1_PRIV_3:
 681         case RT5682_DRC1_PRIV_4:
 682         case RT5682_DRC1_PRIV_5:
 683         case RT5682_DRC1_PRIV_6:
 684         case RT5682_DRC1_PRIV_7:
 685         case RT5682_DRC1_PRIV_8:
 686         case RT5682_EQ_AUTO_RCV_CTRL1:
 687         case RT5682_EQ_AUTO_RCV_CTRL2:
 688         case RT5682_EQ_AUTO_RCV_CTRL3:
 689         case RT5682_EQ_AUTO_RCV_CTRL4:
 690         case RT5682_EQ_AUTO_RCV_CTRL5:
 691         case RT5682_EQ_AUTO_RCV_CTRL6:
 692         case RT5682_EQ_AUTO_RCV_CTRL7:
 693         case RT5682_EQ_AUTO_RCV_CTRL8:
 694         case RT5682_EQ_AUTO_RCV_CTRL9:
 695         case RT5682_EQ_AUTO_RCV_CTRL10:
 696         case RT5682_EQ_AUTO_RCV_CTRL11:
 697         case RT5682_EQ_AUTO_RCV_CTRL12:
 698         case RT5682_EQ_AUTO_RCV_CTRL13:
 699         case RT5682_ADC_L_EQ_LPF1_A1:
 700         case RT5682_R_EQ_LPF1_A1:
 701         case RT5682_L_EQ_LPF1_H0:
 702         case RT5682_R_EQ_LPF1_H0:
 703         case RT5682_L_EQ_BPF1_A1:
 704         case RT5682_R_EQ_BPF1_A1:
 705         case RT5682_L_EQ_BPF1_A2:
 706         case RT5682_R_EQ_BPF1_A2:
 707         case RT5682_L_EQ_BPF1_H0:
 708         case RT5682_R_EQ_BPF1_H0:
 709         case RT5682_L_EQ_BPF2_A1:
 710         case RT5682_R_EQ_BPF2_A1:
 711         case RT5682_L_EQ_BPF2_A2:
 712         case RT5682_R_EQ_BPF2_A2:
 713         case RT5682_L_EQ_BPF2_H0:
 714         case RT5682_R_EQ_BPF2_H0:
 715         case RT5682_L_EQ_BPF3_A1:
 716         case RT5682_R_EQ_BPF3_A1:
 717         case RT5682_L_EQ_BPF3_A2:
 718         case RT5682_R_EQ_BPF3_A2:
 719         case RT5682_L_EQ_BPF3_H0:
 720         case RT5682_R_EQ_BPF3_H0:
 721         case RT5682_L_EQ_BPF4_A1:
 722         case RT5682_R_EQ_BPF4_A1:
 723         case RT5682_L_EQ_BPF4_A2:
 724         case RT5682_R_EQ_BPF4_A2:
 725         case RT5682_L_EQ_BPF4_H0:
 726         case RT5682_R_EQ_BPF4_H0:
 727         case RT5682_L_EQ_HPF1_A1:
 728         case RT5682_R_EQ_HPF1_A1:
 729         case RT5682_L_EQ_HPF1_H0:
 730         case RT5682_R_EQ_HPF1_H0:
 731         case RT5682_L_EQ_PRE_VOL:
 732         case RT5682_R_EQ_PRE_VOL:
 733         case RT5682_L_EQ_POST_VOL:
 734         case RT5682_R_EQ_POST_VOL:
 735         case RT5682_I2C_MODE:
 736                 return true;
 737         default:
 738                 return false;
 739         }
 740 }
 741 EXPORT_SYMBOL_GPL(rt5682_readable_register);
 742
 743 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 744 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 745 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 746
 747 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 748 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 749         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 750         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 751         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 752         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 753         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 754         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 755         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 756 );
 757
 758 /* Interface data select */
 759 static const char * const rt5682_data_select[] = {
 760         "L/R", "R/L", "L/L", "R/R"
 761 };
 762
 763 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 764         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 765
 766 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 767         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 768
 769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 770         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 771
 772 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 773         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 774
 775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 776         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 777
 778 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 779         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 780
 781 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 782         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 783
 784 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 785         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 786
 787 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 788         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 789
 790 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 791         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 792
 793 static const char * const rt5682_dac_select[] = {
 794         "IF1", "SOUND"
 795 };
 796
 797 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
 798         RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
 799
 800 static const struct snd_kcontrol_new rt5682_dac_l_mux =
 801         SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
 802
 803 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
 804         RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
 805
 806 static const struct snd_kcontrol_new rt5682_dac_r_mux =
 807         SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
 808
 809 void rt5682_reset(struct rt5682_priv *rt5682)
 810 {
 811         regmap_write(rt5682->regmap, RT5682_RESET, 0);
 812         if (!rt5682->is_sdw)
 813                 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
 814 }
 815 EXPORT_SYMBOL_GPL(rt5682_reset);
 816
 817 /**
 818  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 819  * @component: SoC audio component device.
 820  * @filter_mask: mask of filters.
 821  * @clk_src: clock source
 822  *
 823  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 824  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 825  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 826  * ASRC function will track i2s clock and generate a corresponding system clock
 827  * for codec. This function provides an API to select the clock source for a
 828  * set of filters specified by the mask. And the component driver will turn on
 829  * ASRC for these filters if ASRC is selected as their clock source.
 830  */
 831 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 832                 unsigned int filter_mask, unsigned int clk_src)
 833 {
 834         switch (clk_src) {
 835         case RT5682_CLK_SEL_SYS:
 836         case RT5682_CLK_SEL_I2S1_ASRC:
 837         case RT5682_CLK_SEL_I2S2_ASRC:
 838                 break;
 839
 840         default:
 841                 return -EINVAL;
 842         }
 843
 844         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 845                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 846                         RT5682_FILTER_CLK_SEL_MASK,
 847                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 848         }
 849
 850         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 851                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 852                         RT5682_FILTER_CLK_SEL_MASK,
 853                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 854         }
 855
 856         return 0;
 857 }
 858 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 859
 860 static int rt5682_button_detect(struct snd_soc_component *component)
 861 {
 862         int btn_type, val;
 863
 864         val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
 865         btn_type = val & 0xfff0;
 866         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 867         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 868         snd_soc_component_update_bits(component,
 869                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 870
 871         return btn_type;
 872 }
 873
 874 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 875                 bool enable)
 876 {
 877         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 878
 879         if (enable) {
 880                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 881                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 882                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 883                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 884                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 885                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 886                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 887                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 888                 if (rt5682->is_sdw)
 889                         snd_soc_component_update_bits(component,
 890                                 RT5682_IRQ_CTRL_3,
 891                                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
 892                                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
 893                 else
 894                         snd_soc_component_update_bits(component,
 895                                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
 896                                 RT5682_IL_IRQ_EN);
 897         } else {
 898                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 899                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 900                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 901                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 902                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 903                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 904                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 905                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 906                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 907                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 908         }
 909 }
 910
 911 /**
 912  * rt5682_headset_detect - Detect headset.
 913  * @component: SoC audio component device.
 914  * @jack_insert: Jack insert or not.
 915  *
 916  * Detect whether is headset or not when jack inserted.
 917  *
 918  * Returns detect status.
 919  */
 920 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
 921 {
 922         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 923         struct snd_soc_dapm_context *dapm = &component->dapm;
 924         unsigned int val, count;
 925
 926         if (jack_insert) {
 927                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 928                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 929                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 930                 snd_soc_component_update_bits(component,
 931                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 932                 usleep_range(15000, 20000);
 933                 snd_soc_component_update_bits(component,
 934                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 935                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 936                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 937                 snd_soc_component_update_bits(component,
 938                         RT5682_HP_CHARGE_PUMP_1,
 939                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
 940                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 941                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 942
 943                 count = 0;
 944                 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
 945                         & RT5682_JACK_TYPE_MASK;
 946                 while (val == 0 && count < 50) {
 947                         usleep_range(10000, 15000);
 948                         val = snd_soc_component_read(component,
 949                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 950                         count++;
 951                 }
 952
 953                 switch (val) {
 954                 case 0x1:
 955                 case 0x2:
 956                         rt5682->jack_type = SND_JACK_HEADSET;
 957                         snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 958                                 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
 959                         rt5682_enable_push_button_irq(component, true);
 960                         break;
 961                 default:
 962                         rt5682->jack_type = SND_JACK_HEADPHONE;
 963                         break;
 964                 }
 965
 966                 snd_soc_component_update_bits(component,
 967                         RT5682_HP_CHARGE_PUMP_1,
 968                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
 969                         RT5682_OSW_L_EN | RT5682_OSW_R_EN);
 970                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 971                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 972                         RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
 973         } else {
 974                 rt5682_enable_push_button_irq(component, false);
 975                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 976                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 977                 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
 978                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 979                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 980                         snd_soc_component_update_bits(component,
 981                                 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
 982                 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
 983                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 984                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 985                         snd_soc_component_update_bits(component,
 986                                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
 987                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 988                         RT5682_PWR_CBJ, 0);
 989                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 990                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 991                         RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
 992                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 993                         RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
 994
 995                 rt5682->jack_type = 0;
 996         }
 997
 998         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
 999         return rt5682->jack_type;
1000 }
1001 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
1002
1003 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1004                 struct snd_soc_jack *hs_jack, void *data)
1005 {
1006         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1007
1008         rt5682->hs_jack = hs_jack;
1009
1010         if (!hs_jack) {
1011                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1012                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1013                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1014                         RT5682_POW_JDH | RT5682_POW_JDL, 0);
1015                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1016
1017                 return 0;
1018         }
1019
1020         if (!rt5682->is_sdw) {
1021                 switch (rt5682->pdata.jd_src) {
1022                 case RT5682_JD1:
1023                         snd_soc_component_update_bits(component,
1024                                 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1025                         snd_soc_component_update_bits(component,
1026                                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1027                                 RT5682_EXT_JD_SRC_MANUAL);
1028                         snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1029                                 0xd142);
1030                         snd_soc_component_update_bits(component,
1031                                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1032                                 RT5682_CBJ_IN_BUF_EN);
1033                         snd_soc_component_update_bits(component,
1034                                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1035                                 RT5682_SAR_POW_EN);
1036                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1037                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1038                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1039                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1040                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1041                                 RT5682_POW_JDH | RT5682_POW_ANA);
1042                         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1043                                 RT5682_PWR_JDH, RT5682_PWR_JDH);
1044                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1045                                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1046                                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1047                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1048                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1049                                 rt5682->pdata.btndet_delay));
1050                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1051                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1052                                 rt5682->pdata.btndet_delay));
1053                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1054                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1055                                 rt5682->pdata.btndet_delay));
1056                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1057                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1058                                 rt5682->pdata.btndet_delay));
1059                         mod_delayed_work(system_power_efficient_wq,
1060                                 &rt5682->jack_detect_work,
1061                                 msecs_to_jiffies(250));
1062                         break;
1063
1064                 case RT5682_JD_NULL:
1065                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1066                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1067                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1068                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1069                         break;
1070
1071                 default:
1072                         dev_warn(component->dev, "Wrong JD source\n");
1073                         break;
1074                 }
1075         }
1076
1077         return 0;
1078 }
1079
1080 void rt5682_jack_detect_handler(struct work_struct *work)
1081 {
1082         struct rt5682_priv *rt5682 =
1083                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1084         int val, btn_type;
1085
1086         while (!rt5682->component)
1087                 usleep_range(10000, 15000);
1088
1089         while (!rt5682->component->card->instantiated)
1090                 usleep_range(10000, 15000);
1091
1092         mutex_lock(&rt5682->calibrate_mutex);
1093
1094         val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1095                 & RT5682_JDH_RS_MASK;
1096         if (!val) {
1097                 /* jack in */
1098                 if (rt5682->jack_type == 0) {
1099                         /* jack was out, report jack type */
1100                         rt5682->jack_type =
1101                                 rt5682_headset_detect(rt5682->component, 1);
1102                         rt5682->irq_work_delay_time = 0;
1103                 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1104                         SND_JACK_HEADSET) {
1105                         /* jack is already in, report button event */
1106                         rt5682->jack_type = SND_JACK_HEADSET;
1107                         btn_type = rt5682_button_detect(rt5682->component);
1108                         /**
1109                          * rt5682 can report three kinds of button behavior,
1110                          * one click, double click and hold. However,
1111                          * currently we will report button pressed/released
1112                          * event. So all the three button behaviors are
1113                          * treated as button pressed.
1114                          */
1115                         switch (btn_type) {
1116                         case 0x8000:
1117                         case 0x4000:
1118                         case 0x2000:
1119                                 rt5682->jack_type |= SND_JACK_BTN_0;
1120                                 break;
1121                         case 0x1000:
1122                         case 0x0800:
1123                         case 0x0400:
1124                                 rt5682->jack_type |= SND_JACK_BTN_1;
1125                                 break;
1126                         case 0x0200:
1127                         case 0x0100:
1128                         case 0x0080:
1129                                 rt5682->jack_type |= SND_JACK_BTN_2;
1130                                 break;
1131                         case 0x0040:
1132                         case 0x0020:
1133                         case 0x0010:
1134                                 rt5682->jack_type |= SND_JACK_BTN_3;
1135                                 break;
1136                         case 0x0000: /* unpressed */
1137                                 break;
1138                         default:
1139                                 dev_err(rt5682->component->dev,
1140                                         "Unexpected button code 0x%04x\n",
1141                                         btn_type);
1142                                 break;
1143                         }
1144                 }
1145         } else {
1146                 /* jack out */
1147                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1148                 rt5682->irq_work_delay_time = 50;
1149         }
1150
1151         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1152                 SND_JACK_HEADSET |
1153                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1154                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1155
1156         if (!rt5682->is_sdw) {
1157                 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1158                         SND_JACK_BTN_2 | SND_JACK_BTN_3))
1159                         schedule_delayed_work(&rt5682->jd_check_work, 0);
1160                 else
1161                         cancel_delayed_work_sync(&rt5682->jd_check_work);
1162         }
1163
1164         mutex_unlock(&rt5682->calibrate_mutex);
1165 }
1166 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1167
1168 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1169         /* DAC Digital Volume */
1170         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1171                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1172
1173         /* IN Boost Volume */
1174         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1175                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1176
1177         /* ADC Digital Volume Control */
1178         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1179                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1180         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1181                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1182
1183         /* ADC Boost Volume Control */
1184         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1185                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1186                 3, 0, adc_bst_tlv),
1187 };
1188
1189 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1190                 int target, const int div[], int size)
1191 {
1192         int i;
1193
1194         if (rt5682->sysclk < target) {
1195                 dev_err(rt5682->component->dev,
1196                         "sysclk rate %d is too low\n", rt5682->sysclk);
1197                 return 0;
1198         }
1199
1200         for (i = 0; i < size - 1; i++) {
1201                 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1202                 if (target * div[i] == rt5682->sysclk)
1203                         return i;
1204                 if (target * div[i + 1] > rt5682->sysclk) {
1205                         dev_dbg(rt5682->component->dev,
1206                                 "can't find div for sysclk %d\n",
1207                                 rt5682->sysclk);
1208                         return i;
1209                 }
1210         }
1211
1212         if (target * div[i] < rt5682->sysclk)
1213                 dev_err(rt5682->component->dev,
1214                         "sysclk rate %d is too high\n", rt5682->sysclk);
1215
1216         return size - 1;
1217 }
1218
1219 /**
1220  * set_dmic_clk - Set parameter of dmic.
1221  *
1222  * @w: DAPM widget.
1223  * @kcontrol: The kcontrol of this widget.
1224  * @event: Event id.
1225  *
1226  * Choose dmic clock between 1MHz and 3MHz.
1227  * It is better for clock to approximate 3MHz.
1228  */
1229 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1230                 struct snd_kcontrol *kcontrol, int event)
1231 {
1232         struct snd_soc_component *component =
1233                 snd_soc_dapm_to_component(w->dapm);
1234         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1235         int idx, dmic_clk_rate = 3072000;
1236         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1237
1238         if (rt5682->pdata.dmic_clk_rate)
1239                 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1240
1241         idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1242
1243         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1244                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1245
1246         return 0;
1247 }
1248
1249 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1250                 struct snd_kcontrol *kcontrol, int event)
1251 {
1252         struct snd_soc_component *component =
1253                 snd_soc_dapm_to_component(w->dapm);
1254         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1255         int ref, val, reg, idx;
1256         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1257         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1258
1259         if (rt5682->is_sdw)
1260                 return 0;
1261
1262         val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1263                 RT5682_GP4_PIN_MASK;
1264         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1265                 val == RT5682_GP4_PIN_ADCDAT2)
1266                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1267         else
1268                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1269
1270         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1271
1272         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1273                 reg = RT5682_PLL_TRACK_3;
1274         else
1275                 reg = RT5682_PLL_TRACK_2;
1276
1277         snd_soc_component_update_bits(component, reg,
1278                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1279
1280         /* select over sample rate */
1281         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1282                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1283                         break;
1284         }
1285
1286         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1287                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1288                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1289
1290         return 0;
1291 }
1292
1293 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1294                 struct snd_soc_dapm_widget *sink)
1295 {
1296         unsigned int val;
1297         struct snd_soc_component *component =
1298                 snd_soc_dapm_to_component(w->dapm);
1299
1300         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1301         val &= RT5682_SCLK_SRC_MASK;
1302         if (val == RT5682_SCLK_SRC_PLL1)
1303                 return 1;
1304         else
1305                 return 0;
1306 }
1307
1308 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1309                 struct snd_soc_dapm_widget *sink)
1310 {
1311         unsigned int val;
1312         struct snd_soc_component *component =
1313                 snd_soc_dapm_to_component(w->dapm);
1314
1315         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1316         val &= RT5682_SCLK_SRC_MASK;
1317         if (val == RT5682_SCLK_SRC_PLL2)
1318                 return 1;
1319         else
1320                 return 0;
1321 }
1322
1323 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1324                 struct snd_soc_dapm_widget *sink)
1325 {
1326         unsigned int reg, shift, val;
1327         struct snd_soc_component *component =
1328                 snd_soc_dapm_to_component(w->dapm);
1329
1330         switch (w->shift) {
1331         case RT5682_ADC_STO1_ASRC_SFT:
1332                 reg = RT5682_PLL_TRACK_3;
1333                 shift = RT5682_FILTER_CLK_SEL_SFT;
1334                 break;
1335         case RT5682_DAC_STO1_ASRC_SFT:
1336                 reg = RT5682_PLL_TRACK_2;
1337                 shift = RT5682_FILTER_CLK_SEL_SFT;
1338                 break;
1339         default:
1340                 return 0;
1341         }
1342
1343         val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1344         switch (val) {
1345         case RT5682_CLK_SEL_I2S1_ASRC:
1346         case RT5682_CLK_SEL_I2S2_ASRC:
1347                 return 1;
1348         default:
1349                 return 0;
1350         }
1351 }
1352
1353 /* Digital Mixer */
1354 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1355         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1356                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1357         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1358                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1359 };
1360
1361 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1362         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1363                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1364         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1365                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1366 };
1367
1368 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1369         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1370                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1371         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1372                         RT5682_M_DAC1_L_SFT, 1, 1),
1373 };
1374
1375 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1376         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1377                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1378         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1379                         RT5682_M_DAC1_R_SFT, 1, 1),
1380 };
1381
1382 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1383         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1384                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1385         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1386                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1387 };
1388
1389 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1390         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1391                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1392         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1393                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1394 };
1395
1396 /* Analog Input Mixer */
1397 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1398         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1399                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1400 };
1401
1402 /* STO1 ADC1 Source */
1403 /* MX-26 [13] [5] */
1404 static const char * const rt5682_sto1_adc1_src[] = {
1405         "DAC MIX", "ADC"
1406 };
1407
1408 static SOC_ENUM_SINGLE_DECL(
1409         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1410         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1411
1412 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1413         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1414
1415 static SOC_ENUM_SINGLE_DECL(
1416         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1417         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1418
1419 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1420         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1421
1422 /* STO1 ADC Source */
1423 /* MX-26 [11:10] [3:2] */
1424 static const char * const rt5682_sto1_adc_src[] = {
1425         "ADC1 L", "ADC1 R"
1426 };
1427
1428 static SOC_ENUM_SINGLE_DECL(
1429         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1430         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1431
1432 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1433         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1434
1435 static SOC_ENUM_SINGLE_DECL(
1436         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1437         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1438
1439 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1440         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1441
1442 /* STO1 ADC2 Source */
1443 /* MX-26 [12] [4] */
1444 static const char * const rt5682_sto1_adc2_src[] = {
1445         "DAC MIX", "DMIC"
1446 };
1447
1448 static SOC_ENUM_SINGLE_DECL(
1449         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1450         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1451
1452 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1453         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1454
1455 static SOC_ENUM_SINGLE_DECL(
1456         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1457         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1458
1459 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1460         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1461
1462 /* MX-79 [6:4] I2S1 ADC data location */
1463 static const unsigned int rt5682_if1_adc_slot_values[] = {
1464         0,
1465         2,
1466         4,
1467         6,
1468 };
1469
1470 static const char * const rt5682_if1_adc_slot_src[] = {
1471         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1472 };
1473
1474 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1475         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1476         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1477
1478 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1479         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1480
1481 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1482 /* MX-2B [4], MX-2B [0]*/
1483 static const char * const rt5682_alg_dac1_src[] = {
1484         "Stereo1 DAC Mixer", "DAC1"
1485 };
1486
1487 static SOC_ENUM_SINGLE_DECL(
1488         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1489         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1490
1491 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1492         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1493
1494 static SOC_ENUM_SINGLE_DECL(
1495         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1496         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1497
1498 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1499         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1500
1501 /* Out Switch */
1502 static const struct snd_kcontrol_new hpol_switch =
1503         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1504                 RT5682_L_MUTE_SFT, 1, 1);
1505 static const struct snd_kcontrol_new hpor_switch =
1506         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1507                 RT5682_R_MUTE_SFT, 1, 1);
1508
1509 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1510                 struct snd_kcontrol *kcontrol, int event)
1511 {
1512         struct snd_soc_component *component =
1513                 snd_soc_dapm_to_component(w->dapm);
1514
1515         switch (event) {
1516         case SND_SOC_DAPM_PRE_PMU:
1517                 snd_soc_component_write(component,
1518                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1519                 snd_soc_component_write(component,
1520                         RT5682_HP_CTRL_2, 0x6000);
1521                 snd_soc_component_update_bits(component,
1522                         RT5682_DEPOP_1, 0x60, 0x60);
1523                 snd_soc_component_update_bits(component,
1524                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1525                 break;
1526
1527         case SND_SOC_DAPM_POST_PMD:
1528                 snd_soc_component_update_bits(component,
1529                         RT5682_DEPOP_1, 0x60, 0x0);
1530                 snd_soc_component_write(component,
1531                         RT5682_HP_CTRL_2, 0x0000);
1532                 snd_soc_component_update_bits(component,
1533                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1534                 break;
1535         }
1536
1537         return 0;
1538 }
1539
1540 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1541                 struct snd_kcontrol *kcontrol, int event)
1542 {
1543         struct snd_soc_component *component =
1544                 snd_soc_dapm_to_component(w->dapm);
1545         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1546         unsigned int delay = 50, val;
1547
1548         if (rt5682->pdata.dmic_delay)
1549                 delay = rt5682->pdata.dmic_delay;
1550
1551         switch (event) {
1552         case SND_SOC_DAPM_POST_PMU:
1553                 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1554                 val &= RT5682_SCLK_SRC_MASK;
1555                 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1556                         snd_soc_component_update_bits(component,
1557                                 RT5682_PWR_ANLG_1,
1558                                 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1559                                 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1560
1561                 /*Add delay to avoid pop noise*/
1562                 msleep(delay);
1563                 break;
1564
1565         case SND_SOC_DAPM_POST_PMD:
1566                 if (!rt5682->jack_type) {
1567                         if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1568                                 snd_soc_component_update_bits(component,
1569                                         RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1570                         if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1571                                 snd_soc_component_update_bits(component,
1572                                         RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1573                 }
1574                 break;
1575         }
1576
1577         return 0;
1578 }
1579
1580 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1581                 struct snd_kcontrol *kcontrol, int event)
1582 {
1583         struct snd_soc_component *component =
1584                 snd_soc_dapm_to_component(w->dapm);
1585
1586         switch (event) {
1587         case SND_SOC_DAPM_PRE_PMU:
1588                 switch (w->shift) {
1589                 case RT5682_PWR_VREF1_BIT:
1590                         snd_soc_component_update_bits(component,
1591                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1592                         break;
1593
1594                 case RT5682_PWR_VREF2_BIT:
1595                         snd_soc_component_update_bits(component,
1596                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1597                         break;
1598                 }
1599                 break;
1600
1601         case SND_SOC_DAPM_POST_PMU:
1602                 usleep_range(15000, 20000);
1603                 switch (w->shift) {
1604                 case RT5682_PWR_VREF1_BIT:
1605                         snd_soc_component_update_bits(component,
1606                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1607                                 RT5682_PWR_FV1);
1608                         break;
1609
1610                 case RT5682_PWR_VREF2_BIT:
1611                         snd_soc_component_update_bits(component,
1612                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1613                                 RT5682_PWR_FV2);
1614                         break;
1615                 }
1616                 break;
1617         }
1618
1619         return 0;
1620 }
1621
1622 static const unsigned int rt5682_adcdat_pin_values[] = {
1623         1,
1624         3,
1625 };
1626
1627 static const char * const rt5682_adcdat_pin_select[] = {
1628         "ADCDAT1",
1629         "ADCDAT2",
1630 };
1631
1632 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1633         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1634         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1635
1636 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1637         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1638
1639 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1640         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1641                 0, NULL, 0),
1642         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1643                 0, NULL, 0),
1644         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1645                 0, NULL, 0),
1646         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1647                 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1648         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1649                 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1650         SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1651         SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1652
1653         /* ASRC */
1654         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1655                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1656         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1657                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1658         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1659                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1660         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1661                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1662         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1663                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1664
1665         /* Input Side */
1666         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1667                 0, NULL, 0),
1668         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1669                 0, NULL, 0),
1670
1671         /* Input Lines */
1672         SND_SOC_DAPM_INPUT("DMIC L1"),
1673         SND_SOC_DAPM_INPUT("DMIC R1"),
1674
1675         SND_SOC_DAPM_INPUT("IN1P"),
1676
1677         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1678                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1679         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1680                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1681                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1682
1683         /* Boost */
1684         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1685                 0, 0, NULL, 0),
1686
1687         /* REC Mixer */
1688         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1689                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1690         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1691                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1692
1693         /* ADCs */
1694         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1695         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1696
1697         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1698                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1699         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1700                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1701         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1702                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1703
1704         /* ADC Mux */
1705         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1706                 &rt5682_sto1_adc1l_mux),
1707         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1708                 &rt5682_sto1_adc1r_mux),
1709         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1710                 &rt5682_sto1_adc2l_mux),
1711         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1712                 &rt5682_sto1_adc2r_mux),
1713         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1714                 &rt5682_sto1_adcl_mux),
1715         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1716                 &rt5682_sto1_adcr_mux),
1717         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1718                 &rt5682_if1_adc_slot_mux),
1719
1720         /* ADC Mixer */
1721         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1722                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1723                 SND_SOC_DAPM_PRE_PMU),
1724         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1725                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1726                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1727         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1728                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1729                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1730         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1731                 14, 1, NULL, 0),
1732
1733         /* ADC PGA */
1734         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1735
1736         /* Digital Interface */
1737         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1738                 0, NULL, 0),
1739         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1740                 0, NULL, 0),
1741         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1742         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1743         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1744         SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1745         SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1746
1747         /* Digital Interface Select */
1748         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1749                 &rt5682_if1_01_adc_swap_mux),
1750         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1751                 &rt5682_if1_23_adc_swap_mux),
1752         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1753                 &rt5682_if1_45_adc_swap_mux),
1754         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1755                 &rt5682_if1_67_adc_swap_mux),
1756         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1757                 &rt5682_if2_adc_swap_mux),
1758
1759         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1760                 &rt5682_adcdat_pin_ctrl),
1761
1762         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1763                 &rt5682_dac_l_mux),
1764         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1765                 &rt5682_dac_r_mux),
1766
1767         /* Audio Interface */
1768         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1769                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1770         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1771                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1772         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1773         SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1774         SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1775
1776         /* Output Side */
1777         /* DAC mixer before sound effect  */
1778         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1779                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1780         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1781                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1782
1783         /* DAC channel Mux */
1784         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1785                 &rt5682_alg_dac_l1_mux),
1786         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1787                 &rt5682_alg_dac_r1_mux),
1788
1789         /* DAC Mixer */
1790         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1791                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1792                 SND_SOC_DAPM_PRE_PMU),
1793         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1794                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1795         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1796                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1797
1798         /* DACs */
1799         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1800                 RT5682_PWR_DAC_L1_BIT, 0),
1801         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1802                 RT5682_PWR_DAC_R1_BIT, 0),
1803         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1804                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1805
1806         /* HPO */
1807         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1808                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1809
1810         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1811                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1812         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1813                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1814         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1815                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1816         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1817                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1818
1819         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1820                 &hpol_switch),
1821         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1822                 &hpor_switch),
1823
1824         /* CLK DET */
1825         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1826                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1827         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1828                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1829         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1830                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1831         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1832                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1833
1834         /* Output Lines */
1835         SND_SOC_DAPM_OUTPUT("HPOL"),
1836         SND_SOC_DAPM_OUTPUT("HPOR"),
1837 };
1838
1839 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1840         /*PLL*/
1841         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1842         {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1843         {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1844         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1845         {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1846         {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1847
1848         /*ASRC*/
1849         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1850         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1851         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1852         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1853         {"ADC STO1 ASRC", NULL, "CLKDET"},
1854         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1855         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1856         {"DAC STO1 ASRC", NULL, "CLKDET"},
1857
1858         /*Vref*/
1859         {"MICBIAS1", NULL, "Vref1"},
1860         {"MICBIAS2", NULL, "Vref1"},
1861
1862         {"CLKDET SYS", NULL, "CLKDET"},
1863
1864         {"BST1 CBJ", NULL, "IN1P"},
1865
1866         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1867         {"RECMIX1L", NULL, "RECMIX1L Power"},
1868
1869         {"ADC1 L", NULL, "RECMIX1L"},
1870         {"ADC1 L", NULL, "ADC1 L Power"},
1871         {"ADC1 L", NULL, "ADC1 clock"},
1872
1873         {"DMIC L1", NULL, "DMIC CLK"},
1874         {"DMIC L1", NULL, "DMIC1 Power"},
1875         {"DMIC R1", NULL, "DMIC CLK"},
1876         {"DMIC R1", NULL, "DMIC1 Power"},
1877         {"DMIC CLK", NULL, "DMIC ASRC"},
1878
1879         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1880         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1881         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1882         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1883
1884         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1885         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1886         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1887         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1888
1889         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1890         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1891         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1892         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1893
1894         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1895         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1896         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1897
1898         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1899         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1900         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1901
1902         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1903
1904         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1905         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1906
1907         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1908         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1909         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1911         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1912         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1913         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1914         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1915         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1916         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1917         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1918         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1919         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1920         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1921         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1922         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1923
1924         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1925         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1926         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1927         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1928         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1929         {"AIF1TX", NULL, "I2S1"},
1930         {"AIF1TX", NULL, "ADCDAT Mux"},
1931         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1932         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1933         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1934         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1935         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1936         {"AIF2TX", NULL, "ADCDAT Mux"},
1937
1938         {"SDWTX", NULL, "PLL2B"},
1939         {"SDWTX", NULL, "PLL2F"},
1940         {"SDWTX", NULL, "ADCDAT Mux"},
1941
1942         {"IF1 DAC1 L", NULL, "AIF1RX"},
1943         {"IF1 DAC1 L", NULL, "I2S1"},
1944         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1945         {"IF1 DAC1 R", NULL, "AIF1RX"},
1946         {"IF1 DAC1 R", NULL, "I2S1"},
1947         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1948
1949         {"SOUND DAC L", NULL, "SDWRX"},
1950         {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1951         {"SOUND DAC L", NULL, "PLL2B"},
1952         {"SOUND DAC L", NULL, "PLL2F"},
1953         {"SOUND DAC R", NULL, "SDWRX"},
1954         {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1955         {"SOUND DAC R", NULL, "PLL2B"},
1956         {"SOUND DAC R", NULL, "PLL2F"},
1957
1958         {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1959         {"DAC L Mux", "SOUND", "SOUND DAC L"},
1960         {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1961         {"DAC R Mux", "SOUND", "SOUND DAC R"},
1962
1963         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1964         {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1965         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1966         {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1967
1968         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1969         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1970
1971         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1972         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1973
1974         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1975         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1976         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1977         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1978
1979         {"DAC L1", NULL, "DAC L1 Source"},
1980         {"DAC R1", NULL, "DAC R1 Source"},
1981
1982         {"DAC L1", NULL, "DAC 1 Clock"},
1983         {"DAC R1", NULL, "DAC 1 Clock"},
1984
1985         {"HP Amp", NULL, "DAC L1"},
1986         {"HP Amp", NULL, "DAC R1"},
1987         {"HP Amp", NULL, "HP Amp L"},
1988         {"HP Amp", NULL, "HP Amp R"},
1989         {"HP Amp", NULL, "Capless"},
1990         {"HP Amp", NULL, "Charge Pump"},
1991         {"HP Amp", NULL, "CLKDET SYS"},
1992         {"HP Amp", NULL, "Vref1"},
1993         {"HPOL Playback", "Switch", "HP Amp"},
1994         {"HPOR Playback", "Switch", "HP Amp"},
1995         {"HPOL", NULL, "HPOL Playback"},
1996         {"HPOR", NULL, "HPOR Playback"},
1997 };
1998
1999 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2000                 unsigned int rx_mask, int slots, int slot_width)
2001 {
2002         struct snd_soc_component *component = dai->component;
2003         unsigned int cl, val = 0;
2004
2005         if (tx_mask || rx_mask)
2006                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2007                         RT5682_TDM_EN, RT5682_TDM_EN);
2008         else
2009                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2010                         RT5682_TDM_EN, 0);
2011
2012         switch (slots) {
2013         case 4:
2014                 val |= RT5682_TDM_TX_CH_4;
2015                 val |= RT5682_TDM_RX_CH_4;
2016                 break;
2017         case 6:
2018                 val |= RT5682_TDM_TX_CH_6;
2019                 val |= RT5682_TDM_RX_CH_6;
2020                 break;
2021         case 8:
2022                 val |= RT5682_TDM_TX_CH_8;
2023                 val |= RT5682_TDM_RX_CH_8;
2024                 break;
2025         case 2:
2026                 break;
2027         default:
2028                 return -EINVAL;
2029         }
2030
2031         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2032                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2033
2034         switch (slot_width) {
2035         case 8:
2036                 if (tx_mask || rx_mask)
2037                         return -EINVAL;
2038                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2039                 break;
2040         case 16:
2041                 val = RT5682_TDM_CL_16;
2042                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2043                 break;
2044         case 20:
2045                 val = RT5682_TDM_CL_20;
2046                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2047                 break;
2048         case 24:
2049                 val = RT5682_TDM_CL_24;
2050                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2051                 break;
2052         case 32:
2053                 val = RT5682_TDM_CL_32;
2054                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2055                 break;
2056         default:
2057                 return -EINVAL;
2058         }
2059
2060         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2061                 RT5682_TDM_CL_MASK, val);
2062         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2063                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2064
2065         return 0;
2066 }
2067
2068 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2069                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2070 {
2071         struct snd_soc_component *component = dai->component;
2072         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2073         unsigned int len_1 = 0, len_2 = 0;
2074         int pre_div, frame_size;
2075
2076         rt5682->lrck[dai->id] = params_rate(params);
2077         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2078
2079         frame_size = snd_soc_params_to_frame_size(params);
2080         if (frame_size < 0) {
2081                 dev_err(component->dev, "Unsupported frame size: %d\n",
2082                         frame_size);
2083                 return -EINVAL;
2084         }
2085
2086         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2087                 rt5682->lrck[dai->id], pre_div, dai->id);
2088
2089         switch (params_width(params)) {
2090         case 16:
2091                 break;
2092         case 20:
2093                 len_1 |= RT5682_I2S1_DL_20;
2094                 len_2 |= RT5682_I2S2_DL_20;
2095                 break;
2096         case 24:
2097                 len_1 |= RT5682_I2S1_DL_24;
2098                 len_2 |= RT5682_I2S2_DL_24;
2099                 break;
2100         case 32:
2101                 len_1 |= RT5682_I2S1_DL_32;
2102                 len_2 |= RT5682_I2S2_DL_24;
2103                 break;
2104         case 8:
2105                 len_1 |= RT5682_I2S2_DL_8;
2106                 len_2 |= RT5682_I2S2_DL_8;
2107                 break;
2108         default:
2109                 return -EINVAL;
2110         }
2111
2112         switch (dai->id) {
2113         case RT5682_AIF1:
2114                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2115                         RT5682_I2S1_DL_MASK, len_1);
2116                 if (rt5682->master[RT5682_AIF1]) {
2117                         snd_soc_component_update_bits(component,
2118                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2119                                 RT5682_I2S_CLK_SRC_MASK,
2120                                 pre_div << RT5682_I2S_M_DIV_SFT |
2121                                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2122                 }
2123                 if (params_channels(params) == 1) /* mono mode */
2124                         snd_soc_component_update_bits(component,
2125                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2126                                 RT5682_I2S1_MONO_EN);
2127                 else
2128                         snd_soc_component_update_bits(component,
2129                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2130                                 RT5682_I2S1_MONO_DIS);
2131                 break;
2132         case RT5682_AIF2:
2133                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2134                         RT5682_I2S2_DL_MASK, len_2);
2135                 if (rt5682->master[RT5682_AIF2]) {
2136                         snd_soc_component_update_bits(component,
2137                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2138                                 pre_div << RT5682_I2S2_M_PD_SFT);
2139                 }
2140                 if (params_channels(params) == 1) /* mono mode */
2141                         snd_soc_component_update_bits(component,
2142                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2143                                 RT5682_I2S2_MONO_EN);
2144                 else
2145                         snd_soc_component_update_bits(component,
2146                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2147                                 RT5682_I2S2_MONO_DIS);
2148                 break;
2149         default:
2150                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2151                 return -EINVAL;
2152         }
2153
2154         return 0;
2155 }
2156
2157 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2158 {
2159         struct snd_soc_component *component = dai->component;
2160         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2161         unsigned int reg_val = 0, tdm_ctrl = 0;
2162
2163         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2164         case SND_SOC_DAIFMT_CBM_CFM:
2165                 rt5682->master[dai->id] = 1;
2166                 break;
2167         case SND_SOC_DAIFMT_CBS_CFS:
2168                 rt5682->master[dai->id] = 0;
2169                 break;
2170         default:
2171                 return -EINVAL;
2172         }
2173
2174         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2175         case SND_SOC_DAIFMT_NB_NF:
2176                 break;
2177         case SND_SOC_DAIFMT_IB_NF:
2178                 reg_val |= RT5682_I2S_BP_INV;
2179                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2180                 break;
2181         case SND_SOC_DAIFMT_NB_IF:
2182                 if (dai->id == RT5682_AIF1)
2183                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2184                 else
2185                         return -EINVAL;
2186                 break;
2187         case SND_SOC_DAIFMT_IB_IF:
2188                 if (dai->id == RT5682_AIF1)
2189                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2190                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2191                 else
2192                         return -EINVAL;
2193                 break;
2194         default:
2195                 return -EINVAL;
2196         }
2197
2198         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2199         case SND_SOC_DAIFMT_I2S:
2200                 break;
2201         case SND_SOC_DAIFMT_LEFT_J:
2202                 reg_val |= RT5682_I2S_DF_LEFT;
2203                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2204                 break;
2205         case SND_SOC_DAIFMT_DSP_A:
2206                 reg_val |= RT5682_I2S_DF_PCM_A;
2207                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2208                 break;
2209         case SND_SOC_DAIFMT_DSP_B:
2210                 reg_val |= RT5682_I2S_DF_PCM_B;
2211                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2212                 break;
2213         default:
2214                 return -EINVAL;
2215         }
2216
2217         switch (dai->id) {
2218         case RT5682_AIF1:
2219                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2220                         RT5682_I2S_DF_MASK, reg_val);
2221                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2222                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2223                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2224                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2225                         tdm_ctrl | rt5682->master[dai->id]);
2226                 break;
2227         case RT5682_AIF2:
2228                 if (rt5682->master[dai->id] == 0)
2229                         reg_val |= RT5682_I2S2_MS_S;
2230                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2231                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2232                         RT5682_I2S_DF_MASK, reg_val);
2233                 break;
2234         default:
2235                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2236                 return -EINVAL;
2237         }
2238         return 0;
2239 }
2240
2241 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2242                 int clk_id, int source, unsigned int freq, int dir)
2243 {
2244         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2245         unsigned int reg_val = 0, src = 0;
2246
2247         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2248                 return 0;
2249
2250         switch (clk_id) {
2251         case RT5682_SCLK_S_MCLK:
2252                 reg_val |= RT5682_SCLK_SRC_MCLK;
2253                 src = RT5682_CLK_SRC_MCLK;
2254                 break;
2255         case RT5682_SCLK_S_PLL1:
2256                 reg_val |= RT5682_SCLK_SRC_PLL1;
2257                 src = RT5682_CLK_SRC_PLL1;
2258                 break;
2259         case RT5682_SCLK_S_PLL2:
2260                 reg_val |= RT5682_SCLK_SRC_PLL2;
2261                 src = RT5682_CLK_SRC_PLL2;
2262                 break;
2263         case RT5682_SCLK_S_RCCLK:
2264                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2265                 src = RT5682_CLK_SRC_RCCLK;
2266                 break;
2267         default:
2268                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2269                 return -EINVAL;
2270         }
2271         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2272                 RT5682_SCLK_SRC_MASK, reg_val);
2273
2274         if (rt5682->master[RT5682_AIF2]) {
2275                 snd_soc_component_update_bits(component,
2276                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2277                         src << RT5682_I2S2_SRC_SFT);
2278         }
2279
2280         rt5682->sysclk = freq;
2281         rt5682->sysclk_src = clk_id;
2282
2283         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2284                 freq, clk_id);
2285
2286         return 0;
2287 }
2288
2289 static int rt5682_set_component_pll(struct snd_soc_component *component,
2290                 int pll_id, int source, unsigned int freq_in,
2291                 unsigned int freq_out)
2292 {
2293         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2294         struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2295         unsigned int pll2_fout1, pll2_ps_val;
2296         int ret;
2297
2298         if (source == rt5682->pll_src[pll_id] &&
2299             freq_in == rt5682->pll_in[pll_id] &&
2300             freq_out == rt5682->pll_out[pll_id])
2301                 return 0;
2302
2303         if (!freq_in || !freq_out) {
2304                 dev_dbg(component->dev, "PLL disabled\n");
2305
2306                 rt5682->pll_in[pll_id] = 0;
2307                 rt5682->pll_out[pll_id] = 0;
2308                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2309                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2310                 return 0;
2311         }
2312
2313         if (pll_id == RT5682_PLL2) {
2314                 switch (source) {
2315                 case RT5682_PLL2_S_MCLK:
2316                         snd_soc_component_update_bits(component,
2317                                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2318                                 RT5682_PLL2_SRC_MCLK);
2319                         break;
2320                 default:
2321                         dev_err(component->dev, "Unknown PLL2 Source %d\n",
2322                                 source);
2323                         return -EINVAL;
2324                 }
2325
2326                 /**
2327                  * PLL2 concatenates 2 PLL units.
2328                  * We suggest the Fout of the front PLL is 3.84MHz.
2329                  */
2330                 pll2_fout1 = 3840000;
2331                 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2332                 if (ret < 0) {
2333                         dev_err(component->dev, "Unsupport input clock %d\n",
2334                                 freq_in);
2335                         return ret;
2336                 }
2337                 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2338                         freq_in, pll2_fout1,
2339                         pll2f_code.m_bp,
2340                         (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2341                         pll2f_code.n_code, pll2f_code.k_code);
2342
2343                 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2344                 if (ret < 0) {
2345                         dev_err(component->dev, "Unsupport input clock %d\n",
2346                                 pll2_fout1);
2347                         return ret;
2348                 }
2349                 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2350                         pll2_fout1, freq_out,
2351                         pll2b_code.m_bp,
2352                         (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2353                         pll2b_code.n_code, pll2b_code.k_code);
2354
2355                 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2356                         pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2357                         pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2358                         pll2b_code.m_code);
2359                 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2360                         pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2361                         pll2b_code.n_code);
2362                 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2363                         pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2364
2365                 if (freq_out == 22579200)
2366                         pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2367                 else
2368                         pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2369                 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2370                         RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2371                         RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2372                         pll2_ps_val |
2373                         (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2374                         (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2375                         0xf);
2376         } else {
2377                 switch (source) {
2378                 case RT5682_PLL1_S_MCLK:
2379                         snd_soc_component_update_bits(component,
2380                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2381                                 RT5682_PLL1_SRC_MCLK);
2382                         break;
2383                 case RT5682_PLL1_S_BCLK1:
2384                         snd_soc_component_update_bits(component,
2385                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2386                                 RT5682_PLL1_SRC_BCLK1);
2387                         break;
2388                 default:
2389                         dev_err(component->dev, "Unknown PLL1 Source %d\n",
2390                                 source);
2391                         return -EINVAL;
2392                 }
2393
2394                 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2395                 if (ret < 0) {
2396                         dev_err(component->dev, "Unsupport input clock %d\n",
2397                                 freq_in);
2398                         return ret;
2399                 }
2400
2401                 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2402                         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2403                         pll_code.n_code, pll_code.k_code);
2404
2405                 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2406                         (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2407                 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2408                         ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2409                         ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2410         }
2411
2412         rt5682->pll_in[pll_id] = freq_in;
2413         rt5682->pll_out[pll_id] = freq_out;
2414         rt5682->pll_src[pll_id] = source;
2415
2416         return 0;
2417 }
2418
2419 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2420 {
2421         struct snd_soc_component *component = dai->component;
2422         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2423
2424         rt5682->bclk[dai->id] = ratio;
2425
2426         switch (ratio) {
2427         case 256:
2428                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2429                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2430                 break;
2431         case 128:
2432                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2433                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2434                 break;
2435         case 64:
2436                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2437                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2438                 break;
2439         case 32:
2440                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2441                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2442                 break;
2443         default:
2444                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2445                 return -EINVAL;
2446         }
2447
2448         return 0;
2449 }
2450
2451 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2452 {
2453         struct snd_soc_component *component = dai->component;
2454         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2455
2456         rt5682->bclk[dai->id] = ratio;
2457
2458         switch (ratio) {
2459         case 64:
2460                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2461                         RT5682_I2S2_BCLK_MS2_MASK,
2462                         RT5682_I2S2_BCLK_MS2_64);
2463                 break;
2464         case 32:
2465                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2466                         RT5682_I2S2_BCLK_MS2_MASK,
2467                         RT5682_I2S2_BCLK_MS2_32);
2468                 break;
2469         default:
2470                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2471                 return -EINVAL;
2472         }
2473
2474         return 0;
2475 }
2476
2477 static int rt5682_set_bias_level(struct snd_soc_component *component,
2478                 enum snd_soc_bias_level level)
2479 {
2480         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2481
2482         switch (level) {
2483         case SND_SOC_BIAS_PREPARE:
2484                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2485                         RT5682_PWR_BG, RT5682_PWR_BG);
2486                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2487                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2488                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2489                 break;
2490
2491         case SND_SOC_BIAS_STANDBY:
2492                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2493                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2494                 break;
2495         case SND_SOC_BIAS_OFF:
2496                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2497                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2498                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2499                         RT5682_PWR_BG, 0);
2500                 break;
2501         case SND_SOC_BIAS_ON:
2502                 break;
2503         }
2504
2505         return 0;
2506 }
2507
2508 #ifdef CONFIG_COMMON_CLK
2509 #define CLK_PLL2_FIN 48000000
2510 #define CLK_48 48000
2511 #define CLK_44 44100
2512
2513 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2514 {
2515         if (!rt5682->master[RT5682_AIF1]) {
2516                 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2517                 return false;
2518         }
2519         return true;
2520 }
2521
2522 static int rt5682_wclk_prepare(struct clk_hw *hw)
2523 {
2524         struct rt5682_priv *rt5682 =
2525                 container_of(hw, struct rt5682_priv,
2526                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2527         struct snd_soc_component *component = rt5682->component;
2528         struct snd_soc_dapm_context *dapm =
2529                         snd_soc_component_get_dapm(component);
2530
2531         if (!rt5682_clk_check(rt5682))
2532                 return -EINVAL;
2533
2534         snd_soc_dapm_mutex_lock(dapm);
2535
2536         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2537         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2538                                 RT5682_PWR_MB, RT5682_PWR_MB);
2539
2540         snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2541         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2542                         RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2543                         RT5682_PWR_VREF2);
2544         usleep_range(55000, 60000);
2545         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2546                         RT5682_PWR_FV2, RT5682_PWR_FV2);
2547
2548         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2549         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2550         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2551         snd_soc_dapm_sync_unlocked(dapm);
2552
2553         snd_soc_dapm_mutex_unlock(dapm);
2554
2555         return 0;
2556 }
2557
2558 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2559 {
2560         struct rt5682_priv *rt5682 =
2561                 container_of(hw, struct rt5682_priv,
2562                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2563         struct snd_soc_component *component = rt5682->component;
2564         struct snd_soc_dapm_context *dapm =
2565                         snd_soc_component_get_dapm(component);
2566
2567         if (!rt5682_clk_check(rt5682))
2568                 return;
2569
2570         snd_soc_dapm_mutex_lock(dapm);
2571
2572         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2573         snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2574         if (!rt5682->jack_type)
2575                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2576                                 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2577                                 RT5682_PWR_MB, 0);
2578
2579         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2580         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2581         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2582         snd_soc_dapm_sync_unlocked(dapm);
2583
2584         snd_soc_dapm_mutex_unlock(dapm);
2585 }
2586
2587 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2588                                              unsigned long parent_rate)
2589 {
2590         struct rt5682_priv *rt5682 =
2591                 container_of(hw, struct rt5682_priv,
2592                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2593         struct snd_soc_component *component = rt5682->component;
2594         const char * const clk_name = clk_hw_get_name(hw);
2595
2596         if (!rt5682_clk_check(rt5682))
2597                 return 0;
2598         /*
2599          * Only accept to set wclk rate to 44.1k or 48kHz.
2600          */
2601         if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2602             rt5682->lrck[RT5682_AIF1] != CLK_44) {
2603                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2604                         __func__, clk_name, CLK_44, CLK_48);
2605                 return 0;
2606         }
2607
2608         return rt5682->lrck[RT5682_AIF1];
2609 }
2610
2611 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2612                                    unsigned long *parent_rate)
2613 {
2614         struct rt5682_priv *rt5682 =
2615                 container_of(hw, struct rt5682_priv,
2616                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2617         struct snd_soc_component *component = rt5682->component;
2618         const char * const clk_name = clk_hw_get_name(hw);
2619
2620         if (!rt5682_clk_check(rt5682))
2621                 return -EINVAL;
2622         /*
2623          * Only accept to set wclk rate to 44.1k or 48kHz.
2624          * It will force to 48kHz if not both.
2625          */
2626         if (rate != CLK_48 && rate != CLK_44) {
2627                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2628                         __func__, clk_name, CLK_44, CLK_48);
2629                 rate = CLK_48;
2630         }
2631
2632         return rate;
2633 }
2634
2635 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2636                                 unsigned long parent_rate)
2637 {
2638         struct rt5682_priv *rt5682 =
2639                 container_of(hw, struct rt5682_priv,
2640                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2641         struct snd_soc_component *component = rt5682->component;
2642         struct clk_hw *parent_hw;
2643         const char * const clk_name = clk_hw_get_name(hw);
2644         int pre_div;
2645         unsigned int clk_pll2_out;
2646
2647         if (!rt5682_clk_check(rt5682))
2648                 return -EINVAL;
2649
2650         /*
2651          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2652          * it is fixed or set to 48MHz before setting wclk rate. It's a
2653          * temporary limitation. Only accept 48MHz clk as the clk provider.
2654          *
2655          * It will set the codec anyway by assuming mclk is 48MHz.
2656          */
2657         parent_hw = clk_hw_get_parent(hw);
2658         if (!parent_hw)
2659                 dev_warn(component->dev,
2660                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2661                         CLK_PLL2_FIN);
2662
2663         if (parent_rate != CLK_PLL2_FIN)
2664                 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2665                         clk_name, CLK_PLL2_FIN);
2666
2667         /*
2668          * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2669          * PLL2 is needed.
2670          */
2671         clk_pll2_out = rate * 512;
2672         rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2673                 CLK_PLL2_FIN, clk_pll2_out);
2674
2675         rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2676                 clk_pll2_out, SND_SOC_CLOCK_IN);
2677
2678         rt5682->lrck[RT5682_AIF1] = rate;
2679
2680         pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2681
2682         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2683                 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2684                 pre_div << RT5682_I2S_M_DIV_SFT |
2685                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2686
2687         return 0;
2688 }
2689
2690 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2691                                              unsigned long parent_rate)
2692 {
2693         struct rt5682_priv *rt5682 =
2694                 container_of(hw, struct rt5682_priv,
2695                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2696         struct snd_soc_component *component = rt5682->component;
2697         unsigned int bclks_per_wclk;
2698
2699         bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2700
2701         switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2702         case RT5682_TDM_BCLK_MS1_256:
2703                 return parent_rate * 256;
2704         case RT5682_TDM_BCLK_MS1_128:
2705                 return parent_rate * 128;
2706         case RT5682_TDM_BCLK_MS1_64:
2707                 return parent_rate * 64;
2708         case RT5682_TDM_BCLK_MS1_32:
2709                 return parent_rate * 32;
2710         default:
2711                 return 0;
2712         }
2713 }
2714
2715 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2716                                             unsigned long parent_rate)
2717 {
2718         unsigned long factor;
2719
2720         factor = rate / parent_rate;
2721         if (factor < 64)
2722                 return 32;
2723         else if (factor < 128)
2724                 return 64;
2725         else if (factor < 256)
2726                 return 128;
2727         else
2728                 return 256;
2729 }
2730
2731 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2732                                    unsigned long *parent_rate)
2733 {
2734         struct rt5682_priv *rt5682 =
2735                 container_of(hw, struct rt5682_priv,
2736                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2737         unsigned long factor;
2738
2739         if (!*parent_rate || !rt5682_clk_check(rt5682))
2740                 return -EINVAL;
2741
2742         /*
2743          * BCLK rates are set as a multiplier of WCLK in HW.
2744          * We don't allow changing the parent WCLK. We just do
2745          * some rounding down based on the parent WCLK rate
2746          * and find the appropriate multiplier of BCLK to
2747          * get the rounded down BCLK value.
2748          */
2749         factor = rt5682_bclk_get_factor(rate, *parent_rate);
2750
2751         return *parent_rate * factor;
2752 }
2753
2754 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2755                                 unsigned long parent_rate)
2756 {
2757         struct rt5682_priv *rt5682 =
2758                 container_of(hw, struct rt5682_priv,
2759                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2760         struct snd_soc_component *component = rt5682->component;
2761         struct snd_soc_dai *dai;
2762         unsigned long factor;
2763
2764         if (!rt5682_clk_check(rt5682))
2765                 return -EINVAL;
2766
2767         factor = rt5682_bclk_get_factor(rate, parent_rate);
2768
2769         for_each_component_dais(component, dai)
2770                 if (dai->id == RT5682_AIF1)
2771                         break;
2772         if (!dai) {
2773                 dev_err(component->dev, "dai %d not found in component\n",
2774                         RT5682_AIF1);
2775                 return -ENODEV;
2776         }
2777
2778         return rt5682_set_bclk1_ratio(dai, factor);
2779 }
2780
2781 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2782         [RT5682_DAI_WCLK_IDX] = {
2783                 .prepare = rt5682_wclk_prepare,
2784                 .unprepare = rt5682_wclk_unprepare,
2785                 .recalc_rate = rt5682_wclk_recalc_rate,
2786                 .round_rate = rt5682_wclk_round_rate,
2787                 .set_rate = rt5682_wclk_set_rate,
2788         },
2789         [RT5682_DAI_BCLK_IDX] = {
2790                 .recalc_rate = rt5682_bclk_recalc_rate,
2791                 .round_rate = rt5682_bclk_round_rate,
2792                 .set_rate = rt5682_bclk_set_rate,
2793         },
2794 };
2795
2796 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2797 {
2798         struct device *dev = component->dev;
2799         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2800         struct rt5682_platform_data *pdata = &rt5682->pdata;
2801         struct clk_hw *dai_clk_hw;
2802         int i, ret;
2803
2804         for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2805                 struct clk_init_data init = { };
2806
2807                 dai_clk_hw = &rt5682->dai_clks_hw[i];
2808
2809                 switch (i) {
2810                 case RT5682_DAI_WCLK_IDX:
2811                         /* Make MCLK the parent of WCLK */
2812                         if (rt5682->mclk) {
2813                                 init.parent_data = &(struct clk_parent_data){
2814                                         .fw_name = "mclk",
2815                                 };
2816                                 init.num_parents = 1;
2817                         }
2818                         break;
2819                 case RT5682_DAI_BCLK_IDX:
2820                         /* Make WCLK the parent of BCLK */
2821                         init.parent_hws = &(const struct clk_hw *){
2822                                 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]
2823                         };
2824                         init.num_parents = 1;
2825                         break;
2826                 default:
2827                         dev_err(dev, "Invalid clock index\n");
2828                         return -EINVAL;
2829                 }
2830
2831                 init.name = pdata->dai_clk_names[i];
2832                 init.ops = &rt5682_dai_clk_ops[i];
2833                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2834                 dai_clk_hw->init = &init;
2835
2836                 ret = devm_clk_hw_register(dev, dai_clk_hw);
2837                 if (ret) {
2838                         dev_warn(dev, "Failed to register %s: %d\n",
2839                                  init.name, ret);
2840                         return ret;
2841                 }
2842
2843                 if (dev->of_node) {
2844                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2845                                                     dai_clk_hw);
2846                 } else {
2847                         ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2848                                                           init.name,
2849                                                           dev_name(dev));
2850                         if (ret)
2851                                 return ret;
2852                 }
2853         }
2854
2855         return 0;
2856 }
2857 #endif /* CONFIG_COMMON_CLK */
2858
2859 static int rt5682_probe(struct snd_soc_component *component)
2860 {
2861         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2862         struct sdw_slave *slave;
2863         unsigned long time;
2864         struct snd_soc_dapm_context *dapm = &component->dapm;
2865
2866 #ifdef CONFIG_COMMON_CLK
2867         int ret;
2868 #endif
2869         rt5682->component = component;
2870
2871         if (rt5682->is_sdw) {
2872                 slave = rt5682->slave;
2873                 time = wait_for_completion_timeout(
2874                         &slave->initialization_complete,
2875                         msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2876                 if (!time) {
2877                         dev_err(&slave->dev, "Initialization not complete, timed out\n");
2878                         return -ETIMEDOUT;
2879                 }
2880         } else {
2881 #ifdef CONFIG_COMMON_CLK
2882                 /* Check if MCLK provided */
2883                 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2884                 if (IS_ERR(rt5682->mclk)) {
2885                         if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2886                                 ret = PTR_ERR(rt5682->mclk);
2887                                 return ret;
2888                         }
2889                         rt5682->mclk = NULL;
2890                 }
2891
2892                 /* Register CCF DAI clock control */
2893                 ret = rt5682_register_dai_clks(component);
2894                 if (ret)
2895                         return ret;
2896
2897                 /* Initial setup for CCF */
2898                 rt5682->lrck[RT5682_AIF1] = CLK_48;
2899 #endif
2900         }
2901
2902         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2903         snd_soc_dapm_disable_pin(dapm, "Vref2");
2904         snd_soc_dapm_sync(dapm);
2905         return 0;
2906 }
2907
2908 static void rt5682_remove(struct snd_soc_component *component)
2909 {
2910         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2911
2912         rt5682_reset(rt5682);
2913 }
2914
2915 #ifdef CONFIG_PM
2916 static int rt5682_suspend(struct snd_soc_component *component)
2917 {
2918         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2919
2920         if (rt5682->is_sdw)
2921                 return 0;
2922
2923         regcache_cache_only(rt5682->regmap, true);
2924         regcache_mark_dirty(rt5682->regmap);
2925         return 0;
2926 }
2927
2928 static int rt5682_resume(struct snd_soc_component *component)
2929 {
2930         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2931
2932         if (rt5682->is_sdw)
2933                 return 0;
2934
2935         regcache_cache_only(rt5682->regmap, false);
2936         regcache_sync(rt5682->regmap);
2937
2938         mod_delayed_work(system_power_efficient_wq,
2939                 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2940
2941         return 0;
2942 }
2943 #else
2944 #define rt5682_suspend NULL
2945 #define rt5682_resume NULL
2946 #endif
2947
2948 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2949         .hw_params = rt5682_hw_params,
2950         .set_fmt = rt5682_set_dai_fmt,
2951         .set_tdm_slot = rt5682_set_tdm_slot,
2952         .set_bclk_ratio = rt5682_set_bclk1_ratio,
2953 };
2954 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2955
2956 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2957         .hw_params = rt5682_hw_params,
2958         .set_fmt = rt5682_set_dai_fmt,
2959         .set_bclk_ratio = rt5682_set_bclk2_ratio,
2960 };
2961 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2962
2963 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2964         .probe = rt5682_probe,
2965         .remove = rt5682_remove,
2966         .suspend = rt5682_suspend,
2967         .resume = rt5682_resume,
2968         .set_bias_level = rt5682_set_bias_level,
2969         .controls = rt5682_snd_controls,
2970         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2971         .dapm_widgets = rt5682_dapm_widgets,
2972         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2973         .dapm_routes = rt5682_dapm_routes,
2974         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2975         .set_sysclk = rt5682_set_component_sysclk,
2976         .set_pll = rt5682_set_component_pll,
2977         .set_jack = rt5682_set_jack_detect,
2978         .use_pmdown_time        = 1,
2979         .endianness             = 1,
2980         .non_legacy_dai_naming  = 1,
2981 };
2982 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2983
2984 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2985 {
2986
2987         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2988                 &rt5682->pdata.dmic1_data_pin);
2989         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2990                 &rt5682->pdata.dmic1_clk_pin);
2991         device_property_read_u32(dev, "realtek,jd-src",
2992                 &rt5682->pdata.jd_src);
2993         device_property_read_u32(dev, "realtek,btndet-delay",
2994                 &rt5682->pdata.btndet_delay);
2995         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2996                 &rt5682->pdata.dmic_clk_rate);
2997         device_property_read_u32(dev, "realtek,dmic-delay-ms",
2998                 &rt5682->pdata.dmic_delay);
2999
3000         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3001                 "realtek,ldo1-en-gpios", 0);
3002
3003         if (device_property_read_string_array(dev, "clock-output-names",
3004                                               rt5682->pdata.dai_clk_names,
3005                                               RT5682_DAI_NUM_CLKS) < 0)
3006                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3007                          rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3008                          rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3009
3010         rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3011                 "realtek,dmic-clk-driving-high");
3012
3013         return 0;
3014 }
3015 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3016
3017 void rt5682_calibrate(struct rt5682_priv *rt5682)
3018 {
3019         int value, count;
3020
3021         mutex_lock(&rt5682->calibrate_mutex);
3022
3023         rt5682_reset(rt5682);
3024         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3025         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3026         usleep_range(15000, 20000);
3027         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3028         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3029         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3030         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3031         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3032         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3033         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3034         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3035         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3036         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3037         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3038         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3039         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3040         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3041         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3042
3043         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3044
3045         for (count = 0; count < 60; count++) {
3046                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3047                 if (!(value & 0x8000))
3048                         break;
3049
3050                 usleep_range(10000, 10005);
3051         }
3052
3053         if (count >= 60)
3054                 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3055
3056         /* restore settings */
3057         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3058         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3059         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3060         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3061         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3062         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3063         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3064         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3065
3066         mutex_unlock(&rt5682->calibrate_mutex);
3067 }
3068 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3069
3070 MODULE_DESCRIPTION("ASoC RT5682 driver");
3071 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3072 MODULE_LICENSE("GPL v2");