sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/acpi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/soc-dapm.h>
  34 #include <sound/initval.h>
  35 #include <sound/tlv.h>
  36 #include <dt-bindings/sound/cs42l42.h>
  37
  38 #include "cs42l42.h"
  39 #include "cirrus_legacy.h"
  40
  41 static const struct reg_default cs42l42_reg_defaults[] = {
  42         { CS42L42_FRZ_CTL,                      0x00 },
  43         { CS42L42_SRC_CTL,                      0x10 },
  44         { CS42L42_MCLK_STATUS,                  0x02 },
  45         { CS42L42_MCLK_CTL,                     0x02 },
  46         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  47         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  48         { CS42L42_I2C_STRETCH,                  0x03 },
  49         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  50         { CS42L42_PWR_CTL1,                     0xFF },
  51         { CS42L42_PWR_CTL2,                     0x84 },
  52         { CS42L42_PWR_CTL3,                     0x20 },
  53         { CS42L42_RSENSE_CTL1,                  0x40 },
  54         { CS42L42_RSENSE_CTL2,                  0x00 },
  55         { CS42L42_OSC_SWITCH,                   0x00 },
  56         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  57         { CS42L42_RSENSE_CTL3,                  0x1B },
  58         { CS42L42_TSENSE_CTL,                   0x1B },
  59         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  60         { CS42L42_TRSENSE_STATUS,               0x00 },
  61         { CS42L42_HSDET_CTL1,                   0x77 },
  62         { CS42L42_HSDET_CTL2,                   0x00 },
  63         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  64         { CS42L42_HS_DET_STATUS,                0x00 },
  65         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  66         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  67         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  68         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  69         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  70         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  71         { CS42L42_FSYNC_P_UPPER,                0x00 },
  72         { CS42L42_ASP_CLK_CFG,                  0x00 },
  73         { CS42L42_ASP_FRM_CFG,                  0x10 },
  74         { CS42L42_FS_RATE_EN,                   0x00 },
  75         { CS42L42_IN_ASRC_CLK,                  0x00 },
  76         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  77         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  78         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  79         { CS42L42_MIXER_STATUS,                 0x00 },
  80         { CS42L42_SRC_STATUS,                   0x00 },
  81         { CS42L42_ASP_RX_STATUS,                0x00 },
  82         { CS42L42_ASP_TX_STATUS,                0x00 },
  83         { CS42L42_CODEC_STATUS,                 0x00 },
  84         { CS42L42_DET_INT_STATUS1,              0x00 },
  85         { CS42L42_DET_INT_STATUS2,              0x00 },
  86         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  87         { CS42L42_VPMON_STATUS,                 0x00 },
  88         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  89         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  90         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  91         { CS42L42_MIXER_INT_MASK,               0x0F },
  92         { CS42L42_SRC_INT_MASK,                 0x0F },
  93         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  94         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  95         { CS42L42_CODEC_INT_MASK,               0x03 },
  96         { CS42L42_SRCPL_INT_MASK,               0xFF },
  97         { CS42L42_VPMON_INT_MASK,               0x01 },
  98         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  99         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
 100         { CS42L42_PLL_CTL1,                     0x00 },
 101         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 102         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 103         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 104         { CS42L42_PLL_DIV_INT,                  0x40 },
 105         { CS42L42_PLL_CTL3,                     0x10 },
 106         { CS42L42_PLL_CAL_RATIO,                0x80 },
 107         { CS42L42_PLL_CTL4,                     0x03 },
 108         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 109         { CS42L42_LOAD_DET_DONE,                0x00 },
 110         { CS42L42_LOAD_DET_EN,                  0x00 },
 111         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 112         { CS42L42_WAKE_CTL,                     0xC0 },
 113         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 114         { CS42L42_TIPSENSE_CTL,                 0x02 },
 115         { CS42L42_MISC_DET_CTL,                 0x03 },
 116         { CS42L42_MIC_DET_CTL1,                 0x1F },
 117         { CS42L42_MIC_DET_CTL2,                 0x2F },
 118         { CS42L42_DET_STATUS1,                  0x00 },
 119         { CS42L42_DET_STATUS2,                  0x00 },
 120         { CS42L42_DET_INT1_MASK,                0xE0 },
 121         { CS42L42_DET_INT2_MASK,                0xFF },
 122         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 123         { CS42L42_ADC_CTL,                      0x00 },
 124         { CS42L42_ADC_VOLUME,                   0x00 },
 125         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 126         { CS42L42_DAC_CTL1,                     0x00 },
 127         { CS42L42_DAC_CTL2,                     0x02 },
 128         { CS42L42_HP_CTL,                       0x0D },
 129         { CS42L42_CLASSH_CTL,                   0x07 },
 130         { CS42L42_MIXER_CHA_VOL,                0x3F },
 131         { CS42L42_MIXER_ADC_VOL,                0x3F },
 132         { CS42L42_MIXER_CHB_VOL,                0x3F },
 133         { CS42L42_EQ_COEF_IN0,                  0x22 },
 134         { CS42L42_EQ_COEF_IN1,                  0x00 },
 135         { CS42L42_EQ_COEF_IN2,                  0x00 },
 136         { CS42L42_EQ_COEF_IN3,                  0x00 },
 137         { CS42L42_EQ_COEF_RW,                   0x00 },
 138         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 139         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 140         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 141         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 142         { CS42L42_EQ_INIT_STAT,                 0x00 },
 143         { CS42L42_EQ_START_FILT,                0x00 },
 144         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 145         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 146         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 147         { CS42L42_SP_RX_FS,                     0x8C },
 148         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 149         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 150         { CS42L42_SP_TX_FS,                     0xCC },
 151         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 152         { CS42L42_SRC_SDIN_FS,                  0x40 },
 153         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 154         { CS42L42_SPDIF_CTL1,                   0x01 },
 155         { CS42L42_SPDIF_CTL2,                   0x00 },
 156         { CS42L42_SPDIF_CTL3,                   0x00 },
 157         { CS42L42_SPDIF_CTL4,                   0x42 },
 158         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 159         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 160         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 161         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 162         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 163         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 164         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 165         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 166         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 167         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 168         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 169         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 170         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 171         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 172         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 173         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 174         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 175         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 176         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 177         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 178         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 179         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 180         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 181         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 182         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 183         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 184         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 185         { CS42L42_SUB_REVID,                    0x03 },
 186 };
 187
 188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 189 {
 190         switch (reg) {
 191         case CS42L42_PAGE_REGISTER:
 192         case CS42L42_DEVID_AB:
 193         case CS42L42_DEVID_CD:
 194         case CS42L42_DEVID_E:
 195         case CS42L42_FABID:
 196         case CS42L42_REVID:
 197         case CS42L42_FRZ_CTL:
 198         case CS42L42_SRC_CTL:
 199         case CS42L42_MCLK_STATUS:
 200         case CS42L42_MCLK_CTL:
 201         case CS42L42_SFTRAMP_RATE:
 202         case CS42L42_I2C_DEBOUNCE:
 203         case CS42L42_I2C_STRETCH:
 204         case CS42L42_I2C_TIMEOUT:
 205         case CS42L42_PWR_CTL1:
 206         case CS42L42_PWR_CTL2:
 207         case CS42L42_PWR_CTL3:
 208         case CS42L42_RSENSE_CTL1:
 209         case CS42L42_RSENSE_CTL2:
 210         case CS42L42_OSC_SWITCH:
 211         case CS42L42_OSC_SWITCH_STATUS:
 212         case CS42L42_RSENSE_CTL3:
 213         case CS42L42_TSENSE_CTL:
 214         case CS42L42_TSRS_INT_DISABLE:
 215         case CS42L42_TRSENSE_STATUS:
 216         case CS42L42_HSDET_CTL1:
 217         case CS42L42_HSDET_CTL2:
 218         case CS42L42_HS_SWITCH_CTL:
 219         case CS42L42_HS_DET_STATUS:
 220         case CS42L42_HS_CLAMP_DISABLE:
 221         case CS42L42_MCLK_SRC_SEL:
 222         case CS42L42_SPDIF_CLK_CFG:
 223         case CS42L42_FSYNC_PW_LOWER:
 224         case CS42L42_FSYNC_PW_UPPER:
 225         case CS42L42_FSYNC_P_LOWER:
 226         case CS42L42_FSYNC_P_UPPER:
 227         case CS42L42_ASP_CLK_CFG:
 228         case CS42L42_ASP_FRM_CFG:
 229         case CS42L42_FS_RATE_EN:
 230         case CS42L42_IN_ASRC_CLK:
 231         case CS42L42_OUT_ASRC_CLK:
 232         case CS42L42_PLL_DIV_CFG1:
 233         case CS42L42_ADC_OVFL_STATUS:
 234         case CS42L42_MIXER_STATUS:
 235         case CS42L42_SRC_STATUS:
 236         case CS42L42_ASP_RX_STATUS:
 237         case CS42L42_ASP_TX_STATUS:
 238         case CS42L42_CODEC_STATUS:
 239         case CS42L42_DET_INT_STATUS1:
 240         case CS42L42_DET_INT_STATUS2:
 241         case CS42L42_SRCPL_INT_STATUS:
 242         case CS42L42_VPMON_STATUS:
 243         case CS42L42_PLL_LOCK_STATUS:
 244         case CS42L42_TSRS_PLUG_STATUS:
 245         case CS42L42_ADC_OVFL_INT_MASK:
 246         case CS42L42_MIXER_INT_MASK:
 247         case CS42L42_SRC_INT_MASK:
 248         case CS42L42_ASP_RX_INT_MASK:
 249         case CS42L42_ASP_TX_INT_MASK:
 250         case CS42L42_CODEC_INT_MASK:
 251         case CS42L42_SRCPL_INT_MASK:
 252         case CS42L42_VPMON_INT_MASK:
 253         case CS42L42_PLL_LOCK_INT_MASK:
 254         case CS42L42_TSRS_PLUG_INT_MASK:
 255         case CS42L42_PLL_CTL1:
 256         case CS42L42_PLL_DIV_FRAC0:
 257         case CS42L42_PLL_DIV_FRAC1:
 258         case CS42L42_PLL_DIV_FRAC2:
 259         case CS42L42_PLL_DIV_INT:
 260         case CS42L42_PLL_CTL3:
 261         case CS42L42_PLL_CAL_RATIO:
 262         case CS42L42_PLL_CTL4:
 263         case CS42L42_LOAD_DET_RCSTAT:
 264         case CS42L42_LOAD_DET_DONE:
 265         case CS42L42_LOAD_DET_EN:
 266         case CS42L42_HSBIAS_SC_AUTOCTL:
 267         case CS42L42_WAKE_CTL:
 268         case CS42L42_ADC_DISABLE_MUTE:
 269         case CS42L42_TIPSENSE_CTL:
 270         case CS42L42_MISC_DET_CTL:
 271         case CS42L42_MIC_DET_CTL1:
 272         case CS42L42_MIC_DET_CTL2:
 273         case CS42L42_DET_STATUS1:
 274         case CS42L42_DET_STATUS2:
 275         case CS42L42_DET_INT1_MASK:
 276         case CS42L42_DET_INT2_MASK:
 277         case CS42L42_HS_BIAS_CTL:
 278         case CS42L42_ADC_CTL:
 279         case CS42L42_ADC_VOLUME:
 280         case CS42L42_ADC_WNF_HPF_CTL:
 281         case CS42L42_DAC_CTL1:
 282         case CS42L42_DAC_CTL2:
 283         case CS42L42_HP_CTL:
 284         case CS42L42_CLASSH_CTL:
 285         case CS42L42_MIXER_CHA_VOL:
 286         case CS42L42_MIXER_ADC_VOL:
 287         case CS42L42_MIXER_CHB_VOL:
 288         case CS42L42_EQ_COEF_IN0:
 289         case CS42L42_EQ_COEF_IN1:
 290         case CS42L42_EQ_COEF_IN2:
 291         case CS42L42_EQ_COEF_IN3:
 292         case CS42L42_EQ_COEF_RW:
 293         case CS42L42_EQ_COEF_OUT0:
 294         case CS42L42_EQ_COEF_OUT1:
 295         case CS42L42_EQ_COEF_OUT2:
 296         case CS42L42_EQ_COEF_OUT3:
 297         case CS42L42_EQ_INIT_STAT:
 298         case CS42L42_EQ_START_FILT:
 299         case CS42L42_EQ_MUTE_CTL:
 300         case CS42L42_SP_RX_CH_SEL:
 301         case CS42L42_SP_RX_ISOC_CTL:
 302         case CS42L42_SP_RX_FS:
 303         case CS42l42_SPDIF_CH_SEL:
 304         case CS42L42_SP_TX_ISOC_CTL:
 305         case CS42L42_SP_TX_FS:
 306         case CS42L42_SPDIF_SW_CTL1:
 307         case CS42L42_SRC_SDIN_FS:
 308         case CS42L42_SRC_SDOUT_FS:
 309         case CS42L42_SPDIF_CTL1:
 310         case CS42L42_SPDIF_CTL2:
 311         case CS42L42_SPDIF_CTL3:
 312         case CS42L42_SPDIF_CTL4:
 313         case CS42L42_ASP_TX_SZ_EN:
 314         case CS42L42_ASP_TX_CH_EN:
 315         case CS42L42_ASP_TX_CH_AP_RES:
 316         case CS42L42_ASP_TX_CH1_BIT_MSB:
 317         case CS42L42_ASP_TX_CH1_BIT_LSB:
 318         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 319         case CS42L42_ASP_TX_CH2_BIT_MSB:
 320         case CS42L42_ASP_TX_CH2_BIT_LSB:
 321         case CS42L42_ASP_RX_DAI0_EN:
 322         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 323         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 324         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 325         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 326         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 327         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 328         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 329         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 330         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 331         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 332         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 333         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 334         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 335         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 336         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 337         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 338         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 339         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 340         case CS42L42_SUB_REVID:
 341                 return true;
 342         default:
 343                 return false;
 344         }
 345 }
 346
 347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 348 {
 349         switch (reg) {
 350         case CS42L42_DEVID_AB:
 351         case CS42L42_DEVID_CD:
 352         case CS42L42_DEVID_E:
 353         case CS42L42_MCLK_STATUS:
 354         case CS42L42_TRSENSE_STATUS:
 355         case CS42L42_HS_DET_STATUS:
 356         case CS42L42_ADC_OVFL_STATUS:
 357         case CS42L42_MIXER_STATUS:
 358         case CS42L42_SRC_STATUS:
 359         case CS42L42_ASP_RX_STATUS:
 360         case CS42L42_ASP_TX_STATUS:
 361         case CS42L42_CODEC_STATUS:
 362         case CS42L42_DET_INT_STATUS1:
 363         case CS42L42_DET_INT_STATUS2:
 364         case CS42L42_SRCPL_INT_STATUS:
 365         case CS42L42_VPMON_STATUS:
 366         case CS42L42_PLL_LOCK_STATUS:
 367         case CS42L42_TSRS_PLUG_STATUS:
 368         case CS42L42_LOAD_DET_RCSTAT:
 369         case CS42L42_LOAD_DET_DONE:
 370         case CS42L42_DET_STATUS1:
 371         case CS42L42_DET_STATUS2:
 372                 return true;
 373         default:
 374                 return false;
 375         }
 376 }
 377
 378 static const struct regmap_range_cfg cs42l42_page_range = {
 379         .name = "Pages",
 380         .range_min = 0,
 381         .range_max = CS42L42_MAX_REGISTER,
 382         .selector_reg = CS42L42_PAGE_REGISTER,
 383         .selector_mask = 0xff,
 384         .selector_shift = 0,
 385         .window_start = 0,
 386         .window_len = 256,
 387 };
 388
 389 static const struct regmap_config cs42l42_regmap = {
 390         .reg_bits = 8,
 391         .val_bits = 8,
 392
 393         .readable_reg = cs42l42_readable_register,
 394         .volatile_reg = cs42l42_volatile_register,
 395
 396         .ranges = &cs42l42_page_range,
 397         .num_ranges = 1,
 398
 399         .max_register = CS42L42_MAX_REGISTER,
 400         .reg_defaults = cs42l42_reg_defaults,
 401         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 402         .cache_type = REGCACHE_RBTREE,
 403
 404         .use_single_read = true,
 405         .use_single_write = true,
 406 };
 407
 408 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 409 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 410
 411 static const char * const cs42l42_hpf_freq_text[] = {
 412         "1.86Hz", "120Hz", "235Hz", "466Hz"
 413 };
 414
 415 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 416                             CS42L42_ADC_HPF_CF_SHIFT,
 417                             cs42l42_hpf_freq_text);
 418
 419 static const char * const cs42l42_wnf3_freq_text[] = {
 420         "160Hz", "180Hz", "200Hz", "220Hz",
 421         "240Hz", "260Hz", "280Hz", "300Hz"
 422 };
 423
 424 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 425                             CS42L42_ADC_WNF_CF_SHIFT,
 426                             cs42l42_wnf3_freq_text);
 427
 428 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 429         /* ADC Volume and Filter Controls */
 430         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 431                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 432         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 433                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 434         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 435                                 CS42L42_ADC_INV_SHIFT, true, false),
 436         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 437                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 438         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 439         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 440                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 441         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 442                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 443         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 444         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 445
 446         /* DAC Volume and Filter Controls */
 447         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 448                                 CS42L42_DACA_INV_SHIFT, true, false),
 449         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 450                                 CS42L42_DACB_INV_SHIFT, true, false),
 451         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 452                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 453         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 454                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 455                                 0x3f, 1, mixer_tlv)
 456 };
 457
 458 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 459         /* Playback Path */
 460         SND_SOC_DAPM_OUTPUT("HP"),
 461         SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1),
 462         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 463         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 464         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 465
 466         /* Playback Requirements */
 467         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 468
 469         /* Capture Path */
 470         SND_SOC_DAPM_INPUT("HS"),
 471         SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1),
 472         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 473         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 474
 475         /* Capture Requirements */
 476         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 477         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 478
 479         /* Playback/Capture Requirements */
 480         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 481 };
 482
 483 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 484         /* Playback Path */
 485         {"HP", NULL, "DAC"},
 486         {"DAC", NULL, "MIXER"},
 487         {"MIXER", NULL, "SDIN1"},
 488         {"MIXER", NULL, "SDIN2"},
 489         {"SDIN1", NULL, "Playback"},
 490         {"SDIN2", NULL, "Playback"},
 491
 492         /* Playback Requirements */
 493         {"SDIN1", NULL, "ASP DAI0"},
 494         {"SDIN2", NULL, "ASP DAI0"},
 495         {"SDIN1", NULL, "SCLK"},
 496         {"SDIN2", NULL, "SCLK"},
 497
 498         /* Capture Path */
 499         {"ADC", NULL, "HS"},
 500         { "SDOUT1", NULL, "ADC" },
 501         { "SDOUT2", NULL, "ADC" },
 502         { "Capture", NULL, "SDOUT1" },
 503         { "Capture", NULL, "SDOUT2" },
 504
 505         /* Capture Requirements */
 506         { "SDOUT1", NULL, "ASP DAO0" },
 507         { "SDOUT2", NULL, "ASP DAO0" },
 508         { "SDOUT1", NULL, "SCLK" },
 509         { "SDOUT2", NULL, "SCLK" },
 510         { "SDOUT1", NULL, "ASP TX EN" },
 511         { "SDOUT2", NULL, "ASP TX EN" },
 512 };
 513
 514 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 515 {
 516         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 517
 518         cs42l42->jack = jk;
 519
 520         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
 521                            CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK |
 522                            CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK,
 523                            (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) |
 524                            (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT));
 525
 526         return 0;
 527 }
 528
 529 static int cs42l42_component_probe(struct snd_soc_component *component)
 530 {
 531         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 532
 533         cs42l42->component = component;
 534
 535         return 0;
 536 }
 537
 538 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 539         .probe                  = cs42l42_component_probe,
 540         .set_jack               = cs42l42_set_jack,
 541         .dapm_widgets           = cs42l42_dapm_widgets,
 542         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 543         .dapm_routes            = cs42l42_audio_map,
 544         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 545         .controls               = cs42l42_snd_controls,
 546         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 547         .idle_bias_on           = 1,
 548         .endianness             = 1,
 549         .non_legacy_dai_naming  = 1,
 550 };
 551
 552 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 553 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 554         {
 555                 .reg = CS42L42_OSC_SWITCH,
 556                 .def = CS42L42_SCLK_PRESENT_MASK,
 557                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 558         },
 559 };
 560
 561 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 562 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 563         {
 564                 .reg = CS42L42_OSC_SWITCH,
 565                 .def = 0,
 566                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 567         },
 568 };
 569
 570 struct cs42l42_pll_params {
 571         u32 sclk;
 572         u8 mclk_div;
 573         u8 mclk_src_sel;
 574         u8 sclk_prediv;
 575         u8 pll_div_int;
 576         u32 pll_div_frac;
 577         u8 pll_mode;
 578         u8 pll_divout;
 579         u32 mclk_int;
 580         u8 pll_cal_ratio;
 581         u8 n;
 582 };
 583
 584 /*
 585  * Common PLL Settings for given SCLK
 586  * Table 4-5 from the Datasheet
 587  */
 588 static const struct cs42l42_pll_params pll_ratio_table[] = {
 589         { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 590         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 591         { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 592         { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 593         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 594         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 595         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 596         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 597         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 598         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 599         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 600         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 601         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 602         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 603         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 604         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1},
 605         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1},
 606         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1}
 607 };
 608
 609 static int cs42l42_pll_config(struct snd_soc_component *component)
 610 {
 611         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 612         int i;
 613         u32 clk;
 614         u32 fsync;
 615
 616         if (!cs42l42->sclk)
 617                 clk = cs42l42->bclk;
 618         else
 619                 clk = cs42l42->sclk;
 620
 621         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 622                 if (pll_ratio_table[i].sclk == clk) {
 623                         cs42l42->pll_config = i;
 624
 625                         /* Configure the internal sample rate */
 626                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 627                                         CS42L42_INTERNAL_FS_MASK,
 628                                         ((pll_ratio_table[i].mclk_int !=
 629                                         12000000) &&
 630                                         (pll_ratio_table[i].mclk_int !=
 631                                         24000000)) <<
 632                                         CS42L42_INTERNAL_FS_SHIFT);
 633
 634                         snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
 635                                         CS42L42_MCLKDIV_MASK,
 636                                         (pll_ratio_table[i].mclk_div <<
 637                                         CS42L42_MCLKDIV_SHIFT));
 638                         /* Set up the LRCLK */
 639                         fsync = clk / cs42l42->srate;
 640                         if (((fsync * cs42l42->srate) != clk)
 641                                 || ((fsync % 2) != 0)) {
 642                                 dev_err(component->dev,
 643                                         "Unsupported sclk %d/sample rate %d\n",
 644                                         clk,
 645                                         cs42l42->srate);
 646                                 return -EINVAL;
 647                         }
 648                         /* Set the LRCLK period */
 649                         snd_soc_component_update_bits(component,
 650                                         CS42L42_FSYNC_P_LOWER,
 651                                         CS42L42_FSYNC_PERIOD_MASK,
 652                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 653                                         CS42L42_FSYNC_PERIOD_SHIFT);
 654                         snd_soc_component_update_bits(component,
 655                                         CS42L42_FSYNC_P_UPPER,
 656                                         CS42L42_FSYNC_PERIOD_MASK,
 657                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 658                                         CS42L42_FSYNC_PERIOD_SHIFT);
 659                         /* Set the LRCLK to 50% duty cycle */
 660                         fsync = fsync / 2;
 661                         snd_soc_component_update_bits(component,
 662                                         CS42L42_FSYNC_PW_LOWER,
 663                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 664                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 665                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 666                         snd_soc_component_update_bits(component,
 667                                         CS42L42_FSYNC_PW_UPPER,
 668                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 669                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 670                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 671                         /* Set the sample rates (96k or lower) */
 672                         snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
 673                                         CS42L42_FS_EN_MASK,
 674                                         (CS42L42_FS_EN_IASRC_96K |
 675                                         CS42L42_FS_EN_OASRC_96K) <<
 676                                         CS42L42_FS_EN_SHIFT);
 677                         /* Set the input/output internal MCLK clock ~12 MHz */
 678                         snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
 679                                         CS42L42_CLK_IASRC_SEL_MASK,
 680                                         CS42L42_CLK_IASRC_SEL_12 <<
 681                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 682                         snd_soc_component_update_bits(component,
 683                                         CS42L42_OUT_ASRC_CLK,
 684                                         CS42L42_CLK_OASRC_SEL_MASK,
 685                                         CS42L42_CLK_OASRC_SEL_12 <<
 686                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 687                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 688                                 /* Pass the clock straight through */
 689                                 snd_soc_component_update_bits(component,
 690                                         CS42L42_PLL_CTL1,
 691                                         CS42L42_PLL_START_MASK, 0);
 692                         } else {
 693                                 /* Configure PLL per table 4-5 */
 694                                 snd_soc_component_update_bits(component,
 695                                         CS42L42_PLL_DIV_CFG1,
 696                                         CS42L42_SCLK_PREDIV_MASK,
 697                                         pll_ratio_table[i].sclk_prediv
 698                                         << CS42L42_SCLK_PREDIV_SHIFT);
 699                                 snd_soc_component_update_bits(component,
 700                                         CS42L42_PLL_DIV_INT,
 701                                         CS42L42_PLL_DIV_INT_MASK,
 702                                         pll_ratio_table[i].pll_div_int
 703                                         << CS42L42_PLL_DIV_INT_SHIFT);
 704                                 snd_soc_component_update_bits(component,
 705                                         CS42L42_PLL_DIV_FRAC0,
 706                                         CS42L42_PLL_DIV_FRAC_MASK,
 707                                         CS42L42_FRAC0_VAL(
 708                                         pll_ratio_table[i].pll_div_frac)
 709                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 710                                 snd_soc_component_update_bits(component,
 711                                         CS42L42_PLL_DIV_FRAC1,
 712                                         CS42L42_PLL_DIV_FRAC_MASK,
 713                                         CS42L42_FRAC1_VAL(
 714                                         pll_ratio_table[i].pll_div_frac)
 715                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 716                                 snd_soc_component_update_bits(component,
 717                                         CS42L42_PLL_DIV_FRAC2,
 718                                         CS42L42_PLL_DIV_FRAC_MASK,
 719                                         CS42L42_FRAC2_VAL(
 720                                         pll_ratio_table[i].pll_div_frac)
 721                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 722                                 snd_soc_component_update_bits(component,
 723                                         CS42L42_PLL_CTL4,
 724                                         CS42L42_PLL_MODE_MASK,
 725                                         pll_ratio_table[i].pll_mode
 726                                         << CS42L42_PLL_MODE_SHIFT);
 727                                 snd_soc_component_update_bits(component,
 728                                         CS42L42_PLL_CTL3,
 729                                         CS42L42_PLL_DIVOUT_MASK,
 730                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 731                                         << CS42L42_PLL_DIVOUT_SHIFT);
 732                                 if (pll_ratio_table[i].n != 1)
 733                                         cs42l42->pll_divout = pll_ratio_table[i].pll_divout;
 734                                 else
 735                                         cs42l42->pll_divout = 0;
 736                                 snd_soc_component_update_bits(component,
 737                                         CS42L42_PLL_CAL_RATIO,
 738                                         CS42L42_PLL_CAL_RATIO_MASK,
 739                                         pll_ratio_table[i].pll_cal_ratio
 740                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 741                         }
 742                         return 0;
 743                 }
 744         }
 745
 746         return -EINVAL;
 747 }
 748
 749 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 750 {
 751         struct snd_soc_component *component = codec_dai->component;
 752         u32 asp_cfg_val = 0;
 753
 754         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 755         case SND_SOC_DAIFMT_CBS_CFM:
 756                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 757                                 CS42L42_ASP_MODE_SHIFT;
 758                 break;
 759         case SND_SOC_DAIFMT_CBS_CFS:
 760                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 761                                 CS42L42_ASP_MODE_SHIFT;
 762                 break;
 763         default:
 764                 return -EINVAL;
 765         }
 766
 767         /* interface format */
 768         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 769         case SND_SOC_DAIFMT_I2S:
 770                 /*
 771                  * 5050 mode, frame starts on falling edge of LRCLK,
 772                  * frame delayed by 1.0 SCLKs
 773                  */
 774                 snd_soc_component_update_bits(component,
 775                                               CS42L42_ASP_FRM_CFG,
 776                                               CS42L42_ASP_STP_MASK |
 777                                               CS42L42_ASP_5050_MASK |
 778                                               CS42L42_ASP_FSD_MASK,
 779                                               CS42L42_ASP_5050_MASK |
 780                                               (CS42L42_ASP_FSD_1_0 <<
 781                                                 CS42L42_ASP_FSD_SHIFT));
 782                 break;
 783         default:
 784                 return -EINVAL;
 785         }
 786
 787         /* Bitclock/frame inversion */
 788         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 789         case SND_SOC_DAIFMT_NB_NF:
 790                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 791                 break;
 792         case SND_SOC_DAIFMT_NB_IF:
 793                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 794                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 795                 break;
 796         case SND_SOC_DAIFMT_IB_NF:
 797                 break;
 798         case SND_SOC_DAIFMT_IB_IF:
 799                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 800                 break;
 801         }
 802
 803         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 804                                                                       CS42L42_ASP_SCPOL_MASK |
 805                                                                       CS42L42_ASP_LCPOL_MASK,
 806                                                                       asp_cfg_val);
 807
 808         return 0;
 809 }
 810
 811 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 812 {
 813         struct snd_soc_component *component = dai->component;
 814         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 815
 816         /*
 817          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 818          * a standard I2S frame. If the machine driver sets SCLK it must be
 819          * legal.
 820          */
 821         if (cs42l42->sclk)
 822                 return 0;
 823
 824         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 825         return snd_pcm_hw_constraint_minmax(substream->runtime,
 826                                             SNDRV_PCM_HW_PARAM_RATE,
 827                                             44100, 192000);
 828 }
 829
 830 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 831                                 struct snd_pcm_hw_params *params,
 832                                 struct snd_soc_dai *dai)
 833 {
 834         struct snd_soc_component *component = dai->component;
 835         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 836         unsigned int channels = params_channels(params);
 837         unsigned int width = (params_width(params) / 8) - 1;
 838         unsigned int val = 0;
 839
 840         cs42l42->srate = params_rate(params);
 841         cs42l42->bclk = snd_soc_params_to_bclk(params);
 842
 843         /* I2S frame always has 2 channels even for mono audio */
 844         if (channels == 1)
 845                 cs42l42->bclk *= 2;
 846
 847         /*
 848          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 849          * more than assumed (which would result in overclocking).
 850          */
 851         if (params_width(params) == 24)
 852                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 853
 854         switch(substream->stream) {
 855         case SNDRV_PCM_STREAM_CAPTURE:
 856                 if (channels == 2) {
 857                         val |= CS42L42_ASP_TX_CH2_AP_MASK;
 858                         val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT;
 859                 }
 860                 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT;
 861
 862                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 863                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 864                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 865                 break;
 866         case SNDRV_PCM_STREAM_PLAYBACK:
 867                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 868                 /* channel 1 on low LRCLK */
 869                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 870                                                          CS42L42_ASP_RX_CH_AP_MASK |
 871                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 872                 /* Channel 2 on high LRCLK */
 873                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 874                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 875                                                          CS42L42_ASP_RX_CH_AP_MASK |
 876                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 877
 878                 /* Channel B comes from the last active channel */
 879                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 880                                               CS42L42_SP_RX_CHB_SEL_MASK,
 881                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 882
 883                 /* Both LRCLK slots must be enabled */
 884                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 885                                               CS42L42_ASP_RX0_CH_EN_MASK,
 886                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 887                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 888                 break;
 889         default:
 890                 break;
 891         }
 892
 893         return cs42l42_pll_config(component);
 894 }
 895
 896 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 897                                 int clk_id, unsigned int freq, int dir)
 898 {
 899         struct snd_soc_component *component = dai->component;
 900         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 901         int i;
 902
 903         if (freq == 0) {
 904                 cs42l42->sclk = 0;
 905                 return 0;
 906         }
 907
 908         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 909                 if (pll_ratio_table[i].sclk == freq) {
 910                         cs42l42->sclk = freq;
 911                         return 0;
 912                 }
 913         }
 914
 915         dev_err(component->dev, "SCLK %u not supported\n", freq);
 916
 917         return -EINVAL;
 918 }
 919
 920 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 921 {
 922         struct snd_soc_component *component = dai->component;
 923         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 924         unsigned int regval;
 925         u8 fullScaleVol;
 926         int ret;
 927
 928         if (mute) {
 929                 /* Mute the headphone */
 930                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 931                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 932                                                       CS42L42_HP_ANA_AMUTE_MASK |
 933                                                       CS42L42_HP_ANA_BMUTE_MASK,
 934                                                       CS42L42_HP_ANA_AMUTE_MASK |
 935                                                       CS42L42_HP_ANA_BMUTE_MASK);
 936
 937                 cs42l42->stream_use &= ~(1 << stream);
 938                 if(!cs42l42->stream_use) {
 939                         /*
 940                          * Switch to the internal oscillator.
 941                          * SCLK must remain running until after this clock switch.
 942                          * Without a source of clock the I2C bus doesn't work.
 943                          */
 944                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
 945                                                ARRAY_SIZE(cs42l42_to_osc_seq));
 946
 947                         /* Must disconnect PLL before stopping it */
 948                         snd_soc_component_update_bits(component,
 949                                                       CS42L42_MCLK_SRC_SEL,
 950                                                       CS42L42_MCLK_SRC_SEL_MASK,
 951                                                       0);
 952                         usleep_range(100, 200);
 953
 954                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 955                                                       CS42L42_PLL_START_MASK, 0);
 956                 }
 957         } else {
 958                 if (!cs42l42->stream_use) {
 959                         /* SCLK must be running before codec unmute */
 960                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
 961                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 962                                                               CS42L42_PLL_START_MASK, 1);
 963
 964                                 if (cs42l42->pll_divout) {
 965                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
 966                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
 967                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
 968                                                                       CS42L42_PLL_DIVOUT_MASK,
 969                                                                       cs42l42->pll_divout <<
 970                                                                       CS42L42_PLL_DIVOUT_SHIFT);
 971                                 }
 972
 973                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
 974                                                                CS42L42_PLL_LOCK_STATUS,
 975                                                                regval,
 976                                                                (regval & 1),
 977                                                                CS42L42_PLL_LOCK_POLL_US,
 978                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
 979                                 if (ret < 0)
 980                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
 981
 982                                 /* PLL must be running to drive glitchless switch logic */
 983                                 snd_soc_component_update_bits(component,
 984                                                               CS42L42_MCLK_SRC_SEL,
 985                                                               CS42L42_MCLK_SRC_SEL_MASK,
 986                                                               CS42L42_MCLK_SRC_SEL_MASK);
 987                         }
 988
 989                         /* Mark SCLK as present, turn off internal oscillator */
 990                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
 991                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
 992                 }
 993                 cs42l42->stream_use |= 1 << stream;
 994
 995                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 996                         /* Read the headphone load */
 997                         regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
 998                         if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) ==
 999                             CS42L42_RLA_STAT_15_OHM) {
1000                                 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
1001                         } else {
1002                                 fullScaleVol = 0;
1003                         }
1004
1005                         /* Un-mute the headphone, set the full scale volume flag */
1006                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1007                                                       CS42L42_HP_ANA_AMUTE_MASK |
1008                                                       CS42L42_HP_ANA_BMUTE_MASK |
1009                                                       CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
1010                 }
1011         }
1012
1013         return 0;
1014 }
1015
1016 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1017                          SNDRV_PCM_FMTBIT_S24_LE |\
1018                          SNDRV_PCM_FMTBIT_S32_LE )
1019
1020 static const struct snd_soc_dai_ops cs42l42_ops = {
1021         .startup        = cs42l42_dai_startup,
1022         .hw_params      = cs42l42_pcm_hw_params,
1023         .set_fmt        = cs42l42_set_dai_fmt,
1024         .set_sysclk     = cs42l42_set_sysclk,
1025         .mute_stream    = cs42l42_mute_stream,
1026 };
1027
1028 static struct snd_soc_dai_driver cs42l42_dai = {
1029                 .name = "cs42l42",
1030                 .playback = {
1031                         .stream_name = "Playback",
1032                         .channels_min = 1,
1033                         .channels_max = 2,
1034                         .rates = SNDRV_PCM_RATE_8000_192000,
1035                         .formats = CS42L42_FORMATS,
1036                 },
1037                 .capture = {
1038                         .stream_name = "Capture",
1039                         .channels_min = 1,
1040                         .channels_max = 2,
1041                         .rates = SNDRV_PCM_RATE_8000_192000,
1042                         .formats = CS42L42_FORMATS,
1043                 },
1044                 .symmetric_rate = 1,
1045                 .symmetric_sample_bits = 1,
1046                 .ops = &cs42l42_ops,
1047 };
1048
1049 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1050 {
1051         unsigned int hs_det_status;
1052         unsigned int int_status;
1053
1054         /* Mask the auto detect interrupt */
1055         regmap_update_bits(cs42l42->regmap,
1056                 CS42L42_CODEC_INT_MASK,
1057                 CS42L42_PDN_DONE_MASK |
1058                 CS42L42_HSDET_AUTO_DONE_MASK,
1059                 (1 << CS42L42_PDN_DONE_SHIFT) |
1060                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1061
1062         /* Set hs detect to automatic, disabled mode */
1063         regmap_update_bits(cs42l42->regmap,
1064                 CS42L42_HSDET_CTL2,
1065                 CS42L42_HSDET_CTRL_MASK |
1066                 CS42L42_HSDET_SET_MASK |
1067                 CS42L42_HSBIAS_REF_MASK |
1068                 CS42L42_HSDET_AUTO_TIME_MASK,
1069                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1070                 (2 << CS42L42_HSDET_SET_SHIFT) |
1071                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1072                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1073
1074         /* Read and save the hs detection result */
1075         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1076
1077         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1078                                 CS42L42_HSDET_TYPE_SHIFT;
1079
1080         /* Set up button detection */
1081         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1082               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1083                 /* Set auto HS bias settings to default */
1084                 regmap_update_bits(cs42l42->regmap,
1085                         CS42L42_HSBIAS_SC_AUTOCTL,
1086                         CS42L42_HSBIAS_SENSE_EN_MASK |
1087                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1088                         CS42L42_TIP_SENSE_EN_MASK |
1089                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1090                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1091                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1092                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1093                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1094
1095                 /* Set up hs detect level sensitivity */
1096                 regmap_update_bits(cs42l42->regmap,
1097                         CS42L42_MIC_DET_CTL1,
1098                         CS42L42_LATCH_TO_VP_MASK |
1099                         CS42L42_EVENT_STAT_SEL_MASK |
1100                         CS42L42_HS_DET_LEVEL_MASK,
1101                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1102                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1103                         (cs42l42->bias_thresholds[0] <<
1104                         CS42L42_HS_DET_LEVEL_SHIFT));
1105
1106                 /* Set auto HS bias settings to default */
1107                 regmap_update_bits(cs42l42->regmap,
1108                         CS42L42_HSBIAS_SC_AUTOCTL,
1109                         CS42L42_HSBIAS_SENSE_EN_MASK |
1110                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1111                         CS42L42_TIP_SENSE_EN_MASK |
1112                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1113                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1114                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1115                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1116                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1117
1118                 /* Turn on level detect circuitry */
1119                 regmap_update_bits(cs42l42->regmap,
1120                         CS42L42_MISC_DET_CTL,
1121                         CS42L42_DETECT_MODE_MASK |
1122                         CS42L42_HSBIAS_CTL_MASK |
1123                         CS42L42_PDN_MIC_LVL_DET_MASK,
1124                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1125                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1126                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1127
1128                 msleep(cs42l42->btn_det_init_dbnce);
1129
1130                 /* Clear any button interrupts before unmasking them */
1131                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1132                             &int_status);
1133
1134                 /* Unmask button detect interrupts */
1135                 regmap_update_bits(cs42l42->regmap,
1136                         CS42L42_DET_INT2_MASK,
1137                         CS42L42_M_DETECT_TF_MASK |
1138                         CS42L42_M_DETECT_FT_MASK |
1139                         CS42L42_M_HSBIAS_HIZ_MASK |
1140                         CS42L42_M_SHORT_RLS_MASK |
1141                         CS42L42_M_SHORT_DET_MASK,
1142                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1143                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1144                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1145                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1146                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1147         } else {
1148                 /* Make sure button detect and HS bias circuits are off */
1149                 regmap_update_bits(cs42l42->regmap,
1150                         CS42L42_MISC_DET_CTL,
1151                         CS42L42_DETECT_MODE_MASK |
1152                         CS42L42_HSBIAS_CTL_MASK |
1153                         CS42L42_PDN_MIC_LVL_DET_MASK,
1154                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1155                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1156                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1157         }
1158
1159         regmap_update_bits(cs42l42->regmap,
1160                                 CS42L42_DAC_CTL2,
1161                                 CS42L42_HPOUT_PULLDOWN_MASK |
1162                                 CS42L42_HPOUT_LOAD_MASK |
1163                                 CS42L42_HPOUT_CLAMP_MASK |
1164                                 CS42L42_DAC_HPF_EN_MASK |
1165                                 CS42L42_DAC_MON_EN_MASK,
1166                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1167                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1168                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1169                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1170                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1171
1172         /* Unmask tip sense interrupts */
1173         regmap_update_bits(cs42l42->regmap,
1174                 CS42L42_TSRS_PLUG_INT_MASK,
1175                 CS42L42_RS_PLUG_MASK |
1176                 CS42L42_RS_UNPLUG_MASK |
1177                 CS42L42_TS_PLUG_MASK |
1178                 CS42L42_TS_UNPLUG_MASK,
1179                 (1 << CS42L42_RS_PLUG_SHIFT) |
1180                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1181                 (0 << CS42L42_TS_PLUG_SHIFT) |
1182                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1183 }
1184
1185 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1186 {
1187         /* Mask tip sense interrupts */
1188         regmap_update_bits(cs42l42->regmap,
1189                                 CS42L42_TSRS_PLUG_INT_MASK,
1190                                 CS42L42_RS_PLUG_MASK |
1191                                 CS42L42_RS_UNPLUG_MASK |
1192                                 CS42L42_TS_PLUG_MASK |
1193                                 CS42L42_TS_UNPLUG_MASK,
1194                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1195                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1196                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1197                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1198
1199         /* Make sure button detect and HS bias circuits are off */
1200         regmap_update_bits(cs42l42->regmap,
1201                                 CS42L42_MISC_DET_CTL,
1202                                 CS42L42_DETECT_MODE_MASK |
1203                                 CS42L42_HSBIAS_CTL_MASK |
1204                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1205                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1206                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1207                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1208
1209         /* Set auto HS bias settings to default */
1210         regmap_update_bits(cs42l42->regmap,
1211                                 CS42L42_HSBIAS_SC_AUTOCTL,
1212                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1213                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1214                                 CS42L42_TIP_SENSE_EN_MASK |
1215                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1216                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1217                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1218                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1219                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1220
1221         /* Set hs detect to manual, disabled mode */
1222         regmap_update_bits(cs42l42->regmap,
1223                                 CS42L42_HSDET_CTL2,
1224                                 CS42L42_HSDET_CTRL_MASK |
1225                                 CS42L42_HSDET_SET_MASK |
1226                                 CS42L42_HSBIAS_REF_MASK |
1227                                 CS42L42_HSDET_AUTO_TIME_MASK,
1228                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1229                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1230                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1231                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1232
1233         regmap_update_bits(cs42l42->regmap,
1234                                 CS42L42_DAC_CTL2,
1235                                 CS42L42_HPOUT_PULLDOWN_MASK |
1236                                 CS42L42_HPOUT_LOAD_MASK |
1237                                 CS42L42_HPOUT_CLAMP_MASK |
1238                                 CS42L42_DAC_HPF_EN_MASK |
1239                                 CS42L42_DAC_MON_EN_MASK,
1240                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1241                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1242                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1243                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1244                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1245
1246         /* Power up HS bias to 2.7V */
1247         regmap_update_bits(cs42l42->regmap,
1248                                 CS42L42_MISC_DET_CTL,
1249                                 CS42L42_DETECT_MODE_MASK |
1250                                 CS42L42_HSBIAS_CTL_MASK |
1251                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1252                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1253                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1254                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1255
1256         /* Wait for HS bias to ramp up */
1257         msleep(cs42l42->hs_bias_ramp_time);
1258
1259         /* Unmask auto detect interrupt */
1260         regmap_update_bits(cs42l42->regmap,
1261                                 CS42L42_CODEC_INT_MASK,
1262                                 CS42L42_PDN_DONE_MASK |
1263                                 CS42L42_HSDET_AUTO_DONE_MASK,
1264                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1265                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1266
1267         /* Set hs detect to automatic, enabled mode */
1268         regmap_update_bits(cs42l42->regmap,
1269                                 CS42L42_HSDET_CTL2,
1270                                 CS42L42_HSDET_CTRL_MASK |
1271                                 CS42L42_HSDET_SET_MASK |
1272                                 CS42L42_HSBIAS_REF_MASK |
1273                                 CS42L42_HSDET_AUTO_TIME_MASK,
1274                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1275                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1276                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1277                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1278 }
1279
1280 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1281 {
1282         /* Mask button detect interrupts */
1283         regmap_update_bits(cs42l42->regmap,
1284                 CS42L42_DET_INT2_MASK,
1285                 CS42L42_M_DETECT_TF_MASK |
1286                 CS42L42_M_DETECT_FT_MASK |
1287                 CS42L42_M_HSBIAS_HIZ_MASK |
1288                 CS42L42_M_SHORT_RLS_MASK |
1289                 CS42L42_M_SHORT_DET_MASK,
1290                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1291                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1292                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1293                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1294                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1295
1296         /* Ground HS bias */
1297         regmap_update_bits(cs42l42->regmap,
1298                                 CS42L42_MISC_DET_CTL,
1299                                 CS42L42_DETECT_MODE_MASK |
1300                                 CS42L42_HSBIAS_CTL_MASK |
1301                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1302                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1303                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1304                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1305
1306         /* Set auto HS bias settings to default */
1307         regmap_update_bits(cs42l42->regmap,
1308                                 CS42L42_HSBIAS_SC_AUTOCTL,
1309                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1310                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1311                                 CS42L42_TIP_SENSE_EN_MASK |
1312                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1313                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1314                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1315                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1316                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1317
1318         /* Set hs detect to manual, disabled mode */
1319         regmap_update_bits(cs42l42->regmap,
1320                                 CS42L42_HSDET_CTL2,
1321                                 CS42L42_HSDET_CTRL_MASK |
1322                                 CS42L42_HSDET_SET_MASK |
1323                                 CS42L42_HSBIAS_REF_MASK |
1324                                 CS42L42_HSDET_AUTO_TIME_MASK,
1325                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1326                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1327                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1328                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1329 }
1330
1331 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1332 {
1333         int bias_level;
1334         unsigned int detect_status;
1335
1336         /* Mask button detect interrupts */
1337         regmap_update_bits(cs42l42->regmap,
1338                 CS42L42_DET_INT2_MASK,
1339                 CS42L42_M_DETECT_TF_MASK |
1340                 CS42L42_M_DETECT_FT_MASK |
1341                 CS42L42_M_HSBIAS_HIZ_MASK |
1342                 CS42L42_M_SHORT_RLS_MASK |
1343                 CS42L42_M_SHORT_DET_MASK,
1344                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1345                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1346                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1347                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1348                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1349
1350         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1351                      cs42l42->btn_det_event_dbnce * 2000);
1352
1353         /* Test all 4 level detect biases */
1354         bias_level = 1;
1355         do {
1356                 /* Adjust button detect level sensitivity */
1357                 regmap_update_bits(cs42l42->regmap,
1358                         CS42L42_MIC_DET_CTL1,
1359                         CS42L42_LATCH_TO_VP_MASK |
1360                         CS42L42_EVENT_STAT_SEL_MASK |
1361                         CS42L42_HS_DET_LEVEL_MASK,
1362                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1363                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1364                         (cs42l42->bias_thresholds[bias_level] <<
1365                         CS42L42_HS_DET_LEVEL_SHIFT));
1366
1367                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1368                                 &detect_status);
1369         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1370                 (++bias_level < CS42L42_NUM_BIASES));
1371
1372         switch (bias_level) {
1373         case 1: /* Function C button press */
1374                 bias_level = SND_JACK_BTN_2;
1375                 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1376                 break;
1377         case 2: /* Function B button press */
1378                 bias_level = SND_JACK_BTN_1;
1379                 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1380                 break;
1381         case 3: /* Function D button press */
1382                 bias_level = SND_JACK_BTN_3;
1383                 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1384                 break;
1385         case 4: /* Function A button press */
1386                 bias_level = SND_JACK_BTN_0;
1387                 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1388                 break;
1389         default:
1390                 bias_level = 0;
1391                 break;
1392         }
1393
1394         /* Set button detect level sensitivity back to default */
1395         regmap_update_bits(cs42l42->regmap,
1396                 CS42L42_MIC_DET_CTL1,
1397                 CS42L42_LATCH_TO_VP_MASK |
1398                 CS42L42_EVENT_STAT_SEL_MASK |
1399                 CS42L42_HS_DET_LEVEL_MASK,
1400                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1401                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1402                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1403
1404         /* Clear any button interrupts before unmasking them */
1405         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1406                     &detect_status);
1407
1408         /* Unmask button detect interrupts */
1409         regmap_update_bits(cs42l42->regmap,
1410                 CS42L42_DET_INT2_MASK,
1411                 CS42L42_M_DETECT_TF_MASK |
1412                 CS42L42_M_DETECT_FT_MASK |
1413                 CS42L42_M_HSBIAS_HIZ_MASK |
1414                 CS42L42_M_SHORT_RLS_MASK |
1415                 CS42L42_M_SHORT_DET_MASK,
1416                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1417                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1418                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1419                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1420                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1421
1422         return bias_level;
1423 }
1424
1425 struct cs42l42_irq_params {
1426         u16 status_addr;
1427         u16 mask_addr;
1428         u8 mask;
1429 };
1430
1431 static const struct cs42l42_irq_params irq_params_table[] = {
1432         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1433                 CS42L42_ADC_OVFL_VAL_MASK},
1434         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1435                 CS42L42_MIXER_VAL_MASK},
1436         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1437                 CS42L42_SRC_VAL_MASK},
1438         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1439                 CS42L42_ASP_RX_VAL_MASK},
1440         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1441                 CS42L42_ASP_TX_VAL_MASK},
1442         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1443                 CS42L42_CODEC_VAL_MASK},
1444         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1445                 CS42L42_DET_INT_VAL1_MASK},
1446         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1447                 CS42L42_DET_INT_VAL2_MASK},
1448         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1449                 CS42L42_SRCPL_VAL_MASK},
1450         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1451                 CS42L42_VPMON_VAL_MASK},
1452         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1453                 CS42L42_PLL_LOCK_VAL_MASK},
1454         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1455                 CS42L42_TSRS_PLUG_VAL_MASK}
1456 };
1457
1458 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1459 {
1460         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1461         struct snd_soc_component *component = cs42l42->component;
1462         unsigned int stickies[12];
1463         unsigned int masks[12];
1464         unsigned int current_plug_status;
1465         unsigned int current_button_status;
1466         unsigned int i;
1467         int report = 0;
1468
1469
1470         /* Read sticky registers to clear interurpt */
1471         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1472                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1473                                 &(stickies[i]));
1474                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1475                                 &(masks[i]));
1476                 stickies[i] = stickies[i] & (~masks[i]) &
1477                                 irq_params_table[i].mask;
1478         }
1479
1480         /* Read tip sense status before handling type detect */
1481         current_plug_status = (stickies[11] &
1482                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1483                 CS42L42_TS_PLUG_SHIFT;
1484
1485         /* Read button sense status */
1486         current_button_status = stickies[7] &
1487                 (CS42L42_M_DETECT_TF_MASK |
1488                 CS42L42_M_DETECT_FT_MASK |
1489                 CS42L42_M_HSBIAS_HIZ_MASK);
1490
1491         /* Check auto-detect status */
1492         if ((~masks[5]) & irq_params_table[5].mask) {
1493                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1494                         cs42l42_process_hs_type_detect(cs42l42);
1495                         switch(cs42l42->hs_type){
1496                         case CS42L42_PLUG_CTIA:
1497                         case CS42L42_PLUG_OMTP:
1498                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1499                                                     SND_JACK_HEADSET);
1500                                 break;
1501                         case CS42L42_PLUG_HEADPHONE:
1502                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1503                                                     SND_JACK_HEADPHONE);
1504                                 break;
1505                         default:
1506                                 break;
1507                         }
1508                         dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1509                 }
1510         }
1511
1512         /* Check tip sense status */
1513         if ((~masks[11]) & irq_params_table[11].mask) {
1514                 switch (current_plug_status) {
1515                 case CS42L42_TS_PLUG:
1516                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1517                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1518                                 cs42l42_init_hs_type_detect(cs42l42);
1519                         }
1520                         break;
1521
1522                 case CS42L42_TS_UNPLUG:
1523                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1524                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1525                                 cs42l42_cancel_hs_type_detect(cs42l42);
1526
1527                                 switch(cs42l42->hs_type){
1528                                 case CS42L42_PLUG_CTIA:
1529                                 case CS42L42_PLUG_OMTP:
1530                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1531                                         break;
1532                                 case CS42L42_PLUG_HEADPHONE:
1533                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1534                                         break;
1535                                 default:
1536                                         break;
1537                                 }
1538                                 snd_soc_jack_report(cs42l42->jack, 0,
1539                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1540                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1541
1542                                 dev_dbg(component->dev, "Unplug event\n");
1543                         }
1544                         break;
1545
1546                 default:
1547                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1548                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1549                 }
1550         }
1551
1552         /* Check button detect status */
1553         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1554                 if (!(current_button_status &
1555                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1556
1557                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1558                                 dev_dbg(component->dev, "Button released\n");
1559                                 report = 0;
1560                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1561                                 report = cs42l42_handle_button_press(cs42l42);
1562
1563                         }
1564                         snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1565                                                                    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1566                 }
1567         }
1568
1569         return IRQ_HANDLED;
1570 }
1571
1572 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1573 {
1574         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1575                         CS42L42_ADC_OVFL_MASK,
1576                         (1 << CS42L42_ADC_OVFL_SHIFT));
1577
1578         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1579                         CS42L42_MIX_CHB_OVFL_MASK |
1580                         CS42L42_MIX_CHA_OVFL_MASK |
1581                         CS42L42_EQ_OVFL_MASK |
1582                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1583                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1584                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1585                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1586                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1587
1588         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1589                         CS42L42_SRC_ILK_MASK |
1590                         CS42L42_SRC_OLK_MASK |
1591                         CS42L42_SRC_IUNLK_MASK |
1592                         CS42L42_SRC_OUNLK_MASK,
1593                         (1 << CS42L42_SRC_ILK_SHIFT) |
1594                         (1 << CS42L42_SRC_OLK_SHIFT) |
1595                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1596                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1597
1598         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1599                         CS42L42_ASPRX_NOLRCK_MASK |
1600                         CS42L42_ASPRX_EARLY_MASK |
1601                         CS42L42_ASPRX_LATE_MASK |
1602                         CS42L42_ASPRX_ERROR_MASK |
1603                         CS42L42_ASPRX_OVLD_MASK,
1604                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1605                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1606                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1607                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1608                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1609
1610         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1611                         CS42L42_ASPTX_NOLRCK_MASK |
1612                         CS42L42_ASPTX_EARLY_MASK |
1613                         CS42L42_ASPTX_LATE_MASK |
1614                         CS42L42_ASPTX_SMERROR_MASK,
1615                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1616                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1617                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1618                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1619
1620         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1621                         CS42L42_PDN_DONE_MASK |
1622                         CS42L42_HSDET_AUTO_DONE_MASK,
1623                         (1 << CS42L42_PDN_DONE_SHIFT) |
1624                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1625
1626         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1627                         CS42L42_SRCPL_ADC_LK_MASK |
1628                         CS42L42_SRCPL_DAC_LK_MASK |
1629                         CS42L42_SRCPL_ADC_UNLK_MASK |
1630                         CS42L42_SRCPL_DAC_UNLK_MASK,
1631                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1632                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1633                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1634                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1635
1636         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1637                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1638                         CS42L42_TIP_SENSE_PLUG_MASK |
1639                         CS42L42_HSBIAS_SENSE_MASK,
1640                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1641                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1642                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1643
1644         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1645                         CS42L42_M_DETECT_TF_MASK |
1646                         CS42L42_M_DETECT_FT_MASK |
1647                         CS42L42_M_HSBIAS_HIZ_MASK |
1648                         CS42L42_M_SHORT_RLS_MASK |
1649                         CS42L42_M_SHORT_DET_MASK,
1650                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1651                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1652                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1653                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1654                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1655
1656         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1657                         CS42L42_VPMON_MASK,
1658                         (1 << CS42L42_VPMON_SHIFT));
1659
1660         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1661                         CS42L42_PLL_LOCK_MASK,
1662                         (1 << CS42L42_PLL_LOCK_SHIFT));
1663
1664         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1665                         CS42L42_RS_PLUG_MASK |
1666                         CS42L42_RS_UNPLUG_MASK |
1667                         CS42L42_TS_PLUG_MASK |
1668                         CS42L42_TS_UNPLUG_MASK,
1669                         (1 << CS42L42_RS_PLUG_SHIFT) |
1670                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1671                         (1 << CS42L42_TS_PLUG_SHIFT) |
1672                         (1 << CS42L42_TS_UNPLUG_SHIFT));
1673 }
1674
1675 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1676 {
1677         unsigned int reg;
1678
1679         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1680
1681         /* Latch analog controls to VP power domain */
1682         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1683                         CS42L42_LATCH_TO_VP_MASK |
1684                         CS42L42_EVENT_STAT_SEL_MASK |
1685                         CS42L42_HS_DET_LEVEL_MASK,
1686                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1687                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1688                         (cs42l42->bias_thresholds[0] <<
1689                         CS42L42_HS_DET_LEVEL_SHIFT));
1690
1691         /* Remove ground noise-suppression clamps */
1692         regmap_update_bits(cs42l42->regmap,
1693                         CS42L42_HS_CLAMP_DISABLE,
1694                         CS42L42_HS_CLAMP_DISABLE_MASK,
1695                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1696
1697         /* Enable the tip sense circuit */
1698         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1699                         CS42L42_TIP_SENSE_CTRL_MASK |
1700                         CS42L42_TIP_SENSE_INV_MASK |
1701                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1702                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1703                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1704                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1705
1706         /* Save the initial status of the tip sense */
1707         regmap_read(cs42l42->regmap,
1708                           CS42L42_TSRS_PLUG_STATUS,
1709                           &reg);
1710         cs42l42->plug_state = (((char) reg) &
1711                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1712                       CS42L42_TS_PLUG_SHIFT;
1713 }
1714
1715 static const unsigned int threshold_defaults[] = {
1716         CS42L42_HS_DET_LEVEL_15,
1717         CS42L42_HS_DET_LEVEL_8,
1718         CS42L42_HS_DET_LEVEL_4,
1719         CS42L42_HS_DET_LEVEL_1
1720 };
1721
1722 static int cs42l42_handle_device_data(struct device *dev,
1723                                         struct cs42l42_private *cs42l42)
1724 {
1725         unsigned int val;
1726         u32 thresholds[CS42L42_NUM_BIASES];
1727         int ret;
1728         int i;
1729
1730         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1731         if (!ret) {
1732                 switch (val) {
1733                 case CS42L42_TS_INV_EN:
1734                 case CS42L42_TS_INV_DIS:
1735                         cs42l42->ts_inv = val;
1736                         break;
1737                 default:
1738                         dev_err(dev,
1739                                 "Wrong cirrus,ts-inv DT value %d\n",
1740                                 val);
1741                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1742                 }
1743         } else {
1744                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1745         }
1746
1747         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1748                         CS42L42_TS_INV_MASK,
1749                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1750
1751         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1752         if (!ret) {
1753                 switch (val) {
1754                 case CS42L42_TS_DBNCE_0:
1755                 case CS42L42_TS_DBNCE_125:
1756                 case CS42L42_TS_DBNCE_250:
1757                 case CS42L42_TS_DBNCE_500:
1758                 case CS42L42_TS_DBNCE_750:
1759                 case CS42L42_TS_DBNCE_1000:
1760                 case CS42L42_TS_DBNCE_1250:
1761                 case CS42L42_TS_DBNCE_1500:
1762                         cs42l42->ts_dbnc_rise = val;
1763                         break;
1764                 default:
1765                         dev_err(dev,
1766                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1767                                 val);
1768                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1769                 }
1770         } else {
1771                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1772         }
1773
1774         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1775                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1776                         (cs42l42->ts_dbnc_rise <<
1777                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1778
1779         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1780         if (!ret) {
1781                 switch (val) {
1782                 case CS42L42_TS_DBNCE_0:
1783                 case CS42L42_TS_DBNCE_125:
1784                 case CS42L42_TS_DBNCE_250:
1785                 case CS42L42_TS_DBNCE_500:
1786                 case CS42L42_TS_DBNCE_750:
1787                 case CS42L42_TS_DBNCE_1000:
1788                 case CS42L42_TS_DBNCE_1250:
1789                 case CS42L42_TS_DBNCE_1500:
1790                         cs42l42->ts_dbnc_fall = val;
1791                         break;
1792                 default:
1793                         dev_err(dev,
1794                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1795                                 val);
1796                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1797                 }
1798         } else {
1799                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1800         }
1801
1802         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1803                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1804                         (cs42l42->ts_dbnc_fall <<
1805                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1806
1807         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1808         if (!ret) {
1809                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1810                         cs42l42->btn_det_init_dbnce = val;
1811                 else {
1812                         dev_err(dev,
1813                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1814                                 val);
1815                         cs42l42->btn_det_init_dbnce =
1816                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1817                 }
1818         } else {
1819                 cs42l42->btn_det_init_dbnce =
1820                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1821         }
1822
1823         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1824         if (!ret) {
1825                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1826                         cs42l42->btn_det_event_dbnce = val;
1827                 else {
1828                         dev_err(dev,
1829                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1830                         cs42l42->btn_det_event_dbnce =
1831                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1832                 }
1833         } else {
1834                 cs42l42->btn_det_event_dbnce =
1835                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1836         }
1837
1838         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1839                                              thresholds, ARRAY_SIZE(thresholds));
1840         if (!ret) {
1841                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1842                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1843                                 cs42l42->bias_thresholds[i] = thresholds[i];
1844                         else {
1845                                 dev_err(dev,
1846                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1847                                         thresholds[i]);
1848                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1849                         }
1850                 }
1851         } else {
1852                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1853                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1854         }
1855
1856         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
1857         if (!ret) {
1858                 switch (val) {
1859                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1860                         cs42l42->hs_bias_ramp_rate = val;
1861                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1862                         break;
1863                 case CS42L42_HSBIAS_RAMP_FAST:
1864                         cs42l42->hs_bias_ramp_rate = val;
1865                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1866                         break;
1867                 case CS42L42_HSBIAS_RAMP_SLOW:
1868                         cs42l42->hs_bias_ramp_rate = val;
1869                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1870                         break;
1871                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1872                         cs42l42->hs_bias_ramp_rate = val;
1873                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1874                         break;
1875                 default:
1876                         dev_err(dev,
1877                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1878                                 val);
1879                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1880                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1881                 }
1882         } else {
1883                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1884                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1885         }
1886
1887         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1888                         CS42L42_HSBIAS_RAMP_MASK,
1889                         (cs42l42->hs_bias_ramp_rate <<
1890                         CS42L42_HSBIAS_RAMP_SHIFT));
1891
1892         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
1893                 cs42l42->hs_bias_sense_en = 0;
1894         else
1895                 cs42l42->hs_bias_sense_en = 1;
1896
1897         return 0;
1898 }
1899
1900 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1901                                        const struct i2c_device_id *id)
1902 {
1903         struct cs42l42_private *cs42l42;
1904         int ret, i, devid;
1905         unsigned int reg;
1906
1907         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1908                                GFP_KERNEL);
1909         if (!cs42l42)
1910                 return -ENOMEM;
1911
1912         i2c_set_clientdata(i2c_client, cs42l42);
1913
1914         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1915         if (IS_ERR(cs42l42->regmap)) {
1916                 ret = PTR_ERR(cs42l42->regmap);
1917                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1918                 return ret;
1919         }
1920
1921         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1922                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1923
1924         ret = devm_regulator_bulk_get(&i2c_client->dev,
1925                                       ARRAY_SIZE(cs42l42->supplies),
1926                                       cs42l42->supplies);
1927         if (ret != 0) {
1928                 dev_err(&i2c_client->dev,
1929                         "Failed to request supplies: %d\n", ret);
1930                 return ret;
1931         }
1932
1933         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1934                                     cs42l42->supplies);
1935         if (ret != 0) {
1936                 dev_err(&i2c_client->dev,
1937                         "Failed to enable supplies: %d\n", ret);
1938                 return ret;
1939         }
1940
1941         /* Reset the Device */
1942         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1943                 "reset", GPIOD_OUT_LOW);
1944         if (IS_ERR(cs42l42->reset_gpio)) {
1945                 ret = PTR_ERR(cs42l42->reset_gpio);
1946                 goto err_disable;
1947         }
1948
1949         if (cs42l42->reset_gpio) {
1950                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1951                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1952         }
1953         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1954
1955         /* Request IRQ */
1956         ret = devm_request_threaded_irq(&i2c_client->dev,
1957                         i2c_client->irq,
1958                         NULL, cs42l42_irq_thread,
1959                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1960                         "cs42l42", cs42l42);
1961
1962         if (ret != 0)
1963                 dev_err(&i2c_client->dev,
1964                         "Failed to request IRQ: %d\n", ret);
1965
1966         /* initialize codec */
1967         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
1968         if (devid < 0) {
1969                 ret = devid;
1970                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1971                 goto err_disable;
1972         }
1973
1974         if (devid != CS42L42_CHIP_ID) {
1975                 ret = -ENODEV;
1976                 dev_err(&i2c_client->dev,
1977                         "CS42L42 Device ID (%X). Expected %X\n",
1978                         devid, CS42L42_CHIP_ID);
1979                 goto err_disable;
1980         }
1981
1982         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1983         if (ret < 0) {
1984                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1985                 goto err_disable;
1986         }
1987
1988         dev_info(&i2c_client->dev,
1989                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1990
1991         /* Power up the codec */
1992         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1993                         CS42L42_ASP_DAO_PDN_MASK |
1994                         CS42L42_ASP_DAI_PDN_MASK |
1995                         CS42L42_MIXER_PDN_MASK |
1996                         CS42L42_EQ_PDN_MASK |
1997                         CS42L42_HP_PDN_MASK |
1998                         CS42L42_ADC_PDN_MASK |
1999                         CS42L42_PDN_ALL_MASK,
2000                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2001                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2002                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2003                         (1 << CS42L42_EQ_PDN_SHIFT) |
2004                         (1 << CS42L42_HP_PDN_SHIFT) |
2005                         (1 << CS42L42_ADC_PDN_SHIFT) |
2006                         (0 << CS42L42_PDN_ALL_SHIFT));
2007
2008         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2009         if (ret != 0)
2010                 goto err_disable;
2011
2012         /* Setup headset detection */
2013         cs42l42_setup_hs_type_detect(cs42l42);
2014
2015         /* Mask/Unmask Interrupts */
2016         cs42l42_set_interrupt_masks(cs42l42);
2017
2018         /* Register codec for machine driver */
2019         ret = devm_snd_soc_register_component(&i2c_client->dev,
2020                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2021         if (ret < 0)
2022                 goto err_disable;
2023         return 0;
2024
2025 err_disable:
2026         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2027                                 cs42l42->supplies);
2028         return ret;
2029 }
2030
2031 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2032 {
2033         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2034
2035         devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
2036         pm_runtime_suspend(&i2c_client->dev);
2037         pm_runtime_disable(&i2c_client->dev);
2038
2039         return 0;
2040 }
2041
2042 #ifdef CONFIG_PM
2043 static int cs42l42_runtime_suspend(struct device *dev)
2044 {
2045         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2046
2047         regcache_cache_only(cs42l42->regmap, true);
2048         regcache_mark_dirty(cs42l42->regmap);
2049
2050         /* Hold down reset */
2051         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2052
2053         /* remove power */
2054         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2055                                 cs42l42->supplies);
2056
2057         return 0;
2058 }
2059
2060 static int cs42l42_runtime_resume(struct device *dev)
2061 {
2062         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2063         int ret;
2064
2065         /* Enable power */
2066         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2067                                         cs42l42->supplies);
2068         if (ret != 0) {
2069                 dev_err(dev, "Failed to enable supplies: %d\n",
2070                         ret);
2071                 return ret;
2072         }
2073
2074         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2075         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2076
2077         regcache_cache_only(cs42l42->regmap, false);
2078         regcache_sync(cs42l42->regmap);
2079
2080         return 0;
2081 }
2082 #endif
2083
2084 static const struct dev_pm_ops cs42l42_runtime_pm = {
2085         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
2086                            NULL)
2087 };
2088
2089 #ifdef CONFIG_OF
2090 static const struct of_device_id cs42l42_of_match[] = {
2091         { .compatible = "cirrus,cs42l42", },
2092         {}
2093 };
2094 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2095 #endif
2096
2097 #ifdef CONFIG_ACPI
2098 static const struct acpi_device_id cs42l42_acpi_match[] = {
2099         {"10134242", 0,},
2100         {}
2101 };
2102 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2103 #endif
2104
2105 static const struct i2c_device_id cs42l42_id[] = {
2106         {"cs42l42", 0},
2107         {}
2108 };
2109
2110 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2111
2112 static struct i2c_driver cs42l42_i2c_driver = {
2113         .driver = {
2114                 .name = "cs42l42",
2115                 .pm = &cs42l42_runtime_pm,
2116                 .of_match_table = of_match_ptr(cs42l42_of_match),
2117                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2118                 },
2119         .id_table = cs42l42_id,
2120         .probe = cs42l42_i2c_probe,
2121         .remove = cs42l42_i2c_remove,
2122 };
2123
2124 module_i2c_driver(cs42l42_i2c_driver);
2125
2126 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2127 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2128 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2129 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2130 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2131 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2132 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2133 MODULE_LICENSE("GPL");