sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <linux/of.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38
  39 static const struct reg_default cs42l42_reg_defaults[] = {
  40         { CS42L42_FRZ_CTL,                      0x00 },
  41         { CS42L42_SRC_CTL,                      0x10 },
  42         { CS42L42_MCLK_STATUS,                  0x02 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  46         { CS42L42_I2C_STRETCH,                  0x03 },
  47         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  48         { CS42L42_PWR_CTL1,                     0xFF },
  49         { CS42L42_PWR_CTL2,                     0x84 },
  50         { CS42L42_PWR_CTL3,                     0x20 },
  51         { CS42L42_RSENSE_CTL1,                  0x40 },
  52         { CS42L42_RSENSE_CTL2,                  0x00 },
  53         { CS42L42_OSC_SWITCH,                   0x00 },
  54         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_TRSENSE_STATUS,               0x00 },
  59         { CS42L42_HSDET_CTL1,                   0x77 },
  60         { CS42L42_HSDET_CTL2,                   0x00 },
  61         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  62         { CS42L42_HS_DET_STATUS,                0x00 },
  63         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  64         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  65         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  66         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  67         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  68         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  69         { CS42L42_FSYNC_P_UPPER,                0x00 },
  70         { CS42L42_ASP_CLK_CFG,                  0x00 },
  71         { CS42L42_ASP_FRM_CFG,                  0x10 },
  72         { CS42L42_FS_RATE_EN,                   0x00 },
  73         { CS42L42_IN_ASRC_CLK,                  0x00 },
  74         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  75         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  76         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  77         { CS42L42_MIXER_STATUS,                 0x00 },
  78         { CS42L42_SRC_STATUS,                   0x00 },
  79         { CS42L42_ASP_RX_STATUS,                0x00 },
  80         { CS42L42_ASP_TX_STATUS,                0x00 },
  81         { CS42L42_CODEC_STATUS,                 0x00 },
  82         { CS42L42_DET_INT_STATUS1,              0x00 },
  83         { CS42L42_DET_INT_STATUS2,              0x00 },
  84         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  85         { CS42L42_VPMON_STATUS,                 0x00 },
  86         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  87         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  88         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  89         { CS42L42_MIXER_INT_MASK,               0x0F },
  90         { CS42L42_SRC_INT_MASK,                 0x0F },
  91         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  92         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  93         { CS42L42_CODEC_INT_MASK,               0x03 },
  94         { CS42L42_SRCPL_INT_MASK,               0xFF },
  95         { CS42L42_VPMON_INT_MASK,               0x01 },
  96         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  97         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  98         { CS42L42_PLL_CTL1,                     0x00 },
  99         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 100         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 101         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 102         { CS42L42_PLL_DIV_INT,                  0x40 },
 103         { CS42L42_PLL_CTL3,                     0x10 },
 104         { CS42L42_PLL_CAL_RATIO,                0x80 },
 105         { CS42L42_PLL_CTL4,                     0x03 },
 106         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 107         { CS42L42_LOAD_DET_DONE,                0x00 },
 108         { CS42L42_LOAD_DET_EN,                  0x00 },
 109         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 110         { CS42L42_WAKE_CTL,                     0xC0 },
 111         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 112         { CS42L42_TIPSENSE_CTL,                 0x02 },
 113         { CS42L42_MISC_DET_CTL,                 0x03 },
 114         { CS42L42_MIC_DET_CTL1,                 0x1F },
 115         { CS42L42_MIC_DET_CTL2,                 0x2F },
 116         { CS42L42_DET_STATUS1,                  0x00 },
 117         { CS42L42_DET_STATUS2,                  0x00 },
 118         { CS42L42_DET_INT1_MASK,                0xE0 },
 119         { CS42L42_DET_INT2_MASK,                0xFF },
 120         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 121         { CS42L42_ADC_CTL,                      0x00 },
 122         { CS42L42_ADC_VOLUME,                   0x00 },
 123         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 124         { CS42L42_DAC_CTL1,                     0x00 },
 125         { CS42L42_DAC_CTL2,                     0x02 },
 126         { CS42L42_HP_CTL,                       0x0D },
 127         { CS42L42_CLASSH_CTL,                   0x07 },
 128         { CS42L42_MIXER_CHA_VOL,                0x3F },
 129         { CS42L42_MIXER_ADC_VOL,                0x3F },
 130         { CS42L42_MIXER_CHB_VOL,                0x3F },
 131         { CS42L42_EQ_COEF_IN0,                  0x22 },
 132         { CS42L42_EQ_COEF_IN1,                  0x00 },
 133         { CS42L42_EQ_COEF_IN2,                  0x00 },
 134         { CS42L42_EQ_COEF_IN3,                  0x00 },
 135         { CS42L42_EQ_COEF_RW,                   0x00 },
 136         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 137         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 138         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 139         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 140         { CS42L42_EQ_INIT_STAT,                 0x00 },
 141         { CS42L42_EQ_START_FILT,                0x00 },
 142         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 143         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 144         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 145         { CS42L42_SP_RX_FS,                     0x8C },
 146         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 147         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 148         { CS42L42_SP_TX_FS,                     0xCC },
 149         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 150         { CS42L42_SRC_SDIN_FS,                  0x40 },
 151         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 152         { CS42L42_SPDIF_CTL1,                   0x01 },
 153         { CS42L42_SPDIF_CTL2,                   0x00 },
 154         { CS42L42_SPDIF_CTL3,                   0x00 },
 155         { CS42L42_SPDIF_CTL4,                   0x42 },
 156         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 157         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 158         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 159         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 160         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 161         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 162         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 163         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 164         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 165         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 166         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 167         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 168         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 169         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 170         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 172         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 173         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 174         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 175         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 176         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 177         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 178         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 179         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 180         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 181         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 182         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 183         { CS42L42_SUB_REVID,                    0x03 },
 184 };
 185
 186 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 187 {
 188         switch (reg) {
 189         case CS42L42_PAGE_REGISTER:
 190         case CS42L42_DEVID_AB:
 191         case CS42L42_DEVID_CD:
 192         case CS42L42_DEVID_E:
 193         case CS42L42_FABID:
 194         case CS42L42_REVID:
 195         case CS42L42_FRZ_CTL:
 196         case CS42L42_SRC_CTL:
 197         case CS42L42_MCLK_STATUS:
 198         case CS42L42_MCLK_CTL:
 199         case CS42L42_SFTRAMP_RATE:
 200         case CS42L42_I2C_DEBOUNCE:
 201         case CS42L42_I2C_STRETCH:
 202         case CS42L42_I2C_TIMEOUT:
 203         case CS42L42_PWR_CTL1:
 204         case CS42L42_PWR_CTL2:
 205         case CS42L42_PWR_CTL3:
 206         case CS42L42_RSENSE_CTL1:
 207         case CS42L42_RSENSE_CTL2:
 208         case CS42L42_OSC_SWITCH:
 209         case CS42L42_OSC_SWITCH_STATUS:
 210         case CS42L42_RSENSE_CTL3:
 211         case CS42L42_TSENSE_CTL:
 212         case CS42L42_TSRS_INT_DISABLE:
 213         case CS42L42_TRSENSE_STATUS:
 214         case CS42L42_HSDET_CTL1:
 215         case CS42L42_HSDET_CTL2:
 216         case CS42L42_HS_SWITCH_CTL:
 217         case CS42L42_HS_DET_STATUS:
 218         case CS42L42_HS_CLAMP_DISABLE:
 219         case CS42L42_MCLK_SRC_SEL:
 220         case CS42L42_SPDIF_CLK_CFG:
 221         case CS42L42_FSYNC_PW_LOWER:
 222         case CS42L42_FSYNC_PW_UPPER:
 223         case CS42L42_FSYNC_P_LOWER:
 224         case CS42L42_FSYNC_P_UPPER:
 225         case CS42L42_ASP_CLK_CFG:
 226         case CS42L42_ASP_FRM_CFG:
 227         case CS42L42_FS_RATE_EN:
 228         case CS42L42_IN_ASRC_CLK:
 229         case CS42L42_OUT_ASRC_CLK:
 230         case CS42L42_PLL_DIV_CFG1:
 231         case CS42L42_ADC_OVFL_STATUS:
 232         case CS42L42_MIXER_STATUS:
 233         case CS42L42_SRC_STATUS:
 234         case CS42L42_ASP_RX_STATUS:
 235         case CS42L42_ASP_TX_STATUS:
 236         case CS42L42_CODEC_STATUS:
 237         case CS42L42_DET_INT_STATUS1:
 238         case CS42L42_DET_INT_STATUS2:
 239         case CS42L42_SRCPL_INT_STATUS:
 240         case CS42L42_VPMON_STATUS:
 241         case CS42L42_PLL_LOCK_STATUS:
 242         case CS42L42_TSRS_PLUG_STATUS:
 243         case CS42L42_ADC_OVFL_INT_MASK:
 244         case CS42L42_MIXER_INT_MASK:
 245         case CS42L42_SRC_INT_MASK:
 246         case CS42L42_ASP_RX_INT_MASK:
 247         case CS42L42_ASP_TX_INT_MASK:
 248         case CS42L42_CODEC_INT_MASK:
 249         case CS42L42_SRCPL_INT_MASK:
 250         case CS42L42_VPMON_INT_MASK:
 251         case CS42L42_PLL_LOCK_INT_MASK:
 252         case CS42L42_TSRS_PLUG_INT_MASK:
 253         case CS42L42_PLL_CTL1:
 254         case CS42L42_PLL_DIV_FRAC0:
 255         case CS42L42_PLL_DIV_FRAC1:
 256         case CS42L42_PLL_DIV_FRAC2:
 257         case CS42L42_PLL_DIV_INT:
 258         case CS42L42_PLL_CTL3:
 259         case CS42L42_PLL_CAL_RATIO:
 260         case CS42L42_PLL_CTL4:
 261         case CS42L42_LOAD_DET_RCSTAT:
 262         case CS42L42_LOAD_DET_DONE:
 263         case CS42L42_LOAD_DET_EN:
 264         case CS42L42_HSBIAS_SC_AUTOCTL:
 265         case CS42L42_WAKE_CTL:
 266         case CS42L42_ADC_DISABLE_MUTE:
 267         case CS42L42_TIPSENSE_CTL:
 268         case CS42L42_MISC_DET_CTL:
 269         case CS42L42_MIC_DET_CTL1:
 270         case CS42L42_MIC_DET_CTL2:
 271         case CS42L42_DET_STATUS1:
 272         case CS42L42_DET_STATUS2:
 273         case CS42L42_DET_INT1_MASK:
 274         case CS42L42_DET_INT2_MASK:
 275         case CS42L42_HS_BIAS_CTL:
 276         case CS42L42_ADC_CTL:
 277         case CS42L42_ADC_VOLUME:
 278         case CS42L42_ADC_WNF_HPF_CTL:
 279         case CS42L42_DAC_CTL1:
 280         case CS42L42_DAC_CTL2:
 281         case CS42L42_HP_CTL:
 282         case CS42L42_CLASSH_CTL:
 283         case CS42L42_MIXER_CHA_VOL:
 284         case CS42L42_MIXER_ADC_VOL:
 285         case CS42L42_MIXER_CHB_VOL:
 286         case CS42L42_EQ_COEF_IN0:
 287         case CS42L42_EQ_COEF_IN1:
 288         case CS42L42_EQ_COEF_IN2:
 289         case CS42L42_EQ_COEF_IN3:
 290         case CS42L42_EQ_COEF_RW:
 291         case CS42L42_EQ_COEF_OUT0:
 292         case CS42L42_EQ_COEF_OUT1:
 293         case CS42L42_EQ_COEF_OUT2:
 294         case CS42L42_EQ_COEF_OUT3:
 295         case CS42L42_EQ_INIT_STAT:
 296         case CS42L42_EQ_START_FILT:
 297         case CS42L42_EQ_MUTE_CTL:
 298         case CS42L42_SP_RX_CH_SEL:
 299         case CS42L42_SP_RX_ISOC_CTL:
 300         case CS42L42_SP_RX_FS:
 301         case CS42l42_SPDIF_CH_SEL:
 302         case CS42L42_SP_TX_ISOC_CTL:
 303         case CS42L42_SP_TX_FS:
 304         case CS42L42_SPDIF_SW_CTL1:
 305         case CS42L42_SRC_SDIN_FS:
 306         case CS42L42_SRC_SDOUT_FS:
 307         case CS42L42_SPDIF_CTL1:
 308         case CS42L42_SPDIF_CTL2:
 309         case CS42L42_SPDIF_CTL3:
 310         case CS42L42_SPDIF_CTL4:
 311         case CS42L42_ASP_TX_SZ_EN:
 312         case CS42L42_ASP_TX_CH_EN:
 313         case CS42L42_ASP_TX_CH_AP_RES:
 314         case CS42L42_ASP_TX_CH1_BIT_MSB:
 315         case CS42L42_ASP_TX_CH1_BIT_LSB:
 316         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 317         case CS42L42_ASP_TX_CH2_BIT_MSB:
 318         case CS42L42_ASP_TX_CH2_BIT_LSB:
 319         case CS42L42_ASP_RX_DAI0_EN:
 320         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 321         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 322         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 324         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 325         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 326         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 327         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 328         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 329         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 330         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 331         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 332         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 333         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 334         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 335         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 336         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 337         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 338         case CS42L42_SUB_REVID:
 339                 return true;
 340         default:
 341                 return false;
 342         }
 343 }
 344
 345 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 346 {
 347         switch (reg) {
 348         case CS42L42_DEVID_AB:
 349         case CS42L42_DEVID_CD:
 350         case CS42L42_DEVID_E:
 351         case CS42L42_MCLK_STATUS:
 352         case CS42L42_TRSENSE_STATUS:
 353         case CS42L42_HS_DET_STATUS:
 354         case CS42L42_ADC_OVFL_STATUS:
 355         case CS42L42_MIXER_STATUS:
 356         case CS42L42_SRC_STATUS:
 357         case CS42L42_ASP_RX_STATUS:
 358         case CS42L42_ASP_TX_STATUS:
 359         case CS42L42_CODEC_STATUS:
 360         case CS42L42_DET_INT_STATUS1:
 361         case CS42L42_DET_INT_STATUS2:
 362         case CS42L42_SRCPL_INT_STATUS:
 363         case CS42L42_VPMON_STATUS:
 364         case CS42L42_PLL_LOCK_STATUS:
 365         case CS42L42_TSRS_PLUG_STATUS:
 366         case CS42L42_LOAD_DET_RCSTAT:
 367         case CS42L42_LOAD_DET_DONE:
 368         case CS42L42_DET_STATUS1:
 369         case CS42L42_DET_STATUS2:
 370                 return true;
 371         default:
 372                 return false;
 373         }
 374 }
 375
 376 static const struct regmap_range_cfg cs42l42_page_range = {
 377         .name = "Pages",
 378         .range_min = 0,
 379         .range_max = CS42L42_MAX_REGISTER,
 380         .selector_reg = CS42L42_PAGE_REGISTER,
 381         .selector_mask = 0xff,
 382         .selector_shift = 0,
 383         .window_start = 0,
 384         .window_len = 256,
 385 };
 386
 387 static const struct regmap_config cs42l42_regmap = {
 388         .reg_bits = 8,
 389         .val_bits = 8,
 390
 391         .readable_reg = cs42l42_readable_register,
 392         .volatile_reg = cs42l42_volatile_register,
 393
 394         .ranges = &cs42l42_page_range,
 395         .num_ranges = 1,
 396
 397         .max_register = CS42L42_MAX_REGISTER,
 398         .reg_defaults = cs42l42_reg_defaults,
 399         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 400         .cache_type = REGCACHE_RBTREE,
 401 };
 402
 403 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false);
 404 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 405
 406 static const char * const cs42l42_hpf_freq_text[] = {
 407         "1.86Hz", "120Hz", "235Hz", "466Hz"
 408 };
 409
 410 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 411                             CS42L42_ADC_HPF_CF_SHIFT,
 412                             cs42l42_hpf_freq_text);
 413
 414 static const char * const cs42l42_wnf3_freq_text[] = {
 415         "160Hz", "180Hz", "200Hz", "220Hz",
 416         "240Hz", "260Hz", "280Hz", "300Hz"
 417 };
 418
 419 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 420                             CS42L42_ADC_WNF_CF_SHIFT,
 421                             cs42l42_wnf3_freq_text);
 422
 423 static const char * const cs42l42_wnf05_freq_text[] = {
 424         "280Hz", "315Hz", "350Hz", "385Hz",
 425         "420Hz", "455Hz", "490Hz", "525Hz"
 426 };
 427
 428 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 429                             CS42L42_ADC_WNF_CF_SHIFT,
 430                             cs42l42_wnf05_freq_text);
 431
 432 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 433         /* ADC Volume and Filter Controls */
 434         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 435                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false),
 436         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 437                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 438         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 439                                 CS42L42_ADC_INV_SHIFT, true, false),
 440         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 441                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 442         SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME,
 443                                 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv),
 444         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 446         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 447                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 448         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 449         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 450         SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
 451
 452         /* DAC Volume and Filter Controls */
 453         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 454                                 CS42L42_DACA_INV_SHIFT, true, false),
 455         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 456                                 CS42L42_DACB_INV_SHIFT, true, false),
 457         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 458                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 459         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 460                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 461                                 0x3f, 1, mixer_tlv)
 462 };
 463
 464 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
 465                                 struct snd_kcontrol *kcontrol, int event)
 466 {
 467         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 468
 469         if (event & SND_SOC_DAPM_POST_PMU) {
 470                 /* Enable the channels */
 471                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 472                                 CS42L42_ASP_RX0_CH_EN_MASK,
 473                                 (CS42L42_ASP_RX0_CH1_EN |
 474                                 CS42L42_ASP_RX0_CH2_EN) <<
 475                                 CS42L42_ASP_RX0_CH_EN_SHIFT);
 476
 477                 /* Power up */
 478                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 479                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 480                                 CS42L42_HP_PDN_MASK, 0);
 481         } else if (event & SND_SOC_DAPM_PRE_PMD) {
 482                 /* Disable the channels */
 483                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 484                                 CS42L42_ASP_RX0_CH_EN_MASK, 0);
 485
 486                 /* Power down */
 487                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 488                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 489                                 CS42L42_HP_PDN_MASK,
 490                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 491                                 CS42L42_HP_PDN_MASK);
 492         } else {
 493                 dev_err(component->dev, "Invalid event 0x%x\n", event);
 494         }
 495         return 0;
 496 }
 497
 498 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 499         SND_SOC_DAPM_OUTPUT("HP"),
 500         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
 501                                         CS42L42_ASP_SCLK_EN_SHIFT, false),
 502         SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
 503                                         0, NULL, 0, cs42l42_hpdrv_evt,
 504                                         SND_SOC_DAPM_POST_PMU |
 505                                         SND_SOC_DAPM_PRE_PMD)
 506 };
 507
 508 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 509         {"SDIN", NULL, "Playback"},
 510         {"HPDRV", NULL, "SDIN"},
 511         {"HP", NULL, "HPDRV"}
 512 };
 513
 514 static int cs42l42_component_probe(struct snd_soc_component *component)
 515 {
 516         struct cs42l42_private *cs42l42 =
 517                 (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
 518
 519         cs42l42->component = component;
 520
 521         return 0;
 522 }
 523
 524 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 525         .probe                  = cs42l42_component_probe,
 526         .dapm_widgets           = cs42l42_dapm_widgets,
 527         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 528         .dapm_routes            = cs42l42_audio_map,
 529         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 530         .controls               = cs42l42_snd_controls,
 531         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 532         .idle_bias_on           = 1,
 533         .endianness             = 1,
 534         .non_legacy_dai_naming  = 1,
 535 };
 536
 537 struct cs42l42_pll_params {
 538         u32 sclk;
 539         u8 mclk_div;
 540         u8 mclk_src_sel;
 541         u8 sclk_prediv;
 542         u8 pll_div_int;
 543         u32 pll_div_frac;
 544         u8 pll_mode;
 545         u8 pll_divout;
 546         u32 mclk_int;
 547         u8 pll_cal_ratio;
 548 };
 549
 550 /*
 551  * Common PLL Settings for given SCLK
 552  * Table 4-5 from the Datasheet
 553  */
 554 static const struct cs42l42_pll_params pll_ratio_table[] = {
 555         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
 556         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 557         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 558         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 559         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
 560         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
 561         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 562         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 563         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 564         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
 565         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
 566         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
 567         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
 568         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
 569         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
 570 };
 571
 572 static int cs42l42_pll_config(struct snd_soc_component *component)
 573 {
 574         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 575         int i;
 576         u32 fsync;
 577
 578         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 579                 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
 580                         /* Configure the internal sample rate */
 581                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 582                                         CS42L42_INTERNAL_FS_MASK,
 583                                         ((pll_ratio_table[i].mclk_int !=
 584                                         12000000) &&
 585                                         (pll_ratio_table[i].mclk_int !=
 586                                         24000000)) <<
 587                                         CS42L42_INTERNAL_FS_SHIFT);
 588                         /* Set the MCLK src (PLL or SCLK) and the divide
 589                          * ratio
 590                          */
 591                         snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
 592                                         CS42L42_MCLK_SRC_SEL_MASK |
 593                                         CS42L42_MCLKDIV_MASK,
 594                                         (pll_ratio_table[i].mclk_src_sel
 595                                         << CS42L42_MCLK_SRC_SEL_SHIFT) |
 596                                         (pll_ratio_table[i].mclk_div <<
 597                                         CS42L42_MCLKDIV_SHIFT));
 598                         /* Set up the LRCLK */
 599                         fsync = cs42l42->sclk / cs42l42->srate;
 600                         if (((fsync * cs42l42->srate) != cs42l42->sclk)
 601                                 || ((fsync % 2) != 0)) {
 602                                 dev_err(component->dev,
 603                                         "Unsupported sclk %d/sample rate %d\n",
 604                                         cs42l42->sclk,
 605                                         cs42l42->srate);
 606                                 return -EINVAL;
 607                         }
 608                         /* Set the LRCLK period */
 609                         snd_soc_component_update_bits(component,
 610                                         CS42L42_FSYNC_P_LOWER,
 611                                         CS42L42_FSYNC_PERIOD_MASK,
 612                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 613                                         CS42L42_FSYNC_PERIOD_SHIFT);
 614                         snd_soc_component_update_bits(component,
 615                                         CS42L42_FSYNC_P_UPPER,
 616                                         CS42L42_FSYNC_PERIOD_MASK,
 617                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 618                                         CS42L42_FSYNC_PERIOD_SHIFT);
 619                         /* Set the LRCLK to 50% duty cycle */
 620                         fsync = fsync / 2;
 621                         snd_soc_component_update_bits(component,
 622                                         CS42L42_FSYNC_PW_LOWER,
 623                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 624                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 625                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 626                         snd_soc_component_update_bits(component,
 627                                         CS42L42_FSYNC_PW_UPPER,
 628                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 629                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 630                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 631                         snd_soc_component_update_bits(component,
 632                                         CS42L42_ASP_FRM_CFG,
 633                                         CS42L42_ASP_5050_MASK,
 634                                         CS42L42_ASP_5050_MASK);
 635                         /* Set the frame delay to 1.0 SCLK clocks */
 636                         snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG,
 637                                         CS42L42_ASP_FSD_MASK,
 638                                         CS42L42_ASP_FSD_1_0 <<
 639                                         CS42L42_ASP_FSD_SHIFT);
 640                         /* Set the sample rates (96k or lower) */
 641                         snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
 642                                         CS42L42_FS_EN_MASK,
 643                                         (CS42L42_FS_EN_IASRC_96K |
 644                                         CS42L42_FS_EN_OASRC_96K) <<
 645                                         CS42L42_FS_EN_SHIFT);
 646                         /* Set the input/output internal MCLK clock ~12 MHz */
 647                         snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
 648                                         CS42L42_CLK_IASRC_SEL_MASK,
 649                                         CS42L42_CLK_IASRC_SEL_12 <<
 650                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 651                         snd_soc_component_update_bits(component,
 652                                         CS42L42_OUT_ASRC_CLK,
 653                                         CS42L42_CLK_OASRC_SEL_MASK,
 654                                         CS42L42_CLK_OASRC_SEL_12 <<
 655                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 656                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 657                                 /* Pass the clock straight through */
 658                                 snd_soc_component_update_bits(component,
 659                                         CS42L42_PLL_CTL1,
 660                                         CS42L42_PLL_START_MASK, 0);
 661                         } else {
 662                                 /* Configure PLL per table 4-5 */
 663                                 snd_soc_component_update_bits(component,
 664                                         CS42L42_PLL_DIV_CFG1,
 665                                         CS42L42_SCLK_PREDIV_MASK,
 666                                         pll_ratio_table[i].sclk_prediv
 667                                         << CS42L42_SCLK_PREDIV_SHIFT);
 668                                 snd_soc_component_update_bits(component,
 669                                         CS42L42_PLL_DIV_INT,
 670                                         CS42L42_PLL_DIV_INT_MASK,
 671                                         pll_ratio_table[i].pll_div_int
 672                                         << CS42L42_PLL_DIV_INT_SHIFT);
 673                                 snd_soc_component_update_bits(component,
 674                                         CS42L42_PLL_DIV_FRAC0,
 675                                         CS42L42_PLL_DIV_FRAC_MASK,
 676                                         CS42L42_FRAC0_VAL(
 677                                         pll_ratio_table[i].pll_div_frac)
 678                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 679                                 snd_soc_component_update_bits(component,
 680                                         CS42L42_PLL_DIV_FRAC1,
 681                                         CS42L42_PLL_DIV_FRAC_MASK,
 682                                         CS42L42_FRAC1_VAL(
 683                                         pll_ratio_table[i].pll_div_frac)
 684                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 685                                 snd_soc_component_update_bits(component,
 686                                         CS42L42_PLL_DIV_FRAC2,
 687                                         CS42L42_PLL_DIV_FRAC_MASK,
 688                                         CS42L42_FRAC2_VAL(
 689                                         pll_ratio_table[i].pll_div_frac)
 690                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 691                                 snd_soc_component_update_bits(component,
 692                                         CS42L42_PLL_CTL4,
 693                                         CS42L42_PLL_MODE_MASK,
 694                                         pll_ratio_table[i].pll_mode
 695                                         << CS42L42_PLL_MODE_SHIFT);
 696                                 snd_soc_component_update_bits(component,
 697                                         CS42L42_PLL_CTL3,
 698                                         CS42L42_PLL_DIVOUT_MASK,
 699                                         pll_ratio_table[i].pll_divout
 700                                         << CS42L42_PLL_DIVOUT_SHIFT);
 701                                 snd_soc_component_update_bits(component,
 702                                         CS42L42_PLL_CAL_RATIO,
 703                                         CS42L42_PLL_CAL_RATIO_MASK,
 704                                         pll_ratio_table[i].pll_cal_ratio
 705                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 706                         }
 707                         return 0;
 708                 }
 709         }
 710
 711         return -EINVAL;
 712 }
 713
 714 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 715 {
 716         struct snd_soc_component *component = codec_dai->component;
 717         u32 asp_cfg_val = 0;
 718
 719         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 720         case SND_SOC_DAIFMT_CBS_CFM:
 721                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 722                                 CS42L42_ASP_MODE_SHIFT;
 723                 break;
 724         case SND_SOC_DAIFMT_CBS_CFS:
 725                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 726                                 CS42L42_ASP_MODE_SHIFT;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731
 732         /* interface format */
 733         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 734         case SND_SOC_DAIFMT_I2S:
 735         case SND_SOC_DAIFMT_LEFT_J:
 736                 break;
 737         default:
 738                 return -EINVAL;
 739         }
 740
 741         /* Bitclock/frame inversion */
 742         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 743         case SND_SOC_DAIFMT_NB_NF:
 744                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 745                 break;
 746         case SND_SOC_DAIFMT_NB_IF:
 747                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 748                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 749                 break;
 750         case SND_SOC_DAIFMT_IB_NF:
 751                 break;
 752         case SND_SOC_DAIFMT_IB_IF:
 753                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 754                 break;
 755         }
 756
 757         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 758                                                                       CS42L42_ASP_SCPOL_MASK |
 759                                                                       CS42L42_ASP_LCPOL_MASK,
 760                                                                       asp_cfg_val);
 761
 762         return 0;
 763 }
 764
 765 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 766                                 struct snd_pcm_hw_params *params,
 767                                 struct snd_soc_dai *dai)
 768 {
 769         struct snd_soc_component *component = dai->component;
 770         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 771         unsigned int width = (params_width(params) / 8) - 1;
 772         unsigned int val = 0;
 773
 774         cs42l42->srate = params_rate(params);
 775
 776         switch(substream->stream) {
 777         case SNDRV_PCM_STREAM_PLAYBACK:
 778                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 779                 /* channel 1 on low LRCLK */
 780                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 781                                                          CS42L42_ASP_RX_CH_AP_MASK |
 782                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 783                 /* Channel 2 on high LRCLK */
 784                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 785                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 786                                                          CS42L42_ASP_RX_CH_AP_MASK |
 787                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 788                 break;
 789         default:
 790                 break;
 791         }
 792
 793         return cs42l42_pll_config(component);
 794 }
 795
 796 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 797                                 int clk_id, unsigned int freq, int dir)
 798 {
 799         struct snd_soc_component *component = dai->component;
 800         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 801
 802         cs42l42->sclk = freq;
 803
 804         return 0;
 805 }
 806
 807 static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
 808 {
 809         struct snd_soc_component *component = dai->component;
 810         unsigned int regval;
 811         u8 fullScaleVol;
 812
 813         if (mute) {
 814                 /* Mark SCLK as not present to turn on the internal
 815                  * oscillator.
 816                  */
 817                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 818                                                 CS42L42_SCLK_PRESENT_MASK, 0);
 819
 820                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 821                                 CS42L42_PLL_START_MASK,
 822                                 0 << CS42L42_PLL_START_SHIFT);
 823
 824                 /* Mute the headphone */
 825                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 826                                 CS42L42_HP_ANA_AMUTE_MASK |
 827                                 CS42L42_HP_ANA_BMUTE_MASK,
 828                                 CS42L42_HP_ANA_AMUTE_MASK |
 829                                 CS42L42_HP_ANA_BMUTE_MASK);
 830         } else {
 831                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 832                                 CS42L42_PLL_START_MASK,
 833                                 1 << CS42L42_PLL_START_SHIFT);
 834                 /* Read the headphone load */
 835                 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
 836                 if (((regval & CS42L42_RLA_STAT_MASK) >>
 837                         CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
 838                         fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
 839                 } else {
 840                         fullScaleVol = 0;
 841                 }
 842
 843                 /* Un-mute the headphone, set the full scale volume flag */
 844                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 845                                 CS42L42_HP_ANA_AMUTE_MASK |
 846                                 CS42L42_HP_ANA_BMUTE_MASK |
 847                                 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
 848
 849                 /* Mark SCLK as present, turn off internal oscillator */
 850                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 851                                 CS42L42_SCLK_PRESENT_MASK,
 852                                 CS42L42_SCLK_PRESENT_MASK);
 853         }
 854
 855         return 0;
 856 }
 857
 858 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 859                          SNDRV_PCM_FMTBIT_S24_LE |\
 860                          SNDRV_PCM_FMTBIT_S32_LE )
 861
 862
 863 static const struct snd_soc_dai_ops cs42l42_ops = {
 864         .hw_params      = cs42l42_pcm_hw_params,
 865         .set_fmt        = cs42l42_set_dai_fmt,
 866         .set_sysclk     = cs42l42_set_sysclk,
 867         .mute_stream    = cs42l42_mute,
 868         .no_capture_mute = 1,
 869 };
 870
 871 static struct snd_soc_dai_driver cs42l42_dai = {
 872                 .name = "cs42l42",
 873                 .playback = {
 874                         .stream_name = "Playback",
 875                         .channels_min = 1,
 876                         .channels_max = 2,
 877                         .rates = SNDRV_PCM_RATE_8000_192000,
 878                         .formats = CS42L42_FORMATS,
 879                 },
 880                 .capture = {
 881                         .stream_name = "Capture",
 882                         .channels_min = 1,
 883                         .channels_max = 2,
 884                         .rates = SNDRV_PCM_RATE_8000_192000,
 885                         .formats = CS42L42_FORMATS,
 886                 },
 887                 .ops = &cs42l42_ops,
 888 };
 889
 890 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
 891 {
 892         unsigned int hs_det_status;
 893         unsigned int int_status;
 894
 895         /* Mask the auto detect interrupt */
 896         regmap_update_bits(cs42l42->regmap,
 897                 CS42L42_CODEC_INT_MASK,
 898                 CS42L42_PDN_DONE_MASK |
 899                 CS42L42_HSDET_AUTO_DONE_MASK,
 900                 (1 << CS42L42_PDN_DONE_SHIFT) |
 901                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
 902
 903         /* Set hs detect to automatic, disabled mode */
 904         regmap_update_bits(cs42l42->regmap,
 905                 CS42L42_HSDET_CTL2,
 906                 CS42L42_HSDET_CTRL_MASK |
 907                 CS42L42_HSDET_SET_MASK |
 908                 CS42L42_HSBIAS_REF_MASK |
 909                 CS42L42_HSDET_AUTO_TIME_MASK,
 910                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
 911                 (2 << CS42L42_HSDET_SET_SHIFT) |
 912                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 913                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 914
 915         /* Read and save the hs detection result */
 916         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
 917
 918         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
 919                                 CS42L42_HSDET_TYPE_SHIFT;
 920
 921         /* Set up button detection */
 922         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
 923               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
 924                 /* Set auto HS bias settings to default */
 925                 regmap_update_bits(cs42l42->regmap,
 926                         CS42L42_HSBIAS_SC_AUTOCTL,
 927                         CS42L42_HSBIAS_SENSE_EN_MASK |
 928                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 929                         CS42L42_TIP_SENSE_EN_MASK |
 930                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 931                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 932                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 933                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 934                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 935
 936                 /* Set up hs detect level sensitivity */
 937                 regmap_update_bits(cs42l42->regmap,
 938                         CS42L42_MIC_DET_CTL1,
 939                         CS42L42_LATCH_TO_VP_MASK |
 940                         CS42L42_EVENT_STAT_SEL_MASK |
 941                         CS42L42_HS_DET_LEVEL_MASK,
 942                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
 943                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
 944                         (cs42l42->bias_thresholds[0] <<
 945                         CS42L42_HS_DET_LEVEL_SHIFT));
 946
 947                 /* Set auto HS bias settings to default */
 948                 regmap_update_bits(cs42l42->regmap,
 949                         CS42L42_HSBIAS_SC_AUTOCTL,
 950                         CS42L42_HSBIAS_SENSE_EN_MASK |
 951                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 952                         CS42L42_TIP_SENSE_EN_MASK |
 953                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 954                         (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 955                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 956                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 957                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 958
 959                 /* Turn on level detect circuitry */
 960                 regmap_update_bits(cs42l42->regmap,
 961                         CS42L42_MISC_DET_CTL,
 962                         CS42L42_DETECT_MODE_MASK |
 963                         CS42L42_HSBIAS_CTL_MASK |
 964                         CS42L42_PDN_MIC_LVL_DET_MASK,
 965                         (0 << CS42L42_DETECT_MODE_SHIFT) |
 966                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
 967                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
 968
 969                 msleep(cs42l42->btn_det_init_dbnce);
 970
 971                 /* Clear any button interrupts before unmasking them */
 972                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
 973                             &int_status);
 974
 975                 /* Unmask button detect interrupts */
 976                 regmap_update_bits(cs42l42->regmap,
 977                         CS42L42_DET_INT2_MASK,
 978                         CS42L42_M_DETECT_TF_MASK |
 979                         CS42L42_M_DETECT_FT_MASK |
 980                         CS42L42_M_HSBIAS_HIZ_MASK |
 981                         CS42L42_M_SHORT_RLS_MASK |
 982                         CS42L42_M_SHORT_DET_MASK,
 983                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
 984                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
 985                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
 986                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
 987                         (1 << CS42L42_M_SHORT_DET_SHIFT));
 988         } else {
 989                 /* Make sure button detect and HS bias circuits are off */
 990                 regmap_update_bits(cs42l42->regmap,
 991                         CS42L42_MISC_DET_CTL,
 992                         CS42L42_DETECT_MODE_MASK |
 993                         CS42L42_HSBIAS_CTL_MASK |
 994                         CS42L42_PDN_MIC_LVL_DET_MASK,
 995                         (0 << CS42L42_DETECT_MODE_SHIFT) |
 996                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
 997                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
 998         }
 999
1000         regmap_update_bits(cs42l42->regmap,
1001                                 CS42L42_DAC_CTL2,
1002                                 CS42L42_HPOUT_PULLDOWN_MASK |
1003                                 CS42L42_HPOUT_LOAD_MASK |
1004                                 CS42L42_HPOUT_CLAMP_MASK |
1005                                 CS42L42_DAC_HPF_EN_MASK |
1006                                 CS42L42_DAC_MON_EN_MASK,
1007                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1008                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1009                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1010                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1011                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1012
1013         /* Unmask tip sense interrupts */
1014         regmap_update_bits(cs42l42->regmap,
1015                 CS42L42_TSRS_PLUG_INT_MASK,
1016                 CS42L42_RS_PLUG_MASK |
1017                 CS42L42_RS_UNPLUG_MASK |
1018                 CS42L42_TS_PLUG_MASK |
1019                 CS42L42_TS_UNPLUG_MASK,
1020                 (1 << CS42L42_RS_PLUG_SHIFT) |
1021                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1022                 (0 << CS42L42_TS_PLUG_SHIFT) |
1023                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1024 }
1025
1026 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1027 {
1028         /* Mask tip sense interrupts */
1029         regmap_update_bits(cs42l42->regmap,
1030                                 CS42L42_TSRS_PLUG_INT_MASK,
1031                                 CS42L42_RS_PLUG_MASK |
1032                                 CS42L42_RS_UNPLUG_MASK |
1033                                 CS42L42_TS_PLUG_MASK |
1034                                 CS42L42_TS_UNPLUG_MASK,
1035                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1036                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1037                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1038                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1039
1040         /* Make sure button detect and HS bias circuits are off */
1041         regmap_update_bits(cs42l42->regmap,
1042                                 CS42L42_MISC_DET_CTL,
1043                                 CS42L42_DETECT_MODE_MASK |
1044                                 CS42L42_HSBIAS_CTL_MASK |
1045                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1046                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1047                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1048                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1049
1050         /* Set auto HS bias settings to default */
1051         regmap_update_bits(cs42l42->regmap,
1052                                 CS42L42_HSBIAS_SC_AUTOCTL,
1053                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1054                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1055                                 CS42L42_TIP_SENSE_EN_MASK |
1056                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1057                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1058                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1059                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1060                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1061
1062         /* Set hs detect to manual, disabled mode */
1063         regmap_update_bits(cs42l42->regmap,
1064                                 CS42L42_HSDET_CTL2,
1065                                 CS42L42_HSDET_CTRL_MASK |
1066                                 CS42L42_HSDET_SET_MASK |
1067                                 CS42L42_HSBIAS_REF_MASK |
1068                                 CS42L42_HSDET_AUTO_TIME_MASK,
1069                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1070                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1071                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1072                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1073
1074         regmap_update_bits(cs42l42->regmap,
1075                                 CS42L42_DAC_CTL2,
1076                                 CS42L42_HPOUT_PULLDOWN_MASK |
1077                                 CS42L42_HPOUT_LOAD_MASK |
1078                                 CS42L42_HPOUT_CLAMP_MASK |
1079                                 CS42L42_DAC_HPF_EN_MASK |
1080                                 CS42L42_DAC_MON_EN_MASK,
1081                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1082                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1083                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1084                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1085                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1086
1087         /* Power up HS bias to 2.7V */
1088         regmap_update_bits(cs42l42->regmap,
1089                                 CS42L42_MISC_DET_CTL,
1090                                 CS42L42_DETECT_MODE_MASK |
1091                                 CS42L42_HSBIAS_CTL_MASK |
1092                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1093                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1094                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1095                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1096
1097         /* Wait for HS bias to ramp up */
1098         msleep(cs42l42->hs_bias_ramp_time);
1099
1100         /* Unmask auto detect interrupt */
1101         regmap_update_bits(cs42l42->regmap,
1102                                 CS42L42_CODEC_INT_MASK,
1103                                 CS42L42_PDN_DONE_MASK |
1104                                 CS42L42_HSDET_AUTO_DONE_MASK,
1105                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1106                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1107
1108         /* Set hs detect to automatic, enabled mode */
1109         regmap_update_bits(cs42l42->regmap,
1110                                 CS42L42_HSDET_CTL2,
1111                                 CS42L42_HSDET_CTRL_MASK |
1112                                 CS42L42_HSDET_SET_MASK |
1113                                 CS42L42_HSBIAS_REF_MASK |
1114                                 CS42L42_HSDET_AUTO_TIME_MASK,
1115                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1116                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1117                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1118                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1119 }
1120
1121 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1122 {
1123         /* Mask button detect interrupts */
1124         regmap_update_bits(cs42l42->regmap,
1125                 CS42L42_DET_INT2_MASK,
1126                 CS42L42_M_DETECT_TF_MASK |
1127                 CS42L42_M_DETECT_FT_MASK |
1128                 CS42L42_M_HSBIAS_HIZ_MASK |
1129                 CS42L42_M_SHORT_RLS_MASK |
1130                 CS42L42_M_SHORT_DET_MASK,
1131                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1132                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1133                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1134                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1135                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1136
1137         /* Ground HS bias */
1138         regmap_update_bits(cs42l42->regmap,
1139                                 CS42L42_MISC_DET_CTL,
1140                                 CS42L42_DETECT_MODE_MASK |
1141                                 CS42L42_HSBIAS_CTL_MASK |
1142                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1143                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1144                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1145                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1146
1147         /* Set auto HS bias settings to default */
1148         regmap_update_bits(cs42l42->regmap,
1149                                 CS42L42_HSBIAS_SC_AUTOCTL,
1150                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1151                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1152                                 CS42L42_TIP_SENSE_EN_MASK |
1153                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1154                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1155                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1156                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1157                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1158
1159         /* Set hs detect to manual, disabled mode */
1160         regmap_update_bits(cs42l42->regmap,
1161                                 CS42L42_HSDET_CTL2,
1162                                 CS42L42_HSDET_CTRL_MASK |
1163                                 CS42L42_HSDET_SET_MASK |
1164                                 CS42L42_HSBIAS_REF_MASK |
1165                                 CS42L42_HSDET_AUTO_TIME_MASK,
1166                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1167                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1168                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1169                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1170 }
1171
1172 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1173 {
1174         int bias_level;
1175         unsigned int detect_status;
1176
1177         /* Mask button detect interrupts */
1178         regmap_update_bits(cs42l42->regmap,
1179                 CS42L42_DET_INT2_MASK,
1180                 CS42L42_M_DETECT_TF_MASK |
1181                 CS42L42_M_DETECT_FT_MASK |
1182                 CS42L42_M_HSBIAS_HIZ_MASK |
1183                 CS42L42_M_SHORT_RLS_MASK |
1184                 CS42L42_M_SHORT_DET_MASK,
1185                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1186                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1187                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1188                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1189                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1190
1191         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1192                      cs42l42->btn_det_event_dbnce * 2000);
1193
1194         /* Test all 4 level detect biases */
1195         bias_level = 1;
1196         do {
1197                 /* Adjust button detect level sensitivity */
1198                 regmap_update_bits(cs42l42->regmap,
1199                         CS42L42_MIC_DET_CTL1,
1200                         CS42L42_LATCH_TO_VP_MASK |
1201                         CS42L42_EVENT_STAT_SEL_MASK |
1202                         CS42L42_HS_DET_LEVEL_MASK,
1203                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1204                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1205                         (cs42l42->bias_thresholds[bias_level] <<
1206                         CS42L42_HS_DET_LEVEL_SHIFT));
1207
1208                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1209                                 &detect_status);
1210         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1211                 (++bias_level < CS42L42_NUM_BIASES));
1212
1213         switch (bias_level) {
1214         case 1: /* Function C button press */
1215                 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1216                 break;
1217         case 2: /* Function B button press */
1218                 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1219                 break;
1220         case 3: /* Function D button press */
1221                 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1222                 break;
1223         case 4: /* Function A button press */
1224                 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1225                 break;
1226         }
1227
1228         /* Set button detect level sensitivity back to default */
1229         regmap_update_bits(cs42l42->regmap,
1230                 CS42L42_MIC_DET_CTL1,
1231                 CS42L42_LATCH_TO_VP_MASK |
1232                 CS42L42_EVENT_STAT_SEL_MASK |
1233                 CS42L42_HS_DET_LEVEL_MASK,
1234                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1235                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1236                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1237
1238         /* Clear any button interrupts before unmasking them */
1239         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1240                     &detect_status);
1241
1242         /* Unmask button detect interrupts */
1243         regmap_update_bits(cs42l42->regmap,
1244                 CS42L42_DET_INT2_MASK,
1245                 CS42L42_M_DETECT_TF_MASK |
1246                 CS42L42_M_DETECT_FT_MASK |
1247                 CS42L42_M_HSBIAS_HIZ_MASK |
1248                 CS42L42_M_SHORT_RLS_MASK |
1249                 CS42L42_M_SHORT_DET_MASK,
1250                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1251                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1252                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1253                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1254                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1255 }
1256
1257 struct cs42l42_irq_params {
1258         u16 status_addr;
1259         u16 mask_addr;
1260         u8 mask;
1261 };
1262
1263 static const struct cs42l42_irq_params irq_params_table[] = {
1264         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1265                 CS42L42_ADC_OVFL_VAL_MASK},
1266         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1267                 CS42L42_MIXER_VAL_MASK},
1268         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1269                 CS42L42_SRC_VAL_MASK},
1270         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1271                 CS42L42_ASP_RX_VAL_MASK},
1272         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1273                 CS42L42_ASP_TX_VAL_MASK},
1274         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1275                 CS42L42_CODEC_VAL_MASK},
1276         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1277                 CS42L42_DET_INT_VAL1_MASK},
1278         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1279                 CS42L42_DET_INT_VAL2_MASK},
1280         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1281                 CS42L42_SRCPL_VAL_MASK},
1282         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1283                 CS42L42_VPMON_VAL_MASK},
1284         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1285                 CS42L42_PLL_LOCK_VAL_MASK},
1286         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1287                 CS42L42_TSRS_PLUG_VAL_MASK}
1288 };
1289
1290 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1291 {
1292         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1293         struct snd_soc_component *component = cs42l42->component;
1294         unsigned int stickies[12];
1295         unsigned int masks[12];
1296         unsigned int current_plug_status;
1297         unsigned int current_button_status;
1298         unsigned int i;
1299
1300         /* Read sticky registers to clear interurpt */
1301         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1302                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1303                                 &(stickies[i]));
1304                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1305                                 &(masks[i]));
1306                 stickies[i] = stickies[i] & (~masks[i]) &
1307                                 irq_params_table[i].mask;
1308         }
1309
1310         /* Read tip sense status before handling type detect */
1311         current_plug_status = (stickies[11] &
1312                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1313                 CS42L42_TS_PLUG_SHIFT;
1314
1315         /* Read button sense status */
1316         current_button_status = stickies[7] &
1317                 (CS42L42_M_DETECT_TF_MASK |
1318                 CS42L42_M_DETECT_FT_MASK |
1319                 CS42L42_M_HSBIAS_HIZ_MASK);
1320
1321         /* Check auto-detect status */
1322         if ((~masks[5]) & irq_params_table[5].mask) {
1323                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1324                         cs42l42_process_hs_type_detect(cs42l42);
1325                         dev_dbg(component->dev,
1326                                 "Auto detect done (%d)\n",
1327                                 cs42l42->hs_type);
1328                 }
1329         }
1330
1331         /* Check tip sense status */
1332         if ((~masks[11]) & irq_params_table[11].mask) {
1333                 switch (current_plug_status) {
1334                 case CS42L42_TS_PLUG:
1335                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1336                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1337                                 cs42l42_init_hs_type_detect(cs42l42);
1338                         }
1339                         break;
1340
1341                 case CS42L42_TS_UNPLUG:
1342                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1343                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1344                                 cs42l42_cancel_hs_type_detect(cs42l42);
1345                                 dev_dbg(component->dev,
1346                                         "Unplug event\n");
1347                         }
1348                         break;
1349
1350                 default:
1351                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1352                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1353                 }
1354         }
1355
1356         /* Check button detect status */
1357         if ((~masks[7]) & irq_params_table[7].mask) {
1358                 if (!(current_button_status &
1359                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1360
1361                         if (current_button_status &
1362                                 CS42L42_M_DETECT_TF_MASK) {
1363                                 dev_dbg(component->dev,
1364                                         "Button released\n");
1365                         } else if (current_button_status &
1366                                 CS42L42_M_DETECT_FT_MASK) {
1367                                 cs42l42_handle_button_press(cs42l42);
1368                         }
1369                 }
1370         }
1371
1372         return IRQ_HANDLED;
1373 }
1374
1375 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1376 {
1377         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1378                         CS42L42_ADC_OVFL_MASK,
1379                         (1 << CS42L42_ADC_OVFL_SHIFT));
1380
1381         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1382                         CS42L42_MIX_CHB_OVFL_MASK |
1383                         CS42L42_MIX_CHA_OVFL_MASK |
1384                         CS42L42_EQ_OVFL_MASK |
1385                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1386                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1387                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1388                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1389                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1390
1391         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1392                         CS42L42_SRC_ILK_MASK |
1393                         CS42L42_SRC_OLK_MASK |
1394                         CS42L42_SRC_IUNLK_MASK |
1395                         CS42L42_SRC_OUNLK_MASK,
1396                         (1 << CS42L42_SRC_ILK_SHIFT) |
1397                         (1 << CS42L42_SRC_OLK_SHIFT) |
1398                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1399                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1400
1401         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1402                         CS42L42_ASPRX_NOLRCK_MASK |
1403                         CS42L42_ASPRX_EARLY_MASK |
1404                         CS42L42_ASPRX_LATE_MASK |
1405                         CS42L42_ASPRX_ERROR_MASK |
1406                         CS42L42_ASPRX_OVLD_MASK,
1407                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1408                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1409                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1410                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1411                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1412
1413         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1414                         CS42L42_ASPTX_NOLRCK_MASK |
1415                         CS42L42_ASPTX_EARLY_MASK |
1416                         CS42L42_ASPTX_LATE_MASK |
1417                         CS42L42_ASPTX_SMERROR_MASK,
1418                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1419                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1420                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1421                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1422
1423         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1424                         CS42L42_PDN_DONE_MASK |
1425                         CS42L42_HSDET_AUTO_DONE_MASK,
1426                         (1 << CS42L42_PDN_DONE_SHIFT) |
1427                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1428
1429         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1430                         CS42L42_SRCPL_ADC_LK_MASK |
1431                         CS42L42_SRCPL_DAC_LK_MASK |
1432                         CS42L42_SRCPL_ADC_UNLK_MASK |
1433                         CS42L42_SRCPL_DAC_UNLK_MASK,
1434                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1435                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1436                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1437                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1438
1439         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1440                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1441                         CS42L42_TIP_SENSE_PLUG_MASK |
1442                         CS42L42_HSBIAS_SENSE_MASK,
1443                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1444                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1445                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1446
1447         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1448                         CS42L42_M_DETECT_TF_MASK |
1449                         CS42L42_M_DETECT_FT_MASK |
1450                         CS42L42_M_HSBIAS_HIZ_MASK |
1451                         CS42L42_M_SHORT_RLS_MASK |
1452                         CS42L42_M_SHORT_DET_MASK,
1453                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1454                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1455                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1456                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1457                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1458
1459         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1460                         CS42L42_VPMON_MASK,
1461                         (1 << CS42L42_VPMON_SHIFT));
1462
1463         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1464                         CS42L42_PLL_LOCK_MASK,
1465                         (1 << CS42L42_PLL_LOCK_SHIFT));
1466
1467         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1468                         CS42L42_RS_PLUG_MASK |
1469                         CS42L42_RS_UNPLUG_MASK |
1470                         CS42L42_TS_PLUG_MASK |
1471                         CS42L42_TS_UNPLUG_MASK,
1472                         (1 << CS42L42_RS_PLUG_SHIFT) |
1473                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1474                         (0 << CS42L42_TS_PLUG_SHIFT) |
1475                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1476 }
1477
1478 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1479 {
1480         unsigned int reg;
1481
1482         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1483
1484         /* Latch analog controls to VP power domain */
1485         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1486                         CS42L42_LATCH_TO_VP_MASK |
1487                         CS42L42_EVENT_STAT_SEL_MASK |
1488                         CS42L42_HS_DET_LEVEL_MASK,
1489                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1490                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1491                         (cs42l42->bias_thresholds[0] <<
1492                         CS42L42_HS_DET_LEVEL_SHIFT));
1493
1494         /* Remove ground noise-suppression clamps */
1495         regmap_update_bits(cs42l42->regmap,
1496                         CS42L42_HS_CLAMP_DISABLE,
1497                         CS42L42_HS_CLAMP_DISABLE_MASK,
1498                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1499
1500         /* Enable the tip sense circuit */
1501         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1502                         CS42L42_TIP_SENSE_CTRL_MASK |
1503                         CS42L42_TIP_SENSE_INV_MASK |
1504                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1505                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1506                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1507                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1508
1509         /* Save the initial status of the tip sense */
1510         regmap_read(cs42l42->regmap,
1511                           CS42L42_TSRS_PLUG_STATUS,
1512                           &reg);
1513         cs42l42->plug_state = (((char) reg) &
1514                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1515                       CS42L42_TS_PLUG_SHIFT;
1516 }
1517
1518 static const unsigned int threshold_defaults[] = {
1519         CS42L42_HS_DET_LEVEL_15,
1520         CS42L42_HS_DET_LEVEL_8,
1521         CS42L42_HS_DET_LEVEL_4,
1522         CS42L42_HS_DET_LEVEL_1
1523 };
1524
1525 static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1526                                         struct cs42l42_private *cs42l42)
1527 {
1528         struct device_node *np = i2c_client->dev.of_node;
1529         unsigned int val;
1530         unsigned int thresholds[CS42L42_NUM_BIASES];
1531         int ret;
1532         int i;
1533
1534         ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1535
1536         if (!ret) {
1537                 switch (val) {
1538                 case CS42L42_TS_INV_EN:
1539                 case CS42L42_TS_INV_DIS:
1540                         cs42l42->ts_inv = val;
1541                         break;
1542                 default:
1543                         dev_err(&i2c_client->dev,
1544                                 "Wrong cirrus,ts-inv DT value %d\n",
1545                                 val);
1546                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1547                 }
1548         } else {
1549                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1550         }
1551
1552         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1553                         CS42L42_TS_INV_MASK,
1554                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1555
1556         ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1557
1558         if (!ret) {
1559                 switch (val) {
1560                 case CS42L42_TS_DBNCE_0:
1561                 case CS42L42_TS_DBNCE_125:
1562                 case CS42L42_TS_DBNCE_250:
1563                 case CS42L42_TS_DBNCE_500:
1564                 case CS42L42_TS_DBNCE_750:
1565                 case CS42L42_TS_DBNCE_1000:
1566                 case CS42L42_TS_DBNCE_1250:
1567                 case CS42L42_TS_DBNCE_1500:
1568                         cs42l42->ts_dbnc_rise = val;
1569                         break;
1570                 default:
1571                         dev_err(&i2c_client->dev,
1572                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1573                                 val);
1574                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1575                 }
1576         } else {
1577                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1578         }
1579
1580         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1581                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1582                         (cs42l42->ts_dbnc_rise <<
1583                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1584
1585         ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1586
1587         if (!ret) {
1588                 switch (val) {
1589                 case CS42L42_TS_DBNCE_0:
1590                 case CS42L42_TS_DBNCE_125:
1591                 case CS42L42_TS_DBNCE_250:
1592                 case CS42L42_TS_DBNCE_500:
1593                 case CS42L42_TS_DBNCE_750:
1594                 case CS42L42_TS_DBNCE_1000:
1595                 case CS42L42_TS_DBNCE_1250:
1596                 case CS42L42_TS_DBNCE_1500:
1597                         cs42l42->ts_dbnc_fall = val;
1598                         break;
1599                 default:
1600                         dev_err(&i2c_client->dev,
1601                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1602                                 val);
1603                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1604                 }
1605         } else {
1606                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1607         }
1608
1609         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1610                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1611                         (cs42l42->ts_dbnc_fall <<
1612                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1613
1614         ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1615
1616         if (!ret) {
1617                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1618                         cs42l42->btn_det_init_dbnce = val;
1619                 else {
1620                         dev_err(&i2c_client->dev,
1621                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1622                                 val);
1623                         cs42l42->btn_det_init_dbnce =
1624                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1625                 }
1626         } else {
1627                 cs42l42->btn_det_init_dbnce =
1628                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1629         }
1630
1631         ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1632
1633         if (!ret) {
1634                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1635                         cs42l42->btn_det_event_dbnce = val;
1636                 else {
1637                         dev_err(&i2c_client->dev,
1638                         "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1639                         cs42l42->btn_det_event_dbnce =
1640                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1641                 }
1642         } else {
1643                 cs42l42->btn_det_event_dbnce =
1644                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1645         }
1646
1647         ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1648                                    (u32 *)thresholds, CS42L42_NUM_BIASES);
1649
1650         if (!ret) {
1651                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1652                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1653                                 cs42l42->bias_thresholds[i] = thresholds[i];
1654                         else {
1655                                 dev_err(&i2c_client->dev,
1656                                 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1657                                         thresholds[i]);
1658                                 cs42l42->bias_thresholds[i] =
1659                                         threshold_defaults[i];
1660                         }
1661                 }
1662         } else {
1663                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1664                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1665         }
1666
1667         ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1668
1669         if (!ret) {
1670                 switch (val) {
1671                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1672                         cs42l42->hs_bias_ramp_rate = val;
1673                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1674                         break;
1675                 case CS42L42_HSBIAS_RAMP_FAST:
1676                         cs42l42->hs_bias_ramp_rate = val;
1677                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1678                         break;
1679                 case CS42L42_HSBIAS_RAMP_SLOW:
1680                         cs42l42->hs_bias_ramp_rate = val;
1681                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1682                         break;
1683                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1684                         cs42l42->hs_bias_ramp_rate = val;
1685                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1686                         break;
1687                 default:
1688                         dev_err(&i2c_client->dev,
1689                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1690                                 val);
1691                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1692                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1693                 }
1694         } else {
1695                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1696                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1697         }
1698
1699         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1700                         CS42L42_HSBIAS_RAMP_MASK,
1701                         (cs42l42->hs_bias_ramp_rate <<
1702                         CS42L42_HSBIAS_RAMP_SHIFT));
1703
1704         return 0;
1705 }
1706
1707 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1708                                        const struct i2c_device_id *id)
1709 {
1710         struct cs42l42_private *cs42l42;
1711         int ret, i;
1712         unsigned int devid = 0;
1713         unsigned int reg;
1714
1715         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1716                                GFP_KERNEL);
1717         if (!cs42l42)
1718                 return -ENOMEM;
1719
1720         i2c_set_clientdata(i2c_client, cs42l42);
1721
1722         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1723         if (IS_ERR(cs42l42->regmap)) {
1724                 ret = PTR_ERR(cs42l42->regmap);
1725                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1726                 return ret;
1727         }
1728
1729         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1730                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1731
1732         ret = devm_regulator_bulk_get(&i2c_client->dev,
1733                                       ARRAY_SIZE(cs42l42->supplies),
1734                                       cs42l42->supplies);
1735         if (ret != 0) {
1736                 dev_err(&i2c_client->dev,
1737                         "Failed to request supplies: %d\n", ret);
1738                 return ret;
1739         }
1740
1741         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1742                                     cs42l42->supplies);
1743         if (ret != 0) {
1744                 dev_err(&i2c_client->dev,
1745                         "Failed to enable supplies: %d\n", ret);
1746                 return ret;
1747         }
1748
1749         /* Reset the Device */
1750         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1751                 "reset", GPIOD_OUT_LOW);
1752         if (IS_ERR(cs42l42->reset_gpio))
1753                 return PTR_ERR(cs42l42->reset_gpio);
1754
1755         if (cs42l42->reset_gpio) {
1756                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1757                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1758         }
1759         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1760
1761         /* Request IRQ */
1762         ret = devm_request_threaded_irq(&i2c_client->dev,
1763                         i2c_client->irq,
1764                         NULL, cs42l42_irq_thread,
1765                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1766                         "cs42l42", cs42l42);
1767
1768         if (ret != 0)
1769                 dev_err(&i2c_client->dev,
1770                         "Failed to request IRQ: %d\n", ret);
1771
1772         /* initialize codec */
1773         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
1774         devid = (reg & 0xFF) << 12;
1775
1776         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
1777         devid |= (reg & 0xFF) << 4;
1778
1779         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
1780         devid |= (reg & 0xF0) >> 4;
1781
1782         if (devid != CS42L42_CHIP_ID) {
1783                 ret = -ENODEV;
1784                 dev_err(&i2c_client->dev,
1785                         "CS42L42 Device ID (%X). Expected %X\n",
1786                         devid, CS42L42_CHIP_ID);
1787                 return ret;
1788         }
1789
1790         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1791         if (ret < 0) {
1792                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1793                 return ret;
1794         }
1795
1796         dev_info(&i2c_client->dev,
1797                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1798
1799         /* Power up the codec */
1800         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1801                         CS42L42_ASP_DAO_PDN_MASK |
1802                         CS42L42_ASP_DAI_PDN_MASK |
1803                         CS42L42_MIXER_PDN_MASK |
1804                         CS42L42_EQ_PDN_MASK |
1805                         CS42L42_HP_PDN_MASK |
1806                         CS42L42_ADC_PDN_MASK |
1807                         CS42L42_PDN_ALL_MASK,
1808                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1809                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1810                         (1 << CS42L42_MIXER_PDN_SHIFT) |
1811                         (1 << CS42L42_EQ_PDN_SHIFT) |
1812                         (1 << CS42L42_HP_PDN_SHIFT) |
1813                         (1 << CS42L42_ADC_PDN_SHIFT) |
1814                         (0 << CS42L42_PDN_ALL_SHIFT));
1815
1816         if (i2c_client->dev.of_node) {
1817                 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1818                 if (ret != 0)
1819                         return ret;
1820         }
1821
1822         /* Setup headset detection */
1823         cs42l42_setup_hs_type_detect(cs42l42);
1824
1825         /* Mask/Unmask Interrupts */
1826         cs42l42_set_interrupt_masks(cs42l42);
1827
1828         /* Register codec for machine driver */
1829         ret = devm_snd_soc_register_component(&i2c_client->dev,
1830                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1831         if (ret < 0)
1832                 goto err_disable;
1833         return 0;
1834
1835 err_disable:
1836         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1837                                 cs42l42->supplies);
1838         return ret;
1839 }
1840
1841 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1842 {
1843         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1844
1845         /* Hold down reset */
1846         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1847
1848         return 0;
1849 }
1850
1851 #ifdef CONFIG_PM
1852 static int cs42l42_runtime_suspend(struct device *dev)
1853 {
1854         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1855
1856         regcache_cache_only(cs42l42->regmap, true);
1857         regcache_mark_dirty(cs42l42->regmap);
1858
1859         /* Hold down reset */
1860         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1861
1862         /* remove power */
1863         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1864                                 cs42l42->supplies);
1865
1866         return 0;
1867 }
1868
1869 static int cs42l42_runtime_resume(struct device *dev)
1870 {
1871         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1872         int ret;
1873
1874         /* Enable power */
1875         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1876                                         cs42l42->supplies);
1877         if (ret != 0) {
1878                 dev_err(dev, "Failed to enable supplies: %d\n",
1879                         ret);
1880                 return ret;
1881         }
1882
1883         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1884         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1885
1886         regcache_cache_only(cs42l42->regmap, false);
1887         regcache_sync(cs42l42->regmap);
1888
1889         return 0;
1890 }
1891 #endif
1892
1893 static const struct dev_pm_ops cs42l42_runtime_pm = {
1894         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1895                            NULL)
1896 };
1897
1898 static const struct of_device_id cs42l42_of_match[] = {
1899         { .compatible = "cirrus,cs42l42", },
1900         {},
1901 };
1902 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1903
1904
1905 static const struct i2c_device_id cs42l42_id[] = {
1906         {"cs42l42", 0},
1907         {}
1908 };
1909
1910 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1911
1912 static struct i2c_driver cs42l42_i2c_driver = {
1913         .driver = {
1914                 .name = "cs42l42",
1915                 .pm = &cs42l42_runtime_pm,
1916                 .of_match_table = cs42l42_of_match,
1917                 },
1918         .id_table = cs42l42_id,
1919         .probe = cs42l42_i2c_probe,
1920         .remove = cs42l42_i2c_remove,
1921 };
1922
1923 module_i2c_driver(cs42l42_i2c_driver);
1924
1925 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1926 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1927 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1928 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1929 MODULE_LICENSE("GPL");