sound/pci/oxygen/oxygen_lib.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * C-Media CMI8788 driver - main driver module
   4  *
   5  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/mutex.h>
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <sound/ac97_codec.h>
  15 #include <sound/asoundef.h>
  16 #include <sound/core.h>
  17 #include <sound/info.h>
  18 #include <sound/mpu401.h>
  19 #include <sound/pcm.h>
  20 #include "oxygen.h"
  21 #include "cm9780.h"
  22
  23 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  24 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  25 MODULE_LICENSE("GPL v2");
  26
  27 #define DRIVER "oxygen"
  28
  29 static inline int oxygen_uart_input_ready(struct oxygen *chip)
  30 {
  31         return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
  32 }
  33
  34 static void oxygen_read_uart(struct oxygen *chip)
  35 {
  36         if (unlikely(!oxygen_uart_input_ready(chip))) {
  37                 /* no data, but read it anyway to clear the interrupt */
  38                 oxygen_read8(chip, OXYGEN_MPU401);
  39                 return;
  40         }
  41         do {
  42                 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
  43                 if (data == MPU401_ACK)
  44                         continue;
  45                 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
  46                         chip->uart_input_count = 0;
  47                 chip->uart_input[chip->uart_input_count++] = data;
  48         } while (oxygen_uart_input_ready(chip));
  49         if (chip->model.uart_input)
  50                 chip->model.uart_input(chip);
  51 }
  52
  53 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  54 {
  55         struct oxygen *chip = dev_id;
  56         unsigned int status, clear, elapsed_streams, i;
  57
  58         status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  59         if (!status)
  60                 return IRQ_NONE;
  61
  62         spin_lock(&chip->reg_lock);
  63
  64         clear = status & (OXYGEN_CHANNEL_A |
  65                           OXYGEN_CHANNEL_B |
  66                           OXYGEN_CHANNEL_C |
  67                           OXYGEN_CHANNEL_SPDIF |
  68                           OXYGEN_CHANNEL_MULTICH |
  69                           OXYGEN_CHANNEL_AC97 |
  70                           OXYGEN_INT_SPDIF_IN_DETECT |
  71                           OXYGEN_INT_GPIO |
  72                           OXYGEN_INT_AC97);
  73         if (clear) {
  74                 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  75                         chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  76                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  77                                chip->interrupt_mask & ~clear);
  78                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  79                                chip->interrupt_mask);
  80         }
  81
  82         elapsed_streams = status & chip->pcm_running;
  83
  84         spin_unlock(&chip->reg_lock);
  85
  86         for (i = 0; i < PCM_COUNT; ++i)
  87                 if ((elapsed_streams & (1 << i)) && chip->streams[i])
  88                         snd_pcm_period_elapsed(chip->streams[i]);
  89
  90         if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
  91                 spin_lock(&chip->reg_lock);
  92                 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
  93                 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
  94                          OXYGEN_SPDIF_RATE_INT)) {
  95                         /* write the interrupt bit(s) to clear */
  96                         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
  97                         schedule_work(&chip->spdif_input_bits_work);
  98                 }
  99                 spin_unlock(&chip->reg_lock);
 100         }
 101
 102         if (status & OXYGEN_INT_GPIO)
 103                 schedule_work(&chip->gpio_work);
 104
 105         if (status & OXYGEN_INT_MIDI) {
 106                 if (chip->midi)
 107                         snd_mpu401_uart_interrupt(0, chip->midi->private_data);
 108                 else
 109                         oxygen_read_uart(chip);
 110         }
 111
 112         if (status & OXYGEN_INT_AC97)
 113                 wake_up(&chip->ac97_waitqueue);
 114
 115         return IRQ_HANDLED;
 116 }
 117
 118 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
 119 {
 120         struct oxygen *chip = container_of(work, struct oxygen,
 121                                            spdif_input_bits_work);
 122         u32 reg;
 123
 124         /*
 125          * This function gets called when there is new activity on the SPDIF
 126          * input, or when we lose lock on the input signal, or when the rate
 127          * changes.
 128          */
 129         msleep(1);
 130         spin_lock_irq(&chip->reg_lock);
 131         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 132         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 133                     OXYGEN_SPDIF_LOCK_STATUS))
 134             == OXYGEN_SPDIF_SENSE_STATUS) {
 135                 /*
 136                  * If we detect activity on the SPDIF input but cannot lock to
 137                  * a signal, the clock bit is likely to be wrong.
 138                  */
 139                 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
 140                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 141                 spin_unlock_irq(&chip->reg_lock);
 142                 msleep(1);
 143                 spin_lock_irq(&chip->reg_lock);
 144                 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 145                 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 146                             OXYGEN_SPDIF_LOCK_STATUS))
 147                     == OXYGEN_SPDIF_SENSE_STATUS) {
 148                         /* nothing detected with either clock; give up */
 149                         if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
 150                             == OXYGEN_SPDIF_IN_CLOCK_192) {
 151                                 /*
 152                                  * Reset clock to <= 96 kHz because this is
 153                                  * more likely to be received next time.
 154                                  */
 155                                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
 156                                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
 157                                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 158                         }
 159                 }
 160         }
 161         spin_unlock_irq(&chip->reg_lock);
 162
 163         if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
 164                 spin_lock_irq(&chip->reg_lock);
 165                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 166                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
 167                                chip->interrupt_mask);
 168                 spin_unlock_irq(&chip->reg_lock);
 169
 170                 /*
 171                  * We don't actually know that any channel status bits have
 172                  * changed, but let's send a notification just to be sure.
 173                  */
 174                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
 175                                &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
 176         }
 177 }
 178
 179 static void oxygen_gpio_changed(struct work_struct *work)
 180 {
 181         struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
 182
 183         if (chip->model.gpio_changed)
 184                 chip->model.gpio_changed(chip);
 185 }
 186
 187 static void oxygen_proc_read(struct snd_info_entry *entry,
 188                              struct snd_info_buffer *buffer)
 189 {
 190         struct oxygen *chip = entry->private_data;
 191         int i, j;
 192
 193         switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
 194         case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
 195         case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
 196         case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
 197         default:                     i = '?'; break;
 198         }
 199         snd_iprintf(buffer, "CMI878%c:\n", i);
 200         for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
 201                 snd_iprintf(buffer, "%02x:", i);
 202                 for (j = 0; j < 0x10; ++j)
 203                         snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
 204                 snd_iprintf(buffer, "\n");
 205         }
 206         if (mutex_lock_interruptible(&chip->mutex) < 0)
 207                 return;
 208         if (chip->has_ac97_0) {
 209                 snd_iprintf(buffer, "\nAC97:\n");
 210                 for (i = 0; i < 0x80; i += 0x10) {
 211                         snd_iprintf(buffer, "%02x:", i);
 212                         for (j = 0; j < 0x10; j += 2)
 213                                 snd_iprintf(buffer, " %04x",
 214                                             oxygen_read_ac97(chip, 0, i + j));
 215                         snd_iprintf(buffer, "\n");
 216                 }
 217         }
 218         if (chip->has_ac97_1) {
 219                 snd_iprintf(buffer, "\nAC97 2:\n");
 220                 for (i = 0; i < 0x80; i += 0x10) {
 221                         snd_iprintf(buffer, "%02x:", i);
 222                         for (j = 0; j < 0x10; j += 2)
 223                                 snd_iprintf(buffer, " %04x",
 224                                             oxygen_read_ac97(chip, 1, i + j));
 225                         snd_iprintf(buffer, "\n");
 226                 }
 227         }
 228         mutex_unlock(&chip->mutex);
 229         if (chip->model.dump_registers)
 230                 chip->model.dump_registers(chip, buffer);
 231 }
 232
 233 static void oxygen_proc_init(struct oxygen *chip)
 234 {
 235         snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
 236 }
 237
 238 static const struct pci_device_id *
 239 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
 240 {
 241         u16 subdevice;
 242
 243         /*
 244          * Make sure the EEPROM pins are available, i.e., not used for SPI.
 245          * (This function is called before we initialize or use SPI.)
 246          */
 247         oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
 248                            OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 249         /*
 250          * Read the subsystem device ID directly from the EEPROM, because the
 251          * chip didn't if the first EEPROM word was overwritten.
 252          */
 253         subdevice = oxygen_read_eeprom(chip, 2);
 254         /* use default ID if EEPROM is missing */
 255         if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
 256                 subdevice = 0x8788;
 257         /*
 258          * We use only the subsystem device ID for searching because it is
 259          * unique even without the subsystem vendor ID, which may have been
 260          * overwritten in the EEPROM.
 261          */
 262         for (; ids->vendor; ++ids)
 263                 if (ids->subdevice == subdevice &&
 264                     ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
 265                         return ids;
 266         return NULL;
 267 }
 268
 269 static void oxygen_restore_eeprom(struct oxygen *chip,
 270                                   const struct pci_device_id *id)
 271 {
 272         u16 eeprom_id;
 273
 274         eeprom_id = oxygen_read_eeprom(chip, 0);
 275         if (eeprom_id != OXYGEN_EEPROM_ID &&
 276             (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
 277                 /*
 278                  * This function gets called only when a known card model has
 279                  * been detected, i.e., we know there is a valid subsystem
 280                  * product ID at index 2 in the EEPROM.  Therefore, we have
 281                  * been able to deduce the correct subsystem vendor ID, and
 282                  * this is enough information to restore the original EEPROM
 283                  * contents.
 284                  */
 285                 oxygen_write_eeprom(chip, 1, id->subvendor);
 286                 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
 287
 288                 oxygen_set_bits8(chip, OXYGEN_MISC,
 289                                  OXYGEN_MISC_WRITE_PCI_SUBID);
 290                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
 291                                       id->subvendor);
 292                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
 293                                       id->subdevice);
 294                 oxygen_clear_bits8(chip, OXYGEN_MISC,
 295                                    OXYGEN_MISC_WRITE_PCI_SUBID);
 296
 297                 dev_info(chip->card->dev, "EEPROM ID restored\n");
 298         }
 299 }
 300
 301 static void configure_pcie_bridge(struct pci_dev *pci)
 302 {
 303         enum { PEX811X, PI7C9X110, XIO2001 };
 304         static const struct pci_device_id bridge_ids[] = {
 305                 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
 306                 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
 307                 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
 308                 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
 309                 { }
 310         };
 311         struct pci_dev *bridge;
 312         const struct pci_device_id *id;
 313         u32 tmp;
 314
 315         if (!pci->bus || !pci->bus->self)
 316                 return;
 317         bridge = pci->bus->self;
 318
 319         id = pci_match_id(bridge_ids, bridge);
 320         if (!id)
 321                 return;
 322
 323         switch (id->driver_data) {
 324         case PEX811X:   /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
 325                 pci_read_config_dword(bridge, 0x48, &tmp);
 326                 tmp |= 1;       /* enable blind prefetching */
 327                 tmp |= 1 << 11; /* enable beacon generation */
 328                 pci_write_config_dword(bridge, 0x48, tmp);
 329
 330                 pci_write_config_dword(bridge, 0x84, 0x0c);
 331                 pci_read_config_dword(bridge, 0x88, &tmp);
 332                 tmp &= ~(7 << 27);
 333                 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
 334                 pci_write_config_dword(bridge, 0x88, tmp);
 335                 break;
 336
 337         case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
 338                 pci_read_config_dword(bridge, 0x40, &tmp);
 339                 tmp |= 1;       /* park the PCI arbiter to the sound chip */
 340                 pci_write_config_dword(bridge, 0x40, tmp);
 341                 break;
 342
 343         case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
 344                 pci_read_config_dword(bridge, 0xe8, &tmp);
 345                 tmp &= ~0xf;    /* request length limit: 64 bytes */
 346                 tmp &= ~(0xf << 8);
 347                 tmp |= 1 << 8;  /* request count limit: one buffer */
 348                 pci_write_config_dword(bridge, 0xe8, tmp);
 349                 break;
 350         }
 351 }
 352
 353 static void oxygen_init(struct oxygen *chip)
 354 {
 355         unsigned int i;
 356
 357         chip->dac_routing = 1;
 358         for (i = 0; i < 8; ++i)
 359                 chip->dac_volume[i] = chip->model.dac_volume_min;
 360         chip->dac_mute = 1;
 361         chip->spdif_playback_enable = 0;
 362         chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
 363                 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
 364         chip->spdif_pcm_bits = chip->spdif_bits;
 365
 366         if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
 367                 oxygen_set_bits8(chip, OXYGEN_MISC,
 368                                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
 369
 370         i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
 371         chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
 372         chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
 373
 374         oxygen_write8_masked(chip, OXYGEN_FUNCTION,
 375                              OXYGEN_FUNCTION_RESET_CODEC |
 376                              chip->model.function_flags,
 377                              OXYGEN_FUNCTION_RESET_CODEC |
 378                              OXYGEN_FUNCTION_2WIRE_SPI_MASK |
 379                              OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 380         oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
 381         oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
 382         oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
 383                       OXYGEN_PLAY_CHANNELS_2 |
 384                       OXYGEN_DMA_A_BURST_8 |
 385                       OXYGEN_DMA_MULTICH_BURST_8);
 386         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 387         oxygen_write8_masked(chip, OXYGEN_MISC,
 388                              chip->model.misc_flags,
 389                              OXYGEN_MISC_WRITE_PCI_SUBID |
 390                              OXYGEN_MISC_REC_C_FROM_SPDIF |
 391                              OXYGEN_MISC_REC_B_FROM_AC97 |
 392                              OXYGEN_MISC_REC_A_FROM_MULTICH |
 393                              OXYGEN_MISC_MIDI);
 394         oxygen_write8(chip, OXYGEN_REC_FORMAT,
 395                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
 396                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
 397                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
 398         oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
 399                       (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
 400                       (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
 401         oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
 402         oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
 403                        OXYGEN_RATE_48000 |
 404                        chip->model.dac_i2s_format |
 405                        OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
 406                        OXYGEN_I2S_BITS_16 |
 407                        OXYGEN_I2S_MASTER |
 408                        OXYGEN_I2S_BCLK_64);
 409         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
 410                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 411                                OXYGEN_RATE_48000 |
 412                                chip->model.adc_i2s_format |
 413                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 414                                OXYGEN_I2S_BITS_16 |
 415                                OXYGEN_I2S_MASTER |
 416                                OXYGEN_I2S_BCLK_64);
 417         else
 418                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 419                                OXYGEN_I2S_MASTER |
 420                                OXYGEN_I2S_MUTE_MCLK);
 421         if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
 422                                          CAPTURE_2_FROM_I2S_2))
 423                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 424                                OXYGEN_RATE_48000 |
 425                                chip->model.adc_i2s_format |
 426                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 427                                OXYGEN_I2S_BITS_16 |
 428                                OXYGEN_I2S_MASTER |
 429                                OXYGEN_I2S_BCLK_64);
 430         else
 431                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 432                                OXYGEN_I2S_MASTER |
 433                                OXYGEN_I2S_MUTE_MCLK);
 434         if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
 435                 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 436                                OXYGEN_RATE_48000 |
 437                                chip->model.adc_i2s_format |
 438                                OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
 439                                OXYGEN_I2S_BITS_16 |
 440                                OXYGEN_I2S_MASTER |
 441                                OXYGEN_I2S_BCLK_64);
 442         else
 443                 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 444                                OXYGEN_I2S_MASTER |
 445                                OXYGEN_I2S_MUTE_MCLK);
 446         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 447                             OXYGEN_SPDIF_OUT_ENABLE |
 448                             OXYGEN_SPDIF_LOOPBACK);
 449         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 450                 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
 451                                       OXYGEN_SPDIF_SENSE_MASK |
 452                                       OXYGEN_SPDIF_LOCK_MASK |
 453                                       OXYGEN_SPDIF_RATE_MASK |
 454                                       OXYGEN_SPDIF_LOCK_PAR |
 455                                       OXYGEN_SPDIF_IN_CLOCK_96,
 456                                       OXYGEN_SPDIF_SENSE_MASK |
 457                                       OXYGEN_SPDIF_LOCK_MASK |
 458                                       OXYGEN_SPDIF_RATE_MASK |
 459                                       OXYGEN_SPDIF_SENSE_PAR |
 460                                       OXYGEN_SPDIF_LOCK_PAR |
 461                                       OXYGEN_SPDIF_IN_CLOCK_MASK);
 462         else
 463                 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 464                                     OXYGEN_SPDIF_SENSE_MASK |
 465                                     OXYGEN_SPDIF_LOCK_MASK |
 466                                     OXYGEN_SPDIF_RATE_MASK);
 467         oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
 468         oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
 469                        OXYGEN_2WIRE_LENGTH_8 |
 470                        OXYGEN_2WIRE_INTERRUPT_MASK |
 471                        OXYGEN_2WIRE_SPEED_STANDARD);
 472         oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
 473         oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
 474         oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
 475         oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
 476                        OXYGEN_PLAY_MULTICH_I2S_DAC |
 477                        OXYGEN_PLAY_SPDIF_SPDIF |
 478                        (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
 479                        (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
 480                        (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
 481                        (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
 482         oxygen_write8(chip, OXYGEN_REC_ROUTING,
 483                       OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
 484                       OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
 485                       OXYGEN_REC_C_ROUTE_SPDIF);
 486         oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
 487         oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
 488                       (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
 489                       (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
 490                       (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
 491                       (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
 492
 493         if (chip->has_ac97_0 | chip->has_ac97_1)
 494                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
 495                               OXYGEN_AC97_INT_READ_DONE |
 496                               OXYGEN_AC97_INT_WRITE_DONE);
 497         else
 498                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
 499         oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
 500         oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
 501         if (!(chip->has_ac97_0 | chip->has_ac97_1))
 502                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 503                                   OXYGEN_AC97_CLOCK_DISABLE);
 504         if (!chip->has_ac97_0) {
 505                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 506                                   OXYGEN_AC97_NO_CODEC_0);
 507         } else {
 508                 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
 509                 msleep(1);
 510                 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
 511                                      CM9780_GPIO0IO | CM9780_GPIO1IO);
 512                 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
 513                                      CM9780_BSTSEL | CM9780_STRO_MIC |
 514                                      CM9780_MIX2FR | CM9780_PCBSW);
 515                 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
 516                                      CM9780_RSOE | CM9780_CBOE |
 517                                      CM9780_SSOE | CM9780_FROE |
 518                                      CM9780_MIC2MIC | CM9780_LI2LI);
 519                 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
 520                 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
 521                 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
 522                 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
 523                 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
 524                 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
 525                 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
 526                 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
 527                 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
 528                 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
 529                 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
 530                                        CM9780_GPO0);
 531                 /* power down unused ADCs and DACs */
 532                 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
 533                                      AC97_PD_PR0 | AC97_PD_PR1);
 534                 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
 535                                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
 536         }
 537         if (chip->has_ac97_1) {
 538                 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
 539                                   OXYGEN_AC97_CODEC1_SLOT3 |
 540                                   OXYGEN_AC97_CODEC1_SLOT4);
 541                 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
 542                 msleep(1);
 543                 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
 544                 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
 545                 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
 546                 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
 547                 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
 548                 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
 549                 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
 550                 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
 551                 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
 552                 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
 553                 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
 554                 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
 555         }
 556 }
 557
 558 static void oxygen_shutdown(struct oxygen *chip)
 559 {
 560         spin_lock_irq(&chip->reg_lock);
 561         chip->interrupt_mask = 0;
 562         chip->pcm_running = 0;
 563         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 564         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 565         spin_unlock_irq(&chip->reg_lock);
 566 }
 567
 568 static void oxygen_card_free(struct snd_card *card)
 569 {
 570         struct oxygen *chip = card->private_data;
 571
 572         oxygen_shutdown(chip);
 573         flush_work(&chip->spdif_input_bits_work);
 574         flush_work(&chip->gpio_work);
 575         chip->model.cleanup(chip);
 576         mutex_destroy(&chip->mutex);
 577 }
 578
 579 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
 580                      struct module *owner,
 581                      const struct pci_device_id *ids,
 582                      int (*get_model)(struct oxygen *chip,
 583                                       const struct pci_device_id *id
 584                                      )
 585                     )
 586 {
 587         struct snd_card *card;
 588         struct oxygen *chip;
 589         const struct pci_device_id *pci_id;
 590         int err;
 591
 592         err = snd_devm_card_new(&pci->dev, index, id, owner,
 593                                 sizeof(*chip), &card);
 594         if (err < 0)
 595                 return err;
 596
 597         chip = card->private_data;
 598         chip->card = card;
 599         chip->pci = pci;
 600         chip->irq = -1;
 601         spin_lock_init(&chip->reg_lock);
 602         mutex_init(&chip->mutex);
 603         INIT_WORK(&chip->spdif_input_bits_work,
 604                   oxygen_spdif_input_bits_changed);
 605         INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
 606         init_waitqueue_head(&chip->ac97_waitqueue);
 607
 608         err = pcim_enable_device(pci);
 609         if (err < 0)
 610                 return err;
 611
 612         err = pci_request_regions(pci, DRIVER);
 613         if (err < 0) {
 614                 dev_err(card->dev, "cannot reserve PCI resources\n");
 615                 return err;
 616         }
 617
 618         if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
 619             pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
 620                 dev_err(card->dev, "invalid PCI I/O range\n");
 621                 return -ENXIO;
 622         }
 623         chip->addr = pci_resource_start(pci, 0);
 624
 625         pci_id = oxygen_search_pci_id(chip, ids);
 626         if (!pci_id)
 627                 return -ENODEV;
 628
 629         oxygen_restore_eeprom(chip, pci_id);
 630         err = get_model(chip, pci_id);
 631         if (err < 0)
 632                 return err;
 633
 634         if (chip->model.model_data_size) {
 635                 chip->model_data = devm_kzalloc(&pci->dev,
 636                                                 chip->model.model_data_size,
 637                                                 GFP_KERNEL);
 638                 if (!chip->model_data)
 639                         return -ENOMEM;
 640         }
 641
 642         pci_set_master(pci);
 643         card->private_free = oxygen_card_free;
 644
 645         configure_pcie_bridge(pci);
 646         oxygen_init(chip);
 647         chip->model.init(chip);
 648
 649         err = devm_request_irq(&pci->dev, pci->irq, oxygen_interrupt,
 650                                IRQF_SHARED, KBUILD_MODNAME, chip);
 651         if (err < 0) {
 652                 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
 653                 return err;
 654         }
 655         chip->irq = pci->irq;
 656         card->sync_irq = chip->irq;
 657
 658         strcpy(card->driver, chip->model.chip);
 659         strcpy(card->shortname, chip->model.shortname);
 660         sprintf(card->longname, "%s at %#lx, irq %i",
 661                 chip->model.longname, chip->addr, chip->irq);
 662         strcpy(card->mixername, chip->model.chip);
 663         snd_component_add(card, chip->model.chip);
 664
 665         err = oxygen_pcm_init(chip);
 666         if (err < 0)
 667                 return err;
 668
 669         err = oxygen_mixer_init(chip);
 670         if (err < 0)
 671                 return err;
 672
 673         if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
 674                 unsigned int info_flags =
 675                                 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
 676                 if (chip->model.device_config & MIDI_OUTPUT)
 677                         info_flags |= MPU401_INFO_OUTPUT;
 678                 if (chip->model.device_config & MIDI_INPUT)
 679                         info_flags |= MPU401_INFO_INPUT;
 680                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
 681                                           chip->addr + OXYGEN_MPU401,
 682                                           info_flags, -1, &chip->midi);
 683                 if (err < 0)
 684                         return err;
 685         }
 686
 687         oxygen_proc_init(chip);
 688
 689         spin_lock_irq(&chip->reg_lock);
 690         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 691                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 692         if (chip->has_ac97_0 | chip->has_ac97_1)
 693                 chip->interrupt_mask |= OXYGEN_INT_AC97;
 694         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 695         spin_unlock_irq(&chip->reg_lock);
 696
 697         err = snd_card_register(card);
 698         if (err < 0)
 699                 return err;
 700
 701         pci_set_drvdata(pci, card);
 702         return 0;
 703 }
 704 EXPORT_SYMBOL(oxygen_pci_probe);
 705
 706 #ifdef CONFIG_PM_SLEEP
 707 static int oxygen_pci_suspend(struct device *dev)
 708 {
 709         struct snd_card *card = dev_get_drvdata(dev);
 710         struct oxygen *chip = card->private_data;
 711         unsigned int saved_interrupt_mask;
 712
 713         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 714
 715         if (chip->model.suspend)
 716                 chip->model.suspend(chip);
 717
 718         spin_lock_irq(&chip->reg_lock);
 719         saved_interrupt_mask = chip->interrupt_mask;
 720         chip->interrupt_mask = 0;
 721         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 722         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 723         spin_unlock_irq(&chip->reg_lock);
 724
 725         flush_work(&chip->spdif_input_bits_work);
 726         flush_work(&chip->gpio_work);
 727         chip->interrupt_mask = saved_interrupt_mask;
 728         return 0;
 729 }
 730
 731 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
 732         0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
 733         0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
 734 };
 735 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
 736         { 0x18284fa2, 0x03060000 },
 737         { 0x00007fa6, 0x00200000 }
 738 };
 739
 740 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
 741 {
 742         return bitmap[bit / 32] & (1 << (bit & 31));
 743 }
 744
 745 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
 746 {
 747         unsigned int i;
 748
 749         oxygen_write_ac97(chip, codec, AC97_RESET, 0);
 750         msleep(1);
 751         for (i = 1; i < 0x40; ++i)
 752                 if (is_bit_set(ac97_registers_to_restore[codec], i))
 753                         oxygen_write_ac97(chip, codec, i * 2,
 754                                           chip->saved_ac97_registers[codec][i]);
 755 }
 756
 757 static int oxygen_pci_resume(struct device *dev)
 758 {
 759         struct snd_card *card = dev_get_drvdata(dev);
 760         struct oxygen *chip = card->private_data;
 761         unsigned int i;
 762
 763         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 764         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 765         for (i = 0; i < OXYGEN_IO_SIZE; ++i)
 766                 if (is_bit_set(registers_to_restore, i))
 767                         oxygen_write8(chip, i, chip->saved_registers._8[i]);
 768         if (chip->has_ac97_0)
 769                 oxygen_restore_ac97(chip, 0);
 770         if (chip->has_ac97_1)
 771                 oxygen_restore_ac97(chip, 1);
 772
 773         if (chip->model.resume)
 774                 chip->model.resume(chip);
 775
 776         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 777
 778         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 779         return 0;
 780 }
 781
 782 SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
 783 EXPORT_SYMBOL(oxygen_pci_pm);
 784 #endif /* CONFIG_PM_SLEEP */
 785
 786 void oxygen_pci_shutdown(struct pci_dev *pci)
 787 {
 788         struct snd_card *card = pci_get_drvdata(pci);
 789         struct oxygen *chip = card->private_data;
 790
 791         oxygen_shutdown(chip);
 792         chip->model.cleanup(chip);
 793 }
 794 EXPORT_SYMBOL(oxygen_pci_shutdown);