1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
9 #ifndef __CS8409_PATCH_H
10 #define __CS8409_PATCH_H
12 #include <linux/pci.h>
13 #include <sound/tlv.h>
14 #include <linux/workqueue.h>
15 #include <sound/hda_codec.h>
16 #include "hda_local.h"
17 #include "hda_auto_parser.h"
19 #include "hda_generic.h"
21 /* CS8409 Specific Definitions */
26 CS8409_PIN_ASP1_OUT_A,
27 CS8409_PIN_ASP1_OUT_B,
28 CS8409_PIN_ASP1_OUT_C,
29 CS8409_PIN_ASP1_OUT_D,
30 CS8409_PIN_ASP1_OUT_E,
31 CS8409_PIN_ASP1_OUT_F,
32 CS8409_PIN_ASP1_OUT_G,
33 CS8409_PIN_ASP1_OUT_H,
34 CS8409_PIN_ASP2_OUT_A,
35 CS8409_PIN_ASP2_OUT_B,
36 CS8409_PIN_ASP2_OUT_C,
37 CS8409_PIN_ASP2_OUT_D,
38 CS8409_PIN_ASP2_OUT_E,
39 CS8409_PIN_ASP2_OUT_F,
40 CS8409_PIN_ASP2_OUT_G,
41 CS8409_PIN_ASP2_OUT_H,
60 CS8409_PIN_ASP1_TRANSMITTER_A,
61 CS8409_PIN_ASP1_TRANSMITTER_B,
62 CS8409_PIN_ASP1_TRANSMITTER_C,
63 CS8409_PIN_ASP1_TRANSMITTER_D,
64 CS8409_PIN_ASP1_TRANSMITTER_E,
65 CS8409_PIN_ASP1_TRANSMITTER_F,
66 CS8409_PIN_ASP1_TRANSMITTER_G,
67 CS8409_PIN_ASP1_TRANSMITTER_H,
68 CS8409_PIN_ASP2_TRANSMITTER_A,
69 CS8409_PIN_ASP2_TRANSMITTER_B,
70 CS8409_PIN_ASP2_TRANSMITTER_C,
71 CS8409_PIN_ASP2_TRANSMITTER_D,
72 CS8409_PIN_ASP2_TRANSMITTER_E,
73 CS8409_PIN_ASP2_TRANSMITTER_F,
74 CS8409_PIN_ASP2_TRANSMITTER_G,
75 CS8409_PIN_ASP2_TRANSMITTER_H,
76 CS8409_PIN_ASP1_RECEIVER_A,
77 CS8409_PIN_ASP1_RECEIVER_B,
78 CS8409_PIN_ASP1_RECEIVER_C,
79 CS8409_PIN_ASP1_RECEIVER_D,
80 CS8409_PIN_ASP1_RECEIVER_E,
81 CS8409_PIN_ASP1_RECEIVER_F,
82 CS8409_PIN_ASP1_RECEIVER_G,
83 CS8409_PIN_ASP1_RECEIVER_H,
84 CS8409_PIN_ASP2_RECEIVER_A,
85 CS8409_PIN_ASP2_RECEIVER_B,
86 CS8409_PIN_ASP2_RECEIVER_C,
87 CS8409_PIN_ASP2_RECEIVER_D,
88 CS8409_PIN_ASP2_RECEIVER_E,
89 CS8409_PIN_ASP2_RECEIVER_F,
90 CS8409_PIN_ASP2_RECEIVER_G,
91 CS8409_PIN_ASP2_RECEIVER_H,
95 CS8409_PIN_VENDOR_WIDGET
98 enum cs8409_coefficient_index_registers {
102 CS8409_ASP1_CLK_CTRL1,
103 CS8409_ASP1_CLK_CTRL2,
104 CS8409_ASP1_CLK_CTRL3,
105 CS8409_ASP2_CLK_CTRL1,
106 CS8409_ASP2_CLK_CTRL2,
107 CS8409_ASP2_CLK_CTRL3,
110 ASP1_RX_NULL_INS_RMV,
113 ASP1_Tx_NULL_INS_RMV,
116 ASP2_Rx_NULL_INS_RMV,
119 ASP2_Tx_NULL_INS_RMV,
198 CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
202 CS8409_PRE_SCALE_ATTN1,
203 CS8409_PRE_SCALE_ATTN2,
204 CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
205 CS8409_PFE_COEF_MON2,
206 CS8409_ASP1_INTRN_STS,
207 CS8409_ASP2_INTRN_STS,
208 CS8409_ASP1_RX_SCLK_COUNT,
209 CS8409_ASP1_TX_SCLK_COUNT,
210 CS8409_ASP2_RX_SCLK_COUNT,
211 CS8409_ASP2_TX_SCLK_COUNT,
212 CS8409_ASP_UNS_RESP_MASK,
213 CS8409_LOOPBACK_CTRL = 0x80,
214 CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
217 /* CS42L42 Specific Definitions */
219 #define CS8409_MAX_CODECS 8
220 #define CS42L42_VOLUMES (4U)
221 #define CS42L42_HP_VOL_REAL_MIN (-63)
222 #define CS42L42_HP_VOL_REAL_MAX (0)
223 #define CS42L42_AMIC_VOL_REAL_MIN (-97)
224 #define CS42L42_AMIC_VOL_REAL_MAX (12)
225 #define CS42L42_REG_HS_VOL_CHA (0x2301)
226 #define CS42L42_REG_HS_VOL_CHB (0x2303)
227 #define CS42L42_REG_HS_VOL_MASK (0x003F)
228 #define CS42L42_REG_AMIC_VOL (0x1D03)
229 #define CS42L42_REG_AMIC_VOL_MASK (0x00FF)
230 #define CS42L42_HSDET_AUTO_DONE (0x02)
231 #define CS42L42_HSTYPE_MASK (0x03)
232 #define CS42L42_JACK_INSERTED (0x0C)
233 #define CS42L42_JACK_REMOVED (0x00)
235 /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
237 #define CS42L42_I2C_ADDR (0x48 << 1)
238 #define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */
239 #define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */
240 #define CS8409_CS42L42_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A
241 #define CS8409_CS42L42_SPK_PIN_NID CS8409_PIN_ASP2_TRANSMITTER_A
242 #define CS8409_CS42L42_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A
243 #define CS8409_CS42L42_DMIC_PIN_NID CS8409_PIN_DMIC1_IN
244 #define CS8409_CS42L42_DMIC_ADC_PIN_NID CS8409_PIN_DMIC1
248 #define DOLPHIN_C0_I2C_ADDR (0x48 << 1)
249 #define DOLPHIN_C1_I2C_ADDR (0x49 << 1)
250 #define DOLPHIN_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A
251 #define DOLPHIN_LO_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_B
252 #define DOLPHIN_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A
254 #define DOLPHIN_C0_INT GENMASK(4, 4)
255 #define DOLPHIN_C1_INT GENMASK(0, 0)
256 #define DOLPHIN_C0_RESET GENMASK(5, 5)
257 #define DOLPHIN_C1_RESET GENMASK(1, 1)
258 #define DOLPHIN_WAKE (DOLPHIN_C0_INT | DOLPHIN_C1_INT)
266 CS8409_DOLPHIN_FIXUPS,
279 struct cs8409_i2c_param {
284 struct cs8409_cir_param {
291 struct hda_codec *codec;
293 unsigned int reset_gpio;
294 unsigned int irq_mask;
295 const struct cs8409_i2c_param *init_seq;
296 unsigned int init_seq_num;
298 unsigned int hp_jack_in:1;
299 unsigned int mic_jack_in:1;
300 unsigned int suspended:1;
301 unsigned int paged:1;
302 unsigned int last_page;
303 unsigned int hsbias_hiz;
304 unsigned int full_scale_vol:1;
305 unsigned int no_type_dect:1;
307 s8 vol[CS42L42_VOLUMES];
311 struct hda_gen_spec gen;
312 struct hda_codec *codec;
314 struct sub_codec *scodecs[CS8409_MAX_CODECS];
315 unsigned int num_scodecs;
317 unsigned int gpio_mask;
318 unsigned int gpio_dir;
319 unsigned int gpio_data;
321 struct mutex i2c_mux;
322 unsigned int i2c_clck_enabled;
323 unsigned int dev_addr;
324 struct delayed_work i2c_clk_work;
326 /* verb exec op override */
327 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
331 extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;
332 extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;
334 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);
335 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
336 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
338 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;
339 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;
340 extern const struct snd_pci_quirk cs8409_fixup_tbl[];
341 extern const struct hda_model_fixup cs8409_models[];
342 extern const struct hda_fixup cs8409_fixups[];
343 extern const struct hda_verb cs8409_cs42l42_init_verbs[];
344 extern const struct hda_pintbl cs8409_cs42l42_pincfgs[];
345 extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];
346 extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];
347 extern struct sub_codec cs8409_cs42l42_codec;
349 extern const struct hda_verb dolphin_init_verbs[];
350 extern const struct hda_pintbl dolphin_pincfgs[];
351 extern const struct cs8409_cir_param dolphin_hw_cfg[];
352 extern struct sub_codec dolphin_cs42l42_0;
353 extern struct sub_codec dolphin_cs42l42_1;
355 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
356 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);