sound/pci/hda/patch_cs8409.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
   4  *
   5  * Copyright (C) 2021 Cirrus Logic, Inc. and
   6  *                    Cirrus Logic International Semiconductor Ltd.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <sound/core.h>
  13 #include <linux/mutex.h>
  14
  15 #include "patch_cs8409.h"
  16
  17 /******************************************************************************
  18  *                        CS8409 Specific Functions
  19  ******************************************************************************/
  20
  21 static int cs8409_parse_auto_config(struct hda_codec *codec)
  22 {
  23         struct cs8409_spec *spec = codec->spec;
  24         int err;
  25         int i;
  26
  27         err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
  28         if (err < 0)
  29                 return err;
  30
  31         err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
  32         if (err < 0)
  33                 return err;
  34
  35         /* keep the ADCs powered up when it's dynamically switchable */
  36         if (spec->gen.dyn_adc_switch) {
  37                 unsigned int done = 0;
  38
  39                 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
  40                         int idx = spec->gen.dyn_adc_idx[i];
  41
  42                         if (done & (1 << idx))
  43                                 continue;
  44                         snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
  45                         done |= 1 << idx;
  46                 }
  47         }
  48
  49         return 0;
  50 }
  51
  52 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
  53
  54 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
  55 {
  56         struct cs8409_spec *spec;
  57
  58         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  59         if (!spec)
  60                 return NULL;
  61         codec->spec = spec;
  62         spec->codec = codec;
  63         codec->power_save_node = 1;
  64         mutex_init(&spec->i2c_mux);
  65         INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
  66         snd_hda_gen_spec_init(&spec->gen);
  67
  68         return spec;
  69 }
  70
  71 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
  72 {
  73         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  74         return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
  75 }
  76
  77 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
  78                                           unsigned int coef)
  79 {
  80         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  81         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
  82 }
  83
  84 /*
  85  * cs8409_enable_i2c_clock - Disable I2C clocks
  86  * @codec: the codec instance
  87  * Disable I2C clocks.
  88  * This must be called when the i2c mutex is unlocked.
  89  */
  90 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
  91 {
  92         struct cs8409_spec *spec = codec->spec;
  93
  94         mutex_lock(&spec->i2c_mux);
  95         if (spec->i2c_clck_enabled) {
  96                 cs8409_vendor_coef_set(spec->codec, 0x0,
  97                                cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
  98                 spec->i2c_clck_enabled = 0;
  99         }
 100         mutex_unlock(&spec->i2c_mux);
 101 }
 102
 103 /*
 104  * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
 105  */
 106 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
 107 {
 108         struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
 109
 110         cs8409_disable_i2c_clock(spec->codec);
 111 }
 112
 113 /*
 114  * cs8409_enable_i2c_clock - Enable I2C clocks
 115  * @codec: the codec instance
 116  * Enable I2C clocks.
 117  * This must be called when the i2c mutex is locked.
 118  */
 119 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
 120 {
 121         struct cs8409_spec *spec = codec->spec;
 122
 123         /* Cancel the disable timer, but do not wait for any running disable functions to finish.
 124          * If the disable timer runs out before cancel, the delayed work thread will be blocked,
 125          * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
 126          * any i2c transaction, so the disable function will run to completion immediately
 127          * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
 128          */
 129         cancel_delayed_work(&spec->i2c_clk_work);
 130
 131         if (!spec->i2c_clck_enabled) {
 132                 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
 133                 spec->i2c_clck_enabled = 1;
 134         }
 135         queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
 136 }
 137
 138 /**
 139  * cs8409_i2c_wait_complete - Wait for I2C transaction
 140  * @codec: the codec instance
 141  *
 142  * Wait for I2C transaction to complete.
 143  * Return -1 if transaction wait times out.
 144  */
 145 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
 146 {
 147         int repeat = 5;
 148         unsigned int retval;
 149
 150         do {
 151                 retval = cs8409_vendor_coef_get(codec, CS8409_I2C_STS);
 152                 if ((retval & 0x18) != 0x18) {
 153                         usleep_range(2000, 4000);
 154                         --repeat;
 155                 } else
 156                         return 0;
 157
 158         } while (repeat);
 159
 160         return -1;
 161 }
 162
 163 /**
 164  * cs8409_set_i2c_dev_addr - Set i2c address for transaction
 165  * @codec: the codec instance
 166  * @addr: I2C Address
 167  */
 168 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
 169 {
 170         struct cs8409_spec *spec = codec->spec;
 171
 172         if (spec->dev_addr != addr) {
 173                 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
 174                 spec->dev_addr = addr;
 175         }
 176 }
 177
 178 /**
 179  * cs8409_i2c_set_page - CS8409 I2C set page register.
 180  * @scodec: the codec instance
 181  * @i2c_reg: Page register
 182  *
 183  * Returns negative on error.
 184  */
 185 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
 186 {
 187         struct hda_codec *codec = scodec->codec;
 188
 189         if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
 190                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
 191                 if (cs8409_i2c_wait_complete(codec) < 0)
 192                         return -EIO;
 193                 scodec->last_page = i2c_reg >> 8;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * cs8409_i2c_read - CS8409 I2C Read.
 201  * @scodec: the codec instance
 202  * @addr: Register to read
 203  *
 204  * Returns negative on error, otherwise returns read value in bits 0-7.
 205  */
 206 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
 207 {
 208         struct hda_codec *codec = scodec->codec;
 209         struct cs8409_spec *spec = codec->spec;
 210         unsigned int i2c_reg_data;
 211         unsigned int read_data;
 212
 213         if (scodec->suspended)
 214                 return -EPERM;
 215
 216         mutex_lock(&spec->i2c_mux);
 217         cs8409_enable_i2c_clock(codec);
 218         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 219
 220         if (cs8409_i2c_set_page(scodec, addr))
 221                 goto error;
 222
 223         i2c_reg_data = (addr << 8) & 0x0ffff;
 224         cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 225         if (cs8409_i2c_wait_complete(codec) < 0)
 226                 goto error;
 227
 228         /* Register in bits 15-8 and the data in 7-0 */
 229         read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
 230
 231         mutex_unlock(&spec->i2c_mux);
 232         return read_data & 0x0ff;
 233
 234 error:
 235         mutex_unlock(&spec->i2c_mux);
 236         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 237         return -EIO;
 238 }
 239
 240 /**
 241  * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
 242  * @scodec: the codec instance
 243  * @seq: Register Sequence to read
 244  * @count: Number of registeres to read
 245  *
 246  * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
 247  */
 248 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
 249 {
 250         struct hda_codec *codec = scodec->codec;
 251         struct cs8409_spec *spec = codec->spec;
 252         unsigned int i2c_reg_data;
 253         int i;
 254
 255         if (scodec->suspended)
 256                 return -EPERM;
 257
 258         mutex_lock(&spec->i2c_mux);
 259         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 260
 261         for (i = 0; i < count; i++) {
 262                 cs8409_enable_i2c_clock(codec);
 263                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 264                         goto error;
 265
 266                 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
 267                 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 268
 269                 if (cs8409_i2c_wait_complete(codec) < 0)
 270                         goto error;
 271
 272                 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
 273         }
 274
 275         mutex_unlock(&spec->i2c_mux);
 276
 277         return 0;
 278
 279 error:
 280         mutex_unlock(&spec->i2c_mux);
 281         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 282         return -EIO;
 283 }
 284
 285 /**
 286  * cs8409_i2c_write - CS8409 I2C Write.
 287  * @scodec: the codec instance
 288  * @addr: Register to write to
 289  * @value: Data to write
 290  *
 291  * Returns negative on error, otherwise returns 0.
 292  */
 293 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
 294 {
 295         struct hda_codec *codec = scodec->codec;
 296         struct cs8409_spec *spec = codec->spec;
 297         unsigned int i2c_reg_data;
 298
 299         if (scodec->suspended)
 300                 return -EPERM;
 301
 302         mutex_lock(&spec->i2c_mux);
 303
 304         cs8409_enable_i2c_clock(codec);
 305         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 306
 307         if (cs8409_i2c_set_page(scodec, addr))
 308                 goto error;
 309
 310         i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
 311         cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 312
 313         if (cs8409_i2c_wait_complete(codec) < 0)
 314                 goto error;
 315
 316         mutex_unlock(&spec->i2c_mux);
 317         return 0;
 318
 319 error:
 320         mutex_unlock(&spec->i2c_mux);
 321         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 322         return -EIO;
 323 }
 324
 325 /**
 326  * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
 327  * @scodec: the codec instance
 328  * @seq: Register Sequence to write
 329  * @count: Number of registeres to write
 330  *
 331  * Returns negative on error.
 332  */
 333 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
 334                                  int count)
 335 {
 336         struct hda_codec *codec = scodec->codec;
 337         struct cs8409_spec *spec = codec->spec;
 338         unsigned int i2c_reg_data;
 339         int i;
 340
 341         if (scodec->suspended)
 342                 return -EPERM;
 343
 344         mutex_lock(&spec->i2c_mux);
 345         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 346
 347         for (i = 0; i < count; i++) {
 348                 cs8409_enable_i2c_clock(codec);
 349                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 350                         goto error;
 351
 352                 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
 353                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 354
 355                 if (cs8409_i2c_wait_complete(codec) < 0)
 356                         goto error;
 357         }
 358
 359         mutex_unlock(&spec->i2c_mux);
 360
 361         return 0;
 362
 363 error:
 364         mutex_unlock(&spec->i2c_mux);
 365         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 366         return -EIO;
 367 }
 368
 369 static int cs8409_init(struct hda_codec *codec)
 370 {
 371         int ret = snd_hda_gen_init(codec);
 372
 373         if (!ret)
 374                 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
 375
 376         return ret;
 377 }
 378
 379 static int cs8409_build_controls(struct hda_codec *codec)
 380 {
 381         int err;
 382
 383         err = snd_hda_gen_build_controls(codec);
 384         if (err < 0)
 385                 return err;
 386         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
 387
 388         return 0;
 389 }
 390
 391 /* Enable/Disable Unsolicited Response */
 392 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
 393 {
 394         struct cs8409_spec *spec = codec->spec;
 395         unsigned int ur_gpios = 0;
 396         int i;
 397
 398         for (i = 0; i < spec->num_scodecs; i++)
 399                 ur_gpios |= spec->scodecs[i]->irq_mask;
 400
 401         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
 402                             flag ? ur_gpios : 0);
 403
 404         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
 405                             flag ? AC_UNSOL_ENABLED : 0);
 406 }
 407
 408 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
 409 {
 410         int caps;
 411
 412         /* CS8409 is simple HDA bridge and intended to be used with a remote
 413          * companion codec. Most of input/output PIN(s) have only basic
 414          * capabilities. Receive and Transmit NID(s) have only OUTC and INC
 415          * capabilities and no presence detect capable (PDC) and call to
 416          * snd_hda_gen_build_controls() will mark them as non detectable
 417          * phantom jacks. However, a companion codec may be
 418          * connected to these pins which supports jack detect
 419          * capabilities. We have to override pin capabilities,
 420          * otherwise they will not be created as input devices.
 421          */
 422         caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
 423         if (caps >= 0)
 424                 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
 425                                        (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
 426
 427         snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
 428 }
 429
 430 /******************************************************************************
 431  *                        CS42L42 Specific Functions
 432  ******************************************************************************/
 433
 434 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
 435 {
 436         unsigned int ofs = get_amp_offset(kctrl);
 437         u8 chs = get_amp_channels(kctrl);
 438
 439         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 440         uinfo->value.integer.step = 1;
 441         uinfo->count = chs == 3 ? 2 : 1;
 442
 443         switch (ofs) {
 444         case CS42L42_VOL_DAC:
 445                 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
 446                 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
 447                 break;
 448         case CS42L42_VOL_ADC:
 449                 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
 450                 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
 451                 break;
 452         default:
 453                 break;
 454         }
 455
 456         return 0;
 457 }
 458
 459 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 460 {
 461         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 462         struct cs8409_spec *spec = codec->spec;
 463         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 464         int chs = get_amp_channels(kctrl);
 465         unsigned int ofs = get_amp_offset(kctrl);
 466         long *valp = uctrl->value.integer.value;
 467
 468         switch (ofs) {
 469         case CS42L42_VOL_DAC:
 470                 if (chs & BIT(0))
 471                         *valp++ = cs42l42->vol[ofs];
 472                 if (chs & BIT(1))
 473                         *valp = cs42l42->vol[ofs+1];
 474                 break;
 475         case CS42L42_VOL_ADC:
 476                 if (chs & BIT(0))
 477                         *valp = cs42l42->vol[ofs];
 478                 break;
 479         default:
 480                 break;
 481         }
 482
 483         return 0;
 484 }
 485
 486 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 487 {
 488         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 489         struct cs8409_spec *spec = codec->spec;
 490         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 491         int chs = get_amp_channels(kctrl);
 492         unsigned int ofs = get_amp_offset(kctrl);
 493         long *valp = uctrl->value.integer.value;
 494
 495         switch (ofs) {
 496         case CS42L42_VOL_DAC:
 497                 if (chs & BIT(0)) {
 498                         cs42l42->vol[ofs] = *valp;
 499                         cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA,
 500                                          -(cs42l42->vol[ofs]) & CS42L42_REG_HS_VOL_MASK);
 501                 }
 502                 if (chs & BIT(1)) {
 503                         ofs++;
 504                         valp++;
 505                         cs42l42->vol[ofs] = *valp;
 506                         cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB,
 507                                          -(cs42l42->vol[ofs]) & CS42L42_REG_HS_VOL_MASK);
 508                 }
 509                 break;
 510         case CS42L42_VOL_ADC:
 511                 if (chs & BIT(0)) {
 512                         cs42l42->vol[ofs] = *valp;
 513                         cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL,
 514                                          cs42l42->vol[ofs] & CS42L42_REG_AMIC_VOL_MASK);
 515                 }
 516                 break;
 517         default:
 518                 break;
 519         }
 520
 521         return 0;
 522 }
 523
 524 /* Configure CS42L42 slave codec for jack autodetect */
 525 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
 526 {
 527         cs8409_i2c_write(cs42l42, 0x1b70, cs42l42->hsbias_hiz);
 528         /* Clear WAKE# */
 529         cs8409_i2c_write(cs42l42, 0x1b71, 0x00C1);
 530         /* Wait ~2.5ms */
 531         usleep_range(2500, 3000);
 532         /* Set mode WAKE# output follows the combination logic directly */
 533         cs8409_i2c_write(cs42l42, 0x1b71, 0x00C0);
 534         /* Clear interrupts status */
 535         cs8409_i2c_read(cs42l42, 0x130f);
 536         /* Enable interrupt */
 537         cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
 538 }
 539
 540 /* Enable and run CS42L42 slave codec jack auto detect */
 541 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
 542 {
 543         /* Clear interrupts */
 544         cs8409_i2c_read(cs42l42, 0x1308);
 545         cs8409_i2c_read(cs42l42, 0x1b77);
 546         cs8409_i2c_write(cs42l42, 0x1320, 0xFF);
 547         cs8409_i2c_read(cs42l42, 0x130f);
 548
 549         cs8409_i2c_write(cs42l42, 0x1102, 0x87);
 550         cs8409_i2c_write(cs42l42, 0x1f06, 0x86);
 551         cs8409_i2c_write(cs42l42, 0x1b74, 0x07);
 552         cs8409_i2c_write(cs42l42, 0x131b, 0xFD);
 553         cs8409_i2c_write(cs42l42, 0x1120, 0x80);
 554         /* Wait ~110ms*/
 555         usleep_range(110000, 200000);
 556         cs8409_i2c_write(cs42l42, 0x111f, 0x77);
 557         cs8409_i2c_write(cs42l42, 0x1120, 0xc0);
 558         /* Wait ~10ms */
 559         usleep_range(10000, 25000);
 560 }
 561
 562 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
 563 {
 564         int status_changed = 0;
 565
 566         /* TIP_SENSE INSERT/REMOVE */
 567         switch (reg_ts_status) {
 568         case CS42L42_JACK_INSERTED:
 569                 if (!cs42l42->hp_jack_in) {
 570                         if (cs42l42->no_type_dect) {
 571                                 status_changed = 1;
 572                                 cs42l42->hp_jack_in = 1;
 573                                 cs42l42->mic_jack_in = 0;
 574                         } else {
 575                                 cs42l42_run_jack_detect(cs42l42);
 576                         }
 577                 }
 578                 break;
 579
 580         case CS42L42_JACK_REMOVED:
 581                 if (cs42l42->hp_jack_in || cs42l42->mic_jack_in) {
 582                         status_changed = 1;
 583                         cs42l42->hp_jack_in = 0;
 584                         cs42l42->mic_jack_in = 0;
 585                 }
 586                 break;
 587         default:
 588                 /* jack in transition */
 589                 break;
 590         }
 591
 592         return status_changed;
 593 }
 594
 595 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
 596 {
 597         int status_changed = 0;
 598         int reg_cdc_status;
 599         int reg_hs_status;
 600         int reg_ts_status;
 601         int type;
 602
 603         /* Read jack detect status registers */
 604         reg_cdc_status = cs8409_i2c_read(cs42l42, 0x1308);
 605         reg_hs_status = cs8409_i2c_read(cs42l42, 0x1124);
 606         reg_ts_status = cs8409_i2c_read(cs42l42, 0x130f);
 607
 608         /* If status values are < 0, read error has occurred. */
 609         if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
 610                 return -EIO;
 611
 612         /* HSDET_AUTO_DONE */
 613         if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE) {
 614
 615                 /* Disable HSDET_AUTO_DONE */
 616                 cs8409_i2c_write(cs42l42, 0x131b, 0xFF);
 617
 618                 type = ((reg_hs_status & CS42L42_HSTYPE_MASK) + 1);
 619
 620                 if (cs42l42->no_type_dect) {
 621                         status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
 622                 } else if (type == 4) {
 623                         /* Type 4 not supported */
 624                         status_changed = cs42l42_handle_tip_sense(cs42l42, CS42L42_JACK_REMOVED);
 625                 } else {
 626                         if (!cs42l42->hp_jack_in) {
 627                                 status_changed = 1;
 628                                 cs42l42->hp_jack_in = 1;
 629                         }
 630                         /* type = 3 has no mic */
 631                         if ((!cs42l42->mic_jack_in) && (type != 3)) {
 632                                 status_changed = 1;
 633                                 cs42l42->mic_jack_in = 1;
 634                         }
 635                 }
 636                 /* Re-Enable Tip Sense Interrupt */
 637                 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
 638         } else {
 639                 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
 640         }
 641
 642         return status_changed;
 643 }
 644
 645 static void cs42l42_resume(struct sub_codec *cs42l42)
 646 {
 647         struct hda_codec *codec = cs42l42->codec;
 648         unsigned int gpio_data;
 649         struct cs8409_i2c_param irq_regs[] = {
 650                 { 0x1308, 0x00 },
 651                 { 0x1309, 0x00 },
 652                 { 0x130A, 0x00 },
 653                 { 0x130F, 0x00 },
 654         };
 655
 656         /* Bring CS42L42 out of Reset */
 657         gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 658         gpio_data |= cs42l42->reset_gpio;
 659         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
 660         usleep_range(10000, 15000);
 661
 662         cs42l42->suspended = 0;
 663
 664         /* Initialize CS42L42 companion codec */
 665         cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
 666
 667         /* Clear interrupts, by reading interrupt status registers */
 668         cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
 669
 670         /* Restore Volumes after Resume */
 671         cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA,
 672                          -(cs42l42->vol[1]) & CS42L42_REG_HS_VOL_MASK);
 673         cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB,
 674                          -(cs42l42->vol[2]) & CS42L42_REG_HS_VOL_MASK);
 675         cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL,
 676                          cs42l42->vol[0] & CS42L42_REG_AMIC_VOL_MASK);
 677
 678         if (cs42l42->full_scale_vol)
 679                 cs8409_i2c_write(cs42l42, 0x2001, 0x01);
 680
 681         cs42l42_enable_jack_detect(cs42l42);
 682 }
 683
 684 #ifdef CONFIG_PM
 685 static void cs42l42_suspend(struct sub_codec *cs42l42)
 686 {
 687         struct hda_codec *codec = cs42l42->codec;
 688         unsigned int gpio_data;
 689
 690         /* Power down CS42L42 ASP/EQ/MIX/HP */
 691         cs8409_i2c_write(cs42l42, 0x1101, 0xfe);
 692         cs42l42->suspended = 1;
 693         cs42l42->last_page = 0;
 694
 695         /* Put CS42L42 into Reset */
 696         gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 697         gpio_data &= ~cs42l42->reset_gpio;
 698         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
 699 }
 700 #endif
 701
 702 static void cs8409_free(struct hda_codec *codec)
 703 {
 704         struct cs8409_spec *spec = codec->spec;
 705
 706         /* Cancel i2c clock disable timer, and disable clock if left enabled */
 707         cancel_delayed_work_sync(&spec->i2c_clk_work);
 708         cs8409_disable_i2c_clock(codec);
 709
 710         snd_hda_gen_free(codec);
 711 }
 712
 713 /******************************************************************************
 714  *                   BULLSEYE / WARLOCK / CYBORG Specific Functions
 715  *                               CS8409/CS42L42
 716  ******************************************************************************/
 717
 718 /*
 719  * In the case of CS8409 we do not have unsolicited events from NID's 0x24
 720  * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
 721  * generate interrupt via gpio 4 to notify jack events. We have to overwrite
 722  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
 723  * and then notify status via generic snd_hda_jack_unsol_event() call.
 724  */
 725 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
 726 {
 727         struct cs8409_spec *spec = codec->spec;
 728         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 729         struct hda_jack_tbl *jk;
 730
 731         /* jack_unsol_event() will be called every time gpio line changing state.
 732          * In this case gpio4 line goes up as a result of reading interrupt status
 733          * registers in previous cs8409_jack_unsol_event() call.
 734          * We don't need to handle this event, ignoring...
 735          */
 736         if (res & cs42l42->irq_mask)
 737                 return;
 738
 739         if (cs42l42_jack_unsol_event(cs42l42)) {
 740                 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
 741                                     cs42l42->hp_jack_in ? 0 : PIN_OUT);
 742                 /* Report jack*/
 743                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
 744                 if (jk)
 745                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 746                                                         AC_UNSOL_RES_TAG);
 747                 /* Report jack*/
 748                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
 749                 if (jk)
 750                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 751                                                          AC_UNSOL_RES_TAG);
 752         }
 753 }
 754
 755 #ifdef CONFIG_PM
 756 /* Manage PDREF, when transition to D3hot */
 757 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
 758 {
 759         struct cs8409_spec *spec = codec->spec;
 760         int i;
 761
 762         cs8409_enable_ur(codec, 0);
 763
 764         for (i = 0; i < spec->num_scodecs; i++)
 765                 cs42l42_suspend(spec->scodecs[i]);
 766
 767         /* Cancel i2c clock disable timer, and disable clock if left enabled */
 768         cancel_delayed_work_sync(&spec->i2c_clk_work);
 769         cs8409_disable_i2c_clock(codec);
 770
 771         snd_hda_shutup_pins(codec);
 772
 773         return 0;
 774 }
 775 #endif
 776
 777 /* Vendor specific HW configuration
 778  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
 779  */
 780 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
 781 {
 782         const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
 783         const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
 784         struct cs8409_spec *spec = codec->spec;
 785         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 786
 787         if (spec->gpio_mask) {
 788                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
 789                         spec->gpio_mask);
 790                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
 791                         spec->gpio_dir);
 792                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
 793                         spec->gpio_data);
 794         }
 795
 796         for (; seq->nid; seq++)
 797                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
 798
 799         if (codec->fixup_id == CS8409_BULLSEYE) {
 800                 for (; seq_bullseye->nid; seq_bullseye++)
 801                         cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
 802         }
 803
 804         /* DMIC1_MO=00b, DMIC1/2_SR=1 */
 805         if (codec->fixup_id == CS8409_WARLOCK || codec->fixup_id == CS8409_CYBORG)
 806                 cs8409_vendor_coef_set(codec, 0x09, 0x0003);
 807
 808         cs42l42_resume(cs42l42);
 809
 810         /* Enable Unsolicited Response */
 811         cs8409_enable_ur(codec, 1);
 812 }
 813
 814 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
 815         .build_controls = cs8409_build_controls,
 816         .build_pcms = snd_hda_gen_build_pcms,
 817         .init = cs8409_init,
 818         .free = cs8409_free,
 819         .unsol_event = cs8409_cs42l42_jack_unsol_event,
 820 #ifdef CONFIG_PM
 821         .suspend = cs8409_cs42l42_suspend,
 822 #endif
 823 };
 824
 825 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
 826                                     unsigned int *res)
 827 {
 828         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
 829         struct cs8409_spec *spec = codec->spec;
 830         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 831
 832         unsigned int nid = ((cmd >> 20) & 0x07f);
 833         unsigned int verb = ((cmd >> 8) & 0x0fff);
 834
 835         /* CS8409 pins have no AC_PINSENSE_PRESENCE
 836          * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
 837          * and return correct pin sense values for read_pin_sense() call from
 838          * hda_jack based on CS42L42 jack detect status.
 839          */
 840         switch (nid) {
 841         case CS8409_CS42L42_HP_PIN_NID:
 842                 if (verb == AC_VERB_GET_PIN_SENSE) {
 843                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
 844                         return 0;
 845                 }
 846                 break;
 847         case CS8409_CS42L42_AMIC_PIN_NID:
 848                 if (verb == AC_VERB_GET_PIN_SENSE) {
 849                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
 850                         return 0;
 851                 }
 852                 break;
 853         default:
 854                 break;
 855         }
 856
 857         return spec->exec_verb(dev, cmd, flags, res);
 858 }
 859
 860 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
 861 {
 862         struct cs8409_spec *spec = codec->spec;
 863
 864         switch (action) {
 865         case HDA_FIXUP_ACT_PRE_PROBE:
 866                 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
 867                 /* verb exec op override */
 868                 spec->exec_verb = codec->core.exec_verb;
 869                 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
 870
 871                 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
 872                 spec->num_scodecs = 1;
 873                 spec->scodecs[CS8409_CODEC0]->codec = codec;
 874                 codec->patch_ops = cs8409_cs42l42_patch_ops;
 875
 876                 spec->gen.suppress_auto_mute = 1;
 877                 spec->gen.no_primary_hp = 1;
 878                 spec->gen.suppress_vmaster = 1;
 879
 880                 /* GPIO 5 out, 3,4 in */
 881                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
 882                 spec->gpio_data = 0;
 883                 spec->gpio_mask = 0x03f;
 884
 885                 /* Basic initial sequence for specific hw configuration */
 886                 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
 887
 888                 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
 889                 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
 890
 891                 /* Set TIP_SENSE_EN for analog front-end of tip sense.
 892                  * Additionally set HSBIAS_SENSE_EN and Full Scale volume for some variants.
 893                  */
 894                 switch (codec->fixup_id) {
 895                 case CS8409_WARLOCK:
 896                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
 897                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
 898                         break;
 899                 case CS8409_BULLSEYE:
 900                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
 901                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 0;
 902                         break;
 903                 case CS8409_CYBORG:
 904                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x00a0;
 905                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
 906                         break;
 907                 default:
 908                         spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0003;
 909                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
 910                         break;
 911                 }
 912
 913                 break;
 914         case HDA_FIXUP_ACT_PROBE:
 915                 /* Set initial DMIC volume to -26 dB */
 916                 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
 917                                               HDA_INPUT, 0, 0xff, 0x19);
 918                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
 919                                 &cs42l42_dac_volume_mixer);
 920                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
 921                                 &cs42l42_adc_volume_mixer);
 922                 /* Disable Unsolicited Response during boot */
 923                 cs8409_enable_ur(codec, 0);
 924                 cs8409_cs42l42_hw_init(codec);
 925                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
 926                 break;
 927         case HDA_FIXUP_ACT_INIT:
 928                 cs8409_cs42l42_hw_init(codec);
 929                 fallthrough;
 930         case HDA_FIXUP_ACT_BUILD:
 931                 /* Run jack auto detect first time on boot
 932                  * after controls have been added, to check if jack has
 933                  * been already plugged in.
 934                  * Run immediately after init.
 935                  */
 936                 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
 937                 usleep_range(100000, 150000);
 938                 break;
 939         default:
 940                 break;
 941         }
 942 }
 943
 944 /******************************************************************************
 945  *                          Dolphin Specific Functions
 946  *                               CS8409/ 2 X CS42L42
 947  ******************************************************************************/
 948
 949 /*
 950  * In the case of CS8409 we do not have unsolicited events when
 951  * hs mic and hp are connected. Companion codec CS42L42 will
 952  * generate interrupt via irq_mask to notify jack events. We have to overwrite
 953  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
 954  * and then notify status via generic snd_hda_jack_unsol_event() call.
 955  */
 956 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
 957 {
 958         struct cs8409_spec *spec = codec->spec;
 959         struct sub_codec *cs42l42;
 960         struct hda_jack_tbl *jk;
 961
 962         cs42l42 = spec->scodecs[CS8409_CODEC0];
 963         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
 964             cs42l42_jack_unsol_event(cs42l42)) {
 965                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
 966                 if (jk)
 967                         snd_hda_jack_unsol_event(codec,
 968                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 969                                                   AC_UNSOL_RES_TAG);
 970
 971                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
 972                 if (jk)
 973                         snd_hda_jack_unsol_event(codec,
 974                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 975                                                   AC_UNSOL_RES_TAG);
 976         }
 977
 978         cs42l42 = spec->scodecs[CS8409_CODEC1];
 979         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
 980             cs42l42_jack_unsol_event(cs42l42)) {
 981                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
 982                 if (jk)
 983                         snd_hda_jack_unsol_event(codec,
 984                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 985                                                   AC_UNSOL_RES_TAG);
 986         }
 987 }
 988
 989 /* Vendor specific HW configuration
 990  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
 991  */
 992 static void dolphin_hw_init(struct hda_codec *codec)
 993 {
 994         const struct cs8409_cir_param *seq = dolphin_hw_cfg;
 995         struct cs8409_spec *spec = codec->spec;
 996         struct sub_codec *cs42l42;
 997         int i;
 998
 999         if (spec->gpio_mask) {
1000                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1001                                     spec->gpio_mask);
1002                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1003                                     spec->gpio_dir);
1004                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1005                                     spec->gpio_data);
1006         }
1007
1008         for (; seq->nid; seq++)
1009                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1010
1011         for (i = 0; i < spec->num_scodecs; i++) {
1012                 cs42l42 = spec->scodecs[i];
1013                 cs42l42_resume(cs42l42);
1014         }
1015
1016         /* Enable Unsolicited Response */
1017         cs8409_enable_ur(codec, 1);
1018 }
1019
1020 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1021         .build_controls = cs8409_build_controls,
1022         .build_pcms = snd_hda_gen_build_pcms,
1023         .init = cs8409_init,
1024         .free = cs8409_free,
1025         .unsol_event = dolphin_jack_unsol_event,
1026 #ifdef CONFIG_PM
1027         .suspend = cs8409_cs42l42_suspend,
1028 #endif
1029 };
1030
1031 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1032                              unsigned int *res)
1033 {
1034         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1035         struct cs8409_spec *spec = codec->spec;
1036         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1037
1038         unsigned int nid = ((cmd >> 20) & 0x07f);
1039         unsigned int verb = ((cmd >> 8) & 0x0fff);
1040
1041         /* CS8409 pins have no AC_PINSENSE_PRESENCE
1042          * capabilities. We have to intercept calls for CS42L42 pins
1043          * and return correct pin sense values for read_pin_sense() call from
1044          * hda_jack based on CS42L42 jack detect status.
1045          */
1046         switch (nid) {
1047         case DOLPHIN_HP_PIN_NID:
1048         case DOLPHIN_LO_PIN_NID:
1049                 if (nid == DOLPHIN_LO_PIN_NID)
1050                         cs42l42 = spec->scodecs[CS8409_CODEC1];
1051                 if (verb == AC_VERB_GET_PIN_SENSE) {
1052                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1053                         return 0;
1054                 }
1055                 break;
1056         case DOLPHIN_AMIC_PIN_NID:
1057                 if (verb == AC_VERB_GET_PIN_SENSE) {
1058                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1059                         return 0;
1060                 }
1061                 break;
1062         default:
1063                 break;
1064         }
1065
1066         return spec->exec_verb(dev, cmd, flags, res);
1067 }
1068
1069 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1070 {
1071         struct cs8409_spec *spec = codec->spec;
1072         struct snd_kcontrol_new *kctrl;
1073         int i;
1074
1075         switch (action) {
1076         case HDA_FIXUP_ACT_PRE_PROBE:
1077                 snd_hda_add_verbs(codec, dolphin_init_verbs);
1078                 /* verb exec op override */
1079                 spec->exec_verb = codec->core.exec_verb;
1080                 codec->core.exec_verb = dolphin_exec_verb;
1081
1082                 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1083                 spec->scodecs[CS8409_CODEC0]->codec = codec;
1084                 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1085                 spec->scodecs[CS8409_CODEC1]->codec = codec;
1086                 spec->num_scodecs = 2;
1087
1088                 codec->patch_ops = cs8409_dolphin_patch_ops;
1089
1090                 /* GPIO 1,5 out, 0,4 in */
1091                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1092                                  spec->scodecs[CS8409_CODEC1]->reset_gpio;
1093                 spec->gpio_data = 0;
1094                 spec->gpio_mask = 0x03f;
1095
1096                 /* Basic initial sequence for specific hw configuration */
1097                 snd_hda_sequence_write(codec, dolphin_init_verbs);
1098
1099                 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1100                                       SND_JACK_HEADPHONE, NULL);
1101
1102                 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1103                 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1104                 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1105
1106                 break;
1107         case HDA_FIXUP_ACT_PROBE:
1108                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1109                                      &cs42l42_dac_volume_mixer);
1110                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1111                 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1112                                              &cs42l42_dac_volume_mixer);
1113                 /* Update Line Out kcontrol template */
1114                 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1115                                        HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1116                 cs8409_enable_ur(codec, 0);
1117                 dolphin_hw_init(codec);
1118                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1119                 break;
1120         case HDA_FIXUP_ACT_INIT:
1121                 dolphin_hw_init(codec);
1122                 fallthrough;
1123         case HDA_FIXUP_ACT_BUILD:
1124                 /* Run jack auto detect first time on boot
1125                  * after controls have been added, to check if jack has
1126                  * been already plugged in.
1127                  * Run immediately after init.
1128                  */
1129                 for (i = 0; i < spec->num_scodecs; i++) {
1130                         cs42l42_run_jack_detect(spec->scodecs[i]);
1131                         usleep_range(100000, 150000);
1132                 }
1133
1134                 break;
1135         default:
1136                 break;
1137         }
1138 }
1139
1140 static int patch_cs8409(struct hda_codec *codec)
1141 {
1142         int err;
1143
1144         if (!cs8409_alloc_spec(codec))
1145                 return -ENOMEM;
1146
1147         snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1148
1149         codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1150                          codec->bus->pci->subsystem_vendor,
1151                          codec->bus->pci->subsystem_device);
1152
1153         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1154
1155         err = cs8409_parse_auto_config(codec);
1156         if (err < 0) {
1157                 cs8409_free(codec);
1158                 return err;
1159         }
1160
1161         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1162         return 0;
1163 }
1164
1165 static const struct hda_device_id snd_hda_id_cs8409[] = {
1166         HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1167         {} /* terminator */
1168 };
1169 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1170
1171 static struct hda_codec_driver cs8409_driver = {
1172         .id = snd_hda_id_cs8409,
1173 };
1174 module_hda_codec_driver(cs8409_driver);
1175
1176 MODULE_LICENSE("GPL");
1177 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");