1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * hda_intel.c - Implementation of primary alsa driver code base
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
61 /* position fix mode */
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
128 static bool dmic_detect = 1;
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
174 #define param_check_xint param_check_int
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
194 #endif /* CONFIG_PM */
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
206 #define hda_snoop true
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
245 MODULE_DESCRIPTION("Intel HDA driver");
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
266 AZX_DRIVER_ATIHDMI_NS,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_BASE \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_SNOOP_TYPE(SCH))
293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
294 #define AZX_DCAPS_INTEL_PCH_NOPM \
295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
297 /* PCH for HSW/BDW; with runtime PM */
298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
299 #define AZX_DCAPS_INTEL_PCH \
300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
301 AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
304 #define AZX_DCAPS_INTEL_HASWELL \
305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
307 AZX_DCAPS_SNOOP_TYPE(SCH))
309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310 #define AZX_DCAPS_INTEL_BROADWELL \
311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313 AZX_DCAPS_SNOOP_TYPE(SCH))
315 #define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
318 #define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
320 AZX_DCAPS_I915_COMPONENT)
322 #define AZX_DCAPS_INTEL_SKYLAKE \
323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
324 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
326 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
328 /* quirks for ATI SB / AMD Hudson */
329 #define AZX_DCAPS_PRESET_ATI_SB \
330 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
331 AZX_DCAPS_SNOOP_TYPE(ATI))
333 /* quirks for ATI/AMD HDMI */
334 #define AZX_DCAPS_PRESET_ATI_HDMI \
335 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
338 /* quirks for ATI HDMI with snoop off */
339 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
340 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342 /* quirks for AMD SB */
343 #define AZX_DCAPS_PRESET_AMD_SB \
344 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
345 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
347 /* quirks for Nvidia */
348 #define AZX_DCAPS_PRESET_NVIDIA \
349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
350 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
352 #define AZX_DCAPS_PRESET_CTHDA \
353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
354 AZX_DCAPS_NO_64BIT |\
355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
358 * vga_switcheroo support
360 #ifdef SUPPORT_VGA_SWITCHEROO
361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
364 #define use_vga_switcheroo(chip) 0
365 #define needs_eld_notify_link(chip) false
368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c) || \
372 ((pci)->device == 0x490d))
374 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
376 static const char * const driver_short_names[] = {
377 [AZX_DRIVER_ICH] = "HDA Intel",
378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
379 [AZX_DRIVER_SCH] = "HDA Intel MID",
380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
382 [AZX_DRIVER_ATI] = "HDA ATI SB",
383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
389 [AZX_DRIVER_TERA] = "HDA Teradici",
390 [AZX_DRIVER_CTX] = "HDA Creative",
391 [AZX_DRIVER_CTHDA] = "HDA Creative",
392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
393 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
397 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
398 static void set_default_power_save(struct azx *chip);
401 * initialize the PCI registers
403 /* update bits in a PCI register byte */
404 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
405 unsigned char mask, unsigned char val)
409 pci_read_config_byte(pci, reg, &data);
411 data |= (val & mask);
412 pci_write_config_byte(pci, reg, data);
415 static void azx_init_pci(struct azx *chip)
417 int snoop_type = azx_get_snoop_type(chip);
419 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
420 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
421 * Ensuring these bits are 0 clears playback static on some HD Audio
423 * The PCI register TCSEL is defined in the Intel manuals.
425 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
426 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
427 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
430 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
431 * we need to enable snoop.
433 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
434 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
436 update_pci_byte(chip->pci,
437 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
438 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
441 /* For NVIDIA HDA, enable snoop */
442 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
443 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
445 update_pci_byte(chip->pci,
446 NVIDIA_HDA_TRANSREG_ADDR,
447 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
448 update_pci_byte(chip->pci,
449 NVIDIA_HDA_ISTRM_COH,
450 0x01, NVIDIA_HDA_ENABLE_COHBIT);
451 update_pci_byte(chip->pci,
452 NVIDIA_HDA_OSTRM_COH,
453 0x01, NVIDIA_HDA_ENABLE_COHBIT);
456 /* Enable SCH/PCH snoop if needed */
457 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
458 unsigned short snoop;
459 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
460 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
461 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
462 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
463 if (!azx_snoop(chip))
464 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
465 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
466 pci_read_config_word(chip->pci,
467 INTEL_SCH_HDA_DEVC, &snoop);
469 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
470 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
471 "Disabled" : "Enabled");
476 * In BXT-P A0, HD-Audio DMA requests is later than expected,
477 * and makes an audio stream sensitive to system latencies when
478 * 24/32 bits are playing.
479 * Adjusting threshold of DMA fifo to force the DMA request
480 * sooner to improve latency tolerance at the expense of power.
482 static void bxt_reduce_dma_latency(struct azx *chip)
486 val = azx_readl(chip, VS_EM4L);
488 azx_writel(chip, VS_EM4L, val);
493 * bit 0: 6 MHz Supported
494 * bit 1: 12 MHz Supported
495 * bit 2: 24 MHz Supported
496 * bit 3: 48 MHz Supported
497 * bit 4: 96 MHz Supported
498 * bit 5: 192 MHz Supported
500 static int intel_get_lctl_scf(struct azx *chip)
502 struct hdac_bus *bus = azx_bus(chip);
503 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
507 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
509 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
510 t = preferred_bits[i];
515 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
519 static int intel_ml_lctl_set_power(struct azx *chip, int state)
521 struct hdac_bus *bus = azx_bus(chip);
526 * the codecs are sharing the first link setting by default
527 * If other links are enabled for stream, they need similar fix
529 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
530 val &= ~AZX_MLCTL_SPA;
531 val |= state << AZX_MLCTL_SPA_SHIFT;
532 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
536 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
537 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
546 static void intel_init_lctl(struct azx *chip)
548 struct hdac_bus *bus = azx_bus(chip);
552 /* 0. check lctl register value is correct or not */
553 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
554 /* if SCF is already set, let's use it */
555 if ((val & ML_LCTL_SCF_MASK) != 0)
559 * Before operating on SPA, CPA must match SPA.
560 * Any deviation may result in undefined behavior.
562 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
563 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
566 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
567 ret = intel_ml_lctl_set_power(chip, 0);
572 /* 2. update SCF to select a properly audio clock*/
573 val &= ~ML_LCTL_SCF_MASK;
574 val |= intel_get_lctl_scf(chip);
575 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
578 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
579 intel_ml_lctl_set_power(chip, 1);
583 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
585 struct hdac_bus *bus = azx_bus(chip);
586 struct pci_dev *pci = chip->pci;
589 snd_hdac_set_codec_wakeup(bus, true);
590 if (chip->driver_type == AZX_DRIVER_SKL) {
591 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
592 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
593 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
595 azx_init_chip(chip, full_reset);
596 if (chip->driver_type == AZX_DRIVER_SKL) {
597 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
598 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
599 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
602 snd_hdac_set_codec_wakeup(bus, false);
604 /* reduce dma latency to avoid noise */
606 bxt_reduce_dma_latency(chip);
608 if (bus->mlcap != NULL)
609 intel_init_lctl(chip);
612 /* calculate runtime delay from LPIB */
613 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
616 struct snd_pcm_substream *substream = azx_dev->core.substream;
617 int stream = substream->stream;
618 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
621 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
622 delay = pos - lpib_pos;
624 delay = lpib_pos - pos;
626 if (delay >= azx_dev->core.delay_negative_threshold)
629 delay += azx_dev->core.bufsize;
632 if (delay >= azx_dev->core.period_bytes) {
633 dev_info(chip->card->dev,
634 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
635 delay, azx_dev->core.period_bytes);
637 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
638 chip->get_delay[stream] = NULL;
641 return bytes_to_frames(substream->runtime, delay);
644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
646 /* called from IRQ */
647 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
649 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
652 ok = azx_position_ok(chip, azx_dev);
654 azx_dev->irq_pending = 0;
656 } else if (ok == 0) {
657 /* bogus IRQ, process it later */
658 azx_dev->irq_pending = 1;
659 schedule_work(&hda->irq_pending_work);
664 #define display_power(chip, enable) \
665 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
668 * Check whether the current DMA position is acceptable for updating
669 * periods. Returns non-zero if it's OK.
671 * Many HD-audio controllers appear pretty inaccurate about
672 * the update-IRQ timing. The IRQ is issued before actually the
673 * data is processed. So, we need to process it afterwords in a
676 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
678 struct snd_pcm_substream *substream = azx_dev->core.substream;
679 int stream = substream->stream;
683 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
684 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
685 return -1; /* bogus (too early) interrupt */
687 if (chip->get_position[stream])
688 pos = chip->get_position[stream](chip, azx_dev);
689 else { /* use the position buffer as default */
690 pos = azx_get_pos_posbuf(chip, azx_dev);
691 if (!pos || pos == (u32)-1) {
692 dev_info(chip->card->dev,
693 "Invalid position buffer, using LPIB read method instead.\n");
694 chip->get_position[stream] = azx_get_pos_lpib;
695 if (chip->get_position[0] == azx_get_pos_lpib &&
696 chip->get_position[1] == azx_get_pos_lpib)
697 azx_bus(chip)->use_posbuf = false;
698 pos = azx_get_pos_lpib(chip, azx_dev);
699 chip->get_delay[stream] = NULL;
701 chip->get_position[stream] = azx_get_pos_posbuf;
702 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
703 chip->get_delay[stream] = azx_get_delay_from_lpib;
707 if (pos >= azx_dev->core.bufsize)
710 if (WARN_ONCE(!azx_dev->core.period_bytes,
711 "hda-intel: zero azx_dev->period_bytes"))
712 return -1; /* this shouldn't happen! */
713 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
714 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
715 /* NG - it's below the first next period boundary */
716 return chip->bdl_pos_adj ? 0 : -1;
717 azx_dev->core.start_wallclk += wallclk;
718 return 1; /* OK, it's fine */
722 * The work for pending PCM period updates.
724 static void azx_irq_pending_work(struct work_struct *work)
726 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
727 struct azx *chip = &hda->chip;
728 struct hdac_bus *bus = azx_bus(chip);
729 struct hdac_stream *s;
732 if (!hda->irq_pending_warned) {
733 dev_info(chip->card->dev,
734 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
736 hda->irq_pending_warned = 1;
741 spin_lock_irq(&bus->reg_lock);
742 list_for_each_entry(s, &bus->stream_list, list) {
743 struct azx_dev *azx_dev = stream_to_azx_dev(s);
744 if (!azx_dev->irq_pending ||
748 ok = azx_position_ok(chip, azx_dev);
750 azx_dev->irq_pending = 0;
751 spin_unlock(&bus->reg_lock);
752 snd_pcm_period_elapsed(s->substream);
753 spin_lock(&bus->reg_lock);
755 pending = 0; /* too early */
759 spin_unlock_irq(&bus->reg_lock);
766 /* clear irq_pending flags and assure no on-going workq */
767 static void azx_clear_irq_pending(struct azx *chip)
769 struct hdac_bus *bus = azx_bus(chip);
770 struct hdac_stream *s;
772 spin_lock_irq(&bus->reg_lock);
773 list_for_each_entry(s, &bus->stream_list, list) {
774 struct azx_dev *azx_dev = stream_to_azx_dev(s);
775 azx_dev->irq_pending = 0;
777 spin_unlock_irq(&bus->reg_lock);
780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
782 struct hdac_bus *bus = azx_bus(chip);
784 if (request_irq(chip->pci->irq, azx_interrupt,
785 chip->msi ? 0 : IRQF_SHARED,
786 chip->card->irq_descr, chip)) {
787 dev_err(chip->card->dev,
788 "unable to grab IRQ %d, disabling device\n",
791 snd_card_disconnect(chip->card);
794 bus->irq = chip->pci->irq;
795 chip->card->sync_irq = bus->irq;
796 pci_intx(chip->pci, !chip->msi);
800 /* get the current DMA position with correction on VIA chips */
801 static unsigned int azx_via_get_position(struct azx *chip,
802 struct azx_dev *azx_dev)
804 unsigned int link_pos, mini_pos, bound_pos;
805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
806 unsigned int fifo_size;
808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
810 /* Playback, no problem using link position */
816 * use mod to get the DMA position just like old chipset
818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
819 mod_dma_pos %= azx_dev->core.period_bytes;
821 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
823 if (azx_dev->insufficient) {
824 /* Link position never gather than FIFO size */
825 if (link_pos <= fifo_size)
828 azx_dev->insufficient = 0;
831 if (link_pos <= fifo_size)
832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
834 mini_pos = link_pos - fifo_size;
836 /* Find nearest previous boudary */
837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
838 mod_link_pos = link_pos % azx_dev->core.period_bytes;
839 if (mod_link_pos >= fifo_size)
840 bound_pos = link_pos - mod_link_pos;
841 else if (mod_dma_pos >= mod_mini_pos)
842 bound_pos = mini_pos - mod_mini_pos;
844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
845 if (bound_pos >= azx_dev->core.bufsize)
849 /* Calculate real DMA position we want */
850 return bound_pos + mod_dma_pos;
853 #define AMD_FIFO_SIZE 32
855 /* get the current DMA position with FIFO size correction */
856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
858 struct snd_pcm_substream *substream = azx_dev->core.substream;
859 struct snd_pcm_runtime *runtime = substream->runtime;
860 unsigned int pos, delay;
862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
866 runtime->delay = AMD_FIFO_SIZE;
867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
868 if (azx_dev->insufficient) {
871 runtime->delay = bytes_to_frames(runtime, pos);
873 azx_dev->insufficient = 0;
877 /* correct the DMA position for capture stream */
878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
880 pos += azx_dev->core.bufsize;
887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
890 struct snd_pcm_substream *substream = azx_dev->core.substream;
892 /* just read back the calculated value in the above */
893 return substream->runtime->delay;
896 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
897 struct azx_dev *azx_dev)
899 return _snd_hdac_chip_readl(azx_bus(chip),
900 AZX_REG_VS_SDXDPIB_XBASE +
901 (AZX_REG_VS_SDXDPIB_XINTERVAL *
902 azx_dev->core.index));
905 /* get the current DMA position with correction on SKL+ chips */
906 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
908 /* DPIB register gives a more accurate position for playback */
909 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
910 return azx_skl_get_dpib_pos(chip, azx_dev);
912 /* For capture, we need to read posbuf, but it requires a delay
913 * for the possible boundary overlap; the read of DPIB fetches the
917 azx_skl_get_dpib_pos(chip, azx_dev);
918 return azx_get_pos_posbuf(chip, azx_dev);
922 static DEFINE_MUTEX(card_list_lock);
923 static LIST_HEAD(card_list);
925 static void azx_add_card_list(struct azx *chip)
927 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
928 mutex_lock(&card_list_lock);
929 list_add(&hda->list, &card_list);
930 mutex_unlock(&card_list_lock);
933 static void azx_del_card_list(struct azx *chip)
935 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
936 mutex_lock(&card_list_lock);
937 list_del_init(&hda->list);
938 mutex_unlock(&card_list_lock);
941 /* trigger power-save check at writing parameter */
942 static int param_set_xint(const char *val, const struct kernel_param *kp)
944 struct hda_intel *hda;
946 int prev = power_save;
947 int ret = param_set_int(val, kp);
949 if (ret || prev == power_save)
952 mutex_lock(&card_list_lock);
953 list_for_each_entry(hda, &card_list, list) {
955 if (!hda->probe_continued || chip->disabled)
957 snd_hda_set_power_save(&chip->bus, power_save * 1000);
959 mutex_unlock(&card_list_lock);
966 static bool azx_is_pm_ready(struct snd_card *card)
969 struct hda_intel *hda;
973 chip = card->private_data;
974 hda = container_of(chip, struct hda_intel, chip);
975 if (chip->disabled || hda->init_failed || !chip->running)
980 static void __azx_runtime_suspend(struct azx *chip)
983 azx_enter_link_reset(chip);
984 azx_clear_irq_pending(chip);
985 display_power(chip, false);
988 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
990 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
991 struct hdac_bus *bus = azx_bus(chip);
992 struct hda_codec *codec;
995 display_power(chip, true);
996 if (hda->need_i915_power)
997 snd_hdac_i915_set_bclk(bus);
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1003 hda_intel_init_chip(chip, true);
1006 list_for_each_codec(codec, &chip->bus) {
1007 if (codec->relaxed_resume)
1010 if (codec->forced_resume || (status & (1 << codec->addr)))
1011 pm_request_resume(hda_codec_dev(codec));
1015 /* power down again for link-controlled chips */
1016 if (!hda->need_i915_power)
1017 display_power(chip, false);
1020 #ifdef CONFIG_PM_SLEEP
1021 static int azx_suspend(struct device *dev)
1023 struct snd_card *card = dev_get_drvdata(dev);
1025 struct hdac_bus *bus;
1027 if (!azx_is_pm_ready(card))
1030 chip = card->private_data;
1031 bus = azx_bus(chip);
1032 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1033 /* An ugly workaround: direct call of __azx_runtime_suspend() and
1034 * __azx_runtime_resume() for old Intel platforms that suffer from
1035 * spurious wakeups after S3 suspend
1037 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
1038 __azx_runtime_suspend(chip);
1040 pm_runtime_force_suspend(dev);
1041 if (bus->irq >= 0) {
1042 free_irq(bus->irq, chip);
1044 chip->card->sync_irq = -1;
1048 pci_disable_msi(chip->pci);
1050 trace_azx_suspend(chip);
1054 static int azx_resume(struct device *dev)
1056 struct snd_card *card = dev_get_drvdata(dev);
1059 if (!azx_is_pm_ready(card))
1062 chip = card->private_data;
1064 if (pci_enable_msi(chip->pci) < 0)
1066 if (azx_acquire_irq(chip, 1) < 0)
1069 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
1070 __azx_runtime_resume(chip, false);
1072 pm_runtime_force_resume(dev);
1073 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1075 trace_azx_resume(chip);
1079 /* put codec down to D3 at hibernation for Intel SKL+;
1080 * otherwise BIOS may still access the codec and screw up the driver
1082 static int azx_freeze_noirq(struct device *dev)
1084 struct snd_card *card = dev_get_drvdata(dev);
1085 struct azx *chip = card->private_data;
1086 struct pci_dev *pci = to_pci_dev(dev);
1088 if (!azx_is_pm_ready(card))
1090 if (chip->driver_type == AZX_DRIVER_SKL)
1091 pci_set_power_state(pci, PCI_D3hot);
1096 static int azx_thaw_noirq(struct device *dev)
1098 struct snd_card *card = dev_get_drvdata(dev);
1099 struct azx *chip = card->private_data;
1100 struct pci_dev *pci = to_pci_dev(dev);
1102 if (!azx_is_pm_ready(card))
1104 if (chip->driver_type == AZX_DRIVER_SKL)
1105 pci_set_power_state(pci, PCI_D0);
1109 #endif /* CONFIG_PM_SLEEP */
1111 static int azx_runtime_suspend(struct device *dev)
1113 struct snd_card *card = dev_get_drvdata(dev);
1116 if (!azx_is_pm_ready(card))
1118 chip = card->private_data;
1120 /* enable controller wake up event */
1121 if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) {
1122 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1126 __azx_runtime_suspend(chip);
1127 trace_azx_runtime_suspend(chip);
1131 static int azx_runtime_resume(struct device *dev)
1133 struct snd_card *card = dev_get_drvdata(dev);
1135 bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0;
1137 if (!azx_is_pm_ready(card))
1139 chip = card->private_data;
1140 __azx_runtime_resume(chip, from_rt);
1142 /* disable controller Wake Up event*/
1144 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1145 ~STATESTS_INT_MASK);
1148 trace_azx_runtime_resume(chip);
1152 static int azx_runtime_idle(struct device *dev)
1154 struct snd_card *card = dev_get_drvdata(dev);
1156 struct hda_intel *hda;
1161 chip = card->private_data;
1162 hda = container_of(chip, struct hda_intel, chip);
1163 if (chip->disabled || hda->init_failed)
1166 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1167 azx_bus(chip)->codec_powered || !chip->running)
1170 /* ELD notification gets broken when HD-audio bus is off */
1171 if (needs_eld_notify_link(chip))
1177 static const struct dev_pm_ops azx_pm = {
1178 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1179 #ifdef CONFIG_PM_SLEEP
1180 .freeze_noirq = azx_freeze_noirq,
1181 .thaw_noirq = azx_thaw_noirq,
1183 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1186 #define AZX_PM_OPS &azx_pm
1188 #define azx_add_card_list(chip) /* NOP */
1189 #define azx_del_card_list(chip) /* NOP */
1190 #define AZX_PM_OPS NULL
1191 #endif /* CONFIG_PM */
1194 static int azx_probe_continue(struct azx *chip);
1196 #ifdef SUPPORT_VGA_SWITCHEROO
1197 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1199 static void azx_vs_set_state(struct pci_dev *pci,
1200 enum vga_switcheroo_state state)
1202 struct snd_card *card = pci_get_drvdata(pci);
1203 struct azx *chip = card->private_data;
1204 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1205 struct hda_codec *codec;
1208 wait_for_completion(&hda->probe_wait);
1209 if (hda->init_failed)
1212 disabled = (state == VGA_SWITCHEROO_OFF);
1213 if (chip->disabled == disabled)
1216 if (!hda->probe_continued) {
1217 chip->disabled = disabled;
1219 dev_info(chip->card->dev,
1220 "Start delayed initialization\n");
1221 if (azx_probe_continue(chip) < 0)
1222 dev_err(chip->card->dev, "initialization error\n");
1225 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1226 disabled ? "Disabling" : "Enabling");
1228 list_for_each_codec(codec, &chip->bus) {
1229 pm_runtime_suspend(hda_codec_dev(codec));
1230 pm_runtime_disable(hda_codec_dev(codec));
1232 pm_runtime_suspend(card->dev);
1233 pm_runtime_disable(card->dev);
1234 /* when we get suspended by vga_switcheroo we end up in D3cold,
1235 * however we have no ACPI handle, so pci/acpi can't put us there,
1236 * put ourselves there */
1237 pci->current_state = PCI_D3cold;
1238 chip->disabled = true;
1239 if (snd_hda_lock_devices(&chip->bus))
1240 dev_warn(chip->card->dev,
1241 "Cannot lock devices!\n");
1243 snd_hda_unlock_devices(&chip->bus);
1244 chip->disabled = false;
1245 pm_runtime_enable(card->dev);
1246 list_for_each_codec(codec, &chip->bus) {
1247 pm_runtime_enable(hda_codec_dev(codec));
1248 pm_runtime_resume(hda_codec_dev(codec));
1254 static bool azx_vs_can_switch(struct pci_dev *pci)
1256 struct snd_card *card = pci_get_drvdata(pci);
1257 struct azx *chip = card->private_data;
1258 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260 wait_for_completion(&hda->probe_wait);
1261 if (hda->init_failed)
1263 if (chip->disabled || !hda->probe_continued)
1265 if (snd_hda_lock_devices(&chip->bus))
1267 snd_hda_unlock_devices(&chip->bus);
1272 * The discrete GPU cannot power down unless the HDA controller runtime
1273 * suspends, so activate runtime PM on codecs even if power_save == 0.
1275 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1278 struct hda_codec *codec;
1280 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1281 list_for_each_codec(codec, &chip->bus)
1282 codec->auto_runtime_pm = 1;
1283 /* reset the power save setup */
1285 set_default_power_save(chip);
1289 static void azx_vs_gpu_bound(struct pci_dev *pci,
1290 enum vga_switcheroo_client_id client_id)
1292 struct snd_card *card = pci_get_drvdata(pci);
1293 struct azx *chip = card->private_data;
1295 if (client_id == VGA_SWITCHEROO_DIS)
1296 chip->bus.keep_power = 0;
1297 setup_vga_switcheroo_runtime_pm(chip);
1300 static void init_vga_switcheroo(struct azx *chip)
1302 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1303 struct pci_dev *p = get_bound_vga(chip->pci);
1304 struct pci_dev *parent;
1306 dev_info(chip->card->dev,
1307 "Handle vga_switcheroo audio client\n");
1308 hda->use_vga_switcheroo = 1;
1310 /* cleared in either gpu_bound op or codec probe, or when its
1311 * upstream port has _PR3 (i.e. dGPU).
1313 parent = pci_upstream_bridge(p);
1314 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1315 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1320 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1321 .set_gpu_state = azx_vs_set_state,
1322 .can_switch = azx_vs_can_switch,
1323 .gpu_bound = azx_vs_gpu_bound,
1326 static int register_vga_switcheroo(struct azx *chip)
1328 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1332 if (!hda->use_vga_switcheroo)
1335 p = get_bound_vga(chip->pci);
1336 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1341 hda->vga_switcheroo_registered = 1;
1346 #define init_vga_switcheroo(chip) /* NOP */
1347 #define register_vga_switcheroo(chip) 0
1348 #define check_hdmi_disabled(pci) false
1349 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1350 #endif /* SUPPORT_VGA_SWITCHER */
1355 static void azx_free(struct azx *chip)
1357 struct pci_dev *pci = chip->pci;
1358 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1359 struct hdac_bus *bus = azx_bus(chip);
1364 if (azx_has_pm_runtime(chip) && chip->running)
1365 pm_runtime_get_noresume(&pci->dev);
1368 azx_del_card_list(chip);
1370 hda->init_failed = 1; /* to be sure */
1371 complete_all(&hda->probe_wait);
1373 if (use_vga_switcheroo(hda)) {
1374 if (chip->disabled && hda->probe_continued)
1375 snd_hda_unlock_devices(&chip->bus);
1376 if (hda->vga_switcheroo_registered)
1377 vga_switcheroo_unregister_client(chip->pci);
1380 if (bus->chip_init) {
1381 azx_clear_irq_pending(chip);
1382 azx_stop_all_streams(chip);
1383 azx_stop_chip(chip);
1387 free_irq(bus->irq, (void*)chip);
1389 pci_disable_msi(chip->pci);
1390 iounmap(bus->remap_addr);
1392 azx_free_stream_pages(chip);
1393 azx_free_streams(chip);
1394 snd_hdac_bus_exit(bus);
1396 if (chip->region_requested)
1397 pci_release_regions(chip->pci);
1399 pci_disable_device(chip->pci);
1400 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1401 release_firmware(chip->fw);
1403 display_power(chip, false);
1405 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1406 snd_hdac_i915_exit(bus);
1411 static int azx_dev_disconnect(struct snd_device *device)
1413 struct azx *chip = device->device_data;
1414 struct hdac_bus *bus = azx_bus(chip);
1416 chip->bus.shutdown = 1;
1417 cancel_work_sync(&bus->unsol_work);
1422 static int azx_dev_free(struct snd_device *device)
1424 azx_free(device->device_data);
1428 #ifdef SUPPORT_VGA_SWITCHEROO
1430 /* ATPX is in the integrated GPU's namespace */
1431 static bool atpx_present(void)
1433 struct pci_dev *pdev = NULL;
1434 acpi_handle dhandle, atpx_handle;
1437 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1438 dhandle = ACPI_HANDLE(&pdev->dev);
1440 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1441 if (!ACPI_FAILURE(status)) {
1447 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1448 dhandle = ACPI_HANDLE(&pdev->dev);
1450 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1451 if (!ACPI_FAILURE(status)) {
1460 static bool atpx_present(void)
1467 * Check of disabled HDMI controller by vga_switcheroo
1469 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1473 /* check only discrete GPU */
1474 switch (pci->vendor) {
1475 case PCI_VENDOR_ID_ATI:
1476 case PCI_VENDOR_ID_AMD:
1477 if (pci->devfn == 1) {
1478 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1479 pci->bus->number, 0);
1481 /* ATPX is in the integrated GPU's ACPI namespace
1482 * rather than the dGPU's namespace. However,
1483 * the dGPU is the one who is involved in
1486 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1493 case PCI_VENDOR_ID_NVIDIA:
1494 if (pci->devfn == 1) {
1495 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1496 pci->bus->number, 0);
1498 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1508 static bool check_hdmi_disabled(struct pci_dev *pci)
1510 bool vga_inactive = false;
1511 struct pci_dev *p = get_bound_vga(pci);
1514 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1515 vga_inactive = true;
1518 return vga_inactive;
1520 #endif /* SUPPORT_VGA_SWITCHEROO */
1523 * allow/deny-listing for position_fix
1525 static const struct snd_pci_quirk position_fix_list[] = {
1526 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1527 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1528 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1529 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1530 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1531 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1532 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1533 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1534 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1535 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1536 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1537 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1538 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1539 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1543 static int check_position_fix(struct azx *chip, int fix)
1545 const struct snd_pci_quirk *q;
1550 case POS_FIX_POSBUF:
1551 case POS_FIX_VIACOMBO:
1558 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1560 dev_info(chip->card->dev,
1561 "position_fix set to %d for device %04x:%04x\n",
1562 q->value, q->subvendor, q->subdevice);
1566 /* Check VIA/ATI HD Audio Controller exist */
1567 if (chip->driver_type == AZX_DRIVER_VIA) {
1568 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1569 return POS_FIX_VIACOMBO;
1571 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1572 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1573 return POS_FIX_FIFO;
1575 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1576 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1577 return POS_FIX_LPIB;
1579 if (chip->driver_type == AZX_DRIVER_SKL) {
1580 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1583 return POS_FIX_AUTO;
1586 static void assign_position_fix(struct azx *chip, int fix)
1588 static const azx_get_pos_callback_t callbacks[] = {
1589 [POS_FIX_AUTO] = NULL,
1590 [POS_FIX_LPIB] = azx_get_pos_lpib,
1591 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1592 [POS_FIX_VIACOMBO] = azx_via_get_position,
1593 [POS_FIX_COMBO] = azx_get_pos_lpib,
1594 [POS_FIX_SKL] = azx_get_pos_skl,
1595 [POS_FIX_FIFO] = azx_get_pos_fifo,
1598 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1600 /* combo mode uses LPIB only for playback */
1601 if (fix == POS_FIX_COMBO)
1602 chip->get_position[1] = NULL;
1604 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1605 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1606 chip->get_delay[0] = chip->get_delay[1] =
1607 azx_get_delay_from_lpib;
1610 if (fix == POS_FIX_FIFO)
1611 chip->get_delay[0] = chip->get_delay[1] =
1612 azx_get_delay_from_fifo;
1616 * deny-lists for probe_mask
1618 static const struct snd_pci_quirk probe_mask_list[] = {
1619 /* Thinkpad often breaks the controller communication when accessing
1620 * to the non-working (or non-existing) modem codec slot.
1622 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1623 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1624 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1626 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1627 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1628 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1629 /* forced codec slots */
1630 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1631 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1632 /* WinFast VP200 H (Teradici) user reported broken communication */
1633 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1637 #define AZX_FORCE_CODEC_MASK 0x100
1639 static void check_probe_mask(struct azx *chip, int dev)
1641 const struct snd_pci_quirk *q;
1643 chip->codec_probe_mask = probe_mask[dev];
1644 if (chip->codec_probe_mask == -1) {
1645 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1647 dev_info(chip->card->dev,
1648 "probe_mask set to 0x%x for device %04x:%04x\n",
1649 q->value, q->subvendor, q->subdevice);
1650 chip->codec_probe_mask = q->value;
1654 /* check forced option */
1655 if (chip->codec_probe_mask != -1 &&
1656 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1657 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1658 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1659 (int)azx_bus(chip)->codec_mask);
1664 * allow/deny-list for enable_msi
1666 static const struct snd_pci_quirk msi_deny_list[] = {
1667 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1668 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1669 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1670 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1671 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1672 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1673 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1674 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1675 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1676 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1680 static void check_msi(struct azx *chip)
1682 const struct snd_pci_quirk *q;
1684 if (enable_msi >= 0) {
1685 chip->msi = !!enable_msi;
1688 chip->msi = 1; /* enable MSI as default */
1689 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1691 dev_info(chip->card->dev,
1692 "msi for device %04x:%04x set to %d\n",
1693 q->subvendor, q->subdevice, q->value);
1694 chip->msi = q->value;
1698 /* NVidia chipsets seem to cause troubles with MSI */
1699 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1700 dev_info(chip->card->dev, "Disabling MSI\n");
1705 /* check the snoop mode availability */
1706 static void azx_check_snoop_available(struct azx *chip)
1708 int snoop = hda_snoop;
1711 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1712 snoop ? "snoop" : "non-snoop");
1713 chip->snoop = snoop;
1714 chip->uc_buffer = !snoop;
1719 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1720 chip->driver_type == AZX_DRIVER_VIA) {
1721 /* force to non-snoop mode for a new VIA controller
1725 pci_read_config_byte(chip->pci, 0x42, &val);
1726 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1727 chip->pci->revision == 0x20))
1731 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1734 chip->snoop = snoop;
1736 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1737 /* C-Media requires non-cached pages only for CORB/RIRB */
1738 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1739 chip->uc_buffer = true;
1743 static void azx_probe_work(struct work_struct *work)
1745 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1746 azx_probe_continue(&hda->chip);
1749 static int default_bdl_pos_adj(struct azx *chip)
1751 /* some exceptions: Atoms seem problematic with value 1 */
1752 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1753 switch (chip->pci->device) {
1754 case 0x0f04: /* Baytrail */
1755 case 0x2284: /* Braswell */
1760 switch (chip->driver_type) {
1761 case AZX_DRIVER_ICH:
1762 case AZX_DRIVER_PCH:
1772 static const struct hda_controller_ops pci_hda_ops;
1774 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1775 int dev, unsigned int driver_caps,
1778 static const struct snd_device_ops ops = {
1779 .dev_disconnect = azx_dev_disconnect,
1780 .dev_free = azx_dev_free,
1782 struct hda_intel *hda;
1788 err = pci_enable_device(pci);
1792 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1794 pci_disable_device(pci);
1799 mutex_init(&chip->open_mutex);
1802 chip->ops = &pci_hda_ops;
1803 chip->driver_caps = driver_caps;
1804 chip->driver_type = driver_caps & 0xff;
1806 chip->dev_index = dev;
1807 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1808 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1809 INIT_LIST_HEAD(&chip->pcm_list);
1810 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1811 INIT_LIST_HEAD(&hda->list);
1812 init_vga_switcheroo(chip);
1813 init_completion(&hda->probe_wait);
1815 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1817 check_probe_mask(chip, dev);
1819 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1820 chip->fallback_to_single_cmd = 1;
1821 else /* explicitly set to single_cmd or not */
1822 chip->single_cmd = single_cmd;
1824 azx_check_snoop_available(chip);
1826 if (bdl_pos_adj[dev] < 0)
1827 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1829 chip->bdl_pos_adj = bdl_pos_adj[dev];
1831 err = azx_bus_init(chip, model[dev]);
1833 pci_disable_device(pci);
1837 /* use the non-cached pages in non-snoop mode */
1838 if (!azx_snoop(chip))
1839 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1841 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1842 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1843 chip->bus.core.needs_damn_long_delay = 1;
1846 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1848 dev_err(card->dev, "Error creating device [card]!\n");
1853 /* continue probing in work context as may trigger request module */
1854 INIT_WORK(&hda->probe_work, azx_probe_work);
1861 static int azx_first_init(struct azx *chip)
1863 int dev = chip->dev_index;
1864 struct pci_dev *pci = chip->pci;
1865 struct snd_card *card = chip->card;
1866 struct hdac_bus *bus = azx_bus(chip);
1868 unsigned short gcap;
1869 unsigned int dma_bits = 64;
1871 #if BITS_PER_LONG != 64
1872 /* Fix up base address on ULI M5461 */
1873 if (chip->driver_type == AZX_DRIVER_ULI) {
1875 pci_read_config_word(pci, 0x40, &tmp3);
1876 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1877 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1881 err = pci_request_regions(pci, "ICH HD audio");
1884 chip->region_requested = 1;
1886 bus->addr = pci_resource_start(pci, 0);
1887 bus->remap_addr = pci_ioremap_bar(pci, 0);
1888 if (bus->remap_addr == NULL) {
1889 dev_err(card->dev, "ioremap error\n");
1893 if (chip->driver_type == AZX_DRIVER_SKL)
1894 snd_hdac_bus_parse_capabilities(bus);
1897 * Some Intel CPUs has always running timer (ART) feature and
1898 * controller may have Global time sync reporting capability, so
1899 * check both of these before declaring synchronized time reporting
1900 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1902 chip->gts_present = false;
1905 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1906 chip->gts_present = true;
1910 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1911 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1912 pci->no_64bit_msi = true;
1914 if (pci_enable_msi(pci) < 0)
1918 pci_set_master(pci);
1920 gcap = azx_readw(chip, GCAP);
1921 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1923 /* AMD devices support 40 or 48bit DMA, take the safe one */
1924 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1927 /* disable SB600 64bit support for safety */
1928 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1929 struct pci_dev *p_smbus;
1931 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1932 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1935 if (p_smbus->revision < 0x30)
1936 gcap &= ~AZX_GCAP_64OK;
1937 pci_dev_put(p_smbus);
1941 /* NVidia hardware normally only supports up to 40 bits of DMA */
1942 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1945 /* disable 64bit DMA address on some devices */
1946 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1947 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1948 gcap &= ~AZX_GCAP_64OK;
1951 /* disable buffer size rounding to 128-byte multiples if supported */
1952 if (align_buffer_size >= 0)
1953 chip->align_buffer_size = !!align_buffer_size;
1955 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1956 chip->align_buffer_size = 0;
1958 chip->align_buffer_size = 1;
1961 /* allow 64bit DMA address if supported by H/W */
1962 if (!(gcap & AZX_GCAP_64OK))
1964 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1965 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1967 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1968 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1971 /* read number of streams from GCAP register instead of using
1974 chip->capture_streams = (gcap >> 8) & 0x0f;
1975 chip->playback_streams = (gcap >> 12) & 0x0f;
1976 if (!chip->playback_streams && !chip->capture_streams) {
1977 /* gcap didn't give any info, switching to old method */
1979 switch (chip->driver_type) {
1980 case AZX_DRIVER_ULI:
1981 chip->playback_streams = ULI_NUM_PLAYBACK;
1982 chip->capture_streams = ULI_NUM_CAPTURE;
1984 case AZX_DRIVER_ATIHDMI:
1985 case AZX_DRIVER_ATIHDMI_NS:
1986 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1987 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1989 case AZX_DRIVER_GENERIC:
1991 chip->playback_streams = ICH6_NUM_PLAYBACK;
1992 chip->capture_streams = ICH6_NUM_CAPTURE;
1996 chip->capture_index_offset = 0;
1997 chip->playback_index_offset = chip->capture_streams;
1998 chip->num_streams = chip->playback_streams + chip->capture_streams;
2000 /* sanity check for the SDxCTL.STRM field overflow */
2001 if (chip->num_streams > 15 &&
2002 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2003 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2004 "forcing separate stream tags", chip->num_streams);
2005 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2008 /* initialize streams */
2009 err = azx_init_streams(chip);
2013 err = azx_alloc_stream_pages(chip);
2017 /* initialize chip */
2020 snd_hdac_i915_set_bclk(bus);
2022 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2024 /* codec detection */
2025 if (!azx_bus(chip)->codec_mask) {
2026 dev_err(card->dev, "no codecs found!\n");
2027 /* keep running the rest for the runtime PM */
2030 if (azx_acquire_irq(chip, 0) < 0)
2033 strcpy(card->driver, "HDA-Intel");
2034 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2035 sizeof(card->shortname));
2036 snprintf(card->longname, sizeof(card->longname),
2037 "%s at 0x%lx irq %i",
2038 card->shortname, bus->addr, bus->irq);
2043 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2044 /* callback from request_firmware_nowait() */
2045 static void azx_firmware_cb(const struct firmware *fw, void *context)
2047 struct snd_card *card = context;
2048 struct azx *chip = card->private_data;
2053 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2054 if (!chip->disabled) {
2055 /* continue probing */
2056 azx_probe_continue(chip);
2061 static int disable_msi_reset_irq(struct azx *chip)
2063 struct hdac_bus *bus = azx_bus(chip);
2066 free_irq(bus->irq, chip);
2068 chip->card->sync_irq = -1;
2069 pci_disable_msi(chip->pci);
2071 err = azx_acquire_irq(chip, 1);
2078 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2079 struct vm_area_struct *area)
2082 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2083 struct azx *chip = apcm->chip;
2084 if (chip->uc_buffer)
2085 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2089 /* Denylist for skipping the whole probe:
2090 * some HD-audio PCI entries are exposed without any codecs, and such devices
2091 * should be ignored from the beginning.
2093 static const struct pci_device_id driver_denylist[] = {
2094 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2095 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2096 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2100 static const struct hda_controller_ops pci_hda_ops = {
2101 .disable_msi_reset_irq = disable_msi_reset_irq,
2102 .pcm_mmap_prepare = pcm_mmap_prepare,
2103 .position_check = azx_position_check,
2106 static int azx_probe(struct pci_dev *pci,
2107 const struct pci_device_id *pci_id)
2110 struct snd_card *card;
2111 struct hda_intel *hda;
2113 bool schedule_probe;
2116 if (pci_match_id(driver_denylist, pci)) {
2117 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2121 if (dev >= SNDRV_CARDS)
2129 * stop probe if another Intel's DSP driver should be activated
2132 err = snd_intel_dsp_driver_probe(pci);
2133 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2134 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2138 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2141 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2144 dev_err(&pci->dev, "Error creating card!\n");
2148 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2151 card->private_data = chip;
2152 hda = container_of(chip, struct hda_intel, chip);
2154 pci_set_drvdata(pci, card);
2156 err = register_vga_switcheroo(chip);
2158 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2162 if (check_hdmi_disabled(pci)) {
2163 dev_info(card->dev, "VGA controller is disabled\n");
2164 dev_info(card->dev, "Delaying initialization\n");
2165 chip->disabled = true;
2168 schedule_probe = !chip->disabled;
2170 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2171 if (patch[dev] && *patch[dev]) {
2172 dev_info(card->dev, "Applying patch firmware '%s'\n",
2174 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2175 &pci->dev, GFP_KERNEL, card,
2179 schedule_probe = false; /* continued in azx_firmware_cb() */
2181 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2183 #ifndef CONFIG_SND_HDA_I915
2184 if (CONTROLLER_IN_GPU(pci))
2185 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2189 schedule_work(&hda->probe_work);
2193 complete_all(&hda->probe_wait);
2197 snd_card_free(card);
2202 /* On some boards setting power_save to a non 0 value leads to clicking /
2203 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2204 * figure out how to avoid these sounds, but that is not always feasible.
2205 * So we keep a list of devices where we disable powersaving as its known
2206 * to causes problems on these devices.
2208 static const struct snd_pci_quirk power_save_denylist[] = {
2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2210 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2212 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2214 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2216 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2218 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2220 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2222 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2224 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2225 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2226 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2227 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2228 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2229 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2230 /* https://bugs.launchpad.net/bugs/1821663 */
2231 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2233 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2234 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2235 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2237 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2238 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2239 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2240 /* https://bugs.launchpad.net/bugs/1821663 */
2241 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2244 #endif /* CONFIG_PM */
2246 static void set_default_power_save(struct azx *chip)
2248 int val = power_save;
2252 const struct snd_pci_quirk *q;
2254 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2256 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2257 q->subvendor, q->subdevice);
2261 #endif /* CONFIG_PM */
2262 snd_hda_set_power_save(&chip->bus, val * 1000);
2265 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2266 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2267 [AZX_DRIVER_NVIDIA] = 8,
2268 [AZX_DRIVER_TERA] = 1,
2271 static int azx_probe_continue(struct azx *chip)
2273 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2274 struct hdac_bus *bus = azx_bus(chip);
2275 struct pci_dev *pci = chip->pci;
2276 int dev = chip->dev_index;
2279 to_hda_bus(bus)->bus_probing = 1;
2280 hda->probe_continued = 1;
2282 /* bind with i915 if needed */
2283 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2284 err = snd_hdac_i915_init(bus);
2286 /* if the controller is bound only with HDMI/DP
2287 * (for HSW and BDW), we need to abort the probe;
2288 * for other chips, still continue probing as other
2289 * codecs can be on the same link.
2291 if (CONTROLLER_IN_GPU(pci)) {
2292 dev_err(chip->card->dev,
2293 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2296 /* don't bother any longer */
2297 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2301 /* HSW/BDW controllers need this power */
2302 if (CONTROLLER_IN_GPU(pci))
2303 hda->need_i915_power = 1;
2306 /* Request display power well for the HDA controller or codec. For
2307 * Haswell/Broadwell, both the display HDA controller and codec need
2308 * this power. For other platforms, like Baytrail/Braswell, only the
2309 * display codec needs the power and it can be released after probe.
2311 display_power(chip, true);
2313 err = azx_first_init(chip);
2317 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2318 chip->beep_mode = beep_mode[dev];
2321 /* create codec instances */
2322 if (bus->codec_mask) {
2323 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2328 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2330 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2335 release_firmware(chip->fw); /* no longer needed */
2340 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2341 err = azx_codec_configure(chip);
2346 err = snd_card_register(chip->card);
2350 setup_vga_switcheroo_runtime_pm(chip);
2353 azx_add_card_list(chip);
2355 set_default_power_save(chip);
2357 if (azx_has_pm_runtime(chip)) {
2358 pm_runtime_use_autosuspend(&pci->dev);
2359 pm_runtime_put_autosuspend(&pci->dev);
2368 if (!hda->need_i915_power)
2369 display_power(chip, false);
2370 complete_all(&hda->probe_wait);
2371 to_hda_bus(bus)->bus_probing = 0;
2375 static void azx_remove(struct pci_dev *pci)
2377 struct snd_card *card = pci_get_drvdata(pci);
2379 struct hda_intel *hda;
2382 /* cancel the pending probing work */
2383 chip = card->private_data;
2384 hda = container_of(chip, struct hda_intel, chip);
2385 /* FIXME: below is an ugly workaround.
2386 * Both device_release_driver() and driver_probe_device()
2387 * take *both* the device's and its parent's lock before
2388 * calling the remove() and probe() callbacks. The codec
2389 * probe takes the locks of both the codec itself and its
2390 * parent, i.e. the PCI controller dev. Meanwhile, when
2391 * the PCI controller is unbound, it takes its lock, too
2392 * ==> ouch, a deadlock!
2393 * As a workaround, we unlock temporarily here the controller
2394 * device during cancel_work_sync() call.
2396 device_unlock(&pci->dev);
2397 cancel_work_sync(&hda->probe_work);
2398 device_lock(&pci->dev);
2400 snd_card_free(card);
2404 static void azx_shutdown(struct pci_dev *pci)
2406 struct snd_card *card = pci_get_drvdata(pci);
2411 chip = card->private_data;
2412 if (chip && chip->running)
2413 azx_stop_chip(chip);
2417 static const struct pci_device_id azx_ids[] = {
2419 { PCI_DEVICE(0x8086, 0x1c20),
2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2422 { PCI_DEVICE(0x8086, 0x1d20),
2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2425 { PCI_DEVICE(0x8086, 0x1e20),
2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2428 { PCI_DEVICE(0x8086, 0x8c20),
2429 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2431 { PCI_DEVICE(0x8086, 0x8ca0),
2432 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434 { PCI_DEVICE(0x8086, 0x8d20),
2435 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2436 { PCI_DEVICE(0x8086, 0x8d21),
2437 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2439 { PCI_DEVICE(0x8086, 0xa1f0),
2440 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2441 { PCI_DEVICE(0x8086, 0xa270),
2442 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2444 { PCI_DEVICE(0x8086, 0x9c20),
2445 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2447 { PCI_DEVICE(0x8086, 0x9c21),
2448 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2449 /* Wildcat Point-LP */
2450 { PCI_DEVICE(0x8086, 0x9ca0),
2451 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2453 { PCI_DEVICE(0x8086, 0xa170),
2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2455 /* Sunrise Point-LP */
2456 { PCI_DEVICE(0x8086, 0x9d70),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2459 { PCI_DEVICE(0x8086, 0xa171),
2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2462 { PCI_DEVICE(0x8086, 0x9d71),
2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2465 { PCI_DEVICE(0x8086, 0xa2f0),
2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2468 { PCI_DEVICE(0x8086, 0xa348),
2469 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471 { PCI_DEVICE(0x8086, 0x9dc8),
2472 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2474 { PCI_DEVICE(0x8086, 0x02C8),
2475 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477 { PCI_DEVICE(0x8086, 0x06C8),
2478 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2480 { PCI_DEVICE(0x8086, 0xa3f0),
2481 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2483 { PCI_DEVICE(0x8086, 0x34c8),
2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2486 { PCI_DEVICE(0x8086, 0x3dc8),
2487 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2489 { PCI_DEVICE(0x8086, 0x38c8),
2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491 { PCI_DEVICE(0x8086, 0x4dc8),
2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494 { PCI_DEVICE(0x8086, 0xa0c8),
2495 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2497 { PCI_DEVICE(0x8086, 0x43c8),
2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2500 { PCI_DEVICE(0x8086, 0x490d),
2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2503 { PCI_DEVICE(0x8086, 0x4b55),
2504 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2505 { PCI_DEVICE(0x8086, 0x4b58),
2506 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2507 /* Broxton-P(Apollolake) */
2508 { PCI_DEVICE(0x8086, 0x5a98),
2509 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2511 { PCI_DEVICE(0x8086, 0x1a98),
2512 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2514 { PCI_DEVICE(0x8086, 0x3198),
2515 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2517 { PCI_DEVICE(0x8086, 0x0a0c),
2518 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2519 { PCI_DEVICE(0x8086, 0x0c0c),
2520 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2521 { PCI_DEVICE(0x8086, 0x0d0c),
2522 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2524 { PCI_DEVICE(0x8086, 0x160c),
2525 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2527 { PCI_DEVICE(0x8086, 0x3b56),
2528 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2530 { PCI_DEVICE(0x8086, 0x811b),
2531 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2533 { PCI_DEVICE(0x8086, 0x080a),
2534 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2536 { PCI_DEVICE(0x8086, 0x0f04),
2537 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2539 { PCI_DEVICE(0x8086, 0x2284),
2540 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2542 { PCI_DEVICE(0x8086, 0x2668),
2543 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2545 { PCI_DEVICE(0x8086, 0x27d8),
2546 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2548 { PCI_DEVICE(0x8086, 0x269a),
2549 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2551 { PCI_DEVICE(0x8086, 0x284b),
2552 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2554 { PCI_DEVICE(0x8086, 0x293e),
2555 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2557 { PCI_DEVICE(0x8086, 0x293f),
2558 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2560 { PCI_DEVICE(0x8086, 0x3a3e),
2561 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2563 { PCI_DEVICE(0x8086, 0x3a6e),
2564 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2567 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2568 .class_mask = 0xffffff,
2569 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2570 /* ATI SB 450/600/700/800/900 */
2571 { PCI_DEVICE(0x1002, 0x437b),
2572 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2573 { PCI_DEVICE(0x1002, 0x4383),
2574 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2576 { PCI_DEVICE(0x1022, 0x780d),
2577 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2578 /* AMD, X370 & co */
2579 { PCI_DEVICE(0x1022, 0x1457),
2580 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2581 /* AMD, X570 & co */
2582 { PCI_DEVICE(0x1022, 0x1487),
2583 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2585 { PCI_DEVICE(0x1022, 0x157a),
2586 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2587 AZX_DCAPS_PM_RUNTIME },
2589 { PCI_DEVICE(0x1022, 0x15e3),
2590 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2592 { PCI_DEVICE(0x1002, 0x0002),
2593 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2594 { PCI_DEVICE(0x1002, 0x1308),
2595 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2596 { PCI_DEVICE(0x1002, 0x157a),
2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2598 { PCI_DEVICE(0x1002, 0x15b3),
2599 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2600 { PCI_DEVICE(0x1002, 0x793b),
2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2602 { PCI_DEVICE(0x1002, 0x7919),
2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2604 { PCI_DEVICE(0x1002, 0x960f),
2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2606 { PCI_DEVICE(0x1002, 0x970f),
2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2608 { PCI_DEVICE(0x1002, 0x9840),
2609 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2610 { PCI_DEVICE(0x1002, 0xaa00),
2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2612 { PCI_DEVICE(0x1002, 0xaa08),
2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2614 { PCI_DEVICE(0x1002, 0xaa10),
2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2616 { PCI_DEVICE(0x1002, 0xaa18),
2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2618 { PCI_DEVICE(0x1002, 0xaa20),
2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2620 { PCI_DEVICE(0x1002, 0xaa28),
2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2622 { PCI_DEVICE(0x1002, 0xaa30),
2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2624 { PCI_DEVICE(0x1002, 0xaa38),
2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2626 { PCI_DEVICE(0x1002, 0xaa40),
2627 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2628 { PCI_DEVICE(0x1002, 0xaa48),
2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630 { PCI_DEVICE(0x1002, 0xaa50),
2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632 { PCI_DEVICE(0x1002, 0xaa58),
2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634 { PCI_DEVICE(0x1002, 0xaa60),
2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636 { PCI_DEVICE(0x1002, 0xaa68),
2637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638 { PCI_DEVICE(0x1002, 0xaa80),
2639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2640 { PCI_DEVICE(0x1002, 0xaa88),
2641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642 { PCI_DEVICE(0x1002, 0xaa90),
2643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644 { PCI_DEVICE(0x1002, 0xaa98),
2645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646 { PCI_DEVICE(0x1002, 0x9902),
2647 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2648 { PCI_DEVICE(0x1002, 0xaaa0),
2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2650 { PCI_DEVICE(0x1002, 0xaaa8),
2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2652 { PCI_DEVICE(0x1002, 0xaab0),
2653 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2654 { PCI_DEVICE(0x1002, 0xaac0),
2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2656 { PCI_DEVICE(0x1002, 0xaac8),
2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2658 { PCI_DEVICE(0x1002, 0xaad8),
2659 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2660 AZX_DCAPS_PM_RUNTIME },
2661 { PCI_DEVICE(0x1002, 0xaae0),
2662 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2663 AZX_DCAPS_PM_RUNTIME },
2664 { PCI_DEVICE(0x1002, 0xaae8),
2665 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2666 AZX_DCAPS_PM_RUNTIME },
2667 { PCI_DEVICE(0x1002, 0xaaf0),
2668 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2669 AZX_DCAPS_PM_RUNTIME },
2670 { PCI_DEVICE(0x1002, 0xaaf8),
2671 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2672 AZX_DCAPS_PM_RUNTIME },
2673 { PCI_DEVICE(0x1002, 0xab00),
2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2675 AZX_DCAPS_PM_RUNTIME },
2676 { PCI_DEVICE(0x1002, 0xab08),
2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2678 AZX_DCAPS_PM_RUNTIME },
2679 { PCI_DEVICE(0x1002, 0xab10),
2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2681 AZX_DCAPS_PM_RUNTIME },
2682 { PCI_DEVICE(0x1002, 0xab18),
2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2684 AZX_DCAPS_PM_RUNTIME },
2685 { PCI_DEVICE(0x1002, 0xab20),
2686 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2687 AZX_DCAPS_PM_RUNTIME },
2688 { PCI_DEVICE(0x1002, 0xab28),
2689 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2690 AZX_DCAPS_PM_RUNTIME },
2691 { PCI_DEVICE(0x1002, 0xab38),
2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2693 AZX_DCAPS_PM_RUNTIME },
2694 /* VIA VT8251/VT8237A */
2695 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2696 /* VIA GFX VT7122/VX900 */
2697 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2698 /* VIA GFX VT6122/VX11 */
2699 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2701 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2703 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2705 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2706 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2707 .class_mask = 0xffffff,
2708 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2710 { PCI_DEVICE(0x6549, 0x1200),
2711 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2712 { PCI_DEVICE(0x6549, 0x2200),
2713 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2714 /* Creative X-Fi (CA0110-IBG) */
2716 { PCI_DEVICE(0x1102, 0x0010),
2717 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2718 { PCI_DEVICE(0x1102, 0x0012),
2719 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2720 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2721 /* the following entry conflicts with snd-ctxfi driver,
2722 * as ctxfi driver mutates from HD-audio to native mode with
2723 * a special command sequence.
2725 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2726 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2727 .class_mask = 0xffffff,
2728 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2729 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2731 /* this entry seems still valid -- i.e. without emu20kx chip */
2732 { PCI_DEVICE(0x1102, 0x0009),
2733 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2734 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2737 { PCI_DEVICE(0x13f6, 0x5011),
2738 .driver_data = AZX_DRIVER_CMEDIA |
2739 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2741 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2742 /* VMware HDAudio */
2743 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2744 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2745 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2746 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2747 .class_mask = 0xffffff,
2748 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2749 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2750 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2751 .class_mask = 0xffffff,
2752 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2754 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2757 MODULE_DEVICE_TABLE(pci, azx_ids);
2759 /* pci_driver definition */
2760 static struct pci_driver azx_driver = {
2761 .name = KBUILD_MODNAME,
2762 .id_table = azx_ids,
2764 .remove = azx_remove,
2765 .shutdown = azx_shutdown,
2771 module_pci_driver(azx_driver);