sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = 1;
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 165                              "(0=off, 1=on) (default=1); "
 166                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 167
 168 #ifdef CONFIG_PM
 169 static int param_set_xint(const char *val, const struct kernel_param *kp);
 170 static const struct kernel_param_ops param_ops_xint = {
 171         .set = param_set_xint,
 172         .get = param_get_int,
 173 };
 174 #define param_check_xint param_check_int
 175
 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 177 module_param(power_save, xint, 0644);
 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 179                  "(in second, 0 = disable).");
 180
 181 static bool pm_blacklist = true;
 182 module_param(pm_blacklist, bool, 0644);
 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
 184
 185 /* reset the HD-audio controller in power save mode.
 186  * this may give more power-saving, but will take longer time to
 187  * wake up.
 188  */
 189 static bool power_save_controller = 1;
 190 module_param(power_save_controller, bool, 0644);
 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 192 #else
 193 #define power_save      0
 194 #endif /* CONFIG_PM */
 195
 196 static int align_buffer_size = -1;
 197 module_param(align_buffer_size, bint, 0644);
 198 MODULE_PARM_DESC(align_buffer_size,
 199                 "Force buffer and period sizes to be multiple of 128 bytes.");
 200
 201 #ifdef CONFIG_X86
 202 static int hda_snoop = -1;
 203 module_param_named(snoop, hda_snoop, bint, 0444);
 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 205 #else
 206 #define hda_snoop               true
 207 #endif
 208
 209
 210 MODULE_LICENSE("GPL");
 211 MODULE_DESCRIPTION("Intel HDA driver");
 212
 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 215 #define SUPPORT_VGA_SWITCHEROO
 216 #endif
 217 #endif
 218
 219
 220 /*
 221  */
 222
 223 /* driver types */
 224 enum {
 225         AZX_DRIVER_ICH,
 226         AZX_DRIVER_PCH,
 227         AZX_DRIVER_SCH,
 228         AZX_DRIVER_SKL,
 229         AZX_DRIVER_HDMI,
 230         AZX_DRIVER_ATI,
 231         AZX_DRIVER_ATIHDMI,
 232         AZX_DRIVER_ATIHDMI_NS,
 233         AZX_DRIVER_VIA,
 234         AZX_DRIVER_SIS,
 235         AZX_DRIVER_ULI,
 236         AZX_DRIVER_NVIDIA,
 237         AZX_DRIVER_TERA,
 238         AZX_DRIVER_CTX,
 239         AZX_DRIVER_CTHDA,
 240         AZX_DRIVER_CMEDIA,
 241         AZX_DRIVER_ZHAOXIN,
 242         AZX_DRIVER_GENERIC,
 243         AZX_NUM_DRIVERS, /* keep this as last entry */
 244 };
 245
 246 #define azx_get_snoop_type(chip) \
 247         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 249
 250 /* quirks for old Intel chipsets */
 251 #define AZX_DCAPS_INTEL_ICH \
 252         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 253
 254 /* quirks for Intel PCH */
 255 #define AZX_DCAPS_INTEL_PCH_BASE \
 256         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 257          AZX_DCAPS_SNOOP_TYPE(SCH))
 258
 259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 260 #define AZX_DCAPS_INTEL_PCH_NOPM \
 261         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 262
 263 /* PCH for HSW/BDW; with runtime PM */
 264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 265 #define AZX_DCAPS_INTEL_PCH \
 266         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 267
 268 /* HSW HDMI */
 269 #define AZX_DCAPS_INTEL_HASWELL \
 270         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 271          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 272          AZX_DCAPS_SNOOP_TYPE(SCH))
 273
 274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 275 #define AZX_DCAPS_INTEL_BROADWELL \
 276         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 277          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 278          AZX_DCAPS_SNOOP_TYPE(SCH))
 279
 280 #define AZX_DCAPS_INTEL_BAYTRAIL \
 281         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 282
 283 #define AZX_DCAPS_INTEL_BRASWELL \
 284         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 285          AZX_DCAPS_I915_COMPONENT)
 286
 287 #define AZX_DCAPS_INTEL_SKYLAKE \
 288         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 289          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 290
 291 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 292
 293 /* quirks for ATI SB / AMD Hudson */
 294 #define AZX_DCAPS_PRESET_ATI_SB \
 295         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
 296          AZX_DCAPS_SNOOP_TYPE(ATI))
 297
 298 /* quirks for ATI/AMD HDMI */
 299 #define AZX_DCAPS_PRESET_ATI_HDMI \
 300         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
 301          AZX_DCAPS_NO_MSI64)
 302
 303 /* quirks for ATI HDMI with snoop off */
 304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 305         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 306
 307 /* quirks for AMD SB */
 308 #define AZX_DCAPS_PRESET_AMD_SB \
 309         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
 310          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 311
 312 /* quirks for Nvidia */
 313 #define AZX_DCAPS_PRESET_NVIDIA \
 314         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 315          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 316
 317 #define AZX_DCAPS_PRESET_CTHDA \
 318         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_NO_64BIT |\
 320          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 321
 322 /*
 323  * vga_switcheroo support
 324  */
 325 #ifdef SUPPORT_VGA_SWITCHEROO
 326 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 327 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 328 #else
 329 #define use_vga_switcheroo(chip)        0
 330 #define needs_eld_notify_link(chip)     false
 331 #endif
 332
 333 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 334                                         ((pci)->device == 0x0c0c) || \
 335                                         ((pci)->device == 0x0d0c) || \
 336                                         ((pci)->device == 0x160c) || \
 337                                         ((pci)->device == 0x490d))
 338
 339 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 340
 341 static const char * const driver_short_names[] = {
 342         [AZX_DRIVER_ICH] = "HDA Intel",
 343         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 344         [AZX_DRIVER_SCH] = "HDA Intel MID",
 345         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 346         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 347         [AZX_DRIVER_ATI] = "HDA ATI SB",
 348         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 349         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 350         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 351         [AZX_DRIVER_SIS] = "HDA SIS966",
 352         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 353         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 354         [AZX_DRIVER_TERA] = "HDA Teradici",
 355         [AZX_DRIVER_CTX] = "HDA Creative",
 356         [AZX_DRIVER_CTHDA] = "HDA Creative",
 357         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 358         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 363 static void set_default_power_save(struct azx *chip);
 364
 365 /*
 366  * initialize the PCI registers
 367  */
 368 /* update bits in a PCI register byte */
 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 370                             unsigned char mask, unsigned char val)
 371 {
 372         unsigned char data;
 373
 374         pci_read_config_byte(pci, reg, &data);
 375         data &= ~mask;
 376         data |= (val & mask);
 377         pci_write_config_byte(pci, reg, data);
 378 }
 379
 380 static void azx_init_pci(struct azx *chip)
 381 {
 382         int snoop_type = azx_get_snoop_type(chip);
 383
 384         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 385          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 386          * Ensuring these bits are 0 clears playback static on some HD Audio
 387          * codecs.
 388          * The PCI register TCSEL is defined in the Intel manuals.
 389          */
 390         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 391                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 392                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 393         }
 394
 395         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 396          * we need to enable snoop.
 397          */
 398         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 399                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 400                         azx_snoop(chip));
 401                 update_pci_byte(chip->pci,
 402                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 403                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 404         }
 405
 406         /* For NVIDIA HDA, enable snoop */
 407         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 408                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 409                         azx_snoop(chip));
 410                 update_pci_byte(chip->pci,
 411                                 NVIDIA_HDA_TRANSREG_ADDR,
 412                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 413                 update_pci_byte(chip->pci,
 414                                 NVIDIA_HDA_ISTRM_COH,
 415                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 416                 update_pci_byte(chip->pci,
 417                                 NVIDIA_HDA_OSTRM_COH,
 418                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 419         }
 420
 421         /* Enable SCH/PCH snoop if needed */
 422         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 423                 unsigned short snoop;
 424                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 425                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 426                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 427                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 428                         if (!azx_snoop(chip))
 429                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 430                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 431                         pci_read_config_word(chip->pci,
 432                                 INTEL_SCH_HDA_DEVC, &snoop);
 433                 }
 434                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 435                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 436                         "Disabled" : "Enabled");
 437         }
 438 }
 439
 440 /*
 441  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 442  * and makes an audio stream sensitive to system latencies when
 443  * 24/32 bits are playing.
 444  * Adjusting threshold of DMA fifo to force the DMA request
 445  * sooner to improve latency tolerance at the expense of power.
 446  */
 447 static void bxt_reduce_dma_latency(struct azx *chip)
 448 {
 449         u32 val;
 450
 451         val = azx_readl(chip, VS_EM4L);
 452         val &= (0x3 << 20);
 453         azx_writel(chip, VS_EM4L, val);
 454 }
 455
 456 /*
 457  * ML_LCAP bits:
 458  *  bit 0: 6 MHz Supported
 459  *  bit 1: 12 MHz Supported
 460  *  bit 2: 24 MHz Supported
 461  *  bit 3: 48 MHz Supported
 462  *  bit 4: 96 MHz Supported
 463  *  bit 5: 192 MHz Supported
 464  */
 465 static int intel_get_lctl_scf(struct azx *chip)
 466 {
 467         struct hdac_bus *bus = azx_bus(chip);
 468         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 469         u32 val, t;
 470         int i;
 471
 472         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 473
 474         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 475                 t = preferred_bits[i];
 476                 if (val & (1 << t))
 477                         return t;
 478         }
 479
 480         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 481         return 0;
 482 }
 483
 484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 485 {
 486         struct hdac_bus *bus = azx_bus(chip);
 487         u32 val;
 488         int timeout;
 489
 490         /*
 491          * the codecs are sharing the first link setting by default
 492          * If other links are enabled for stream, they need similar fix
 493          */
 494         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 495         val &= ~AZX_MLCTL_SPA;
 496         val |= state << AZX_MLCTL_SPA_SHIFT;
 497         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 498         /* wait for CPA */
 499         timeout = 50;
 500         while (timeout) {
 501                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 502                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 503                         return 0;
 504                 timeout--;
 505                 udelay(10);
 506         }
 507
 508         return -1;
 509 }
 510
 511 static void intel_init_lctl(struct azx *chip)
 512 {
 513         struct hdac_bus *bus = azx_bus(chip);
 514         u32 val;
 515         int ret;
 516
 517         /* 0. check lctl register value is correct or not */
 518         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 519         /* if SCF is already set, let's use it */
 520         if ((val & ML_LCTL_SCF_MASK) != 0)
 521                 return;
 522
 523         /*
 524          * Before operating on SPA, CPA must match SPA.
 525          * Any deviation may result in undefined behavior.
 526          */
 527         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 528                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 529                 return;
 530
 531         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 532         ret = intel_ml_lctl_set_power(chip, 0);
 533         udelay(100);
 534         if (ret)
 535                 goto set_spa;
 536
 537         /* 2. update SCF to select a properly audio clock*/
 538         val &= ~ML_LCTL_SCF_MASK;
 539         val |= intel_get_lctl_scf(chip);
 540         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 541
 542 set_spa:
 543         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 544         intel_ml_lctl_set_power(chip, 1);
 545         udelay(100);
 546 }
 547
 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         struct pci_dev *pci = chip->pci;
 552         u32 val;
 553
 554         snd_hdac_set_codec_wakeup(bus, true);
 555         if (chip->driver_type == AZX_DRIVER_SKL) {
 556                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 557                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 558                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 559         }
 560         azx_init_chip(chip, full_reset);
 561         if (chip->driver_type == AZX_DRIVER_SKL) {
 562                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 563                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 564                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 565         }
 566
 567         snd_hdac_set_codec_wakeup(bus, false);
 568
 569         /* reduce dma latency to avoid noise */
 570         if (IS_BXT(pci))
 571                 bxt_reduce_dma_latency(chip);
 572
 573         if (bus->mlcap != NULL)
 574                 intel_init_lctl(chip);
 575 }
 576
 577 /* calculate runtime delay from LPIB */
 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 579                                    unsigned int pos)
 580 {
 581         struct snd_pcm_substream *substream = azx_dev->core.substream;
 582         int stream = substream->stream;
 583         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 584         int delay;
 585
 586         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 587                 delay = pos - lpib_pos;
 588         else
 589                 delay = lpib_pos - pos;
 590         if (delay < 0) {
 591                 if (delay >= azx_dev->core.delay_negative_threshold)
 592                         delay = 0;
 593                 else
 594                         delay += azx_dev->core.bufsize;
 595         }
 596
 597         if (delay >= azx_dev->core.period_bytes) {
 598                 dev_info(chip->card->dev,
 599                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 600                          delay, azx_dev->core.period_bytes);
 601                 delay = 0;
 602                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 603                 chip->get_delay[stream] = NULL;
 604         }
 605
 606         return bytes_to_frames(substream->runtime, delay);
 607 }
 608
 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 610
 611 /* called from IRQ */
 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 613 {
 614         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 615         int ok;
 616
 617         ok = azx_position_ok(chip, azx_dev);
 618         if (ok == 1) {
 619                 azx_dev->irq_pending = 0;
 620                 return ok;
 621         } else if (ok == 0) {
 622                 /* bogus IRQ, process it later */
 623                 azx_dev->irq_pending = 1;
 624                 schedule_work(&hda->irq_pending_work);
 625         }
 626         return 0;
 627 }
 628
 629 #define display_power(chip, enable) \
 630         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 631
 632 /*
 633  * Check whether the current DMA position is acceptable for updating
 634  * periods.  Returns non-zero if it's OK.
 635  *
 636  * Many HD-audio controllers appear pretty inaccurate about
 637  * the update-IRQ timing.  The IRQ is issued before actually the
 638  * data is processed.  So, we need to process it afterwords in a
 639  * workqueue.
 640  */
 641 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 642 {
 643         struct snd_pcm_substream *substream = azx_dev->core.substream;
 644         int stream = substream->stream;
 645         u32 wallclk;
 646         unsigned int pos;
 647
 648         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 649         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 650                 return -1;      /* bogus (too early) interrupt */
 651
 652         if (chip->get_position[stream])
 653                 pos = chip->get_position[stream](chip, azx_dev);
 654         else { /* use the position buffer as default */
 655                 pos = azx_get_pos_posbuf(chip, azx_dev);
 656                 if (!pos || pos == (u32)-1) {
 657                         dev_info(chip->card->dev,
 658                                  "Invalid position buffer, using LPIB read method instead.\n");
 659                         chip->get_position[stream] = azx_get_pos_lpib;
 660                         if (chip->get_position[0] == azx_get_pos_lpib &&
 661                             chip->get_position[1] == azx_get_pos_lpib)
 662                                 azx_bus(chip)->use_posbuf = false;
 663                         pos = azx_get_pos_lpib(chip, azx_dev);
 664                         chip->get_delay[stream] = NULL;
 665                 } else {
 666                         chip->get_position[stream] = azx_get_pos_posbuf;
 667                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 668                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 669                 }
 670         }
 671
 672         if (pos >= azx_dev->core.bufsize)
 673                 pos = 0;
 674
 675         if (WARN_ONCE(!azx_dev->core.period_bytes,
 676                       "hda-intel: zero azx_dev->period_bytes"))
 677                 return -1; /* this shouldn't happen! */
 678         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 679             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 680                 /* NG - it's below the first next period boundary */
 681                 return chip->bdl_pos_adj ? 0 : -1;
 682         azx_dev->core.start_wallclk += wallclk;
 683         return 1; /* OK, it's fine */
 684 }
 685
 686 /*
 687  * The work for pending PCM period updates.
 688  */
 689 static void azx_irq_pending_work(struct work_struct *work)
 690 {
 691         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 692         struct azx *chip = &hda->chip;
 693         struct hdac_bus *bus = azx_bus(chip);
 694         struct hdac_stream *s;
 695         int pending, ok;
 696
 697         if (!hda->irq_pending_warned) {
 698                 dev_info(chip->card->dev,
 699                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 700                          chip->card->number);
 701                 hda->irq_pending_warned = 1;
 702         }
 703
 704         for (;;) {
 705                 pending = 0;
 706                 spin_lock_irq(&bus->reg_lock);
 707                 list_for_each_entry(s, &bus->stream_list, list) {
 708                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 709                         if (!azx_dev->irq_pending ||
 710                             !s->substream ||
 711                             !s->running)
 712                                 continue;
 713                         ok = azx_position_ok(chip, azx_dev);
 714                         if (ok > 0) {
 715                                 azx_dev->irq_pending = 0;
 716                                 spin_unlock(&bus->reg_lock);
 717                                 snd_pcm_period_elapsed(s->substream);
 718                                 spin_lock(&bus->reg_lock);
 719                         } else if (ok < 0) {
 720                                 pending = 0;    /* too early */
 721                         } else
 722                                 pending++;
 723                 }
 724                 spin_unlock_irq(&bus->reg_lock);
 725                 if (!pending)
 726                         return;
 727                 msleep(1);
 728         }
 729 }
 730
 731 /* clear irq_pending flags and assure no on-going workq */
 732 static void azx_clear_irq_pending(struct azx *chip)
 733 {
 734         struct hdac_bus *bus = azx_bus(chip);
 735         struct hdac_stream *s;
 736
 737         spin_lock_irq(&bus->reg_lock);
 738         list_for_each_entry(s, &bus->stream_list, list) {
 739                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 740                 azx_dev->irq_pending = 0;
 741         }
 742         spin_unlock_irq(&bus->reg_lock);
 743 }
 744
 745 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 746 {
 747         struct hdac_bus *bus = azx_bus(chip);
 748
 749         if (request_irq(chip->pci->irq, azx_interrupt,
 750                         chip->msi ? 0 : IRQF_SHARED,
 751                         chip->card->irq_descr, chip)) {
 752                 dev_err(chip->card->dev,
 753                         "unable to grab IRQ %d, disabling device\n",
 754                         chip->pci->irq);
 755                 if (do_disconnect)
 756                         snd_card_disconnect(chip->card);
 757                 return -1;
 758         }
 759         bus->irq = chip->pci->irq;
 760         chip->card->sync_irq = bus->irq;
 761         pci_intx(chip->pci, !chip->msi);
 762         return 0;
 763 }
 764
 765 /* get the current DMA position with correction on VIA chips */
 766 static unsigned int azx_via_get_position(struct azx *chip,
 767                                          struct azx_dev *azx_dev)
 768 {
 769         unsigned int link_pos, mini_pos, bound_pos;
 770         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 771         unsigned int fifo_size;
 772
 773         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 774         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 775                 /* Playback, no problem using link position */
 776                 return link_pos;
 777         }
 778
 779         /* Capture */
 780         /* For new chipset,
 781          * use mod to get the DMA position just like old chipset
 782          */
 783         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 784         mod_dma_pos %= azx_dev->core.period_bytes;
 785
 786         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 787
 788         if (azx_dev->insufficient) {
 789                 /* Link position never gather than FIFO size */
 790                 if (link_pos <= fifo_size)
 791                         return 0;
 792
 793                 azx_dev->insufficient = 0;
 794         }
 795
 796         if (link_pos <= fifo_size)
 797                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 798         else
 799                 mini_pos = link_pos - fifo_size;
 800
 801         /* Find nearest previous boudary */
 802         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 803         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 804         if (mod_link_pos >= fifo_size)
 805                 bound_pos = link_pos - mod_link_pos;
 806         else if (mod_dma_pos >= mod_mini_pos)
 807                 bound_pos = mini_pos - mod_mini_pos;
 808         else {
 809                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 810                 if (bound_pos >= azx_dev->core.bufsize)
 811                         bound_pos = 0;
 812         }
 813
 814         /* Calculate real DMA position we want */
 815         return bound_pos + mod_dma_pos;
 816 }
 817
 818 #define AMD_FIFO_SIZE   32
 819
 820 /* get the current DMA position with FIFO size correction */
 821 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 822 {
 823         struct snd_pcm_substream *substream = azx_dev->core.substream;
 824         struct snd_pcm_runtime *runtime = substream->runtime;
 825         unsigned int pos, delay;
 826
 827         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 828         if (!runtime)
 829                 return pos;
 830
 831         runtime->delay = AMD_FIFO_SIZE;
 832         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 833         if (azx_dev->insufficient) {
 834                 if (pos < delay) {
 835                         delay = pos;
 836                         runtime->delay = bytes_to_frames(runtime, pos);
 837                 } else {
 838                         azx_dev->insufficient = 0;
 839                 }
 840         }
 841
 842         /* correct the DMA position for capture stream */
 843         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 844                 if (pos < delay)
 845                         pos += azx_dev->core.bufsize;
 846                 pos -= delay;
 847         }
 848
 849         return pos;
 850 }
 851
 852 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 853                                    unsigned int pos)
 854 {
 855         struct snd_pcm_substream *substream = azx_dev->core.substream;
 856
 857         /* just read back the calculated value in the above */
 858         return substream->runtime->delay;
 859 }
 860
 861 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 862                                          struct azx_dev *azx_dev)
 863 {
 864         return _snd_hdac_chip_readl(azx_bus(chip),
 865                                     AZX_REG_VS_SDXDPIB_XBASE +
 866                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 867                                      azx_dev->core.index));
 868 }
 869
 870 /* get the current DMA position with correction on SKL+ chips */
 871 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 872 {
 873         /* DPIB register gives a more accurate position for playback */
 874         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 875                 return azx_skl_get_dpib_pos(chip, azx_dev);
 876
 877         /* For capture, we need to read posbuf, but it requires a delay
 878          * for the possible boundary overlap; the read of DPIB fetches the
 879          * actual posbuf
 880          */
 881         udelay(20);
 882         azx_skl_get_dpib_pos(chip, azx_dev);
 883         return azx_get_pos_posbuf(chip, azx_dev);
 884 }
 885
 886 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
 887 {
 888         azx_stop_chip(chip);
 889         if (!skip_link_reset)
 890                 azx_enter_link_reset(chip);
 891         azx_clear_irq_pending(chip);
 892         display_power(chip, false);
 893 }
 894
 895 #ifdef CONFIG_PM
 896 static DEFINE_MUTEX(card_list_lock);
 897 static LIST_HEAD(card_list);
 898
 899 static void azx_shutdown_chip(struct azx *chip)
 900 {
 901         __azx_shutdown_chip(chip, false);
 902 }
 903
 904 static void azx_add_card_list(struct azx *chip)
 905 {
 906         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 907         mutex_lock(&card_list_lock);
 908         list_add(&hda->list, &card_list);
 909         mutex_unlock(&card_list_lock);
 910 }
 911
 912 static void azx_del_card_list(struct azx *chip)
 913 {
 914         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 915         mutex_lock(&card_list_lock);
 916         list_del_init(&hda->list);
 917         mutex_unlock(&card_list_lock);
 918 }
 919
 920 /* trigger power-save check at writing parameter */
 921 static int param_set_xint(const char *val, const struct kernel_param *kp)
 922 {
 923         struct hda_intel *hda;
 924         struct azx *chip;
 925         int prev = power_save;
 926         int ret = param_set_int(val, kp);
 927
 928         if (ret || prev == power_save)
 929                 return ret;
 930
 931         mutex_lock(&card_list_lock);
 932         list_for_each_entry(hda, &card_list, list) {
 933                 chip = &hda->chip;
 934                 if (!hda->probe_continued || chip->disabled)
 935                         continue;
 936                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 937         }
 938         mutex_unlock(&card_list_lock);
 939         return 0;
 940 }
 941
 942 /*
 943  * power management
 944  */
 945 static bool azx_is_pm_ready(struct snd_card *card)
 946 {
 947         struct azx *chip;
 948         struct hda_intel *hda;
 949
 950         if (!card)
 951                 return false;
 952         chip = card->private_data;
 953         hda = container_of(chip, struct hda_intel, chip);
 954         if (chip->disabled || hda->init_failed || !chip->running)
 955                 return false;
 956         return true;
 957 }
 958
 959 static void __azx_runtime_resume(struct azx *chip)
 960 {
 961         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 962         struct hdac_bus *bus = azx_bus(chip);
 963         struct hda_codec *codec;
 964         int status;
 965
 966         display_power(chip, true);
 967         if (hda->need_i915_power)
 968                 snd_hdac_i915_set_bclk(bus);
 969
 970         /* Read STATESTS before controller reset */
 971         status = azx_readw(chip, STATESTS);
 972
 973         azx_init_pci(chip);
 974         hda_intel_init_chip(chip, true);
 975
 976         /* Avoid codec resume if runtime resume is for system suspend */
 977         if (!chip->pm_prepared) {
 978                 list_for_each_codec(codec, &chip->bus) {
 979                         if (codec->relaxed_resume)
 980                                 continue;
 981
 982                         if (codec->forced_resume || (status & (1 << codec->addr)))
 983                                 pm_request_resume(hda_codec_dev(codec));
 984                 }
 985         }
 986
 987         /* power down again for link-controlled chips */
 988         if (!hda->need_i915_power)
 989                 display_power(chip, false);
 990 }
 991
 992 #ifdef CONFIG_PM_SLEEP
 993 static int azx_prepare(struct device *dev)
 994 {
 995         struct snd_card *card = dev_get_drvdata(dev);
 996         struct azx *chip;
 997
 998         if (!azx_is_pm_ready(card))
 999                 return 0;
1000
1001         chip = card->private_data;
1002         chip->pm_prepared = 1;
1003         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1004
1005         flush_work(&azx_bus(chip)->unsol_work);
1006
1007         /* HDA controller always requires different WAKEEN for runtime suspend
1008          * and system suspend, so don't use direct-complete here.
1009          */
1010         return 0;
1011 }
1012
1013 static void azx_complete(struct device *dev)
1014 {
1015         struct snd_card *card = dev_get_drvdata(dev);
1016         struct azx *chip;
1017
1018         if (!azx_is_pm_ready(card))
1019                 return;
1020
1021         chip = card->private_data;
1022         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1023         chip->pm_prepared = 0;
1024 }
1025
1026 static int azx_suspend(struct device *dev)
1027 {
1028         struct snd_card *card = dev_get_drvdata(dev);
1029         struct azx *chip;
1030         struct hdac_bus *bus;
1031
1032         if (!azx_is_pm_ready(card))
1033                 return 0;
1034
1035         chip = card->private_data;
1036         bus = azx_bus(chip);
1037         azx_shutdown_chip(chip);
1038         if (bus->irq >= 0) {
1039                 free_irq(bus->irq, chip);
1040                 bus->irq = -1;
1041                 chip->card->sync_irq = -1;
1042         }
1043
1044         if (chip->msi)
1045                 pci_disable_msi(chip->pci);
1046
1047         trace_azx_suspend(chip);
1048         return 0;
1049 }
1050
1051 static int azx_resume(struct device *dev)
1052 {
1053         struct snd_card *card = dev_get_drvdata(dev);
1054         struct azx *chip;
1055
1056         if (!azx_is_pm_ready(card))
1057                 return 0;
1058
1059         chip = card->private_data;
1060         if (chip->msi)
1061                 if (pci_enable_msi(chip->pci) < 0)
1062                         chip->msi = 0;
1063         if (azx_acquire_irq(chip, 1) < 0)
1064                 return -EIO;
1065
1066         __azx_runtime_resume(chip);
1067
1068         trace_azx_resume(chip);
1069         return 0;
1070 }
1071
1072 /* put codec down to D3 at hibernation for Intel SKL+;
1073  * otherwise BIOS may still access the codec and screw up the driver
1074  */
1075 static int azx_freeze_noirq(struct device *dev)
1076 {
1077         struct snd_card *card = dev_get_drvdata(dev);
1078         struct azx *chip = card->private_data;
1079         struct pci_dev *pci = to_pci_dev(dev);
1080
1081         if (!azx_is_pm_ready(card))
1082                 return 0;
1083         if (chip->driver_type == AZX_DRIVER_SKL)
1084                 pci_set_power_state(pci, PCI_D3hot);
1085
1086         return 0;
1087 }
1088
1089 static int azx_thaw_noirq(struct device *dev)
1090 {
1091         struct snd_card *card = dev_get_drvdata(dev);
1092         struct azx *chip = card->private_data;
1093         struct pci_dev *pci = to_pci_dev(dev);
1094
1095         if (!azx_is_pm_ready(card))
1096                 return 0;
1097         if (chip->driver_type == AZX_DRIVER_SKL)
1098                 pci_set_power_state(pci, PCI_D0);
1099
1100         return 0;
1101 }
1102 #endif /* CONFIG_PM_SLEEP */
1103
1104 static int azx_runtime_suspend(struct device *dev)
1105 {
1106         struct snd_card *card = dev_get_drvdata(dev);
1107         struct azx *chip;
1108
1109         if (!azx_is_pm_ready(card))
1110                 return 0;
1111         chip = card->private_data;
1112
1113         /* enable controller wake up event */
1114         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1115
1116         azx_shutdown_chip(chip);
1117         trace_azx_runtime_suspend(chip);
1118         return 0;
1119 }
1120
1121 static int azx_runtime_resume(struct device *dev)
1122 {
1123         struct snd_card *card = dev_get_drvdata(dev);
1124         struct azx *chip;
1125
1126         if (!azx_is_pm_ready(card))
1127                 return 0;
1128         chip = card->private_data;
1129         __azx_runtime_resume(chip);
1130
1131         /* disable controller Wake Up event*/
1132         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1133
1134         trace_azx_runtime_resume(chip);
1135         return 0;
1136 }
1137
1138 static int azx_runtime_idle(struct device *dev)
1139 {
1140         struct snd_card *card = dev_get_drvdata(dev);
1141         struct azx *chip;
1142         struct hda_intel *hda;
1143
1144         if (!card)
1145                 return 0;
1146
1147         chip = card->private_data;
1148         hda = container_of(chip, struct hda_intel, chip);
1149         if (chip->disabled || hda->init_failed)
1150                 return 0;
1151
1152         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1153             azx_bus(chip)->codec_powered || !chip->running)
1154                 return -EBUSY;
1155
1156         /* ELD notification gets broken when HD-audio bus is off */
1157         if (needs_eld_notify_link(chip))
1158                 return -EBUSY;
1159
1160         return 0;
1161 }
1162
1163 static const struct dev_pm_ops azx_pm = {
1164         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1165 #ifdef CONFIG_PM_SLEEP
1166         .prepare = azx_prepare,
1167         .complete = azx_complete,
1168         .freeze_noirq = azx_freeze_noirq,
1169         .thaw_noirq = azx_thaw_noirq,
1170 #endif
1171         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1172 };
1173
1174 #define AZX_PM_OPS      &azx_pm
1175 #else
1176 #define azx_add_card_list(chip) /* NOP */
1177 #define azx_del_card_list(chip) /* NOP */
1178 #define AZX_PM_OPS      NULL
1179 #endif /* CONFIG_PM */
1180
1181
1182 static int azx_probe_continue(struct azx *chip);
1183
1184 #ifdef SUPPORT_VGA_SWITCHEROO
1185 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1186
1187 static void azx_vs_set_state(struct pci_dev *pci,
1188                              enum vga_switcheroo_state state)
1189 {
1190         struct snd_card *card = pci_get_drvdata(pci);
1191         struct azx *chip = card->private_data;
1192         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1193         struct hda_codec *codec;
1194         bool disabled;
1195
1196         wait_for_completion(&hda->probe_wait);
1197         if (hda->init_failed)
1198                 return;
1199
1200         disabled = (state == VGA_SWITCHEROO_OFF);
1201         if (chip->disabled == disabled)
1202                 return;
1203
1204         if (!hda->probe_continued) {
1205                 chip->disabled = disabled;
1206                 if (!disabled) {
1207                         dev_info(chip->card->dev,
1208                                  "Start delayed initialization\n");
1209                         if (azx_probe_continue(chip) < 0)
1210                                 dev_err(chip->card->dev, "initialization error\n");
1211                 }
1212         } else {
1213                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1214                          disabled ? "Disabling" : "Enabling");
1215                 if (disabled) {
1216                         list_for_each_codec(codec, &chip->bus) {
1217                                 pm_runtime_suspend(hda_codec_dev(codec));
1218                                 pm_runtime_disable(hda_codec_dev(codec));
1219                         }
1220                         pm_runtime_suspend(card->dev);
1221                         pm_runtime_disable(card->dev);
1222                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1223                          * however we have no ACPI handle, so pci/acpi can't put us there,
1224                          * put ourselves there */
1225                         pci->current_state = PCI_D3cold;
1226                         chip->disabled = true;
1227                         if (snd_hda_lock_devices(&chip->bus))
1228                                 dev_warn(chip->card->dev,
1229                                          "Cannot lock devices!\n");
1230                 } else {
1231                         snd_hda_unlock_devices(&chip->bus);
1232                         chip->disabled = false;
1233                         pm_runtime_enable(card->dev);
1234                         list_for_each_codec(codec, &chip->bus) {
1235                                 pm_runtime_enable(hda_codec_dev(codec));
1236                                 pm_runtime_resume(hda_codec_dev(codec));
1237                         }
1238                 }
1239         }
1240 }
1241
1242 static bool azx_vs_can_switch(struct pci_dev *pci)
1243 {
1244         struct snd_card *card = pci_get_drvdata(pci);
1245         struct azx *chip = card->private_data;
1246         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1247
1248         wait_for_completion(&hda->probe_wait);
1249         if (hda->init_failed)
1250                 return false;
1251         if (chip->disabled || !hda->probe_continued)
1252                 return true;
1253         if (snd_hda_lock_devices(&chip->bus))
1254                 return false;
1255         snd_hda_unlock_devices(&chip->bus);
1256         return true;
1257 }
1258
1259 /*
1260  * The discrete GPU cannot power down unless the HDA controller runtime
1261  * suspends, so activate runtime PM on codecs even if power_save == 0.
1262  */
1263 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1264 {
1265         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1266         struct hda_codec *codec;
1267
1268         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1269                 list_for_each_codec(codec, &chip->bus)
1270                         codec->auto_runtime_pm = 1;
1271                 /* reset the power save setup */
1272                 if (chip->running)
1273                         set_default_power_save(chip);
1274         }
1275 }
1276
1277 static void azx_vs_gpu_bound(struct pci_dev *pci,
1278                              enum vga_switcheroo_client_id client_id)
1279 {
1280         struct snd_card *card = pci_get_drvdata(pci);
1281         struct azx *chip = card->private_data;
1282
1283         if (client_id == VGA_SWITCHEROO_DIS)
1284                 chip->bus.keep_power = 0;
1285         setup_vga_switcheroo_runtime_pm(chip);
1286 }
1287
1288 static void init_vga_switcheroo(struct azx *chip)
1289 {
1290         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1291         struct pci_dev *p = get_bound_vga(chip->pci);
1292         struct pci_dev *parent;
1293         if (p) {
1294                 dev_info(chip->card->dev,
1295                          "Handle vga_switcheroo audio client\n");
1296                 hda->use_vga_switcheroo = 1;
1297
1298                 /* cleared in either gpu_bound op or codec probe, or when its
1299                  * upstream port has _PR3 (i.e. dGPU).
1300                  */
1301                 parent = pci_upstream_bridge(p);
1302                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1303                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1304                 pci_dev_put(p);
1305         }
1306 }
1307
1308 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1309         .set_gpu_state = azx_vs_set_state,
1310         .can_switch = azx_vs_can_switch,
1311         .gpu_bound = azx_vs_gpu_bound,
1312 };
1313
1314 static int register_vga_switcheroo(struct azx *chip)
1315 {
1316         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1317         struct pci_dev *p;
1318         int err;
1319
1320         if (!hda->use_vga_switcheroo)
1321                 return 0;
1322
1323         p = get_bound_vga(chip->pci);
1324         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1325         pci_dev_put(p);
1326
1327         if (err < 0)
1328                 return err;
1329         hda->vga_switcheroo_registered = 1;
1330
1331         return 0;
1332 }
1333 #else
1334 #define init_vga_switcheroo(chip)               /* NOP */
1335 #define register_vga_switcheroo(chip)           0
1336 #define check_hdmi_disabled(pci)        false
1337 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1338 #endif /* SUPPORT_VGA_SWITCHER */
1339
1340 /*
1341  * destructor
1342  */
1343 static void azx_free(struct azx *chip)
1344 {
1345         struct pci_dev *pci = chip->pci;
1346         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1347         struct hdac_bus *bus = azx_bus(chip);
1348
1349         if (hda->freed)
1350                 return;
1351
1352         if (azx_has_pm_runtime(chip) && chip->running)
1353                 pm_runtime_get_noresume(&pci->dev);
1354         chip->running = 0;
1355
1356         azx_del_card_list(chip);
1357
1358         hda->init_failed = 1; /* to be sure */
1359         complete_all(&hda->probe_wait);
1360
1361         if (use_vga_switcheroo(hda)) {
1362                 if (chip->disabled && hda->probe_continued)
1363                         snd_hda_unlock_devices(&chip->bus);
1364                 if (hda->vga_switcheroo_registered)
1365                         vga_switcheroo_unregister_client(chip->pci);
1366         }
1367
1368         if (bus->chip_init) {
1369                 azx_clear_irq_pending(chip);
1370                 azx_stop_all_streams(chip);
1371                 azx_stop_chip(chip);
1372         }
1373
1374         if (bus->irq >= 0)
1375                 free_irq(bus->irq, (void*)chip);
1376         if (chip->msi)
1377                 pci_disable_msi(chip->pci);
1378         iounmap(bus->remap_addr);
1379
1380         azx_free_stream_pages(chip);
1381         azx_free_streams(chip);
1382         snd_hdac_bus_exit(bus);
1383
1384         if (chip->region_requested)
1385                 pci_release_regions(chip->pci);
1386
1387         pci_disable_device(chip->pci);
1388 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1389         release_firmware(chip->fw);
1390 #endif
1391         display_power(chip, false);
1392
1393         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1394                 snd_hdac_i915_exit(bus);
1395
1396         hda->freed = 1;
1397 }
1398
1399 static int azx_dev_disconnect(struct snd_device *device)
1400 {
1401         struct azx *chip = device->device_data;
1402         struct hdac_bus *bus = azx_bus(chip);
1403
1404         chip->bus.shutdown = 1;
1405         cancel_work_sync(&bus->unsol_work);
1406
1407         return 0;
1408 }
1409
1410 static int azx_dev_free(struct snd_device *device)
1411 {
1412         azx_free(device->device_data);
1413         return 0;
1414 }
1415
1416 #ifdef SUPPORT_VGA_SWITCHEROO
1417 #ifdef CONFIG_ACPI
1418 /* ATPX is in the integrated GPU's namespace */
1419 static bool atpx_present(void)
1420 {
1421         struct pci_dev *pdev = NULL;
1422         acpi_handle dhandle, atpx_handle;
1423         acpi_status status;
1424
1425         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1426                 dhandle = ACPI_HANDLE(&pdev->dev);
1427                 if (dhandle) {
1428                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1429                         if (ACPI_SUCCESS(status)) {
1430                                 pci_dev_put(pdev);
1431                                 return true;
1432                         }
1433                 }
1434         }
1435         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1436                 dhandle = ACPI_HANDLE(&pdev->dev);
1437                 if (dhandle) {
1438                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1439                         if (ACPI_SUCCESS(status)) {
1440                                 pci_dev_put(pdev);
1441                                 return true;
1442                         }
1443                 }
1444         }
1445         return false;
1446 }
1447 #else
1448 static bool atpx_present(void)
1449 {
1450         return false;
1451 }
1452 #endif
1453
1454 /*
1455  * Check of disabled HDMI controller by vga_switcheroo
1456  */
1457 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1458 {
1459         struct pci_dev *p;
1460
1461         /* check only discrete GPU */
1462         switch (pci->vendor) {
1463         case PCI_VENDOR_ID_ATI:
1464         case PCI_VENDOR_ID_AMD:
1465                 if (pci->devfn == 1) {
1466                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1467                                                         pci->bus->number, 0);
1468                         if (p) {
1469                                 /* ATPX is in the integrated GPU's ACPI namespace
1470                                  * rather than the dGPU's namespace. However,
1471                                  * the dGPU is the one who is involved in
1472                                  * vgaswitcheroo.
1473                                  */
1474                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1475                                     atpx_present())
1476                                         return p;
1477                                 pci_dev_put(p);
1478                         }
1479                 }
1480                 break;
1481         case PCI_VENDOR_ID_NVIDIA:
1482                 if (pci->devfn == 1) {
1483                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1484                                                         pci->bus->number, 0);
1485                         if (p) {
1486                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1487                                         return p;
1488                                 pci_dev_put(p);
1489                         }
1490                 }
1491                 break;
1492         }
1493         return NULL;
1494 }
1495
1496 static bool check_hdmi_disabled(struct pci_dev *pci)
1497 {
1498         bool vga_inactive = false;
1499         struct pci_dev *p = get_bound_vga(pci);
1500
1501         if (p) {
1502                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1503                         vga_inactive = true;
1504                 pci_dev_put(p);
1505         }
1506         return vga_inactive;
1507 }
1508 #endif /* SUPPORT_VGA_SWITCHEROO */
1509
1510 /*
1511  * allow/deny-listing for position_fix
1512  */
1513 static const struct snd_pci_quirk position_fix_list[] = {
1514         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1515         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1522         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1523         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1524         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1525         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1526         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1527         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1528         {}
1529 };
1530
1531 static int check_position_fix(struct azx *chip, int fix)
1532 {
1533         const struct snd_pci_quirk *q;
1534
1535         switch (fix) {
1536         case POS_FIX_AUTO:
1537         case POS_FIX_LPIB:
1538         case POS_FIX_POSBUF:
1539         case POS_FIX_VIACOMBO:
1540         case POS_FIX_COMBO:
1541         case POS_FIX_SKL:
1542         case POS_FIX_FIFO:
1543                 return fix;
1544         }
1545
1546         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1547         if (q) {
1548                 dev_info(chip->card->dev,
1549                          "position_fix set to %d for device %04x:%04x\n",
1550                          q->value, q->subvendor, q->subdevice);
1551                 return q->value;
1552         }
1553
1554         /* Check VIA/ATI HD Audio Controller exist */
1555         if (chip->driver_type == AZX_DRIVER_VIA) {
1556                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1557                 return POS_FIX_VIACOMBO;
1558         }
1559         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1560                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1561                 return POS_FIX_FIFO;
1562         }
1563         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1564                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1565                 return POS_FIX_LPIB;
1566         }
1567         if (chip->driver_type == AZX_DRIVER_SKL) {
1568                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1569                 return POS_FIX_SKL;
1570         }
1571         return POS_FIX_AUTO;
1572 }
1573
1574 static void assign_position_fix(struct azx *chip, int fix)
1575 {
1576         static const azx_get_pos_callback_t callbacks[] = {
1577                 [POS_FIX_AUTO] = NULL,
1578                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1579                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1580                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1581                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1582                 [POS_FIX_SKL] = azx_get_pos_skl,
1583                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1584         };
1585
1586         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1587
1588         /* combo mode uses LPIB only for playback */
1589         if (fix == POS_FIX_COMBO)
1590                 chip->get_position[1] = NULL;
1591
1592         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1593             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1594                 chip->get_delay[0] = chip->get_delay[1] =
1595                         azx_get_delay_from_lpib;
1596         }
1597
1598         if (fix == POS_FIX_FIFO)
1599                 chip->get_delay[0] = chip->get_delay[1] =
1600                         azx_get_delay_from_fifo;
1601 }
1602
1603 /*
1604  * deny-lists for probe_mask
1605  */
1606 static const struct snd_pci_quirk probe_mask_list[] = {
1607         /* Thinkpad often breaks the controller communication when accessing
1608          * to the non-working (or non-existing) modem codec slot.
1609          */
1610         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1611         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1612         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1613         /* broken BIOS */
1614         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1615         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1616         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1617         /* forced codec slots */
1618         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1619         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1620         /* WinFast VP200 H (Teradici) user reported broken communication */
1621         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1622         {}
1623 };
1624
1625 #define AZX_FORCE_CODEC_MASK    0x100
1626
1627 static void check_probe_mask(struct azx *chip, int dev)
1628 {
1629         const struct snd_pci_quirk *q;
1630
1631         chip->codec_probe_mask = probe_mask[dev];
1632         if (chip->codec_probe_mask == -1) {
1633                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1634                 if (q) {
1635                         dev_info(chip->card->dev,
1636                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1637                                  q->value, q->subvendor, q->subdevice);
1638                         chip->codec_probe_mask = q->value;
1639                 }
1640         }
1641
1642         /* check forced option */
1643         if (chip->codec_probe_mask != -1 &&
1644             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1645                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1646                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1647                          (int)azx_bus(chip)->codec_mask);
1648         }
1649 }
1650
1651 /*
1652  * allow/deny-list for enable_msi
1653  */
1654 static const struct snd_pci_quirk msi_deny_list[] = {
1655         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1656         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1657         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1658         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1659         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1660         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1661         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1662         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1663         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1664         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1665         {}
1666 };
1667
1668 static void check_msi(struct azx *chip)
1669 {
1670         const struct snd_pci_quirk *q;
1671
1672         if (enable_msi >= 0) {
1673                 chip->msi = !!enable_msi;
1674                 return;
1675         }
1676         chip->msi = 1;  /* enable MSI as default */
1677         q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1678         if (q) {
1679                 dev_info(chip->card->dev,
1680                          "msi for device %04x:%04x set to %d\n",
1681                          q->subvendor, q->subdevice, q->value);
1682                 chip->msi = q->value;
1683                 return;
1684         }
1685
1686         /* NVidia chipsets seem to cause troubles with MSI */
1687         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1688                 dev_info(chip->card->dev, "Disabling MSI\n");
1689                 chip->msi = 0;
1690         }
1691 }
1692
1693 /* check the snoop mode availability */
1694 static void azx_check_snoop_available(struct azx *chip)
1695 {
1696         int snoop = hda_snoop;
1697
1698         if (snoop >= 0) {
1699                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1700                          snoop ? "snoop" : "non-snoop");
1701                 chip->snoop = snoop;
1702                 chip->uc_buffer = !snoop;
1703                 return;
1704         }
1705
1706         snoop = true;
1707         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1708             chip->driver_type == AZX_DRIVER_VIA) {
1709                 /* force to non-snoop mode for a new VIA controller
1710                  * when BIOS is set
1711                  */
1712                 u8 val;
1713                 pci_read_config_byte(chip->pci, 0x42, &val);
1714                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1715                                       chip->pci->revision == 0x20))
1716                         snoop = false;
1717         }
1718
1719         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1720                 snoop = false;
1721
1722         chip->snoop = snoop;
1723         if (!snoop) {
1724                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1725                 /* C-Media requires non-cached pages only for CORB/RIRB */
1726                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1727                         chip->uc_buffer = true;
1728         }
1729 }
1730
1731 static void azx_probe_work(struct work_struct *work)
1732 {
1733         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1734         azx_probe_continue(&hda->chip);
1735 }
1736
1737 static int default_bdl_pos_adj(struct azx *chip)
1738 {
1739         /* some exceptions: Atoms seem problematic with value 1 */
1740         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1741                 switch (chip->pci->device) {
1742                 case 0x0f04: /* Baytrail */
1743                 case 0x2284: /* Braswell */
1744                         return 32;
1745                 }
1746         }
1747
1748         switch (chip->driver_type) {
1749         case AZX_DRIVER_ICH:
1750         case AZX_DRIVER_PCH:
1751                 return 1;
1752         default:
1753                 return 32;
1754         }
1755 }
1756
1757 /*
1758  * constructor
1759  */
1760 static const struct hda_controller_ops pci_hda_ops;
1761
1762 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1763                       int dev, unsigned int driver_caps,
1764                       struct azx **rchip)
1765 {
1766         static const struct snd_device_ops ops = {
1767                 .dev_disconnect = azx_dev_disconnect,
1768                 .dev_free = azx_dev_free,
1769         };
1770         struct hda_intel *hda;
1771         struct azx *chip;
1772         int err;
1773
1774         *rchip = NULL;
1775
1776         err = pci_enable_device(pci);
1777         if (err < 0)
1778                 return err;
1779
1780         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1781         if (!hda) {
1782                 pci_disable_device(pci);
1783                 return -ENOMEM;
1784         }
1785
1786         chip = &hda->chip;
1787         mutex_init(&chip->open_mutex);
1788         chip->card = card;
1789         chip->pci = pci;
1790         chip->ops = &pci_hda_ops;
1791         chip->driver_caps = driver_caps;
1792         chip->driver_type = driver_caps & 0xff;
1793         check_msi(chip);
1794         chip->dev_index = dev;
1795         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1796                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1797         INIT_LIST_HEAD(&chip->pcm_list);
1798         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1799         INIT_LIST_HEAD(&hda->list);
1800         init_vga_switcheroo(chip);
1801         init_completion(&hda->probe_wait);
1802
1803         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1804
1805         check_probe_mask(chip, dev);
1806
1807         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1808                 chip->fallback_to_single_cmd = 1;
1809         else /* explicitly set to single_cmd or not */
1810                 chip->single_cmd = single_cmd;
1811
1812         azx_check_snoop_available(chip);
1813
1814         if (bdl_pos_adj[dev] < 0)
1815                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1816         else
1817                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1818
1819         err = azx_bus_init(chip, model[dev]);
1820         if (err < 0) {
1821                 pci_disable_device(pci);
1822                 return err;
1823         }
1824
1825         /* use the non-cached pages in non-snoop mode */
1826         if (!azx_snoop(chip))
1827                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1828
1829         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1830                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1831                 chip->bus.core.needs_damn_long_delay = 1;
1832         }
1833
1834         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1835         if (err < 0) {
1836                 dev_err(card->dev, "Error creating device [card]!\n");
1837                 azx_free(chip);
1838                 return err;
1839         }
1840
1841         /* continue probing in work context as may trigger request module */
1842         INIT_WORK(&hda->probe_work, azx_probe_work);
1843
1844         *rchip = chip;
1845
1846         return 0;
1847 }
1848
1849 static int azx_first_init(struct azx *chip)
1850 {
1851         int dev = chip->dev_index;
1852         struct pci_dev *pci = chip->pci;
1853         struct snd_card *card = chip->card;
1854         struct hdac_bus *bus = azx_bus(chip);
1855         int err;
1856         unsigned short gcap;
1857         unsigned int dma_bits = 64;
1858
1859 #if BITS_PER_LONG != 64
1860         /* Fix up base address on ULI M5461 */
1861         if (chip->driver_type == AZX_DRIVER_ULI) {
1862                 u16 tmp3;
1863                 pci_read_config_word(pci, 0x40, &tmp3);
1864                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1865                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1866         }
1867 #endif
1868
1869         err = pci_request_regions(pci, "ICH HD audio");
1870         if (err < 0)
1871                 return err;
1872         chip->region_requested = 1;
1873
1874         bus->addr = pci_resource_start(pci, 0);
1875         bus->remap_addr = pci_ioremap_bar(pci, 0);
1876         if (bus->remap_addr == NULL) {
1877                 dev_err(card->dev, "ioremap error\n");
1878                 return -ENXIO;
1879         }
1880
1881         if (chip->driver_type == AZX_DRIVER_SKL)
1882                 snd_hdac_bus_parse_capabilities(bus);
1883
1884         /*
1885          * Some Intel CPUs has always running timer (ART) feature and
1886          * controller may have Global time sync reporting capability, so
1887          * check both of these before declaring synchronized time reporting
1888          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1889          */
1890         chip->gts_present = false;
1891
1892 #ifdef CONFIG_X86
1893         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1894                 chip->gts_present = true;
1895 #endif
1896
1897         if (chip->msi) {
1898                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1899                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1900                         pci->no_64bit_msi = true;
1901                 }
1902                 if (pci_enable_msi(pci) < 0)
1903                         chip->msi = 0;
1904         }
1905
1906         pci_set_master(pci);
1907
1908         gcap = azx_readw(chip, GCAP);
1909         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1910
1911         /* AMD devices support 40 or 48bit DMA, take the safe one */
1912         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1913                 dma_bits = 40;
1914
1915         /* disable SB600 64bit support for safety */
1916         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1917                 struct pci_dev *p_smbus;
1918                 dma_bits = 40;
1919                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1920                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1921                                          NULL);
1922                 if (p_smbus) {
1923                         if (p_smbus->revision < 0x30)
1924                                 gcap &= ~AZX_GCAP_64OK;
1925                         pci_dev_put(p_smbus);
1926                 }
1927         }
1928
1929         /* NVidia hardware normally only supports up to 40 bits of DMA */
1930         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1931                 dma_bits = 40;
1932
1933         /* disable 64bit DMA address on some devices */
1934         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1935                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1936                 gcap &= ~AZX_GCAP_64OK;
1937         }
1938
1939         /* disable buffer size rounding to 128-byte multiples if supported */
1940         if (align_buffer_size >= 0)
1941                 chip->align_buffer_size = !!align_buffer_size;
1942         else {
1943                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1944                         chip->align_buffer_size = 0;
1945                 else
1946                         chip->align_buffer_size = 1;
1947         }
1948
1949         /* allow 64bit DMA address if supported by H/W */
1950         if (!(gcap & AZX_GCAP_64OK))
1951                 dma_bits = 32;
1952         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1953                 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1954
1955         /* read number of streams from GCAP register instead of using
1956          * hardcoded value
1957          */
1958         chip->capture_streams = (gcap >> 8) & 0x0f;
1959         chip->playback_streams = (gcap >> 12) & 0x0f;
1960         if (!chip->playback_streams && !chip->capture_streams) {
1961                 /* gcap didn't give any info, switching to old method */
1962
1963                 switch (chip->driver_type) {
1964                 case AZX_DRIVER_ULI:
1965                         chip->playback_streams = ULI_NUM_PLAYBACK;
1966                         chip->capture_streams = ULI_NUM_CAPTURE;
1967                         break;
1968                 case AZX_DRIVER_ATIHDMI:
1969                 case AZX_DRIVER_ATIHDMI_NS:
1970                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1971                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1972                         break;
1973                 case AZX_DRIVER_GENERIC:
1974                 default:
1975                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1976                         chip->capture_streams = ICH6_NUM_CAPTURE;
1977                         break;
1978                 }
1979         }
1980         chip->capture_index_offset = 0;
1981         chip->playback_index_offset = chip->capture_streams;
1982         chip->num_streams = chip->playback_streams + chip->capture_streams;
1983
1984         /* sanity check for the SDxCTL.STRM field overflow */
1985         if (chip->num_streams > 15 &&
1986             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1987                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1988                          "forcing separate stream tags", chip->num_streams);
1989                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1990         }
1991
1992         /* initialize streams */
1993         err = azx_init_streams(chip);
1994         if (err < 0)
1995                 return err;
1996
1997         err = azx_alloc_stream_pages(chip);
1998         if (err < 0)
1999                 return err;
2000
2001         /* initialize chip */
2002         azx_init_pci(chip);
2003
2004         snd_hdac_i915_set_bclk(bus);
2005
2006         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2007
2008         /* codec detection */
2009         if (!azx_bus(chip)->codec_mask) {
2010                 dev_err(card->dev, "no codecs found!\n");
2011                 /* keep running the rest for the runtime PM */
2012         }
2013
2014         if (azx_acquire_irq(chip, 0) < 0)
2015                 return -EBUSY;
2016
2017         strcpy(card->driver, "HDA-Intel");
2018         strscpy(card->shortname, driver_short_names[chip->driver_type],
2019                 sizeof(card->shortname));
2020         snprintf(card->longname, sizeof(card->longname),
2021                  "%s at 0x%lx irq %i",
2022                  card->shortname, bus->addr, bus->irq);
2023
2024         return 0;
2025 }
2026
2027 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2028 /* callback from request_firmware_nowait() */
2029 static void azx_firmware_cb(const struct firmware *fw, void *context)
2030 {
2031         struct snd_card *card = context;
2032         struct azx *chip = card->private_data;
2033
2034         if (fw)
2035                 chip->fw = fw;
2036         else
2037                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2038         if (!chip->disabled) {
2039                 /* continue probing */
2040                 azx_probe_continue(chip);
2041         }
2042 }
2043 #endif
2044
2045 static int disable_msi_reset_irq(struct azx *chip)
2046 {
2047         struct hdac_bus *bus = azx_bus(chip);
2048         int err;
2049
2050         free_irq(bus->irq, chip);
2051         bus->irq = -1;
2052         chip->card->sync_irq = -1;
2053         pci_disable_msi(chip->pci);
2054         chip->msi = 0;
2055         err = azx_acquire_irq(chip, 1);
2056         if (err < 0)
2057                 return err;
2058
2059         return 0;
2060 }
2061
2062 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2063                              struct vm_area_struct *area)
2064 {
2065 #ifdef CONFIG_X86
2066         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2067         struct azx *chip = apcm->chip;
2068         if (chip->uc_buffer)
2069                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2070 #endif
2071 }
2072
2073 /* Denylist for skipping the whole probe:
2074  * some HD-audio PCI entries are exposed without any codecs, and such devices
2075  * should be ignored from the beginning.
2076  */
2077 static const struct pci_device_id driver_denylist[] = {
2078         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2079         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2080         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2081         {}
2082 };
2083
2084 static const struct hda_controller_ops pci_hda_ops = {
2085         .disable_msi_reset_irq = disable_msi_reset_irq,
2086         .pcm_mmap_prepare = pcm_mmap_prepare,
2087         .position_check = azx_position_check,
2088 };
2089
2090 static int azx_probe(struct pci_dev *pci,
2091                      const struct pci_device_id *pci_id)
2092 {
2093         static int dev;
2094         struct snd_card *card;
2095         struct hda_intel *hda;
2096         struct azx *chip;
2097         bool schedule_probe;
2098         int err;
2099
2100         if (pci_match_id(driver_denylist, pci)) {
2101                 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2102                 return -ENODEV;
2103         }
2104
2105         if (dev >= SNDRV_CARDS)
2106                 return -ENODEV;
2107         if (!enable[dev]) {
2108                 dev++;
2109                 return -ENOENT;
2110         }
2111
2112         /*
2113          * stop probe if another Intel's DSP driver should be activated
2114          */
2115         if (dmic_detect) {
2116                 err = snd_intel_dsp_driver_probe(pci);
2117                 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2118                         dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2119                         return -ENODEV;
2120                 }
2121         } else {
2122                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2123         }
2124
2125         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2126                            0, &card);
2127         if (err < 0) {
2128                 dev_err(&pci->dev, "Error creating card!\n");
2129                 return err;
2130         }
2131
2132         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2133         if (err < 0)
2134                 goto out_free;
2135         card->private_data = chip;
2136         hda = container_of(chip, struct hda_intel, chip);
2137
2138         pci_set_drvdata(pci, card);
2139
2140         err = register_vga_switcheroo(chip);
2141         if (err < 0) {
2142                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2143                 goto out_free;
2144         }
2145
2146         if (check_hdmi_disabled(pci)) {
2147                 dev_info(card->dev, "VGA controller is disabled\n");
2148                 dev_info(card->dev, "Delaying initialization\n");
2149                 chip->disabled = true;
2150         }
2151
2152         schedule_probe = !chip->disabled;
2153
2154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2155         if (patch[dev] && *patch[dev]) {
2156                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2157                          patch[dev]);
2158                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2159                                               &pci->dev, GFP_KERNEL, card,
2160                                               azx_firmware_cb);
2161                 if (err < 0)
2162                         goto out_free;
2163                 schedule_probe = false; /* continued in azx_firmware_cb() */
2164         }
2165 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2166
2167 #ifndef CONFIG_SND_HDA_I915
2168         if (CONTROLLER_IN_GPU(pci))
2169                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2170 #endif
2171
2172         if (schedule_probe)
2173                 schedule_work(&hda->probe_work);
2174
2175         dev++;
2176         if (chip->disabled)
2177                 complete_all(&hda->probe_wait);
2178         return 0;
2179
2180 out_free:
2181         snd_card_free(card);
2182         return err;
2183 }
2184
2185 #ifdef CONFIG_PM
2186 /* On some boards setting power_save to a non 0 value leads to clicking /
2187  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2188  * figure out how to avoid these sounds, but that is not always feasible.
2189  * So we keep a list of devices where we disable powersaving as its known
2190  * to causes problems on these devices.
2191  */
2192 static const struct snd_pci_quirk power_save_denylist[] = {
2193         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2194         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2195         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2196         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2197         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2198         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2199         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2200         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2201         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2202         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2203         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2204         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2205         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2206         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2207         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2208         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2209         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2210         /* https://bugs.launchpad.net/bugs/1821663 */
2211         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2212         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2213         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2214         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2215         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2216         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2217         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2218         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2219         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2220         /* https://bugs.launchpad.net/bugs/1821663 */
2221         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2222         {}
2223 };
2224 #endif /* CONFIG_PM */
2225
2226 static void set_default_power_save(struct azx *chip)
2227 {
2228         int val = power_save;
2229
2230 #ifdef CONFIG_PM
2231         if (pm_blacklist) {
2232                 const struct snd_pci_quirk *q;
2233
2234                 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2235                 if (q && val) {
2236                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2237                                  q->subvendor, q->subdevice);
2238                         val = 0;
2239                 }
2240         }
2241 #endif /* CONFIG_PM */
2242         snd_hda_set_power_save(&chip->bus, val * 1000);
2243 }
2244
2245 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2246 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2247         [AZX_DRIVER_NVIDIA] = 8,
2248         [AZX_DRIVER_TERA] = 1,
2249 };
2250
2251 static int azx_probe_continue(struct azx *chip)
2252 {
2253         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2254         struct hdac_bus *bus = azx_bus(chip);
2255         struct pci_dev *pci = chip->pci;
2256         int dev = chip->dev_index;
2257         int err;
2258
2259         to_hda_bus(bus)->bus_probing = 1;
2260         hda->probe_continued = 1;
2261
2262         /* bind with i915 if needed */
2263         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2264                 err = snd_hdac_i915_init(bus);
2265                 if (err < 0) {
2266                         /* if the controller is bound only with HDMI/DP
2267                          * (for HSW and BDW), we need to abort the probe;
2268                          * for other chips, still continue probing as other
2269                          * codecs can be on the same link.
2270                          */
2271                         if (CONTROLLER_IN_GPU(pci)) {
2272                                 dev_err(chip->card->dev,
2273                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2274                                 goto out_free;
2275                         } else {
2276                                 /* don't bother any longer */
2277                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2278                         }
2279                 }
2280
2281                 /* HSW/BDW controllers need this power */
2282                 if (CONTROLLER_IN_GPU(pci))
2283                         hda->need_i915_power = true;
2284         }
2285
2286         /* Request display power well for the HDA controller or codec. For
2287          * Haswell/Broadwell, both the display HDA controller and codec need
2288          * this power. For other platforms, like Baytrail/Braswell, only the
2289          * display codec needs the power and it can be released after probe.
2290          */
2291         display_power(chip, true);
2292
2293         err = azx_first_init(chip);
2294         if (err < 0)
2295                 goto out_free;
2296
2297 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2298         chip->beep_mode = beep_mode[dev];
2299 #endif
2300
2301         /* create codec instances */
2302         if (bus->codec_mask) {
2303                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2304                 if (err < 0)
2305                         goto out_free;
2306         }
2307
2308 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2309         if (chip->fw) {
2310                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2311                                          chip->fw->data);
2312                 if (err < 0)
2313                         goto out_free;
2314 #ifndef CONFIG_PM
2315                 release_firmware(chip->fw); /* no longer needed */
2316                 chip->fw = NULL;
2317 #endif
2318         }
2319 #endif
2320         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2321                 err = azx_codec_configure(chip);
2322                 if (err < 0)
2323                         goto out_free;
2324         }
2325
2326         err = snd_card_register(chip->card);
2327         if (err < 0)
2328                 goto out_free;
2329
2330         setup_vga_switcheroo_runtime_pm(chip);
2331
2332         chip->running = 1;
2333         azx_add_card_list(chip);
2334
2335         set_default_power_save(chip);
2336
2337         if (azx_has_pm_runtime(chip)) {
2338                 pm_runtime_use_autosuspend(&pci->dev);
2339                 pm_runtime_allow(&pci->dev);
2340                 pm_runtime_put_autosuspend(&pci->dev);
2341         }
2342
2343 out_free:
2344         if (err < 0) {
2345                 azx_free(chip);
2346                 return err;
2347         }
2348
2349         if (!hda->need_i915_power)
2350                 display_power(chip, false);
2351         complete_all(&hda->probe_wait);
2352         to_hda_bus(bus)->bus_probing = 0;
2353         return 0;
2354 }
2355
2356 static void azx_remove(struct pci_dev *pci)
2357 {
2358         struct snd_card *card = pci_get_drvdata(pci);
2359         struct azx *chip;
2360         struct hda_intel *hda;
2361
2362         if (card) {
2363                 /* cancel the pending probing work */
2364                 chip = card->private_data;
2365                 hda = container_of(chip, struct hda_intel, chip);
2366                 /* FIXME: below is an ugly workaround.
2367                  * Both device_release_driver() and driver_probe_device()
2368                  * take *both* the device's and its parent's lock before
2369                  * calling the remove() and probe() callbacks.  The codec
2370                  * probe takes the locks of both the codec itself and its
2371                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2372                  * the PCI controller is unbound, it takes its lock, too
2373                  * ==> ouch, a deadlock!
2374                  * As a workaround, we unlock temporarily here the controller
2375                  * device during cancel_work_sync() call.
2376                  */
2377                 device_unlock(&pci->dev);
2378                 cancel_work_sync(&hda->probe_work);
2379                 device_lock(&pci->dev);
2380
2381                 snd_card_free(card);
2382         }
2383 }
2384
2385 static void azx_shutdown(struct pci_dev *pci)
2386 {
2387         struct snd_card *card = pci_get_drvdata(pci);
2388         struct azx *chip;
2389
2390         if (!card)
2391                 return;
2392         chip = card->private_data;
2393         if (chip && chip->running)
2394                 __azx_shutdown_chip(chip, true);
2395 }
2396
2397 /* PCI IDs */
2398 static const struct pci_device_id azx_ids[] = {
2399         /* CPT */
2400         { PCI_DEVICE(0x8086, 0x1c20),
2401           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402         /* PBG */
2403         { PCI_DEVICE(0x8086, 0x1d20),
2404           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2405         /* Panther Point */
2406         { PCI_DEVICE(0x8086, 0x1e20),
2407           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2408         /* Lynx Point */
2409         { PCI_DEVICE(0x8086, 0x8c20),
2410           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2411         /* 9 Series */
2412         { PCI_DEVICE(0x8086, 0x8ca0),
2413           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2414         /* Wellsburg */
2415         { PCI_DEVICE(0x8086, 0x8d20),
2416           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2417         { PCI_DEVICE(0x8086, 0x8d21),
2418           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2419         /* Lewisburg */
2420         { PCI_DEVICE(0x8086, 0xa1f0),
2421           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2422         { PCI_DEVICE(0x8086, 0xa270),
2423           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2424         /* Lynx Point-LP */
2425         { PCI_DEVICE(0x8086, 0x9c20),
2426           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2427         /* Lynx Point-LP */
2428         { PCI_DEVICE(0x8086, 0x9c21),
2429           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2430         /* Wildcat Point-LP */
2431         { PCI_DEVICE(0x8086, 0x9ca0),
2432           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2433         /* Sunrise Point */
2434         { PCI_DEVICE(0x8086, 0xa170),
2435           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2436         /* Sunrise Point-LP */
2437         { PCI_DEVICE(0x8086, 0x9d70),
2438           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2439         /* Kabylake */
2440         { PCI_DEVICE(0x8086, 0xa171),
2441           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2442         /* Kabylake-LP */
2443         { PCI_DEVICE(0x8086, 0x9d71),
2444           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2445         /* Kabylake-H */
2446         { PCI_DEVICE(0x8086, 0xa2f0),
2447           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2448         /* Coffelake */
2449         { PCI_DEVICE(0x8086, 0xa348),
2450           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2451         /* Cannonlake */
2452         { PCI_DEVICE(0x8086, 0x9dc8),
2453           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2454         /* CometLake-LP */
2455         { PCI_DEVICE(0x8086, 0x02C8),
2456           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2457         /* CometLake-H */
2458         { PCI_DEVICE(0x8086, 0x06C8),
2459           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2460         { PCI_DEVICE(0x8086, 0xf1c8),
2461           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2462         /* CometLake-S */
2463         { PCI_DEVICE(0x8086, 0xa3f0),
2464           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2465         /* CometLake-R */
2466         { PCI_DEVICE(0x8086, 0xf0c8),
2467           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468         /* Icelake */
2469         { PCI_DEVICE(0x8086, 0x34c8),
2470           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2471         /* Icelake-H */
2472         { PCI_DEVICE(0x8086, 0x3dc8),
2473           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2474         /* Jasperlake */
2475         { PCI_DEVICE(0x8086, 0x38c8),
2476           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2477         { PCI_DEVICE(0x8086, 0x4dc8),
2478           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2479         /* Tigerlake */
2480         { PCI_DEVICE(0x8086, 0xa0c8),
2481           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2482         /* Tigerlake-H */
2483         { PCI_DEVICE(0x8086, 0x43c8),
2484           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2485         /* DG1 */
2486         { PCI_DEVICE(0x8086, 0x490d),
2487           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2488         /* Alderlake-S */
2489         { PCI_DEVICE(0x8086, 0x7ad0),
2490           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491         /* Alderlake-P */
2492         { PCI_DEVICE(0x8086, 0x51c8),
2493           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494         /* Alderlake-M */
2495         { PCI_DEVICE(0x8086, 0x51cc),
2496           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2497         /* Elkhart Lake */
2498         { PCI_DEVICE(0x8086, 0x4b55),
2499           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2500         { PCI_DEVICE(0x8086, 0x4b58),
2501           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2502         /* Broxton-P(Apollolake) */
2503         { PCI_DEVICE(0x8086, 0x5a98),
2504           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2505         /* Broxton-T */
2506         { PCI_DEVICE(0x8086, 0x1a98),
2507           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2508         /* Gemini-Lake */
2509         { PCI_DEVICE(0x8086, 0x3198),
2510           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2511         /* Haswell */
2512         { PCI_DEVICE(0x8086, 0x0a0c),
2513           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2514         { PCI_DEVICE(0x8086, 0x0c0c),
2515           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2516         { PCI_DEVICE(0x8086, 0x0d0c),
2517           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2518         /* Broadwell */
2519         { PCI_DEVICE(0x8086, 0x160c),
2520           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2521         /* 5 Series/3400 */
2522         { PCI_DEVICE(0x8086, 0x3b56),
2523           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2524         /* Poulsbo */
2525         { PCI_DEVICE(0x8086, 0x811b),
2526           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2527         /* Oaktrail */
2528         { PCI_DEVICE(0x8086, 0x080a),
2529           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2530         /* BayTrail */
2531         { PCI_DEVICE(0x8086, 0x0f04),
2532           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2533         /* Braswell */
2534         { PCI_DEVICE(0x8086, 0x2284),
2535           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2536         /* ICH6 */
2537         { PCI_DEVICE(0x8086, 0x2668),
2538           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2539         /* ICH7 */
2540         { PCI_DEVICE(0x8086, 0x27d8),
2541           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2542         /* ESB2 */
2543         { PCI_DEVICE(0x8086, 0x269a),
2544           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2545         /* ICH8 */
2546         { PCI_DEVICE(0x8086, 0x284b),
2547           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2548         /* ICH9 */
2549         { PCI_DEVICE(0x8086, 0x293e),
2550           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2551         /* ICH9 */
2552         { PCI_DEVICE(0x8086, 0x293f),
2553           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2554         /* ICH10 */
2555         { PCI_DEVICE(0x8086, 0x3a3e),
2556           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2557         /* ICH10 */
2558         { PCI_DEVICE(0x8086, 0x3a6e),
2559           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2560         /* Generic Intel */
2561         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2562           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2563           .class_mask = 0xffffff,
2564           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2565         /* ATI SB 450/600/700/800/900 */
2566         { PCI_DEVICE(0x1002, 0x437b),
2567           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2568         { PCI_DEVICE(0x1002, 0x4383),
2569           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2570         /* AMD Hudson */
2571         { PCI_DEVICE(0x1022, 0x780d),
2572           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2573         /* AMD, X370 & co */
2574         { PCI_DEVICE(0x1022, 0x1457),
2575           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2576         /* AMD, X570 & co */
2577         { PCI_DEVICE(0x1022, 0x1487),
2578           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2579         /* AMD Stoney */
2580         { PCI_DEVICE(0x1022, 0x157a),
2581           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2582                          AZX_DCAPS_PM_RUNTIME },
2583         /* AMD Raven */
2584         { PCI_DEVICE(0x1022, 0x15e3),
2585           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2586         /* ATI HDMI */
2587         { PCI_DEVICE(0x1002, 0x0002),
2588           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2589           AZX_DCAPS_PM_RUNTIME },
2590         { PCI_DEVICE(0x1002, 0x1308),
2591           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2592         { PCI_DEVICE(0x1002, 0x157a),
2593           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2594         { PCI_DEVICE(0x1002, 0x15b3),
2595           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2596         { PCI_DEVICE(0x1002, 0x793b),
2597           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2598         { PCI_DEVICE(0x1002, 0x7919),
2599           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2600         { PCI_DEVICE(0x1002, 0x960f),
2601           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2602         { PCI_DEVICE(0x1002, 0x970f),
2603           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2604         { PCI_DEVICE(0x1002, 0x9840),
2605           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2606         { PCI_DEVICE(0x1002, 0xaa00),
2607           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2608         { PCI_DEVICE(0x1002, 0xaa08),
2609           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2610         { PCI_DEVICE(0x1002, 0xaa10),
2611           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2612         { PCI_DEVICE(0x1002, 0xaa18),
2613           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2614         { PCI_DEVICE(0x1002, 0xaa20),
2615           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2616         { PCI_DEVICE(0x1002, 0xaa28),
2617           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2618         { PCI_DEVICE(0x1002, 0xaa30),
2619           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2620         { PCI_DEVICE(0x1002, 0xaa38),
2621           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2622         { PCI_DEVICE(0x1002, 0xaa40),
2623           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2624         { PCI_DEVICE(0x1002, 0xaa48),
2625           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2626         { PCI_DEVICE(0x1002, 0xaa50),
2627           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2628         { PCI_DEVICE(0x1002, 0xaa58),
2629           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630         { PCI_DEVICE(0x1002, 0xaa60),
2631           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632         { PCI_DEVICE(0x1002, 0xaa68),
2633           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634         { PCI_DEVICE(0x1002, 0xaa80),
2635           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2636         { PCI_DEVICE(0x1002, 0xaa88),
2637           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638         { PCI_DEVICE(0x1002, 0xaa90),
2639           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2640         { PCI_DEVICE(0x1002, 0xaa98),
2641           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642         { PCI_DEVICE(0x1002, 0x9902),
2643           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2644         { PCI_DEVICE(0x1002, 0xaaa0),
2645           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2646         { PCI_DEVICE(0x1002, 0xaaa8),
2647           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2648         { PCI_DEVICE(0x1002, 0xaab0),
2649           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2650         { PCI_DEVICE(0x1002, 0xaac0),
2651           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652           AZX_DCAPS_PM_RUNTIME },
2653         { PCI_DEVICE(0x1002, 0xaac8),
2654           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655           AZX_DCAPS_PM_RUNTIME },
2656         { PCI_DEVICE(0x1002, 0xaad8),
2657           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658           AZX_DCAPS_PM_RUNTIME },
2659         { PCI_DEVICE(0x1002, 0xaae0),
2660           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661           AZX_DCAPS_PM_RUNTIME },
2662         { PCI_DEVICE(0x1002, 0xaae8),
2663           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664           AZX_DCAPS_PM_RUNTIME },
2665         { PCI_DEVICE(0x1002, 0xaaf0),
2666           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667           AZX_DCAPS_PM_RUNTIME },
2668         { PCI_DEVICE(0x1002, 0xaaf8),
2669           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2670           AZX_DCAPS_PM_RUNTIME },
2671         { PCI_DEVICE(0x1002, 0xab00),
2672           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2673           AZX_DCAPS_PM_RUNTIME },
2674         { PCI_DEVICE(0x1002, 0xab08),
2675           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2676           AZX_DCAPS_PM_RUNTIME },
2677         { PCI_DEVICE(0x1002, 0xab10),
2678           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2679           AZX_DCAPS_PM_RUNTIME },
2680         { PCI_DEVICE(0x1002, 0xab18),
2681           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2682           AZX_DCAPS_PM_RUNTIME },
2683         { PCI_DEVICE(0x1002, 0xab20),
2684           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685           AZX_DCAPS_PM_RUNTIME },
2686         { PCI_DEVICE(0x1002, 0xab28),
2687           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2688           AZX_DCAPS_PM_RUNTIME },
2689         { PCI_DEVICE(0x1002, 0xab38),
2690           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2691           AZX_DCAPS_PM_RUNTIME },
2692         /* VIA VT8251/VT8237A */
2693         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2694         /* VIA GFX VT7122/VX900 */
2695         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2696         /* VIA GFX VT6122/VX11 */
2697         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2698         /* SIS966 */
2699         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2700         /* ULI M5461 */
2701         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2702         /* NVIDIA MCP */
2703         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2704           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2705           .class_mask = 0xffffff,
2706           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2707         /* Teradici */
2708         { PCI_DEVICE(0x6549, 0x1200),
2709           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2710         { PCI_DEVICE(0x6549, 0x2200),
2711           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2712         /* Creative X-Fi (CA0110-IBG) */
2713         /* CTHDA chips */
2714         { PCI_DEVICE(0x1102, 0x0010),
2715           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2716         { PCI_DEVICE(0x1102, 0x0012),
2717           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2718 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2719         /* the following entry conflicts with snd-ctxfi driver,
2720          * as ctxfi driver mutates from HD-audio to native mode with
2721          * a special command sequence.
2722          */
2723         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2724           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2725           .class_mask = 0xffffff,
2726           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2727           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2728 #else
2729         /* this entry seems still valid -- i.e. without emu20kx chip */
2730         { PCI_DEVICE(0x1102, 0x0009),
2731           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2732           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2733 #endif
2734         /* CM8888 */
2735         { PCI_DEVICE(0x13f6, 0x5011),
2736           .driver_data = AZX_DRIVER_CMEDIA |
2737           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2738         /* Vortex86MX */
2739         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2740         /* VMware HDAudio */
2741         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2742         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2743         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2744           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2745           .class_mask = 0xffffff,
2746           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2747         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2748           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2749           .class_mask = 0xffffff,
2750           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2751         /* Zhaoxin */
2752         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2753         { 0, }
2754 };
2755 MODULE_DEVICE_TABLE(pci, azx_ids);
2756
2757 /* pci_driver definition */
2758 static struct pci_driver azx_driver = {
2759         .name = KBUILD_MODNAME,
2760         .id_table = azx_ids,
2761         .probe = azx_probe,
2762         .remove = azx_remove,
2763         .shutdown = azx_shutdown,
2764         .driver = {
2765                 .pm = AZX_PM_OPS,
2766         },
2767 };
2768
2769 module_pci_driver(azx_driver);