sound/pci/cs4281.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Driver for Cirrus Logic CS4281 based PCI soundcard
   4  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
   5  */
   6
   7 #include <linux/io.h>
   8 #include <linux/delay.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/init.h>
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/gameport.h>
  14 #include <linux/module.h>
  15 #include <sound/core.h>
  16 #include <sound/control.h>
  17 #include <sound/pcm.h>
  18 #include <sound/rawmidi.h>
  19 #include <sound/ac97_codec.h>
  20 #include <sound/tlv.h>
  21 #include <sound/opl3.h>
  22 #include <sound/initval.h>
  23
  24
  25 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  26 MODULE_DESCRIPTION("Cirrus Logic CS4281");
  27 MODULE_LICENSE("GPL");
  28 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
  29
  30 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  31 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  32 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  33 static bool dual_codec[SNDRV_CARDS];    /* dual codec */
  34
  35 module_param_array(index, int, NULL, 0444);
  36 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
  37 module_param_array(id, charp, NULL, 0444);
  38 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
  39 module_param_array(enable, bool, NULL, 0444);
  40 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
  41 module_param_array(dual_codec, bool, NULL, 0444);
  42 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
  43
  44 /*
  45  *  Direct registers
  46  */
  47
  48 #define CS4281_BA0_SIZE         0x1000
  49 #define CS4281_BA1_SIZE         0x10000
  50
  51 /*
  52  *  BA0 registers
  53  */
  54 #define BA0_HISR                0x0000  /* Host Interrupt Status Register */
  55 #define BA0_HISR_INTENA         (1<<31) /* Internal Interrupt Enable Bit */
  56 #define BA0_HISR_MIDI           (1<<22) /* MIDI port interrupt */
  57 #define BA0_HISR_FIFOI          (1<<20) /* FIFO polled interrupt */
  58 #define BA0_HISR_DMAI           (1<<18) /* DMA interrupt (half or end) */
  59 #define BA0_HISR_FIFO(c)        (1<<(12+(c))) /* FIFO channel interrupt */
  60 #define BA0_HISR_DMA(c)         (1<<(8+(c)))  /* DMA channel interrupt */
  61 #define BA0_HISR_GPPI           (1<<5)  /* General Purpose Input (Primary chip) */
  62 #define BA0_HISR_GPSI           (1<<4)  /* General Purpose Input (Secondary chip) */
  63 #define BA0_HISR_GP3I           (1<<3)  /* GPIO3 pin Interrupt */
  64 #define BA0_HISR_GP1I           (1<<2)  /* GPIO1 pin Interrupt */
  65 #define BA0_HISR_VUPI           (1<<1)  /* VOLUP pin Interrupt */
  66 #define BA0_HISR_VDNI           (1<<0)  /* VOLDN pin Interrupt */
  67
  68 #define BA0_HICR                0x0008  /* Host Interrupt Control Register */
  69 #define BA0_HICR_CHGM           (1<<1)  /* INTENA Change Mask */
  70 #define BA0_HICR_IEV            (1<<0)  /* INTENA Value */
  71 #define BA0_HICR_EOI            (3<<0)  /* End of Interrupt command */
  72
  73 #define BA0_HIMR                0x000c  /* Host Interrupt Mask Register */
  74                                         /* Use same contants as for BA0_HISR */
  75
  76 #define BA0_IIER                0x0010  /* ISA Interrupt Enable Register */
  77
  78 #define BA0_HDSR0               0x00f0  /* Host DMA Engine 0 Status Register */
  79 #define BA0_HDSR1               0x00f4  /* Host DMA Engine 1 Status Register */
  80 #define BA0_HDSR2               0x00f8  /* Host DMA Engine 2 Status Register */
  81 #define BA0_HDSR3               0x00fc  /* Host DMA Engine 3 Status Register */
  82
  83 #define BA0_HDSR_CH1P           (1<<25) /* Channel 1 Pending */
  84 #define BA0_HDSR_CH2P           (1<<24) /* Channel 2 Pending */
  85 #define BA0_HDSR_DHTC           (1<<17) /* DMA Half Terminal Count */
  86 #define BA0_HDSR_DTC            (1<<16) /* DMA Terminal Count */
  87 #define BA0_HDSR_DRUN           (1<<15) /* DMA Running */
  88 #define BA0_HDSR_RQ             (1<<7)  /* Pending Request */
  89
  90 #define BA0_DCA0                0x0110  /* Host DMA Engine 0 Current Address */
  91 #define BA0_DCC0                0x0114  /* Host DMA Engine 0 Current Count */
  92 #define BA0_DBA0                0x0118  /* Host DMA Engine 0 Base Address */
  93 #define BA0_DBC0                0x011c  /* Host DMA Engine 0 Base Count */
  94 #define BA0_DCA1                0x0120  /* Host DMA Engine 1 Current Address */
  95 #define BA0_DCC1                0x0124  /* Host DMA Engine 1 Current Count */
  96 #define BA0_DBA1                0x0128  /* Host DMA Engine 1 Base Address */
  97 #define BA0_DBC1                0x012c  /* Host DMA Engine 1 Base Count */
  98 #define BA0_DCA2                0x0130  /* Host DMA Engine 2 Current Address */
  99 #define BA0_DCC2                0x0134  /* Host DMA Engine 2 Current Count */
 100 #define BA0_DBA2                0x0138  /* Host DMA Engine 2 Base Address */
 101 #define BA0_DBC2                0x013c  /* Host DMA Engine 2 Base Count */
 102 #define BA0_DCA3                0x0140  /* Host DMA Engine 3 Current Address */
 103 #define BA0_DCC3                0x0144  /* Host DMA Engine 3 Current Count */
 104 #define BA0_DBA3                0x0148  /* Host DMA Engine 3 Base Address */
 105 #define BA0_DBC3                0x014c  /* Host DMA Engine 3 Base Count */
 106 #define BA0_DMR0                0x0150  /* Host DMA Engine 0 Mode */
 107 #define BA0_DCR0                0x0154  /* Host DMA Engine 0 Command */
 108 #define BA0_DMR1                0x0158  /* Host DMA Engine 1 Mode */
 109 #define BA0_DCR1                0x015c  /* Host DMA Engine 1 Command */
 110 #define BA0_DMR2                0x0160  /* Host DMA Engine 2 Mode */
 111 #define BA0_DCR2                0x0164  /* Host DMA Engine 2 Command */
 112 #define BA0_DMR3                0x0168  /* Host DMA Engine 3 Mode */
 113 #define BA0_DCR3                0x016c  /* Host DMA Engine 3 Command */
 114
 115 #define BA0_DMR_DMA             (1<<29) /* Enable DMA mode */
 116 #define BA0_DMR_POLL            (1<<28) /* Enable poll mode */
 117 #define BA0_DMR_TBC             (1<<25) /* Transfer By Channel */
 118 #define BA0_DMR_CBC             (1<<24) /* Count By Channel (0 = frame resolution) */
 119 #define BA0_DMR_SWAPC           (1<<22) /* Swap Left/Right Channels */
 120 #define BA0_DMR_SIZE20          (1<<20) /* Sample is 20-bit */
 121 #define BA0_DMR_USIGN           (1<<19) /* Unsigned */
 122 #define BA0_DMR_BEND            (1<<18) /* Big Endian */
 123 #define BA0_DMR_MONO            (1<<17) /* Mono */
 124 #define BA0_DMR_SIZE8           (1<<16) /* Sample is 8-bit */
 125 #define BA0_DMR_TYPE_DEMAND     (0<<6)
 126 #define BA0_DMR_TYPE_SINGLE     (1<<6)
 127 #define BA0_DMR_TYPE_BLOCK      (2<<6)
 128 #define BA0_DMR_TYPE_CASCADE    (3<<6)  /* Not supported */
 129 #define BA0_DMR_DEC             (1<<5)  /* Access Increment (0) or Decrement (1) */
 130 #define BA0_DMR_AUTO            (1<<4)  /* Auto-Initialize */
 131 #define BA0_DMR_TR_VERIFY       (0<<2)  /* Verify Transfer */
 132 #define BA0_DMR_TR_WRITE        (1<<2)  /* Write Transfer */
 133 #define BA0_DMR_TR_READ         (2<<2)  /* Read Transfer */
 134
 135 #define BA0_DCR_HTCIE           (1<<17) /* Half Terminal Count Interrupt */
 136 #define BA0_DCR_TCIE            (1<<16) /* Terminal Count Interrupt */
 137 #define BA0_DCR_MSK             (1<<0)  /* DMA Mask bit */
 138
 139 #define BA0_FCR0                0x0180  /* FIFO Control 0 */
 140 #define BA0_FCR1                0x0184  /* FIFO Control 1 */
 141 #define BA0_FCR2                0x0188  /* FIFO Control 2 */
 142 #define BA0_FCR3                0x018c  /* FIFO Control 3 */
 143
 144 #define BA0_FCR_FEN             (1<<31) /* FIFO Enable bit */
 145 #define BA0_FCR_DACZ            (1<<30) /* DAC Zero */
 146 #define BA0_FCR_PSH             (1<<29) /* Previous Sample Hold */
 147 #define BA0_FCR_RS(x)           (((x)&0x1f)<<24) /* Right Slot Mapping */
 148 #define BA0_FCR_LS(x)           (((x)&0x1f)<<16) /* Left Slot Mapping */
 149 #define BA0_FCR_SZ(x)           (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
 150 #define BA0_FCR_OF(x)           (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
 151
 152 #define BA0_FPDR0               0x0190  /* FIFO Polled Data 0 */
 153 #define BA0_FPDR1               0x0194  /* FIFO Polled Data 1 */
 154 #define BA0_FPDR2               0x0198  /* FIFO Polled Data 2 */
 155 #define BA0_FPDR3               0x019c  /* FIFO Polled Data 3 */
 156
 157 #define BA0_FCHS                0x020c  /* FIFO Channel Status */
 158 #define BA0_FCHS_RCO(x)         (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
 159 #define BA0_FCHS_LCO(x)         (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
 160 #define BA0_FCHS_MRP(x)         (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
 161 #define BA0_FCHS_FE(x)          (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
 162 #define BA0_FCHS_FF(x)          (1<<(3+(((x)&3)<<3))) /* FIFO Full */
 163 #define BA0_FCHS_IOR(x)         (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
 164 #define BA0_FCHS_RCI(x)         (1<<(1+(((x)&3)<<3))) /* Right Channel In */
 165 #define BA0_FCHS_LCI(x)         (1<<(0+(((x)&3)<<3))) /* Left Channel In */
 166
 167 #define BA0_FSIC0               0x0210  /* FIFO Status and Interrupt Control 0 */
 168 #define BA0_FSIC1               0x0214  /* FIFO Status and Interrupt Control 1 */
 169 #define BA0_FSIC2               0x0218  /* FIFO Status and Interrupt Control 2 */
 170 #define BA0_FSIC3               0x021c  /* FIFO Status and Interrupt Control 3 */
 171
 172 #define BA0_FSIC_FIC(x)         (((x)&0x7f)<<24) /* FIFO Interrupt Count */
 173 #define BA0_FSIC_FORIE          (1<<23) /* FIFO OverRun Interrupt Enable */
 174 #define BA0_FSIC_FURIE          (1<<22) /* FIFO UnderRun Interrupt Enable */
 175 #define BA0_FSIC_FSCIE          (1<<16) /* FIFO Sample Count Interrupt Enable */
 176 #define BA0_FSIC_FSC(x)         (((x)&0x7f)<<8) /* FIFO Sample Count */
 177 #define BA0_FSIC_FOR            (1<<7)  /* FIFO OverRun */
 178 #define BA0_FSIC_FUR            (1<<6)  /* FIFO UnderRun */
 179 #define BA0_FSIC_FSCR           (1<<0)  /* FIFO Sample Count Reached */
 180
 181 #define BA0_PMCS                0x0344  /* Power Management Control/Status */
 182 #define BA0_CWPR                0x03e0  /* Configuration Write Protect */
 183
 184 #define BA0_EPPMC               0x03e4  /* Extended PCI Power Management Control */
 185 #define BA0_EPPMC_FPDN          (1<<14) /* Full Power DowN */
 186
 187 #define BA0_GPIOR               0x03e8  /* GPIO Pin Interface Register */
 188
 189 #define BA0_SPMC                0x03ec  /* Serial Port Power Management Control (& ASDIN2 enable) */
 190 #define BA0_SPMC_GIPPEN         (1<<15) /* GP INT Primary PME# Enable */
 191 #define BA0_SPMC_GISPEN         (1<<14) /* GP INT Secondary PME# Enable */
 192 #define BA0_SPMC_EESPD          (1<<9)  /* EEPROM Serial Port Disable */
 193 #define BA0_SPMC_ASDI2E         (1<<8)  /* ASDIN2 Enable */
 194 #define BA0_SPMC_ASDO           (1<<7)  /* Asynchronous ASDOUT Assertion */
 195 #define BA0_SPMC_WUP2           (1<<3)  /* Wakeup for Secondary Input */
 196 #define BA0_SPMC_WUP1           (1<<2)  /* Wakeup for Primary Input */
 197 #define BA0_SPMC_ASYNC          (1<<1)  /* Asynchronous ASYNC Assertion */
 198 #define BA0_SPMC_RSTN           (1<<0)  /* Reset Not! */
 199
 200 #define BA0_CFLR                0x03f0  /* Configuration Load Register (EEPROM or BIOS) */
 201 #define BA0_CFLR_DEFAULT        0x00000001 /* CFLR must be in AC97 link mode */
 202 #define BA0_IISR                0x03f4  /* ISA Interrupt Select */
 203 #define BA0_TMS                 0x03f8  /* Test Register */
 204 #define BA0_SSVID               0x03fc  /* Subsystem ID register */
 205
 206 #define BA0_CLKCR1              0x0400  /* Clock Control Register 1 */
 207 #define BA0_CLKCR1_CLKON        (1<<25) /* Read Only */
 208 #define BA0_CLKCR1_DLLRDY       (1<<24) /* DLL Ready */
 209 #define BA0_CLKCR1_DLLOS        (1<<6)  /* DLL Output Select */
 210 #define BA0_CLKCR1_SWCE         (1<<5)  /* Clock Enable */
 211 #define BA0_CLKCR1_DLLP         (1<<4)  /* DLL PowerUp */
 212 #define BA0_CLKCR1_DLLSS        (((x)&3)<<3) /* DLL Source Select */
 213
 214 #define BA0_FRR                 0x0410  /* Feature Reporting Register */
 215 #define BA0_SLT12O              0x041c  /* Slot 12 GPIO Output Register for AC-Link */
 216
 217 #define BA0_SERMC               0x0420  /* Serial Port Master Control */
 218 #define BA0_SERMC_FCRN          (1<<27) /* Force Codec Ready Not */
 219 #define BA0_SERMC_ODSEN2        (1<<25) /* On-Demand Support Enable ASDIN2 */
 220 #define BA0_SERMC_ODSEN1        (1<<24) /* On-Demand Support Enable ASDIN1 */
 221 #define BA0_SERMC_SXLB          (1<<21) /* ASDIN2 to ASDOUT Loopback */
 222 #define BA0_SERMC_SLB           (1<<20) /* ASDOUT to ASDIN2 Loopback */
 223 #define BA0_SERMC_LOVF          (1<<19) /* Loopback Output Valid Frame bit */
 224 #define BA0_SERMC_TCID(x)       (((x)&3)<<16) /* Target Secondary Codec ID */
 225 #define BA0_SERMC_PXLB          (5<<1)  /* Primary Port External Loopback */
 226 #define BA0_SERMC_PLB           (4<<1)  /* Primary Port Internal Loopback */
 227 #define BA0_SERMC_PTC           (7<<1)  /* Port Timing Configuration */
 228 #define BA0_SERMC_PTC_AC97      (1<<1)  /* AC97 mode */
 229 #define BA0_SERMC_MSPE          (1<<0)  /* Master Serial Port Enable */
 230
 231 #define BA0_SERC1               0x0428  /* Serial Port Configuration 1 */
 232 #define BA0_SERC1_SO1F(x)       (((x)&7)>>1) /* Primary Output Port Format */
 233 #define BA0_SERC1_AC97          (1<<1)
 234 #define BA0_SERC1_SO1EN         (1<<0)  /* Primary Output Port Enable */
 235
 236 #define BA0_SERC2               0x042c  /* Serial Port Configuration 2 */
 237 #define BA0_SERC2_SI1F(x)       (((x)&7)>>1) /* Primary Input Port Format */
 238 #define BA0_SERC2_AC97          (1<<1)
 239 #define BA0_SERC2_SI1EN         (1<<0)  /* Primary Input Port Enable */
 240
 241 #define BA0_SLT12M              0x045c  /* Slot 12 Monitor Register for Primary AC-Link */
 242
 243 #define BA0_ACCTL               0x0460  /* AC'97 Control */
 244 #define BA0_ACCTL_TC            (1<<6)  /* Target Codec */
 245 #define BA0_ACCTL_CRW           (1<<4)  /* 0=Write, 1=Read Command */
 246 #define BA0_ACCTL_DCV           (1<<3)  /* Dynamic Command Valid */
 247 #define BA0_ACCTL_VFRM          (1<<2)  /* Valid Frame */
 248 #define BA0_ACCTL_ESYN          (1<<1)  /* Enable Sync */
 249
 250 #define BA0_ACSTS               0x0464  /* AC'97 Status */
 251 #define BA0_ACSTS_VSTS          (1<<1)  /* Valid Status */
 252 #define BA0_ACSTS_CRDY          (1<<0)  /* Codec Ready */
 253
 254 #define BA0_ACOSV               0x0468  /* AC'97 Output Slot Valid */
 255 #define BA0_ACOSV_SLV(x)        (1<<((x)-3))
 256
 257 #define BA0_ACCAD               0x046c  /* AC'97 Command Address */
 258 #define BA0_ACCDA               0x0470  /* AC'97 Command Data */
 259
 260 #define BA0_ACISV               0x0474  /* AC'97 Input Slot Valid */
 261 #define BA0_ACISV_SLV(x)        (1<<((x)-3))
 262
 263 #define BA0_ACSAD               0x0478  /* AC'97 Status Address */
 264 #define BA0_ACSDA               0x047c  /* AC'97 Status Data */
 265 #define BA0_JSPT                0x0480  /* Joystick poll/trigger */
 266 #define BA0_JSCTL               0x0484  /* Joystick control */
 267 #define BA0_JSC1                0x0488  /* Joystick control */
 268 #define BA0_JSC2                0x048c  /* Joystick control */
 269 #define BA0_JSIO                0x04a0
 270
 271 #define BA0_MIDCR               0x0490  /* MIDI Control */
 272 #define BA0_MIDCR_MRST          (1<<5)  /* Reset MIDI Interface */
 273 #define BA0_MIDCR_MLB           (1<<4)  /* MIDI Loop Back Enable */
 274 #define BA0_MIDCR_TIE           (1<<3)  /* MIDI Transmuit Interrupt Enable */
 275 #define BA0_MIDCR_RIE           (1<<2)  /* MIDI Receive Interrupt Enable */
 276 #define BA0_MIDCR_RXE           (1<<1)  /* MIDI Receive Enable */
 277 #define BA0_MIDCR_TXE           (1<<0)  /* MIDI Transmit Enable */
 278
 279 #define BA0_MIDCMD              0x0494  /* MIDI Command (wo) */
 280
 281 #define BA0_MIDSR               0x0494  /* MIDI Status (ro) */
 282 #define BA0_MIDSR_RDA           (1<<15) /* Sticky bit (RBE 1->0) */
 283 #define BA0_MIDSR_TBE           (1<<14) /* Sticky bit (TBF 0->1) */
 284 #define BA0_MIDSR_RBE           (1<<7)  /* Receive Buffer Empty */
 285 #define BA0_MIDSR_TBF           (1<<6)  /* Transmit Buffer Full */
 286
 287 #define BA0_MIDWP               0x0498  /* MIDI Write */
 288 #define BA0_MIDRP               0x049c  /* MIDI Read (ro) */
 289
 290 #define BA0_AODSD1              0x04a8  /* AC'97 On-Demand Slot Disable for primary link (ro) */
 291 #define BA0_AODSD1_NDS(x)       (1<<((x)-3))
 292
 293 #define BA0_AODSD2              0x04ac  /* AC'97 On-Demand Slot Disable for secondary link (ro) */
 294 #define BA0_AODSD2_NDS(x)       (1<<((x)-3))
 295
 296 #define BA0_CFGI                0x04b0  /* Configure Interface (EEPROM interface) */
 297 #define BA0_SLT12M2             0x04dc  /* Slot 12 Monitor Register 2 for secondary AC-link */
 298 #define BA0_ACSTS2              0x04e4  /* AC'97 Status Register 2 */
 299 #define BA0_ACISV2              0x04f4  /* AC'97 Input Slot Valid Register 2 */
 300 #define BA0_ACSAD2              0x04f8  /* AC'97 Status Address Register 2 */
 301 #define BA0_ACSDA2              0x04fc  /* AC'97 Status Data Register 2 */
 302 #define BA0_FMSR                0x0730  /* FM Synthesis Status (ro) */
 303 #define BA0_B0AP                0x0730  /* FM Bank 0 Address Port (wo) */
 304 #define BA0_FMDP                0x0734  /* FM Data Port */
 305 #define BA0_B1AP                0x0738  /* FM Bank 1 Address Port */
 306 #define BA0_B1DP                0x073c  /* FM Bank 1 Data Port */
 307
 308 #define BA0_SSPM                0x0740  /* Sound System Power Management */
 309 #define BA0_SSPM_MIXEN          (1<<6)  /* Playback SRC + FM/Wavetable MIX */
 310 #define BA0_SSPM_CSRCEN         (1<<5)  /* Capture Sample Rate Converter Enable */
 311 #define BA0_SSPM_PSRCEN         (1<<4)  /* Playback Sample Rate Converter Enable */
 312 #define BA0_SSPM_JSEN           (1<<3)  /* Joystick Enable */
 313 #define BA0_SSPM_ACLEN          (1<<2)  /* Serial Port Engine and AC-Link Enable */
 314 #define BA0_SSPM_FMEN           (1<<1)  /* FM Synthesis Block Enable */
 315
 316 #define BA0_DACSR               0x0744  /* DAC Sample Rate - Playback SRC */
 317 #define BA0_ADCSR               0x0748  /* ADC Sample Rate - Capture SRC */
 318
 319 #define BA0_SSCR                0x074c  /* Sound System Control Register */
 320 #define BA0_SSCR_HVS1           (1<<23) /* Hardwave Volume Step (0=1,1=2) */
 321 #define BA0_SSCR_MVCS           (1<<19) /* Master Volume Codec Select */
 322 #define BA0_SSCR_MVLD           (1<<18) /* Master Volume Line Out Disable */
 323 #define BA0_SSCR_MVAD           (1<<17) /* Master Volume Alternate Out Disable */
 324 #define BA0_SSCR_MVMD           (1<<16) /* Master Volume Mono Out Disable */
 325 #define BA0_SSCR_XLPSRC         (1<<8)  /* External SRC Loopback Mode */
 326 #define BA0_SSCR_LPSRC          (1<<7)  /* SRC Loopback Mode */
 327 #define BA0_SSCR_CDTX           (1<<5)  /* CD Transfer Data */
 328 #define BA0_SSCR_HVC            (1<<3)  /* Harware Volume Control Enable */
 329
 330 #define BA0_FMLVC               0x0754  /* FM Synthesis Left Volume Control */
 331 #define BA0_FMRVC               0x0758  /* FM Synthesis Right Volume Control */
 332 #define BA0_SRCSA               0x075c  /* SRC Slot Assignments */
 333 #define BA0_PPLVC               0x0760  /* PCM Playback Left Volume Control */
 334 #define BA0_PPRVC               0x0764  /* PCM Playback Right Volume Control */
 335 #define BA0_PASR                0x0768  /* playback sample rate */
 336 #define BA0_CASR                0x076C  /* capture sample rate */
 337
 338 /* Source Slot Numbers - Playback */
 339 #define SRCSLOT_LEFT_PCM_PLAYBACK               0
 340 #define SRCSLOT_RIGHT_PCM_PLAYBACK              1
 341 #define SRCSLOT_PHONE_LINE_1_DAC                2
 342 #define SRCSLOT_CENTER_PCM_PLAYBACK             3
 343 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK      4
 344 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK     5
 345 #define SRCSLOT_LFE_PCM_PLAYBACK                6
 346 #define SRCSLOT_PHONE_LINE_2_DAC                7
 347 #define SRCSLOT_HEADSET_DAC                     8
 348 #define SRCSLOT_LEFT_WT                         29  /* invalid for BA0_SRCSA */
 349 #define SRCSLOT_RIGHT_WT                        30  /* invalid for BA0_SRCSA */
 350
 351 /* Source Slot Numbers - Capture */
 352 #define SRCSLOT_LEFT_PCM_RECORD                 10
 353 #define SRCSLOT_RIGHT_PCM_RECORD                11
 354 #define SRCSLOT_PHONE_LINE_1_ADC                12
 355 #define SRCSLOT_MIC_ADC                         13
 356 #define SRCSLOT_PHONE_LINE_2_ADC                17
 357 #define SRCSLOT_HEADSET_ADC                     18
 358 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD       20
 359 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD      21
 360 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC      22
 361 #define SRCSLOT_SECONDARY_MIC_ADC               23
 362 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC      27
 363 #define SRCSLOT_SECONDARY_HEADSET_ADC           28
 364
 365 /* Source Slot Numbers - Others */
 366 #define SRCSLOT_POWER_DOWN                      31
 367
 368 /* MIDI modes */
 369 #define CS4281_MODE_OUTPUT              (1<<0)
 370 #define CS4281_MODE_INPUT               (1<<1)
 371
 372 /* joystick bits */
 373 /* Bits for JSPT */
 374 #define JSPT_CAX                                0x00000001
 375 #define JSPT_CAY                                0x00000002
 376 #define JSPT_CBX                                0x00000004
 377 #define JSPT_CBY                                0x00000008
 378 #define JSPT_BA1                                0x00000010
 379 #define JSPT_BA2                                0x00000020
 380 #define JSPT_BB1                                0x00000040
 381 #define JSPT_BB2                                0x00000080
 382
 383 /* Bits for JSCTL */
 384 #define JSCTL_SP_MASK                           0x00000003
 385 #define JSCTL_SP_SLOW                           0x00000000
 386 #define JSCTL_SP_MEDIUM_SLOW                    0x00000001
 387 #define JSCTL_SP_MEDIUM_FAST                    0x00000002
 388 #define JSCTL_SP_FAST                           0x00000003
 389 #define JSCTL_ARE                               0x00000004
 390
 391 /* Data register pairs masks */
 392 #define JSC1_Y1V_MASK                           0x0000FFFF
 393 #define JSC1_X1V_MASK                           0xFFFF0000
 394 #define JSC1_Y1V_SHIFT                          0
 395 #define JSC1_X1V_SHIFT                          16
 396 #define JSC2_Y2V_MASK                           0x0000FFFF
 397 #define JSC2_X2V_MASK                           0xFFFF0000
 398 #define JSC2_Y2V_SHIFT                          0
 399 #define JSC2_X2V_SHIFT                          16
 400
 401 /* JS GPIO */
 402 #define JSIO_DAX                                0x00000001
 403 #define JSIO_DAY                                0x00000002
 404 #define JSIO_DBX                                0x00000004
 405 #define JSIO_DBY                                0x00000008
 406 #define JSIO_AXOE                               0x00000010
 407 #define JSIO_AYOE                               0x00000020
 408 #define JSIO_BXOE                               0x00000040
 409 #define JSIO_BYOE                               0x00000080
 410
 411 /*
 412  *
 413  */
 414
 415 struct cs4281_dma {
 416         struct snd_pcm_substream *substream;
 417         unsigned int regDBA;            /* offset to DBA register */
 418         unsigned int regDCA;            /* offset to DCA register */
 419         unsigned int regDBC;            /* offset to DBC register */
 420         unsigned int regDCC;            /* offset to DCC register */
 421         unsigned int regDMR;            /* offset to DMR register */
 422         unsigned int regDCR;            /* offset to DCR register */
 423         unsigned int regHDSR;           /* offset to HDSR register */
 424         unsigned int regFCR;            /* offset to FCR register */
 425         unsigned int regFSIC;           /* offset to FSIC register */
 426         unsigned int valDMR;            /* DMA mode */
 427         unsigned int valDCR;            /* DMA command */
 428         unsigned int valFCR;            /* FIFO control */
 429         unsigned int fifo_offset;       /* FIFO offset within BA1 */
 430         unsigned char left_slot;        /* FIFO left slot */
 431         unsigned char right_slot;       /* FIFO right slot */
 432         int frag;                       /* period number */
 433 };
 434
 435 #define SUSPEND_REGISTERS       20
 436
 437 struct cs4281 {
 438         int irq;
 439
 440         void __iomem *ba0;              /* virtual (accessible) address */
 441         void __iomem *ba1;              /* virtual (accessible) address */
 442         unsigned long ba0_addr;
 443         unsigned long ba1_addr;
 444
 445         int dual_codec;
 446
 447         struct snd_ac97_bus *ac97_bus;
 448         struct snd_ac97 *ac97;
 449         struct snd_ac97 *ac97_secondary;
 450
 451         struct pci_dev *pci;
 452         struct snd_card *card;
 453         struct snd_pcm *pcm;
 454         struct snd_rawmidi *rmidi;
 455         struct snd_rawmidi_substream *midi_input;
 456         struct snd_rawmidi_substream *midi_output;
 457
 458         struct cs4281_dma dma[4];
 459
 460         unsigned char src_left_play_slot;
 461         unsigned char src_right_play_slot;
 462         unsigned char src_left_rec_slot;
 463         unsigned char src_right_rec_slot;
 464
 465         unsigned int spurious_dhtc_irq;
 466         unsigned int spurious_dtc_irq;
 467
 468         spinlock_t reg_lock;
 469         unsigned int midcr;
 470         unsigned int uartm;
 471
 472         struct gameport *gameport;
 473
 474 #ifdef CONFIG_PM_SLEEP
 475         u32 suspend_regs[SUSPEND_REGISTERS];
 476 #endif
 477
 478 };
 479
 480 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
 481
 482 static const struct pci_device_id snd_cs4281_ids[] = {
 483         { PCI_VDEVICE(CIRRUS, 0x6005), 0, },    /* CS4281 */
 484         { 0, }
 485 };
 486
 487 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
 488
 489 /*
 490  *  constants
 491  */
 492
 493 #define CS4281_FIFO_SIZE        32
 494
 495 /*
 496  *  common I/O routines
 497  */
 498
 499 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
 500                                       unsigned int val)
 501 {
 502         writel(val, chip->ba0 + offset);
 503 }
 504
 505 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
 506 {
 507         return readl(chip->ba0 + offset);
 508 }
 509
 510 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
 511                                   unsigned short reg, unsigned short val)
 512 {
 513         /*
 514          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 515          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 516          *  3. Write ACCTL = Control Register = 460h for initiating the write
 517          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 518          *  5. if DCV not cleared, break and return error
 519          */
 520         struct cs4281 *chip = ac97->private_data;
 521         int count;
 522
 523         /*
 524          *  Setup the AC97 control registers on the CS461x to send the
 525          *  appropriate command to the AC97 to perform the read.
 526          *  ACCAD = Command Address Register = 46Ch
 527          *  ACCDA = Command Data Register = 470h
 528          *  ACCTL = Control Register = 460h
 529          *  set DCV - will clear when process completed
 530          *  reset CRW - Write command
 531          *  set VFRM - valid frame enabled
 532          *  set ESYN - ASYNC generation enabled
 533          *  set RSTN - ARST# inactive, AC97 codec not reset
 534          */
 535         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 536         snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
 537         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
 538                                             BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
 539         for (count = 0; count < 2000; count++) {
 540                 /*
 541                  *  First, we want to wait for a short time.
 542                  */
 543                 udelay(10);
 544                 /*
 545                  *  Now, check to see if the write has completed.
 546                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 547                  */
 548                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
 549                         return;
 550                 }
 551         }
 552         dev_err(chip->card->dev,
 553                 "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
 554 }
 555
 556 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
 557                                            unsigned short reg)
 558 {
 559         struct cs4281 *chip = ac97->private_data;
 560         int count;
 561         unsigned short result;
 562         // FIXME: volatile is necessary in the following due to a bug of
 563         // some gcc versions
 564         volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
 565
 566         /*
 567          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 568          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 569          *  3. Write ACCTL = Control Register = 460h for initiating the write
 570          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 571          *  5. if DCV not cleared, break and return error
 572          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 573          */
 574
 575         snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 576
 577         /*
 578          *  Setup the AC97 control registers on the CS461x to send the
 579          *  appropriate command to the AC97 to perform the read.
 580          *  ACCAD = Command Address Register = 46Ch
 581          *  ACCDA = Command Data Register = 470h
 582          *  ACCTL = Control Register = 460h
 583          *  set DCV - will clear when process completed
 584          *  set CRW - Read command
 585          *  set VFRM - valid frame enabled
 586          *  set ESYN - ASYNC generation enabled
 587          *  set RSTN - ARST# inactive, AC97 codec not reset
 588          */
 589
 590         snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
 591         snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
 592         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
 593                                             BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
 594                            (ac97_num ? BA0_ACCTL_TC : 0));
 595
 596
 597         /*
 598          *  Wait for the read to occur.
 599          */
 600         for (count = 0; count < 500; count++) {
 601                 /*
 602                  *  First, we want to wait for a short time.
 603                  */
 604                 udelay(10);
 605                 /*
 606                  *  Now, check to see if the read has completed.
 607                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 608                  */
 609                 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
 610                         goto __ok1;
 611         }
 612
 613         dev_err(chip->card->dev,
 614                 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 615         result = 0xffff;
 616         goto __end;
 617
 618       __ok1:
 619         /*
 620          *  Wait for the valid status bit to go active.
 621          */
 622         for (count = 0; count < 100; count++) {
 623                 /*
 624                  *  Read the AC97 status register.
 625                  *  ACSTS = Status Register = 464h
 626                  *  VSTS - Valid Status
 627                  */
 628                 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
 629                         goto __ok2;
 630                 udelay(10);
 631         }
 632
 633         dev_err(chip->card->dev,
 634                 "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
 635         result = 0xffff;
 636         goto __end;
 637
 638       __ok2:
 639         /*
 640          *  Read the data returned from the AC97 register.
 641          *  ACSDA = Status Data Register = 474h
 642          */
 643         result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
 644
 645       __end:
 646         return result;
 647 }
 648
 649 /*
 650  *  PCM part
 651  */
 652
 653 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
 654 {
 655         struct cs4281_dma *dma = substream->runtime->private_data;
 656         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 657
 658         spin_lock(&chip->reg_lock);
 659         switch (cmd) {
 660         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 661                 dma->valDCR |= BA0_DCR_MSK;
 662                 dma->valFCR |= BA0_FCR_FEN;
 663                 break;
 664         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 665                 dma->valDCR &= ~BA0_DCR_MSK;
 666                 dma->valFCR &= ~BA0_FCR_FEN;
 667                 break;
 668         case SNDRV_PCM_TRIGGER_START:
 669         case SNDRV_PCM_TRIGGER_RESUME:
 670                 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
 671                 dma->valDMR |= BA0_DMR_DMA;
 672                 dma->valDCR &= ~BA0_DCR_MSK;
 673                 dma->valFCR |= BA0_FCR_FEN;
 674                 break;
 675         case SNDRV_PCM_TRIGGER_STOP:
 676         case SNDRV_PCM_TRIGGER_SUSPEND:
 677                 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
 678                 dma->valDCR |= BA0_DCR_MSK;
 679                 dma->valFCR &= ~BA0_FCR_FEN;
 680                 /* Leave wave playback FIFO enabled for FM */
 681                 if (dma->regFCR != BA0_FCR0)
 682                         dma->valFCR &= ~BA0_FCR_FEN;
 683                 break;
 684         default:
 685                 spin_unlock(&chip->reg_lock);
 686                 return -EINVAL;
 687         }
 688         snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
 689         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
 690         snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
 691         spin_unlock(&chip->reg_lock);
 692         return 0;
 693 }
 694
 695 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
 696 {
 697         unsigned int val;
 698
 699         if (real_rate)
 700                 *real_rate = rate;
 701         /* special "hardcoded" rates */
 702         switch (rate) {
 703         case 8000:      return 5;
 704         case 11025:     return 4;
 705         case 16000:     return 3;
 706         case 22050:     return 2;
 707         case 44100:     return 1;
 708         case 48000:     return 0;
 709         default:
 710                 break;
 711         }
 712         val = 1536000 / rate;
 713         if (real_rate)
 714                 *real_rate = 1536000 / val;
 715         return val;
 716 }
 717
 718 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
 719                             struct snd_pcm_runtime *runtime,
 720                             int capture, int src)
 721 {
 722         int rec_mono;
 723
 724         dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
 725                       (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
 726         if (runtime->channels == 1)
 727                 dma->valDMR |= BA0_DMR_MONO;
 728         if (snd_pcm_format_unsigned(runtime->format) > 0)
 729                 dma->valDMR |= BA0_DMR_USIGN;
 730         if (snd_pcm_format_big_endian(runtime->format) > 0)
 731                 dma->valDMR |= BA0_DMR_BEND;
 732         switch (snd_pcm_format_width(runtime->format)) {
 733         case 8: dma->valDMR |= BA0_DMR_SIZE8;
 734                 if (runtime->channels == 1)
 735                         dma->valDMR |= BA0_DMR_SWAPC;
 736                 break;
 737         case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
 738         }
 739         dma->frag = 0;  /* for workaround */
 740         dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
 741         if (runtime->buffer_size != runtime->period_size)
 742                 dma->valDCR |= BA0_DCR_HTCIE;
 743         /* Initialize DMA */
 744         snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
 745         snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
 746         rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
 747         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
 748                                             (chip->src_right_play_slot << 8) |
 749                                             (chip->src_left_rec_slot << 16) |
 750                                             ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
 751         if (!src)
 752                 goto __skip_src;
 753         if (!capture) {
 754                 if (dma->left_slot == chip->src_left_play_slot) {
 755                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 756                         snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
 757                         snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
 758                 }
 759         } else {
 760                 if (dma->left_slot == chip->src_left_rec_slot) {
 761                         unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
 762                         snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
 763                         snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
 764                 }
 765         }
 766       __skip_src:
 767         /* Deactivate wave playback FIFO before changing slot assignments */
 768         if (dma->regFCR == BA0_FCR0)
 769                 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
 770         /* Initialize FIFO */
 771         dma->valFCR = BA0_FCR_LS(dma->left_slot) |
 772                       BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
 773                       BA0_FCR_SZ(CS4281_FIFO_SIZE) |
 774                       BA0_FCR_OF(dma->fifo_offset);
 775         snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
 776         /* Activate FIFO again for FM playback */
 777         if (dma->regFCR == BA0_FCR0)
 778                 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
 779         /* Clear FIFO Status and Interrupt Control Register */
 780         snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
 781 }
 782
 783 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
 784 {
 785         struct snd_pcm_runtime *runtime = substream->runtime;
 786         struct cs4281_dma *dma = runtime->private_data;
 787         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 788
 789         spin_lock_irq(&chip->reg_lock);
 790         snd_cs4281_mode(chip, dma, runtime, 0, 1);
 791         spin_unlock_irq(&chip->reg_lock);
 792         return 0;
 793 }
 794
 795 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
 796 {
 797         struct snd_pcm_runtime *runtime = substream->runtime;
 798         struct cs4281_dma *dma = runtime->private_data;
 799         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 800
 801         spin_lock_irq(&chip->reg_lock);
 802         snd_cs4281_mode(chip, dma, runtime, 1, 1);
 803         spin_unlock_irq(&chip->reg_lock);
 804         return 0;
 805 }
 806
 807 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
 808 {
 809         struct snd_pcm_runtime *runtime = substream->runtime;
 810         struct cs4281_dma *dma = runtime->private_data;
 811         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 812
 813         /*
 814         dev_dbg(chip->card->dev,
 815                 "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
 816                 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
 817                jiffies);
 818         */
 819         return runtime->buffer_size -
 820                snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
 821 }
 822
 823 static const struct snd_pcm_hardware snd_cs4281_playback =
 824 {
 825         .info =                 SNDRV_PCM_INFO_MMAP |
 826                                 SNDRV_PCM_INFO_INTERLEAVED |
 827                                 SNDRV_PCM_INFO_MMAP_VALID |
 828                                 SNDRV_PCM_INFO_PAUSE |
 829                                 SNDRV_PCM_INFO_RESUME,
 830         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 831                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 832                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 833                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 834                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 835         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 836         .rate_min =             4000,
 837         .rate_max =             48000,
 838         .channels_min =         1,
 839         .channels_max =         2,
 840         .buffer_bytes_max =     (512*1024),
 841         .period_bytes_min =     64,
 842         .period_bytes_max =     (512*1024),
 843         .periods_min =          1,
 844         .periods_max =          2,
 845         .fifo_size =            CS4281_FIFO_SIZE,
 846 };
 847
 848 static const struct snd_pcm_hardware snd_cs4281_capture =
 849 {
 850         .info =                 SNDRV_PCM_INFO_MMAP |
 851                                 SNDRV_PCM_INFO_INTERLEAVED |
 852                                 SNDRV_PCM_INFO_MMAP_VALID |
 853                                 SNDRV_PCM_INFO_PAUSE |
 854                                 SNDRV_PCM_INFO_RESUME,
 855         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
 856                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
 857                                 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
 858                                 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
 859                                 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
 860         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
 861         .rate_min =             4000,
 862         .rate_max =             48000,
 863         .channels_min =         1,
 864         .channels_max =         2,
 865         .buffer_bytes_max =     (512*1024),
 866         .period_bytes_min =     64,
 867         .period_bytes_max =     (512*1024),
 868         .periods_min =          1,
 869         .periods_max =          2,
 870         .fifo_size =            CS4281_FIFO_SIZE,
 871 };
 872
 873 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
 874 {
 875         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 876         struct snd_pcm_runtime *runtime = substream->runtime;
 877         struct cs4281_dma *dma;
 878
 879         dma = &chip->dma[0];
 880         dma->substream = substream;
 881         dma->left_slot = 0;
 882         dma->right_slot = 1;
 883         runtime->private_data = dma;
 884         runtime->hw = snd_cs4281_playback;
 885         /* should be detected from the AC'97 layer, but it seems
 886            that although CS4297A rev B reports 18-bit ADC resolution,
 887            samples are 20-bit */
 888         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 889         return 0;
 890 }
 891
 892 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
 893 {
 894         struct cs4281 *chip = snd_pcm_substream_chip(substream);
 895         struct snd_pcm_runtime *runtime = substream->runtime;
 896         struct cs4281_dma *dma;
 897
 898         dma = &chip->dma[1];
 899         dma->substream = substream;
 900         dma->left_slot = 10;
 901         dma->right_slot = 11;
 902         runtime->private_data = dma;
 903         runtime->hw = snd_cs4281_capture;
 904         /* should be detected from the AC'97 layer, but it seems
 905            that although CS4297A rev B reports 18-bit ADC resolution,
 906            samples are 20-bit */
 907         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
 908         return 0;
 909 }
 910
 911 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
 912 {
 913         struct cs4281_dma *dma = substream->runtime->private_data;
 914
 915         dma->substream = NULL;
 916         return 0;
 917 }
 918
 919 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
 920 {
 921         struct cs4281_dma *dma = substream->runtime->private_data;
 922
 923         dma->substream = NULL;
 924         return 0;
 925 }
 926
 927 static const struct snd_pcm_ops snd_cs4281_playback_ops = {
 928         .open =         snd_cs4281_playback_open,
 929         .close =        snd_cs4281_playback_close,
 930         .prepare =      snd_cs4281_playback_prepare,
 931         .trigger =      snd_cs4281_trigger,
 932         .pointer =      snd_cs4281_pointer,
 933 };
 934
 935 static const struct snd_pcm_ops snd_cs4281_capture_ops = {
 936         .open =         snd_cs4281_capture_open,
 937         .close =        snd_cs4281_capture_close,
 938         .prepare =      snd_cs4281_capture_prepare,
 939         .trigger =      snd_cs4281_trigger,
 940         .pointer =      snd_cs4281_pointer,
 941 };
 942
 943 static int snd_cs4281_pcm(struct cs4281 *chip, int device)
 944 {
 945         struct snd_pcm *pcm;
 946         int err;
 947
 948         err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
 949         if (err < 0)
 950                 return err;
 951
 952         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
 953         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
 954
 955         pcm->private_data = chip;
 956         pcm->info_flags = 0;
 957         strcpy(pcm->name, "CS4281");
 958         chip->pcm = pcm;
 959
 960         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
 961                                        64*1024, 512*1024);
 962
 963         return 0;
 964 }
 965
 966 /*
 967  *  Mixer section
 968  */
 969
 970 #define CS_VOL_MASK     0x1f
 971
 972 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
 973                                   struct snd_ctl_elem_info *uinfo)
 974 {
 975         uinfo->type              = SNDRV_CTL_ELEM_TYPE_INTEGER;
 976         uinfo->count             = 2;
 977         uinfo->value.integer.min = 0;
 978         uinfo->value.integer.max = CS_VOL_MASK;
 979         return 0;
 980 }
 981
 982 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
 983                                  struct snd_ctl_elem_value *ucontrol)
 984 {
 985         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
 986         int regL = (kcontrol->private_value >> 16) & 0xffff;
 987         int regR = kcontrol->private_value & 0xffff;
 988         int volL, volR;
 989
 990         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
 991         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
 992
 993         ucontrol->value.integer.value[0] = volL;
 994         ucontrol->value.integer.value[1] = volR;
 995         return 0;
 996 }
 997
 998 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
 999                                  struct snd_ctl_elem_value *ucontrol)
1000 {
1001         struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1002         int change = 0;
1003         int regL = (kcontrol->private_value >> 16) & 0xffff;
1004         int regR = kcontrol->private_value & 0xffff;
1005         int volL, volR;
1006
1007         volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1008         volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1009
1010         if (ucontrol->value.integer.value[0] != volL) {
1011                 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1012                 snd_cs4281_pokeBA0(chip, regL, volL);
1013                 change = 1;
1014         }
1015         if (ucontrol->value.integer.value[1] != volR) {
1016                 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1017                 snd_cs4281_pokeBA0(chip, regR, volR);
1018                 change = 1;
1019         }
1020         return change;
1021 }
1022
1023 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1024
1025 static const struct snd_kcontrol_new snd_cs4281_fm_vol =
1026 {
1027         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1028         .name = "Synth Playback Volume",
1029         .info = snd_cs4281_info_volume,
1030         .get = snd_cs4281_get_volume,
1031         .put = snd_cs4281_put_volume,
1032         .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1033         .tlv = { .p = db_scale_dsp },
1034 };
1035
1036 static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
1037 {
1038         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1039         .name = "PCM Stream Playback Volume",
1040         .info = snd_cs4281_info_volume,
1041         .get = snd_cs4281_get_volume,
1042         .put = snd_cs4281_put_volume,
1043         .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1044         .tlv = { .p = db_scale_dsp },
1045 };
1046
1047 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1048 {
1049         struct cs4281 *chip = bus->private_data;
1050         chip->ac97_bus = NULL;
1051 }
1052
1053 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1054 {
1055         struct cs4281 *chip = ac97->private_data;
1056         if (ac97->num)
1057                 chip->ac97_secondary = NULL;
1058         else
1059                 chip->ac97 = NULL;
1060 }
1061
1062 static int snd_cs4281_mixer(struct cs4281 *chip)
1063 {
1064         struct snd_card *card = chip->card;
1065         struct snd_ac97_template ac97;
1066         int err;
1067         static const struct snd_ac97_bus_ops ops = {
1068                 .write = snd_cs4281_ac97_write,
1069                 .read = snd_cs4281_ac97_read,
1070         };
1071
1072         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1073                 return err;
1074         chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1075
1076         memset(&ac97, 0, sizeof(ac97));
1077         ac97.private_data = chip;
1078         ac97.private_free = snd_cs4281_mixer_free_ac97;
1079         if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1080                 return err;
1081         if (chip->dual_codec) {
1082                 ac97.num = 1;
1083                 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1084                         return err;
1085         }
1086         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1087                 return err;
1088         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1089                 return err;
1090         return 0;
1091 }
1092
1093
1094 /*
1095  * proc interface
1096  */
1097
1098 static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1099                                   struct snd_info_buffer *buffer)
1100 {
1101         struct cs4281 *chip = entry->private_data;
1102
1103         snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1104         snd_iprintf(buffer, "Spurious half IRQs   : %u\n", chip->spurious_dhtc_irq);
1105         snd_iprintf(buffer, "Spurious end IRQs    : %u\n", chip->spurious_dtc_irq);
1106 }
1107
1108 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1109                                    void *file_private_data,
1110                                    struct file *file, char __user *buf,
1111                                    size_t count, loff_t pos)
1112 {
1113         struct cs4281 *chip = entry->private_data;
1114
1115         if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1116                 return -EFAULT;
1117         return count;
1118 }
1119
1120 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1121                                    void *file_private_data,
1122                                    struct file *file, char __user *buf,
1123                                    size_t count, loff_t pos)
1124 {
1125         struct cs4281 *chip = entry->private_data;
1126
1127         if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1128                 return -EFAULT;
1129         return count;
1130 }
1131
1132 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1133         .read = snd_cs4281_BA0_read,
1134 };
1135
1136 static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1137         .read = snd_cs4281_BA1_read,
1138 };
1139
1140 static void snd_cs4281_proc_init(struct cs4281 *chip)
1141 {
1142         struct snd_info_entry *entry;
1143
1144         snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
1145         if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1146                 entry->content = SNDRV_INFO_CONTENT_DATA;
1147                 entry->private_data = chip;
1148                 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1149                 entry->size = CS4281_BA0_SIZE;
1150         }
1151         if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1152                 entry->content = SNDRV_INFO_CONTENT_DATA;
1153                 entry->private_data = chip;
1154                 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1155                 entry->size = CS4281_BA1_SIZE;
1156         }
1157 }
1158
1159 /*
1160  * joystick support
1161  */
1162
1163 #if IS_REACHABLE(CONFIG_GAMEPORT)
1164
1165 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1166 {
1167         struct cs4281 *chip = gameport_get_port_data(gameport);
1168
1169         if (snd_BUG_ON(!chip))
1170                 return;
1171         snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1172 }
1173
1174 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1175 {
1176         struct cs4281 *chip = gameport_get_port_data(gameport);
1177
1178         if (snd_BUG_ON(!chip))
1179                 return 0;
1180         return snd_cs4281_peekBA0(chip, BA0_JSPT);
1181 }
1182
1183 #ifdef COOKED_MODE
1184 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1185                                            int *axes, int *buttons)
1186 {
1187         struct cs4281 *chip = gameport_get_port_data(gameport);
1188         unsigned js1, js2, jst;
1189
1190         if (snd_BUG_ON(!chip))
1191                 return 0;
1192
1193         js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1194         js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1195         jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1196
1197         *buttons = (~jst >> 4) & 0x0F;
1198
1199         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1200         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1201         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1202         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1203
1204         for (jst = 0; jst < 4; ++jst)
1205                 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1206         return 0;
1207 }
1208 #else
1209 #define snd_cs4281_gameport_cooked_read NULL
1210 #endif
1211
1212 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1213 {
1214         switch (mode) {
1215 #ifdef COOKED_MODE
1216         case GAMEPORT_MODE_COOKED:
1217                 return 0;
1218 #endif
1219         case GAMEPORT_MODE_RAW:
1220                 return 0;
1221         default:
1222                 return -1;
1223         }
1224         return 0;
1225 }
1226
1227 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1228 {
1229         struct gameport *gp;
1230
1231         chip->gameport = gp = gameport_allocate_port();
1232         if (!gp) {
1233                 dev_err(chip->card->dev,
1234                         "cannot allocate memory for gameport\n");
1235                 return -ENOMEM;
1236         }
1237
1238         gameport_set_name(gp, "CS4281 Gameport");
1239         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1240         gameport_set_dev_parent(gp, &chip->pci->dev);
1241         gp->open = snd_cs4281_gameport_open;
1242         gp->read = snd_cs4281_gameport_read;
1243         gp->trigger = snd_cs4281_gameport_trigger;
1244         gp->cooked_read = snd_cs4281_gameport_cooked_read;
1245         gameport_set_port_data(gp, chip);
1246
1247         snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1248         snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1249
1250         gameport_register_port(gp);
1251
1252         return 0;
1253 }
1254
1255 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1256 {
1257         if (chip->gameport) {
1258                 gameport_unregister_port(chip->gameport);
1259                 chip->gameport = NULL;
1260         }
1261 }
1262 #else
1263 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1264 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1265 #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
1266
1267 static int snd_cs4281_free(struct cs4281 *chip)
1268 {
1269         snd_cs4281_free_gameport(chip);
1270
1271         /* Mask interrupts */
1272         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1273         /* Stop the DLL Clock logic. */
1274         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1275         /* Sound System Power Management - Turn Everything OFF */
1276         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1277         /* PCI interface - D3 state */
1278         pci_set_power_state(chip->pci, PCI_D3hot);
1279
1280         if (chip->irq >= 0)
1281                 free_irq(chip->irq, chip);
1282         iounmap(chip->ba0);
1283         iounmap(chip->ba1);
1284         pci_release_regions(chip->pci);
1285         pci_disable_device(chip->pci);
1286
1287         kfree(chip);
1288         return 0;
1289 }
1290
1291 static int snd_cs4281_dev_free(struct snd_device *device)
1292 {
1293         struct cs4281 *chip = device->device_data;
1294         return snd_cs4281_free(chip);
1295 }
1296
1297 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1298
1299 static int snd_cs4281_create(struct snd_card *card,
1300                              struct pci_dev *pci,
1301                              struct cs4281 **rchip,
1302                              int dual_codec)
1303 {
1304         struct cs4281 *chip;
1305         unsigned int tmp;
1306         int err;
1307         static const struct snd_device_ops ops = {
1308                 .dev_free =     snd_cs4281_dev_free,
1309         };
1310
1311         *rchip = NULL;
1312         if ((err = pci_enable_device(pci)) < 0)
1313                 return err;
1314         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1315         if (chip == NULL) {
1316                 pci_disable_device(pci);
1317                 return -ENOMEM;
1318         }
1319         spin_lock_init(&chip->reg_lock);
1320         chip->card = card;
1321         chip->pci = pci;
1322         chip->irq = -1;
1323         pci_set_master(pci);
1324         if (dual_codec < 0 || dual_codec > 3) {
1325                 dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
1326                 dual_codec = 0;
1327         }
1328         chip->dual_codec = dual_codec;
1329
1330         if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1331                 kfree(chip);
1332                 pci_disable_device(pci);
1333                 return err;
1334         }
1335         chip->ba0_addr = pci_resource_start(pci, 0);
1336         chip->ba1_addr = pci_resource_start(pci, 1);
1337
1338         chip->ba0 = pci_ioremap_bar(pci, 0);
1339         chip->ba1 = pci_ioremap_bar(pci, 1);
1340         if (!chip->ba0 || !chip->ba1) {
1341                 snd_cs4281_free(chip);
1342                 return -ENOMEM;
1343         }
1344
1345         if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1346                         KBUILD_MODNAME, chip)) {
1347                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1348                 snd_cs4281_free(chip);
1349                 return -ENOMEM;
1350         }
1351         chip->irq = pci->irq;
1352         card->sync_irq = chip->irq;
1353
1354         tmp = snd_cs4281_chip_init(chip);
1355         if (tmp) {
1356                 snd_cs4281_free(chip);
1357                 return tmp;
1358         }
1359
1360         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1361                 snd_cs4281_free(chip);
1362                 return err;
1363         }
1364
1365         snd_cs4281_proc_init(chip);
1366
1367         *rchip = chip;
1368         return 0;
1369 }
1370
1371 static int snd_cs4281_chip_init(struct cs4281 *chip)
1372 {
1373         unsigned int tmp;
1374         unsigned long end_time;
1375         int retry_count = 2;
1376
1377         /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1378         tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1379         if (tmp & BA0_EPPMC_FPDN)
1380                 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1381
1382       __retry:
1383         tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1384         if (tmp != BA0_CFLR_DEFAULT) {
1385                 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1386                 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1387                 if (tmp != BA0_CFLR_DEFAULT) {
1388                         dev_err(chip->card->dev,
1389                                 "CFLR setup failed (0x%x)\n", tmp);
1390                         return -EIO;
1391                 }
1392         }
1393
1394         /* Set the 'Configuration Write Protect' register
1395          * to 4281h.  Allows vendor-defined configuration
1396          * space between 0e4h and 0ffh to be written. */
1397         snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1398
1399         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1400                 dev_err(chip->card->dev,
1401                         "SERC1 AC'97 check failed (0x%x)\n", tmp);
1402                 return -EIO;
1403         }
1404         if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1405                 dev_err(chip->card->dev,
1406                         "SERC2 AC'97 check failed (0x%x)\n", tmp);
1407                 return -EIO;
1408         }
1409
1410         /* Sound System Power Management */
1411         snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1412                                            BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1413                                            BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1414
1415         /* Serial Port Power Management */
1416         /* Blast the clock control register to zero so that the
1417          * PLL starts out in a known state, and blast the master serial
1418          * port control register to zero so that the serial ports also
1419          * start out in a known state. */
1420         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1421         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1422
1423         /* Make ESYN go to zero to turn off
1424          * the Sync pulse on the AC97 link. */
1425         snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1426         udelay(50);
1427
1428         /*  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1429          *  spec) and then drive it high.  This is done for non AC97 modes since
1430          *  there might be logic external to the CS4281 that uses the ARST# line
1431          *  for a reset. */
1432         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1433         udelay(50);
1434         snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1435         msleep(50);
1436
1437         if (chip->dual_codec)
1438                 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1439
1440         /*
1441          *  Set the serial port timing configuration.
1442          */
1443         snd_cs4281_pokeBA0(chip, BA0_SERMC,
1444                            (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1445                            BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1446
1447         /*
1448          *  Start the DLL Clock logic.
1449          */
1450         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1451         msleep(50);
1452         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1453
1454         /*
1455          * Wait for the DLL ready signal from the clock logic.
1456          */
1457         end_time = jiffies + HZ;
1458         do {
1459                 /*
1460                  *  Read the AC97 status register to see if we've seen a CODEC
1461                  *  signal from the AC97 codec.
1462                  */
1463                 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1464                         goto __ok0;
1465                 schedule_timeout_uninterruptible(1);
1466         } while (time_after_eq(end_time, jiffies));
1467
1468         dev_err(chip->card->dev, "DLLRDY not seen\n");
1469         return -EIO;
1470
1471       __ok0:
1472
1473         /*
1474          *  The first thing we do here is to enable sync generation.  As soon
1475          *  as we start receiving bit clock, we'll start producing the SYNC
1476          *  signal.
1477          */
1478         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1479
1480         /*
1481          * Wait for the codec ready signal from the AC97 codec.
1482          */
1483         end_time = jiffies + HZ;
1484         do {
1485                 /*
1486                  *  Read the AC97 status register to see if we've seen a CODEC
1487                  *  signal from the AC97 codec.
1488                  */
1489                 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1490                         goto __ok1;
1491                 schedule_timeout_uninterruptible(1);
1492         } while (time_after_eq(end_time, jiffies));
1493
1494         dev_err(chip->card->dev,
1495                 "never read codec ready from AC'97 (0x%x)\n",
1496                 snd_cs4281_peekBA0(chip, BA0_ACSTS));
1497         return -EIO;
1498
1499       __ok1:
1500         if (chip->dual_codec) {
1501                 end_time = jiffies + HZ;
1502                 do {
1503                         if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1504                                 goto __codec2_ok;
1505                         schedule_timeout_uninterruptible(1);
1506                 } while (time_after_eq(end_time, jiffies));
1507                 dev_info(chip->card->dev,
1508                          "secondary codec doesn't respond. disable it...\n");
1509                 chip->dual_codec = 0;
1510         __codec2_ok: ;
1511         }
1512
1513         /*
1514          *  Assert the valid frame signal so that we can start sending commands
1515          *  to the AC97 codec.
1516          */
1517
1518         snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1519
1520         /*
1521          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
1522          *  the codec is pumping ADC data across the AC-link.
1523          */
1524
1525         end_time = jiffies + HZ;
1526         do {
1527                 /*
1528                  *  Read the input slot valid register and see if input slots 3
1529                  *  4 are valid yet.
1530                  */
1531                 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1532                         goto __ok2;
1533                 schedule_timeout_uninterruptible(1);
1534         } while (time_after_eq(end_time, jiffies));
1535
1536         if (--retry_count > 0)
1537                 goto __retry;
1538         dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
1539         return -EIO;
1540
1541       __ok2:
1542
1543         /*
1544          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
1545          *  commense the transfer of digital audio data to the AC97 codec.
1546          */
1547         snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1548
1549         /*
1550          *  Initialize DMA structures
1551          */
1552         for (tmp = 0; tmp < 4; tmp++) {
1553                 struct cs4281_dma *dma = &chip->dma[tmp];
1554                 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1555                 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1556                 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1557                 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1558                 dma->regDMR = BA0_DMR0 + (tmp * 8);
1559                 dma->regDCR = BA0_DCR0 + (tmp * 8);
1560                 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1561                 dma->regFCR = BA0_FCR0 + (tmp * 4);
1562                 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1563                 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1564                 snd_cs4281_pokeBA0(chip, dma->regFCR,
1565                                    BA0_FCR_LS(31) |
1566                                    BA0_FCR_RS(31) |
1567                                    BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1568                                    BA0_FCR_OF(dma->fifo_offset));
1569         }
1570
1571         chip->src_left_play_slot = 0;   /* AC'97 left PCM playback (3) */
1572         chip->src_right_play_slot = 1;  /* AC'97 right PCM playback (4) */
1573         chip->src_left_rec_slot = 10;   /* AC'97 left PCM record (3) */
1574         chip->src_right_rec_slot = 11;  /* AC'97 right PCM record (4) */
1575
1576         /* Activate wave playback FIFO for FM playback */
1577         chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1578                               BA0_FCR_RS(1) |
1579                               BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1580                               BA0_FCR_OF(chip->dma[0].fifo_offset);
1581         snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1582         snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1583                                             (chip->src_right_play_slot << 8) |
1584                                             (chip->src_left_rec_slot << 16) |
1585                                             (chip->src_right_rec_slot << 24));
1586
1587         /* Initialize digital volume */
1588         snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1589         snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1590
1591         /* Enable IRQs */
1592         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1593         /* Unmask interrupts */
1594         snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1595                                         BA0_HISR_MIDI |
1596                                         BA0_HISR_DMAI |
1597                                         BA0_HISR_DMA(0) |
1598                                         BA0_HISR_DMA(1) |
1599                                         BA0_HISR_DMA(2) |
1600                                         BA0_HISR_DMA(3)));
1601
1602         return 0;
1603 }
1604
1605 /*
1606  *  MIDI section
1607  */
1608
1609 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1610 {
1611         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1612         udelay(100);
1613         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1614 }
1615
1616 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1617 {
1618         struct cs4281 *chip = substream->rmidi->private_data;
1619
1620         spin_lock_irq(&chip->reg_lock);
1621         chip->midcr |= BA0_MIDCR_RXE;
1622         chip->midi_input = substream;
1623         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1624                 snd_cs4281_midi_reset(chip);
1625         } else {
1626                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1627         }
1628         spin_unlock_irq(&chip->reg_lock);
1629         return 0;
1630 }
1631
1632 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1633 {
1634         struct cs4281 *chip = substream->rmidi->private_data;
1635
1636         spin_lock_irq(&chip->reg_lock);
1637         chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1638         chip->midi_input = NULL;
1639         if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1640                 snd_cs4281_midi_reset(chip);
1641         } else {
1642                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1643         }
1644         chip->uartm &= ~CS4281_MODE_INPUT;
1645         spin_unlock_irq(&chip->reg_lock);
1646         return 0;
1647 }
1648
1649 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1650 {
1651         struct cs4281 *chip = substream->rmidi->private_data;
1652
1653         spin_lock_irq(&chip->reg_lock);
1654         chip->uartm |= CS4281_MODE_OUTPUT;
1655         chip->midcr |= BA0_MIDCR_TXE;
1656         chip->midi_output = substream;
1657         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1658                 snd_cs4281_midi_reset(chip);
1659         } else {
1660                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1661         }
1662         spin_unlock_irq(&chip->reg_lock);
1663         return 0;
1664 }
1665
1666 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1667 {
1668         struct cs4281 *chip = substream->rmidi->private_data;
1669
1670         spin_lock_irq(&chip->reg_lock);
1671         chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1672         chip->midi_output = NULL;
1673         if (!(chip->uartm & CS4281_MODE_INPUT)) {
1674                 snd_cs4281_midi_reset(chip);
1675         } else {
1676                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1677         }
1678         chip->uartm &= ~CS4281_MODE_OUTPUT;
1679         spin_unlock_irq(&chip->reg_lock);
1680         return 0;
1681 }
1682
1683 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1684 {
1685         unsigned long flags;
1686         struct cs4281 *chip = substream->rmidi->private_data;
1687
1688         spin_lock_irqsave(&chip->reg_lock, flags);
1689         if (up) {
1690                 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1691                         chip->midcr |= BA0_MIDCR_RIE;
1692                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1693                 }
1694         } else {
1695                 if (chip->midcr & BA0_MIDCR_RIE) {
1696                         chip->midcr &= ~BA0_MIDCR_RIE;
1697                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1698                 }
1699         }
1700         spin_unlock_irqrestore(&chip->reg_lock, flags);
1701 }
1702
1703 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1704 {
1705         unsigned long flags;
1706         struct cs4281 *chip = substream->rmidi->private_data;
1707         unsigned char byte;
1708
1709         spin_lock_irqsave(&chip->reg_lock, flags);
1710         if (up) {
1711                 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1712                         chip->midcr |= BA0_MIDCR_TIE;
1713                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1714                         while ((chip->midcr & BA0_MIDCR_TIE) &&
1715                                (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1716                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1717                                         chip->midcr &= ~BA0_MIDCR_TIE;
1718                                 } else {
1719                                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1720                                 }
1721                         }
1722                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1723                 }
1724         } else {
1725                 if (chip->midcr & BA0_MIDCR_TIE) {
1726                         chip->midcr &= ~BA0_MIDCR_TIE;
1727                         snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1728                 }
1729         }
1730         spin_unlock_irqrestore(&chip->reg_lock, flags);
1731 }
1732
1733 static const struct snd_rawmidi_ops snd_cs4281_midi_output =
1734 {
1735         .open =         snd_cs4281_midi_output_open,
1736         .close =        snd_cs4281_midi_output_close,
1737         .trigger =      snd_cs4281_midi_output_trigger,
1738 };
1739
1740 static const struct snd_rawmidi_ops snd_cs4281_midi_input =
1741 {
1742         .open =         snd_cs4281_midi_input_open,
1743         .close =        snd_cs4281_midi_input_close,
1744         .trigger =      snd_cs4281_midi_input_trigger,
1745 };
1746
1747 static int snd_cs4281_midi(struct cs4281 *chip, int device)
1748 {
1749         struct snd_rawmidi *rmidi;
1750         int err;
1751
1752         if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1753                 return err;
1754         strcpy(rmidi->name, "CS4281");
1755         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1756         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1757         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1758         rmidi->private_data = chip;
1759         chip->rmidi = rmidi;
1760         return 0;
1761 }
1762
1763 /*
1764  *  Interrupt handler
1765  */
1766
1767 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1768 {
1769         struct cs4281 *chip = dev_id;
1770         unsigned int status, dma, val;
1771         struct cs4281_dma *cdma;
1772
1773         if (chip == NULL)
1774                 return IRQ_NONE;
1775         status = snd_cs4281_peekBA0(chip, BA0_HISR);
1776         if ((status & 0x7fffffff) == 0) {
1777                 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1778                 return IRQ_NONE;
1779         }
1780
1781         if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1782                 for (dma = 0; dma < 4; dma++)
1783                         if (status & BA0_HISR_DMA(dma)) {
1784                                 cdma = &chip->dma[dma];
1785                                 spin_lock(&chip->reg_lock);
1786                                 /* ack DMA IRQ */
1787                                 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1788                                 /* workaround, sometimes CS4281 acknowledges */
1789                                 /* end or middle transfer position twice */
1790                                 cdma->frag++;
1791                                 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1792                                         cdma->frag--;
1793                                         chip->spurious_dhtc_irq++;
1794                                         spin_unlock(&chip->reg_lock);
1795                                         continue;
1796                                 }
1797                                 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1798                                         cdma->frag--;
1799                                         chip->spurious_dtc_irq++;
1800                                         spin_unlock(&chip->reg_lock);
1801                                         continue;
1802                                 }
1803                                 spin_unlock(&chip->reg_lock);
1804                                 snd_pcm_period_elapsed(cdma->substream);
1805                         }
1806         }
1807
1808         if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1809                 unsigned char c;
1810
1811                 spin_lock(&chip->reg_lock);
1812                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1813                         c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1814                         if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1815                                 continue;
1816                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1817                 }
1818                 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1819                         if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1820                                 break;
1821                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1822                                 chip->midcr &= ~BA0_MIDCR_TIE;
1823                                 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1824                                 break;
1825                         }
1826                         snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1827                 }
1828                 spin_unlock(&chip->reg_lock);
1829         }
1830
1831         /* EOI to the PCI part... reenables interrupts */
1832         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1833
1834         return IRQ_HANDLED;
1835 }
1836
1837
1838 /*
1839  * OPL3 command
1840  */
1841 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1842                                     unsigned char val)
1843 {
1844         unsigned long flags;
1845         struct cs4281 *chip = opl3->private_data;
1846         void __iomem *port;
1847
1848         if (cmd & OPL3_RIGHT)
1849                 port = chip->ba0 + BA0_B1AP; /* right port */
1850         else
1851                 port = chip->ba0 + BA0_B0AP; /* left port */
1852
1853         spin_lock_irqsave(&opl3->reg_lock, flags);
1854
1855         writel((unsigned int)cmd, port);
1856         udelay(10);
1857
1858         writel((unsigned int)val, port + 4);
1859         udelay(30);
1860
1861         spin_unlock_irqrestore(&opl3->reg_lock, flags);
1862 }
1863
1864 static int snd_cs4281_probe(struct pci_dev *pci,
1865                             const struct pci_device_id *pci_id)
1866 {
1867         static int dev;
1868         struct snd_card *card;
1869         struct cs4281 *chip;
1870         struct snd_opl3 *opl3;
1871         int err;
1872
1873         if (dev >= SNDRV_CARDS)
1874                 return -ENODEV;
1875         if (!enable[dev]) {
1876                 dev++;
1877                 return -ENOENT;
1878         }
1879
1880         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1881                            0, &card);
1882         if (err < 0)
1883                 return err;
1884
1885         if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1886                 snd_card_free(card);
1887                 return err;
1888         }
1889         card->private_data = chip;
1890
1891         if ((err = snd_cs4281_mixer(chip)) < 0) {
1892                 snd_card_free(card);
1893                 return err;
1894         }
1895         if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
1896                 snd_card_free(card);
1897                 return err;
1898         }
1899         if ((err = snd_cs4281_midi(chip, 0)) < 0) {
1900                 snd_card_free(card);
1901                 return err;
1902         }
1903         if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1904                 snd_card_free(card);
1905                 return err;
1906         }
1907         opl3->private_data = chip;
1908         opl3->command = snd_cs4281_opl3_command;
1909         snd_opl3_init(opl3);
1910         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1911                 snd_card_free(card);
1912                 return err;
1913         }
1914         snd_cs4281_create_gameport(chip);
1915         strcpy(card->driver, "CS4281");
1916         strcpy(card->shortname, "Cirrus Logic CS4281");
1917         sprintf(card->longname, "%s at 0x%lx, irq %d",
1918                 card->shortname,
1919                 chip->ba0_addr,
1920                 chip->irq);
1921
1922         if ((err = snd_card_register(card)) < 0) {
1923                 snd_card_free(card);
1924                 return err;
1925         }
1926
1927         pci_set_drvdata(pci, card);
1928         dev++;
1929         return 0;
1930 }
1931
1932 static void snd_cs4281_remove(struct pci_dev *pci)
1933 {
1934         snd_card_free(pci_get_drvdata(pci));
1935 }
1936
1937 /*
1938  * Power Management
1939  */
1940 #ifdef CONFIG_PM_SLEEP
1941
1942 static const int saved_regs[SUSPEND_REGISTERS] = {
1943         BA0_JSCTL,
1944         BA0_GPIOR,
1945         BA0_SSCR,
1946         BA0_MIDCR,
1947         BA0_SRCSA,
1948         BA0_PASR,
1949         BA0_CASR,
1950         BA0_DACSR,
1951         BA0_ADCSR,
1952         BA0_FMLVC,
1953         BA0_FMRVC,
1954         BA0_PPLVC,
1955         BA0_PPRVC,
1956 };
1957
1958 #define CLKCR1_CKRA                             0x00010000L
1959
1960 static int cs4281_suspend(struct device *dev)
1961 {
1962         struct snd_card *card = dev_get_drvdata(dev);
1963         struct cs4281 *chip = card->private_data;
1964         u32 ulCLK;
1965         unsigned int i;
1966
1967         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1968         snd_ac97_suspend(chip->ac97);
1969         snd_ac97_suspend(chip->ac97_secondary);
1970
1971         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1972         ulCLK |= CLKCR1_CKRA;
1973         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1974
1975         /* Disable interrupts. */
1976         snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
1977
1978         /* remember the status registers */
1979         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
1980                 if (saved_regs[i])
1981                         chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
1982
1983         /* Turn off the serial ports. */
1984         snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1985
1986         /* Power off FM, Joystick, AC link, */
1987         snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1988
1989         /* DLL off. */
1990         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1991
1992         /* AC link off. */
1993         snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1994
1995         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
1996         ulCLK &= ~CLKCR1_CKRA;
1997         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
1998         return 0;
1999 }
2000
2001 static int cs4281_resume(struct device *dev)
2002 {
2003         struct snd_card *card = dev_get_drvdata(dev);
2004         struct cs4281 *chip = card->private_data;
2005         unsigned int i;
2006         u32 ulCLK;
2007
2008         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2009         ulCLK |= CLKCR1_CKRA;
2010         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2011
2012         snd_cs4281_chip_init(chip);
2013
2014         /* restore the status registers */
2015         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2016                 if (saved_regs[i])
2017                         snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2018
2019         snd_ac97_resume(chip->ac97);
2020         snd_ac97_resume(chip->ac97_secondary);
2021
2022         ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2023         ulCLK &= ~CLKCR1_CKRA;
2024         snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2025
2026         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2027         return 0;
2028 }
2029
2030 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2031 #define CS4281_PM_OPS   &cs4281_pm
2032 #else
2033 #define CS4281_PM_OPS   NULL
2034 #endif /* CONFIG_PM_SLEEP */
2035
2036 static struct pci_driver cs4281_driver = {
2037         .name = KBUILD_MODNAME,
2038         .id_table = snd_cs4281_ids,
2039         .probe = snd_cs4281_probe,
2040         .remove = snd_cs4281_remove,
2041         .driver = {
2042                 .pm = CS4281_PM_OPS,
2043         },
2044 };
2045
2046 module_pci_driver(cs4281_driver);