sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33
  34 #if IS_REACHABLE(CONFIG_GAMEPORT)
  35 #define SUPPORT_JOYSTICK 1
  36 #endif
  37
  38 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  39 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  40 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  41 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
  42 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  43 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  44 #ifdef SUPPORT_JOYSTICK
  45 static int joystick_port[SNDRV_CARDS];
  46 #endif
  47
  48 module_param_array(index, int, NULL, 0444);
  49 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  50 module_param_array(id, charp, NULL, 0444);
  51 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  52 module_param_array(enable, bool, NULL, 0444);
  53 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  54 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  55 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  56 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  57 MODULE_PARM_DESC(fm_port, "FM port.");
  58 module_param_array(soft_ac3, bool, NULL, 0444);
  59 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  60 #ifdef SUPPORT_JOYSTICK
  61 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  62 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  63 #endif
  64
  65 /*
  66  * CM8x38 registers definition
  67  */
  68
  69 #define CM_REG_FUNCTRL0         0x00
  70 #define CM_RST_CH1              0x00080000
  71 #define CM_RST_CH0              0x00040000
  72 #define CM_CHEN1                0x00020000      /* ch1: enable */
  73 #define CM_CHEN0                0x00010000      /* ch0: enable */
  74 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  75 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  76 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  77 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  78
  79 #define CM_REG_FUNCTRL1         0x04
  80 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  81 #define CM_DSFC_SHIFT           13
  82 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  83 #define CM_ASFC_SHIFT           10
  84 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  85 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  86 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  87 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  88 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  89 #define CM_BREQ                 0x00000010      /* bus master enabled */
  90 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  91 #define CM_UART_EN              0x00000004      /* legacy UART */
  92 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  93 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  94
  95 #define CM_REG_CHFORMAT         0x08
  96
  97 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
  98 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
  99 #define CM_CHB3D                0x20000000      /* 4 channels */
 100
 101 #define CM_CHIP_MASK1           0x1f000000
 102 #define CM_CHIP_037             0x01000000
 103 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 104 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 105 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 106 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 107 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 108 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 109 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 110
 111 #define CM_ADCBITLEN_MASK       0x0000C000
 112 #define CM_ADCBITLEN_16         0x00000000
 113 #define CM_ADCBITLEN_15         0x00004000
 114 #define CM_ADCBITLEN_14         0x00008000
 115 #define CM_ADCBITLEN_13         0x0000C000
 116
 117 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 118 #define CM_ADCDACLEN_060        0x00000000
 119 #define CM_ADCDACLEN_066        0x00001000
 120 #define CM_ADCDACLEN_130        0x00002000
 121 #define CM_ADCDACLEN_280        0x00003000
 122
 123 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 124 #define CM_ADCDLEN_ORIGINAL     0x00000000
 125 #define CM_ADCDLEN_EXTRA        0x00001000
 126 #define CM_ADCDLEN_24K          0x00002000
 127 #define CM_ADCDLEN_WEIGHT       0x00003000
 128
 129 #define CM_CH1_SRATE_176K       0x00000800
 130 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 131 #define CM_CH1_SRATE_88K        0x00000400
 132 #define CM_CH0_SRATE_176K       0x00000200
 133 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 134 #define CM_CH0_SRATE_88K        0x00000100
 135 #define CM_CH0_SRATE_128K       0x00000300
 136 #define CM_CH0_SRATE_MASK       0x00000300
 137
 138 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 139 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 140 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 141 #define CM_SPDLOCKED            0x00000010
 142
 143 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 144 #define CM_CH1FMT_SHIFT         2
 145 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 146 #define CM_CH0FMT_SHIFT         0
 147
 148 #define CM_REG_INT_HLDCLR       0x0C
 149 #define CM_CHIP_MASK2           0xff000000
 150 #define CM_CHIP_8768            0x20000000
 151 #define CM_CHIP_055             0x08000000
 152 #define CM_CHIP_039             0x04000000
 153 #define CM_CHIP_039_6CH         0x01000000
 154 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 155 #define CM_TDMA_INT_EN          0x00040000
 156 #define CM_CH1_INT_EN           0x00020000
 157 #define CM_CH0_INT_EN           0x00010000
 158
 159 #define CM_REG_INT_STATUS       0x10
 160 #define CM_INTR                 0x80000000
 161 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 162 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 163 #define CM_UARTINT              0x00010000
 164 #define CM_LTDMAINT             0x00008000
 165 #define CM_HTDMAINT             0x00004000
 166 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 167 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 168 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 169 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 170 #define CM_CH1BUSY              0x00000008
 171 #define CM_CH0BUSY              0x00000004
 172 #define CM_CHINT1               0x00000002
 173 #define CM_CHINT0               0x00000001
 174
 175 #define CM_REG_LEGACY_CTRL      0x14
 176 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 177 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 178 #define CM_VMPU_330             0x00000000
 179 #define CM_VMPU_320             0x20000000
 180 #define CM_VMPU_310             0x40000000
 181 #define CM_VMPU_300             0x60000000
 182 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 183 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 184 #define CM_VSBSEL_220           0x00000000
 185 #define CM_VSBSEL_240           0x04000000
 186 #define CM_VSBSEL_260           0x08000000
 187 #define CM_VSBSEL_280           0x0C000000
 188 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 189 #define CM_FMSEL_388            0x00000000
 190 #define CM_FMSEL_3C8            0x01000000
 191 #define CM_FMSEL_3E0            0x02000000
 192 #define CM_FMSEL_3E8            0x03000000
 193 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 194 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 195 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 196 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 197 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 198 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 199 #define CM_C_EECS               0x00040000
 200 #define CM_C_EEDI46             0x00020000
 201 #define CM_C_EECK46             0x00010000
 202 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 203 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 204 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 205 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 206
 207 #define CM_REG_MISC_CTRL        0x18
 208 #define CM_PWD                  0x80000000      /* power down */
 209 #define CM_RESET                0x40000000
 210 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 211 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 212 #define CM_TXVX                 0x08000000      /* model 037? */
 213 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 214 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 215 #define CM_SPDIF48K             0x01000000      /* write */
 216 #define CM_SPATUS48K            0x01000000      /* read */
 217 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 218 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 219 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 220 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 221 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 222 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 223 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 224 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 225 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 226 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 227 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 228 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 229 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 230 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 231 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 232 #define CM_ENCENTER             0x00000080
 233 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 234 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 235 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 236 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 237 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 238 #define CM_UPDDMA_2048          0x00000000
 239 #define CM_UPDDMA_1024          0x00000004
 240 #define CM_UPDDMA_512           0x00000008
 241 #define CM_UPDDMA_256           0x0000000C
 242 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 243 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 244 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 245
 246 #define CM_REG_TDMA_POSITION    0x1C
 247 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 248 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 249
 250         /* byte */
 251 #define CM_REG_MIXER0           0x20
 252 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 253 #define CM_REG_DEV              0x20            /* read: hardware device version */
 254
 255 #define CM_REG_MIXER21          0x21
 256 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 257 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 258 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 259 #define CM_X_SB16               0x01            /* SB16 compatible */
 260
 261 #define CM_REG_SB16_DATA        0x22
 262 #define CM_REG_SB16_ADDR        0x23
 263
 264 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 265 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 266 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 267 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 268
 269 #define CM_REG_MIXER1           0x24
 270 #define CM_FMMUTE               0x80    /* mute FM */
 271 #define CM_FMMUTE_SHIFT         7
 272 #define CM_WSMUTE               0x40    /* mute PCM */
 273 #define CM_WSMUTE_SHIFT         6
 274 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 275 #define CM_REAR2LIN_SHIFT       5
 276 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 277 #define CM_REAR2FRONT_SHIFT     4
 278 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 279 #define CM_WAVEINL_SHIFT        3
 280 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 281 #define CM_WAVEINR_SHIFT        2
 282 #define CM_X3DEN                0x02    /* 3D surround enable */
 283 #define CM_X3DEN_SHIFT          1
 284 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 285 #define CM_CDPLAY_SHIFT         0
 286
 287 #define CM_REG_MIXER2           0x25
 288 #define CM_RAUXREN              0x80    /* AUX right capture */
 289 #define CM_RAUXREN_SHIFT        7
 290 #define CM_RAUXLEN              0x40    /* AUX left capture */
 291 #define CM_RAUXLEN_SHIFT        6
 292 #define CM_VAUXRM               0x20    /* AUX right mute */
 293 #define CM_VAUXRM_SHIFT         5
 294 #define CM_VAUXLM               0x10    /* AUX left mute */
 295 #define CM_VAUXLM_SHIFT         4
 296 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 297 #define CM_VADMIC_SHIFT         1
 298 #define CM_MICGAINZ             0x01    /* mic boost */
 299 #define CM_MICGAINZ_SHIFT       0
 300
 301 #define CM_REG_MIXER3           0x24
 302 #define CM_REG_AUX_VOL          0x26
 303 #define CM_VAUXL_MASK           0xf0
 304 #define CM_VAUXR_MASK           0x0f
 305
 306 #define CM_REG_MISC             0x27
 307 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 308 #define CM_XGPO1                0x20
 309 // #define CM_XGPBIO            0x04
 310 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 311 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 312 #define CM_SPDVALID             0x02    /* spdif input valid check */
 313 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 314
 315 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 316 /*
 317  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 318  * or identical with AC97 codec?
 319  */
 320 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 321
 322 /*
 323  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 324  */
 325 #define CM_REG_MPU_PCI          0x40
 326
 327 /*
 328  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 329  */
 330 #define CM_REG_FM_PCI           0x50
 331
 332 /*
 333  * access from SB-mixer port
 334  */
 335 #define CM_REG_EXTENT_IND       0xf0
 336 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 337 #define CM_VPHONE_SHIFT         5
 338 #define CM_VPHOM                0x10    /* Phone mute control */
 339 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 340 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 341 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 342 #define CM_VADMIC3              0x01    /* Mic record boost */
 343
 344 /*
 345  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 346  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 347  * unit (readonly?).
 348  */
 349 #define CM_REG_PLL              0xf8
 350
 351 /*
 352  * extended registers
 353  */
 354 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 355 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 356 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 357 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 358
 359 #define CM_REG_EXT_MISC         0x90
 360 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 361 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 362 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 363 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 364 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 365 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 366 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 367 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 368
 369 /*
 370  * size of i/o region
 371  */
 372 #define CM_EXTENT_CODEC   0x100
 373 #define CM_EXTENT_MIDI    0x2
 374 #define CM_EXTENT_SYNTH   0x4
 375
 376
 377 /*
 378  * channels for playback / capture
 379  */
 380 #define CM_CH_PLAY      0
 381 #define CM_CH_CAPT      1
 382
 383 /*
 384  * flags to check device open/close
 385  */
 386 #define CM_OPEN_NONE    0
 387 #define CM_OPEN_CH_MASK 0x01
 388 #define CM_OPEN_DAC     0x10
 389 #define CM_OPEN_ADC     0x20
 390 #define CM_OPEN_SPDIF   0x40
 391 #define CM_OPEN_MCHAN   0x80
 392 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 393 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 394 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 395 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 396 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 397 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 398
 399
 400 #if CM_CH_PLAY == 1
 401 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 402 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 403 #define CM_CAPTURE_SPDF         CM_SPDF_0
 404 #else
 405 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 406 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 407 #define CM_CAPTURE_SPDF         CM_SPDF_1
 408 #endif
 409
 410
 411 /*
 412  * driver data
 413  */
 414
 415 struct cmipci_pcm {
 416         struct snd_pcm_substream *substream;
 417         u8 running;             /* dac/adc running? */
 418         u8 fmt;                 /* format bits */
 419         u8 is_dac;
 420         u8 needs_silencing;
 421         unsigned int dma_size;  /* in frames */
 422         unsigned int shift;
 423         unsigned int ch;        /* channel (0/1) */
 424         unsigned int offset;    /* physical address of the buffer */
 425 };
 426
 427 /* mixer elements toggled/resumed during ac3 playback */
 428 struct cmipci_mixer_auto_switches {
 429         const char *name;       /* switch to toggle */
 430         int toggle_on;          /* value to change when ac3 mode */
 431 };
 432 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 433         {"PCM Playback Switch", 0},
 434         {"IEC958 Output Switch", 1},
 435         {"IEC958 Mix Analog", 0},
 436         // {"IEC958 Out To DAC", 1}, // no longer used
 437         {"IEC958 Loop", 0},
 438 };
 439 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 440
 441 struct cmipci {
 442         struct snd_card *card;
 443
 444         struct pci_dev *pci;
 445         unsigned int device;    /* device ID */
 446         int irq;
 447
 448         unsigned long iobase;
 449         unsigned int ctrl;      /* FUNCTRL0 current value */
 450
 451         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 452         struct snd_pcm *pcm2;   /* 2nd DAC */
 453         struct snd_pcm *pcm_spdif;      /* SPDIF */
 454
 455         int chip_version;
 456         int max_channels;
 457         unsigned int can_ac3_sw: 1;
 458         unsigned int can_ac3_hw: 1;
 459         unsigned int can_multi_ch: 1;
 460         unsigned int can_96k: 1;        /* samplerate above 48k */
 461         unsigned int do_soft_ac3: 1;
 462
 463         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 464         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 465         int spdif_counter;      /* for software AC3 */
 466
 467         unsigned int dig_status;
 468         unsigned int dig_pcm_status;
 469
 470         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 471
 472         int opened[2];  /* open mode */
 473         struct mutex open_mutex;
 474
 475         unsigned int mixer_insensitive: 1;
 476         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 477         int mixer_res_status[CM_SAVED_MIXERS];
 478
 479         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 480
 481         /* external MIDI */
 482         struct snd_rawmidi *rmidi;
 483
 484 #ifdef SUPPORT_JOYSTICK
 485         struct gameport *gameport;
 486 #endif
 487
 488         spinlock_t reg_lock;
 489
 490 #ifdef CONFIG_PM_SLEEP
 491         unsigned int saved_regs[0x20];
 492         unsigned char saved_mixers[0x20];
 493 #endif
 494 };
 495
 496
 497 /* read/write operations for dword register */
 498 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 499 {
 500         outl(data, cm->iobase + cmd);
 501 }
 502
 503 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 504 {
 505         return inl(cm->iobase + cmd);
 506 }
 507
 508 /* read/write operations for word register */
 509 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 510 {
 511         outw(data, cm->iobase + cmd);
 512 }
 513
 514 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 515 {
 516         return inw(cm->iobase + cmd);
 517 }
 518
 519 /* read/write operations for byte register */
 520 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 521 {
 522         outb(data, cm->iobase + cmd);
 523 }
 524
 525 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 526 {
 527         return inb(cm->iobase + cmd);
 528 }
 529
 530 /* bit operations for dword register */
 531 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 532 {
 533         unsigned int val, oval;
 534         val = oval = inl(cm->iobase + cmd);
 535         val |= flag;
 536         if (val == oval)
 537                 return 0;
 538         outl(val, cm->iobase + cmd);
 539         return 1;
 540 }
 541
 542 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 543 {
 544         unsigned int val, oval;
 545         val = oval = inl(cm->iobase + cmd);
 546         val &= ~flag;
 547         if (val == oval)
 548                 return 0;
 549         outl(val, cm->iobase + cmd);
 550         return 1;
 551 }
 552
 553 /* bit operations for byte register */
 554 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 555 {
 556         unsigned char val, oval;
 557         val = oval = inb(cm->iobase + cmd);
 558         val |= flag;
 559         if (val == oval)
 560                 return 0;
 561         outb(val, cm->iobase + cmd);
 562         return 1;
 563 }
 564
 565 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 566 {
 567         unsigned char val, oval;
 568         val = oval = inb(cm->iobase + cmd);
 569         val &= ~flag;
 570         if (val == oval)
 571                 return 0;
 572         outb(val, cm->iobase + cmd);
 573         return 1;
 574 }
 575
 576
 577 /*
 578  * PCM interface
 579  */
 580
 581 /*
 582  * calculate frequency
 583  */
 584
 585 static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 586
 587 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 588 {
 589         unsigned int i;
 590
 591         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 592                 if (rates[i] == rate)
 593                         return i;
 594         }
 595         snd_BUG();
 596         return 0;
 597 }
 598
 599 #ifdef USE_VAR48KRATE
 600 /*
 601  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 602  * does it this way .. maybe not.  Never get any information from C-Media about
 603  * that <werner@suse.de>.
 604  */
 605 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 606 {
 607         unsigned int delta, tolerance;
 608         int xm, xn, xr;
 609
 610         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 611                 rate <<= 1;
 612         *n = -1;
 613         if (*r > 0xff)
 614                 goto out;
 615         tolerance = rate*CM_TOLERANCE_RATE;
 616
 617         for (xn = (1+2); xn < (0x1f+2); xn++) {
 618                 for (xm = (1+2); xm < (0xff+2); xm++) {
 619                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 620
 621                         if (xr < rate)
 622                                 delta = rate - xr;
 623                         else
 624                                 delta = xr - rate;
 625
 626                         /*
 627                          * If we found one, remember this,
 628                          * and try to find a closer one
 629                          */
 630                         if (delta < tolerance) {
 631                                 tolerance = delta;
 632                                 *m = xm - 2;
 633                                 *n = xn - 2;
 634                         }
 635                 }
 636         }
 637 out:
 638         return (*n > -1);
 639 }
 640
 641 /*
 642  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 643  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 644  * at the register CM_REG_FUNCTRL1 (0x04).
 645  * Problem: other ways are also possible (any information about that?)
 646  */
 647 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 648 {
 649         unsigned int reg = CM_REG_PLL + slot;
 650         /*
 651          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 652          * for DSFC/ASFC (000 up to 111).
 653          */
 654
 655         /* FIXME: Init (Do we've to set an other register first before programming?) */
 656
 657         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 658         snd_cmipci_write_b(cm, reg, rate>>8);
 659         snd_cmipci_write_b(cm, reg, rate&0xff);
 660
 661         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 662 }
 663 #endif /* USE_VAR48KRATE */
 664
 665 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 666                                           struct snd_pcm_hw_params *hw_params)
 667 {
 668         struct cmipci *cm = snd_pcm_substream_chip(substream);
 669         if (params_channels(hw_params) > 2) {
 670                 mutex_lock(&cm->open_mutex);
 671                 if (cm->opened[CM_CH_PLAY]) {
 672                         mutex_unlock(&cm->open_mutex);
 673                         return -EBUSY;
 674                 }
 675                 /* reserve the channel A */
 676                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 677                 mutex_unlock(&cm->open_mutex);
 678         }
 679         return 0;
 680 }
 681
 682 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 683 {
 684         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 685         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 686         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 687         udelay(10);
 688 }
 689
 690
 691 /*
 692  */
 693
 694 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 695 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 696         .count = 3,
 697         .list = hw_channels,
 698         .mask = 0,
 699 };
 700 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 701         .count = 4,
 702         .list = hw_channels,
 703         .mask = 0,
 704 };
 705 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 706         .count = 5,
 707         .list = hw_channels,
 708         .mask = 0,
 709 };
 710
 711 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 712 {
 713         if (channels > 2) {
 714                 if (!cm->can_multi_ch || !rec->ch)
 715                         return -EINVAL;
 716                 if (rec->fmt != 0x03) /* stereo 16bit only */
 717                         return -EINVAL;
 718         }
 719
 720         if (cm->can_multi_ch) {
 721                 spin_lock_irq(&cm->reg_lock);
 722                 if (channels > 2) {
 723                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 724                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 725                 } else {
 726                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 727                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 728                 }
 729                 if (channels == 8)
 730                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 731                 else
 732                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 733                 if (channels == 6) {
 734                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 735                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 736                 } else {
 737                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 738                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 739                 }
 740                 if (channels == 4)
 741                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 742                 else
 743                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 744                 spin_unlock_irq(&cm->reg_lock);
 745         }
 746         return 0;
 747 }
 748
 749
 750 /*
 751  * prepare playback/capture channel
 752  * channel to be used must have been set in rec->ch.
 753  */
 754 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 755                                  struct snd_pcm_substream *substream)
 756 {
 757         unsigned int reg, freq, freq_ext, val;
 758         unsigned int period_size;
 759         struct snd_pcm_runtime *runtime = substream->runtime;
 760
 761         rec->fmt = 0;
 762         rec->shift = 0;
 763         if (snd_pcm_format_width(runtime->format) >= 16) {
 764                 rec->fmt |= 0x02;
 765                 if (snd_pcm_format_width(runtime->format) > 16)
 766                         rec->shift++; /* 24/32bit */
 767         }
 768         if (runtime->channels > 1)
 769                 rec->fmt |= 0x01;
 770         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 771                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 772                 return -EINVAL;
 773         }
 774
 775         rec->offset = runtime->dma_addr;
 776         /* buffer and period sizes in frame */
 777         rec->dma_size = runtime->buffer_size << rec->shift;
 778         period_size = runtime->period_size << rec->shift;
 779         if (runtime->channels > 2) {
 780                 /* multi-channels */
 781                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 782                 period_size = (period_size * runtime->channels) / 2;
 783         }
 784
 785         spin_lock_irq(&cm->reg_lock);
 786
 787         /* set buffer address */
 788         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 789         snd_cmipci_write(cm, reg, rec->offset);
 790         /* program sample counts */
 791         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 792         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 793         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 794
 795         /* set adc/dac flag */
 796         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 797         if (rec->is_dac)
 798                 cm->ctrl &= ~val;
 799         else
 800                 cm->ctrl |= val;
 801         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 802         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 803
 804         /* set sample rate */
 805         freq = 0;
 806         freq_ext = 0;
 807         if (runtime->rate > 48000)
 808                 switch (runtime->rate) {
 809                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 810                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 811                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 812                 default:     snd_BUG(); break;
 813                 }
 814         else
 815                 freq = snd_cmipci_rate_freq(runtime->rate);
 816         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 817         if (rec->ch) {
 818                 val &= ~CM_DSFC_MASK;
 819                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 820         } else {
 821                 val &= ~CM_ASFC_MASK;
 822                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 823         }
 824         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 825         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 826
 827         /* set format */
 828         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 829         if (rec->ch) {
 830                 val &= ~CM_CH1FMT_MASK;
 831                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 832         } else {
 833                 val &= ~CM_CH0FMT_MASK;
 834                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 835         }
 836         if (cm->can_96k) {
 837                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 838                 val |= freq_ext << (rec->ch * 2);
 839         }
 840         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 841         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 842
 843         if (!rec->is_dac && cm->chip_version) {
 844                 if (runtime->rate > 44100)
 845                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 846                 else
 847                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 848         }
 849
 850         rec->running = 0;
 851         spin_unlock_irq(&cm->reg_lock);
 852
 853         return 0;
 854 }
 855
 856 /*
 857  * PCM trigger/stop
 858  */
 859 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 860                                   int cmd)
 861 {
 862         unsigned int inthld, chen, reset, pause;
 863         int result = 0;
 864
 865         inthld = CM_CH0_INT_EN << rec->ch;
 866         chen = CM_CHEN0 << rec->ch;
 867         reset = CM_RST_CH0 << rec->ch;
 868         pause = CM_PAUSE0 << rec->ch;
 869
 870         spin_lock(&cm->reg_lock);
 871         switch (cmd) {
 872         case SNDRV_PCM_TRIGGER_START:
 873                 rec->running = 1;
 874                 /* set interrupt */
 875                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 876                 cm->ctrl |= chen;
 877                 /* enable channel */
 878                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 879                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 880                 break;
 881         case SNDRV_PCM_TRIGGER_STOP:
 882                 rec->running = 0;
 883                 /* disable interrupt */
 884                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 885                 /* reset */
 886                 cm->ctrl &= ~chen;
 887                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 888                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 889                 rec->needs_silencing = rec->is_dac;
 890                 break;
 891         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 892         case SNDRV_PCM_TRIGGER_SUSPEND:
 893                 cm->ctrl |= pause;
 894                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 895                 break;
 896         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 897         case SNDRV_PCM_TRIGGER_RESUME:
 898                 cm->ctrl &= ~pause;
 899                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 900                 break;
 901         default:
 902                 result = -EINVAL;
 903                 break;
 904         }
 905         spin_unlock(&cm->reg_lock);
 906         return result;
 907 }
 908
 909 /*
 910  * return the current pointer
 911  */
 912 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 913                                                 struct snd_pcm_substream *substream)
 914 {
 915         size_t ptr;
 916         unsigned int reg, rem, tries;
 917
 918         if (!rec->running)
 919                 return 0;
 920 #if 1 // this seems better..
 921         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 922         for (tries = 0; tries < 3; tries++) {
 923                 rem = snd_cmipci_read_w(cm, reg);
 924                 if (rem < rec->dma_size)
 925                         goto ok;
 926         }
 927         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 928         return SNDRV_PCM_POS_XRUN;
 929 ok:
 930         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 931 #else
 932         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 933         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 934         ptr = bytes_to_frames(substream->runtime, ptr);
 935 #endif
 936         if (substream->runtime->channels > 2)
 937                 ptr = (ptr * 2) / substream->runtime->channels;
 938         return ptr;
 939 }
 940
 941 /*
 942  * playback
 943  */
 944
 945 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 946                                        int cmd)
 947 {
 948         struct cmipci *cm = snd_pcm_substream_chip(substream);
 949         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 950 }
 951
 952 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 953 {
 954         struct cmipci *cm = snd_pcm_substream_chip(substream);
 955         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 956 }
 957
 958
 959
 960 /*
 961  * capture
 962  */
 963
 964 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 965                                      int cmd)
 966 {
 967         struct cmipci *cm = snd_pcm_substream_chip(substream);
 968         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 969 }
 970
 971 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 972 {
 973         struct cmipci *cm = snd_pcm_substream_chip(substream);
 974         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 975 }
 976
 977
 978 /*
 979  * hw preparation for spdif
 980  */
 981
 982 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 983                                          struct snd_ctl_elem_info *uinfo)
 984 {
 985         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 986         uinfo->count = 1;
 987         return 0;
 988 }
 989
 990 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
 991                                         struct snd_ctl_elem_value *ucontrol)
 992 {
 993         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 994         int i;
 995
 996         spin_lock_irq(&chip->reg_lock);
 997         for (i = 0; i < 4; i++)
 998                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 999         spin_unlock_irq(&chip->reg_lock);
1000         return 0;
1001 }
1002
1003 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1004                                          struct snd_ctl_elem_value *ucontrol)
1005 {
1006         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1007         int i, change;
1008         unsigned int val;
1009
1010         val = 0;
1011         spin_lock_irq(&chip->reg_lock);
1012         for (i = 0; i < 4; i++)
1013                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1014         change = val != chip->dig_status;
1015         chip->dig_status = val;
1016         spin_unlock_irq(&chip->reg_lock);
1017         return change;
1018 }
1019
1020 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1021 {
1022         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1023         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1024         .info =         snd_cmipci_spdif_default_info,
1025         .get =          snd_cmipci_spdif_default_get,
1026         .put =          snd_cmipci_spdif_default_put
1027 };
1028
1029 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1030                                       struct snd_ctl_elem_info *uinfo)
1031 {
1032         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1033         uinfo->count = 1;
1034         return 0;
1035 }
1036
1037 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1038                                      struct snd_ctl_elem_value *ucontrol)
1039 {
1040         ucontrol->value.iec958.status[0] = 0xff;
1041         ucontrol->value.iec958.status[1] = 0xff;
1042         ucontrol->value.iec958.status[2] = 0xff;
1043         ucontrol->value.iec958.status[3] = 0xff;
1044         return 0;
1045 }
1046
1047 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1048 {
1049         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1050         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1051         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1052         .info =         snd_cmipci_spdif_mask_info,
1053         .get =          snd_cmipci_spdif_mask_get,
1054 };
1055
1056 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1057                                         struct snd_ctl_elem_info *uinfo)
1058 {
1059         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1060         uinfo->count = 1;
1061         return 0;
1062 }
1063
1064 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1065                                        struct snd_ctl_elem_value *ucontrol)
1066 {
1067         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1068         int i;
1069
1070         spin_lock_irq(&chip->reg_lock);
1071         for (i = 0; i < 4; i++)
1072                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1073         spin_unlock_irq(&chip->reg_lock);
1074         return 0;
1075 }
1076
1077 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1078                                        struct snd_ctl_elem_value *ucontrol)
1079 {
1080         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1081         int i, change;
1082         unsigned int val;
1083
1084         val = 0;
1085         spin_lock_irq(&chip->reg_lock);
1086         for (i = 0; i < 4; i++)
1087                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1088         change = val != chip->dig_pcm_status;
1089         chip->dig_pcm_status = val;
1090         spin_unlock_irq(&chip->reg_lock);
1091         return change;
1092 }
1093
1094 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1095 {
1096         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1097         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1098         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1099         .info =         snd_cmipci_spdif_stream_info,
1100         .get =          snd_cmipci_spdif_stream_get,
1101         .put =          snd_cmipci_spdif_stream_put
1102 };
1103
1104 /*
1105  */
1106
1107 /* save mixer setting and mute for AC3 playback */
1108 static int save_mixer_state(struct cmipci *cm)
1109 {
1110         if (! cm->mixer_insensitive) {
1111                 struct snd_ctl_elem_value *val;
1112                 unsigned int i;
1113
1114                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1115                 if (!val)
1116                         return -ENOMEM;
1117                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1118                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1119                         if (ctl) {
1120                                 int event;
1121                                 memset(val, 0, sizeof(*val));
1122                                 ctl->get(ctl, val);
1123                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1124                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1125                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1126                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1127                                         ctl->put(ctl, val); /* toggle */
1128                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1129                                 }
1130                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1131                                 snd_ctl_notify(cm->card, event, &ctl->id);
1132                         }
1133                 }
1134                 kfree(val);
1135                 cm->mixer_insensitive = 1;
1136         }
1137         return 0;
1138 }
1139
1140
1141 /* restore the previously saved mixer status */
1142 static void restore_mixer_state(struct cmipci *cm)
1143 {
1144         if (cm->mixer_insensitive) {
1145                 struct snd_ctl_elem_value *val;
1146                 unsigned int i;
1147
1148                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1149                 if (!val)
1150                         return;
1151                 cm->mixer_insensitive = 0; /* at first clear this;
1152                                               otherwise the changes will be ignored */
1153                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1154                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1155                         if (ctl) {
1156                                 int event;
1157
1158                                 memset(val, 0, sizeof(*val));
1159                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1160                                 ctl->get(ctl, val);
1161                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1162                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1163                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1164                                         ctl->put(ctl, val);
1165                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1166                                 }
1167                                 snd_ctl_notify(cm->card, event, &ctl->id);
1168                         }
1169                 }
1170                 kfree(val);
1171         }
1172 }
1173
1174 /* spinlock held! */
1175 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1176 {
1177         if (do_ac3) {
1178                 /* AC3EN for 037 */
1179                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1180                 /* AC3EN for 039 */
1181                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1182
1183                 if (cm->can_ac3_hw) {
1184                         /* SPD24SEL for 037, 0x02 */
1185                         /* SPD24SEL for 039, 0x20, but cannot be set */
1186                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1187                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188                 } else { /* can_ac3_sw */
1189                         /* SPD32SEL for 037 & 039, 0x20 */
1190                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191                         /* set 176K sample rate to fix 033 HW bug */
1192                         if (cm->chip_version == 33) {
1193                                 if (rate >= 48000) {
1194                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1195                                 } else {
1196                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1197                                 }
1198                         }
1199                 }
1200
1201         } else {
1202                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1203                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1204
1205                 if (cm->can_ac3_hw) {
1206                         /* chip model >= 37 */
1207                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1208                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1209                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1210                         } else {
1211                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1212                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1213                         }
1214                 } else {
1215                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1217                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1218                 }
1219         }
1220 }
1221
1222 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1223 {
1224         int rate, err;
1225
1226         rate = subs->runtime->rate;
1227
1228         if (up && do_ac3) {
1229                 err = save_mixer_state(cm);
1230                 if (err < 0)
1231                         return err;
1232         }
1233
1234         spin_lock_irq(&cm->reg_lock);
1235         cm->spdif_playback_avail = up;
1236         if (up) {
1237                 /* they are controlled via "IEC958 Output Switch" */
1238                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1239                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1240                 if (cm->spdif_playback_enabled)
1241                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1242                 setup_ac3(cm, subs, do_ac3, rate);
1243
1244                 if (rate == 48000 || rate == 96000)
1245                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1246                 else
1247                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1248                 if (rate > 48000)
1249                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1250                 else
1251                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1252         } else {
1253                 /* they are controlled via "IEC958 Output Switch" */
1254                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1255                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1256                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1257                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1258                 setup_ac3(cm, subs, 0, 0);
1259         }
1260         spin_unlock_irq(&cm->reg_lock);
1261         return 0;
1262 }
1263
1264
1265 /*
1266  * preparation
1267  */
1268
1269 /* playback - enable spdif only on the certain condition */
1270 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1271 {
1272         struct cmipci *cm = snd_pcm_substream_chip(substream);
1273         int rate = substream->runtime->rate;
1274         int err, do_spdif, do_ac3 = 0;
1275
1276         do_spdif = (rate >= 44100 && rate <= 96000 &&
1277                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1278                     substream->runtime->channels == 2);
1279         if (do_spdif && cm->can_ac3_hw)
1280                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1281         err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1282         if (err < 0)
1283                 return err;
1284         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1285 }
1286
1287 /* playback  (via device #2) - enable spdif always */
1288 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1289 {
1290         struct cmipci *cm = snd_pcm_substream_chip(substream);
1291         int err, do_ac3;
1292
1293         if (cm->can_ac3_hw)
1294                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1295         else
1296                 do_ac3 = 1; /* doesn't matter */
1297         err = setup_spdif_playback(cm, substream, 1, do_ac3);
1298         if (err < 0)
1299                 return err;
1300         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1301 }
1302
1303 /*
1304  * Apparently, the samples last played on channel A stay in some buffer, even
1305  * after the channel is reset, and get added to the data for the rear DACs when
1306  * playing a multichannel stream on channel B.  This is likely to generate
1307  * wraparounds and thus distortions.
1308  * To avoid this, we play at least one zero sample after the actual stream has
1309  * stopped.
1310  */
1311 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1312 {
1313         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1314         unsigned int reg, val;
1315
1316         if (rec->needs_silencing && runtime && runtime->dma_area) {
1317                 /* set up a small silence buffer */
1318                 memset(runtime->dma_area, 0, PAGE_SIZE);
1319                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1320                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1321                 snd_cmipci_write(cm, reg, val);
1322
1323                 /* configure for 16 bits, 2 channels, 8 kHz */
1324                 if (runtime->channels > 2)
1325                         set_dac_channels(cm, rec, 2);
1326                 spin_lock_irq(&cm->reg_lock);
1327                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1328                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1329                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1330                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1331                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1332                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1333                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1334                 if (cm->can_96k)
1335                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1336                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1337
1338                 /* start stream (we don't need interrupts) */
1339                 cm->ctrl |= CM_CHEN0 << rec->ch;
1340                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1341                 spin_unlock_irq(&cm->reg_lock);
1342
1343                 msleep(1);
1344
1345                 /* stop and reset stream */
1346                 spin_lock_irq(&cm->reg_lock);
1347                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1348                 val = CM_RST_CH0 << rec->ch;
1349                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1350                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1351                 spin_unlock_irq(&cm->reg_lock);
1352
1353                 rec->needs_silencing = 0;
1354         }
1355 }
1356
1357 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1358 {
1359         struct cmipci *cm = snd_pcm_substream_chip(substream);
1360         setup_spdif_playback(cm, substream, 0, 0);
1361         restore_mixer_state(cm);
1362         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1363         return 0;
1364 }
1365
1366 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1367 {
1368         struct cmipci *cm = snd_pcm_substream_chip(substream);
1369         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1370         return 0;
1371 }
1372
1373 /* capture */
1374 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1375 {
1376         struct cmipci *cm = snd_pcm_substream_chip(substream);
1377         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1378 }
1379
1380 /* capture with spdif (via device #2) */
1381 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1382 {
1383         struct cmipci *cm = snd_pcm_substream_chip(substream);
1384
1385         spin_lock_irq(&cm->reg_lock);
1386         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1387         if (cm->can_96k) {
1388                 if (substream->runtime->rate > 48000)
1389                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1390                 else
1391                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1392         }
1393         if (snd_pcm_format_width(substream->runtime->format) > 16)
1394                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1395         else
1396                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1397
1398         spin_unlock_irq(&cm->reg_lock);
1399
1400         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1401 }
1402
1403 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1404 {
1405         struct cmipci *cm = snd_pcm_substream_chip(subs);
1406
1407         spin_lock_irq(&cm->reg_lock);
1408         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1409         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1410         spin_unlock_irq(&cm->reg_lock);
1411
1412         return 0;
1413 }
1414
1415
1416 /*
1417  * interrupt handler
1418  */
1419 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1420 {
1421         struct cmipci *cm = dev_id;
1422         unsigned int status, mask = 0;
1423
1424         /* fastpath out, to ease interrupt sharing */
1425         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1426         if (!(status & CM_INTR))
1427                 return IRQ_NONE;
1428
1429         /* acknowledge interrupt */
1430         spin_lock(&cm->reg_lock);
1431         if (status & CM_CHINT0)
1432                 mask |= CM_CH0_INT_EN;
1433         if (status & CM_CHINT1)
1434                 mask |= CM_CH1_INT_EN;
1435         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1436         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1437         spin_unlock(&cm->reg_lock);
1438
1439         if (cm->rmidi && (status & CM_UARTINT))
1440                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1441
1442         if (cm->pcm) {
1443                 if ((status & CM_CHINT0) && cm->channel[0].running)
1444                         snd_pcm_period_elapsed(cm->channel[0].substream);
1445                 if ((status & CM_CHINT1) && cm->channel[1].running)
1446                         snd_pcm_period_elapsed(cm->channel[1].substream);
1447         }
1448         return IRQ_HANDLED;
1449 }
1450
1451 /*
1452  * h/w infos
1453  */
1454
1455 /* playback on channel A */
1456 static const struct snd_pcm_hardware snd_cmipci_playback =
1457 {
1458         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1459                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1460                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1461         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1462         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1463         .rate_min =             5512,
1464         .rate_max =             48000,
1465         .channels_min =         1,
1466         .channels_max =         2,
1467         .buffer_bytes_max =     (128*1024),
1468         .period_bytes_min =     64,
1469         .period_bytes_max =     (128*1024),
1470         .periods_min =          2,
1471         .periods_max =          1024,
1472         .fifo_size =            0,
1473 };
1474
1475 /* capture on channel B */
1476 static const struct snd_pcm_hardware snd_cmipci_capture =
1477 {
1478         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1479                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1480                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1481         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1482         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1483         .rate_min =             5512,
1484         .rate_max =             48000,
1485         .channels_min =         1,
1486         .channels_max =         2,
1487         .buffer_bytes_max =     (128*1024),
1488         .period_bytes_min =     64,
1489         .period_bytes_max =     (128*1024),
1490         .periods_min =          2,
1491         .periods_max =          1024,
1492         .fifo_size =            0,
1493 };
1494
1495 /* playback on channel B - stereo 16bit only? */
1496 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1497 {
1498         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1499                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1500                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1501         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1502         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1503         .rate_min =             5512,
1504         .rate_max =             48000,
1505         .channels_min =         2,
1506         .channels_max =         2,
1507         .buffer_bytes_max =     (128*1024),
1508         .period_bytes_min =     64,
1509         .period_bytes_max =     (128*1024),
1510         .periods_min =          2,
1511         .periods_max =          1024,
1512         .fifo_size =            0,
1513 };
1514
1515 /* spdif playback on channel A */
1516 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1517 {
1518         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1519                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1520                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1521         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1522         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1523         .rate_min =             44100,
1524         .rate_max =             48000,
1525         .channels_min =         2,
1526         .channels_max =         2,
1527         .buffer_bytes_max =     (128*1024),
1528         .period_bytes_min =     64,
1529         .period_bytes_max =     (128*1024),
1530         .periods_min =          2,
1531         .periods_max =          1024,
1532         .fifo_size =            0,
1533 };
1534
1535 /* spdif playback on channel A (32bit, IEC958 subframes) */
1536 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1537 {
1538         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1539                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1540                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1541         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1542         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1543         .rate_min =             44100,
1544         .rate_max =             48000,
1545         .channels_min =         2,
1546         .channels_max =         2,
1547         .buffer_bytes_max =     (128*1024),
1548         .period_bytes_min =     64,
1549         .period_bytes_max =     (128*1024),
1550         .periods_min =          2,
1551         .periods_max =          1024,
1552         .fifo_size =            0,
1553 };
1554
1555 /* spdif capture on channel B */
1556 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1557 {
1558         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1559                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1560                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1561         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1562                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1563         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1564         .rate_min =             44100,
1565         .rate_max =             48000,
1566         .channels_min =         2,
1567         .channels_max =         2,
1568         .buffer_bytes_max =     (128*1024),
1569         .period_bytes_min =     64,
1570         .period_bytes_max =     (128*1024),
1571         .periods_min =          2,
1572         .periods_max =          1024,
1573         .fifo_size =            0,
1574 };
1575
1576 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1577                         32000, 44100, 48000, 88200, 96000, 128000 };
1578 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1579                 .count = ARRAY_SIZE(rate_constraints),
1580                 .list = rate_constraints,
1581                 .mask = 0,
1582 };
1583
1584 /*
1585  * check device open/close
1586  */
1587 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1588 {
1589         int ch = mode & CM_OPEN_CH_MASK;
1590
1591         /* FIXME: a file should wait until the device becomes free
1592          * when it's opened on blocking mode.  however, since the current
1593          * pcm framework doesn't pass file pointer before actually opened,
1594          * we can't know whether blocking mode or not in open callback..
1595          */
1596         mutex_lock(&cm->open_mutex);
1597         if (cm->opened[ch]) {
1598                 mutex_unlock(&cm->open_mutex);
1599                 return -EBUSY;
1600         }
1601         cm->opened[ch] = mode;
1602         cm->channel[ch].substream = subs;
1603         if (! (mode & CM_OPEN_DAC)) {
1604                 /* disable dual DAC mode */
1605                 cm->channel[ch].is_dac = 0;
1606                 spin_lock_irq(&cm->reg_lock);
1607                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1608                 spin_unlock_irq(&cm->reg_lock);
1609         }
1610         mutex_unlock(&cm->open_mutex);
1611         return 0;
1612 }
1613
1614 static void close_device_check(struct cmipci *cm, int mode)
1615 {
1616         int ch = mode & CM_OPEN_CH_MASK;
1617
1618         mutex_lock(&cm->open_mutex);
1619         if (cm->opened[ch] == mode) {
1620                 if (cm->channel[ch].substream) {
1621                         snd_cmipci_ch_reset(cm, ch);
1622                         cm->channel[ch].running = 0;
1623                         cm->channel[ch].substream = NULL;
1624                 }
1625                 cm->opened[ch] = 0;
1626                 if (! cm->channel[ch].is_dac) {
1627                         /* enable dual DAC mode again */
1628                         cm->channel[ch].is_dac = 1;
1629                         spin_lock_irq(&cm->reg_lock);
1630                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1631                         spin_unlock_irq(&cm->reg_lock);
1632                 }
1633         }
1634         mutex_unlock(&cm->open_mutex);
1635 }
1636
1637 /*
1638  */
1639
1640 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1641 {
1642         struct cmipci *cm = snd_pcm_substream_chip(substream);
1643         struct snd_pcm_runtime *runtime = substream->runtime;
1644         int err;
1645
1646         err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1647         if (err < 0)
1648                 return err;
1649         runtime->hw = snd_cmipci_playback;
1650         if (cm->chip_version == 68) {
1651                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1652                                      SNDRV_PCM_RATE_96000;
1653                 runtime->hw.rate_max = 96000;
1654         } else if (cm->chip_version == 55) {
1655                 err = snd_pcm_hw_constraint_list(runtime, 0,
1656                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1657                 if (err < 0)
1658                         return err;
1659                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1660                 runtime->hw.rate_max = 128000;
1661         }
1662         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1663         cm->dig_pcm_status = cm->dig_status;
1664         return 0;
1665 }
1666
1667 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1668 {
1669         struct cmipci *cm = snd_pcm_substream_chip(substream);
1670         struct snd_pcm_runtime *runtime = substream->runtime;
1671         int err;
1672
1673         err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1674         if (err < 0)
1675                 return err;
1676         runtime->hw = snd_cmipci_capture;
1677         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1678                 runtime->hw.rate_min = 41000;
1679                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1680         } else if (cm->chip_version == 55) {
1681                 err = snd_pcm_hw_constraint_list(runtime, 0,
1682                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1683                 if (err < 0)
1684                         return err;
1685                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1686                 runtime->hw.rate_max = 128000;
1687         }
1688         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1689         return 0;
1690 }
1691
1692 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1693 {
1694         struct cmipci *cm = snd_pcm_substream_chip(substream);
1695         struct snd_pcm_runtime *runtime = substream->runtime;
1696         int err;
1697
1698         /* use channel B */
1699         err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1700         if (err < 0)
1701                 return err;
1702         runtime->hw = snd_cmipci_playback2;
1703         mutex_lock(&cm->open_mutex);
1704         if (! cm->opened[CM_CH_PLAY]) {
1705                 if (cm->can_multi_ch) {
1706                         runtime->hw.channels_max = cm->max_channels;
1707                         if (cm->max_channels == 4)
1708                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1709                         else if (cm->max_channels == 6)
1710                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1711                         else if (cm->max_channels == 8)
1712                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1713                 }
1714         }
1715         mutex_unlock(&cm->open_mutex);
1716         if (cm->chip_version == 68) {
1717                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1718                                      SNDRV_PCM_RATE_96000;
1719                 runtime->hw.rate_max = 96000;
1720         } else if (cm->chip_version == 55) {
1721                 err = snd_pcm_hw_constraint_list(runtime, 0,
1722                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1723                 if (err < 0)
1724                         return err;
1725                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1726                 runtime->hw.rate_max = 128000;
1727         }
1728         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1729         return 0;
1730 }
1731
1732 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1733 {
1734         struct cmipci *cm = snd_pcm_substream_chip(substream);
1735         struct snd_pcm_runtime *runtime = substream->runtime;
1736         int err;
1737
1738         /* use channel A */
1739         err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1740         if (err < 0)
1741                 return err;
1742         if (cm->can_ac3_hw) {
1743                 runtime->hw = snd_cmipci_playback_spdif;
1744                 if (cm->chip_version >= 37) {
1745                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1746                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1747                 }
1748                 if (cm->can_96k) {
1749                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1750                                              SNDRV_PCM_RATE_96000;
1751                         runtime->hw.rate_max = 96000;
1752                 }
1753         } else {
1754                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1755         }
1756         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1757         cm->dig_pcm_status = cm->dig_status;
1758         return 0;
1759 }
1760
1761 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1762 {
1763         struct cmipci *cm = snd_pcm_substream_chip(substream);
1764         struct snd_pcm_runtime *runtime = substream->runtime;
1765         int err;
1766
1767         /* use channel B */
1768         err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1769         if (err < 0)
1770                 return err;
1771         runtime->hw = snd_cmipci_capture_spdif;
1772         if (cm->can_96k && !(cm->chip_version == 68)) {
1773                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1774                                      SNDRV_PCM_RATE_96000;
1775                 runtime->hw.rate_max = 96000;
1776         }
1777         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1778         return 0;
1779 }
1780
1781
1782 /*
1783  */
1784
1785 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1786 {
1787         struct cmipci *cm = snd_pcm_substream_chip(substream);
1788         close_device_check(cm, CM_OPEN_PLAYBACK);
1789         return 0;
1790 }
1791
1792 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1793 {
1794         struct cmipci *cm = snd_pcm_substream_chip(substream);
1795         close_device_check(cm, CM_OPEN_CAPTURE);
1796         return 0;
1797 }
1798
1799 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1800 {
1801         struct cmipci *cm = snd_pcm_substream_chip(substream);
1802         close_device_check(cm, CM_OPEN_PLAYBACK2);
1803         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1804         return 0;
1805 }
1806
1807 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1808 {
1809         struct cmipci *cm = snd_pcm_substream_chip(substream);
1810         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1811         return 0;
1812 }
1813
1814 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1815 {
1816         struct cmipci *cm = snd_pcm_substream_chip(substream);
1817         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1818         return 0;
1819 }
1820
1821
1822 /*
1823  */
1824
1825 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1826         .open =         snd_cmipci_playback_open,
1827         .close =        snd_cmipci_playback_close,
1828         .hw_free =      snd_cmipci_playback_hw_free,
1829         .prepare =      snd_cmipci_playback_prepare,
1830         .trigger =      snd_cmipci_playback_trigger,
1831         .pointer =      snd_cmipci_playback_pointer,
1832 };
1833
1834 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1835         .open =         snd_cmipci_capture_open,
1836         .close =        snd_cmipci_capture_close,
1837         .prepare =      snd_cmipci_capture_prepare,
1838         .trigger =      snd_cmipci_capture_trigger,
1839         .pointer =      snd_cmipci_capture_pointer,
1840 };
1841
1842 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1843         .open =         snd_cmipci_playback2_open,
1844         .close =        snd_cmipci_playback2_close,
1845         .hw_params =    snd_cmipci_playback2_hw_params,
1846         .hw_free =      snd_cmipci_playback2_hw_free,
1847         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1848         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1849         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1850 };
1851
1852 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1853         .open =         snd_cmipci_playback_spdif_open,
1854         .close =        snd_cmipci_playback_spdif_close,
1855         .hw_free =      snd_cmipci_playback_hw_free,
1856         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1857         .trigger =      snd_cmipci_playback_trigger,
1858         .pointer =      snd_cmipci_playback_pointer,
1859 };
1860
1861 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1862         .open =         snd_cmipci_capture_spdif_open,
1863         .close =        snd_cmipci_capture_spdif_close,
1864         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1865         .prepare =      snd_cmipci_capture_spdif_prepare,
1866         .trigger =      snd_cmipci_capture_trigger,
1867         .pointer =      snd_cmipci_capture_pointer,
1868 };
1869
1870
1871 /*
1872  */
1873
1874 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1875 {
1876         struct snd_pcm *pcm;
1877         int err;
1878
1879         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1880         if (err < 0)
1881                 return err;
1882
1883         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1884         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1885
1886         pcm->private_data = cm;
1887         pcm->info_flags = 0;
1888         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1889         cm->pcm = pcm;
1890
1891         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1892                                        &cm->pci->dev, 64*1024, 128*1024);
1893
1894         return 0;
1895 }
1896
1897 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1898 {
1899         struct snd_pcm *pcm;
1900         int err;
1901
1902         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1903         if (err < 0)
1904                 return err;
1905
1906         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1907
1908         pcm->private_data = cm;
1909         pcm->info_flags = 0;
1910         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1911         cm->pcm2 = pcm;
1912
1913         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1914                                        &cm->pci->dev, 64*1024, 128*1024);
1915
1916         return 0;
1917 }
1918
1919 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1920 {
1921         struct snd_pcm *pcm;
1922         int err;
1923
1924         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1925         if (err < 0)
1926                 return err;
1927
1928         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1929         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1930
1931         pcm->private_data = cm;
1932         pcm->info_flags = 0;
1933         strcpy(pcm->name, "C-Media PCI IEC958");
1934         cm->pcm_spdif = pcm;
1935
1936         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1937                                        &cm->pci->dev, 64*1024, 128*1024);
1938
1939         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1940                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1941                                      NULL);
1942         if (err < 0)
1943                 return err;
1944
1945         return 0;
1946 }
1947
1948 /*
1949  * mixer interface:
1950  * - CM8338/8738 has a compatible mixer interface with SB16, but
1951  *   lack of some elements like tone control, i/o gain and AGC.
1952  * - Access to native registers:
1953  *   - A 3D switch
1954  *   - Output mute switches
1955  */
1956
1957 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1958 {
1959         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1960         outb(data, s->iobase + CM_REG_SB16_DATA);
1961 }
1962
1963 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1964 {
1965         unsigned char v;
1966
1967         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1968         v = inb(s->iobase + CM_REG_SB16_DATA);
1969         return v;
1970 }
1971
1972 /*
1973  * general mixer element
1974  */
1975 struct cmipci_sb_reg {
1976         unsigned int left_reg, right_reg;
1977         unsigned int left_shift, right_shift;
1978         unsigned int mask;
1979         unsigned int invert: 1;
1980         unsigned int stereo: 1;
1981 };
1982
1983 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1984  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1985
1986 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1987 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1988   .info = snd_cmipci_info_volume, \
1989   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1990   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1991 }
1992
1993 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1994 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1995 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1996 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1997
1998 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1999 {
2000         r->left_reg = val & 0xff;
2001         r->right_reg = (val >> 8) & 0xff;
2002         r->left_shift = (val >> 16) & 0x07;
2003         r->right_shift = (val >> 19) & 0x07;
2004         r->invert = (val >> 22) & 1;
2005         r->stereo = (val >> 23) & 1;
2006         r->mask = (val >> 24) & 0xff;
2007 }
2008
2009 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2010                                   struct snd_ctl_elem_info *uinfo)
2011 {
2012         struct cmipci_sb_reg reg;
2013
2014         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2015         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2016         uinfo->count = reg.stereo + 1;
2017         uinfo->value.integer.min = 0;
2018         uinfo->value.integer.max = reg.mask;
2019         return 0;
2020 }
2021
2022 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2023                                  struct snd_ctl_elem_value *ucontrol)
2024 {
2025         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2026         struct cmipci_sb_reg reg;
2027         int val;
2028
2029         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2030         spin_lock_irq(&cm->reg_lock);
2031         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2032         if (reg.invert)
2033                 val = reg.mask - val;
2034         ucontrol->value.integer.value[0] = val;
2035         if (reg.stereo) {
2036                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2037                 if (reg.invert)
2038                         val = reg.mask - val;
2039                 ucontrol->value.integer.value[1] = val;
2040         }
2041         spin_unlock_irq(&cm->reg_lock);
2042         return 0;
2043 }
2044
2045 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2046                                  struct snd_ctl_elem_value *ucontrol)
2047 {
2048         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2049         struct cmipci_sb_reg reg;
2050         int change;
2051         int left, right, oleft, oright;
2052
2053         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2054         left = ucontrol->value.integer.value[0] & reg.mask;
2055         if (reg.invert)
2056                 left = reg.mask - left;
2057         left <<= reg.left_shift;
2058         if (reg.stereo) {
2059                 right = ucontrol->value.integer.value[1] & reg.mask;
2060                 if (reg.invert)
2061                         right = reg.mask - right;
2062                 right <<= reg.right_shift;
2063         } else
2064                 right = 0;
2065         spin_lock_irq(&cm->reg_lock);
2066         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2067         left |= oleft & ~(reg.mask << reg.left_shift);
2068         change = left != oleft;
2069         if (reg.stereo) {
2070                 if (reg.left_reg != reg.right_reg) {
2071                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2072                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2073                 } else
2074                         oright = left;
2075                 right |= oright & ~(reg.mask << reg.right_shift);
2076                 change |= right != oright;
2077                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2078         } else
2079                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2080         spin_unlock_irq(&cm->reg_lock);
2081         return change;
2082 }
2083
2084 /*
2085  * input route (left,right) -> (left,right)
2086  */
2087 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2088 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2089   .info = snd_cmipci_info_input_sw, \
2090   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2091   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2092 }
2093
2094 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2095                                     struct snd_ctl_elem_info *uinfo)
2096 {
2097         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2098         uinfo->count = 4;
2099         uinfo->value.integer.min = 0;
2100         uinfo->value.integer.max = 1;
2101         return 0;
2102 }
2103
2104 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2105                                    struct snd_ctl_elem_value *ucontrol)
2106 {
2107         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2108         struct cmipci_sb_reg reg;
2109         int val1, val2;
2110
2111         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2112         spin_lock_irq(&cm->reg_lock);
2113         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2114         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2115         spin_unlock_irq(&cm->reg_lock);
2116         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2117         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2118         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2119         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2120         return 0;
2121 }
2122
2123 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2124                                    struct snd_ctl_elem_value *ucontrol)
2125 {
2126         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2127         struct cmipci_sb_reg reg;
2128         int change;
2129         int val1, val2, oval1, oval2;
2130
2131         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2132         spin_lock_irq(&cm->reg_lock);
2133         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2134         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2135         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2136         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2137         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2138         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2139         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2140         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2141         change = val1 != oval1 || val2 != oval2;
2142         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2143         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2144         spin_unlock_irq(&cm->reg_lock);
2145         return change;
2146 }
2147
2148 /*
2149  * native mixer switches/volumes
2150  */
2151
2152 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2153 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2154   .info = snd_cmipci_info_native_mixer, \
2155   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2156   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2157 }
2158
2159 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2160 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2161   .info = snd_cmipci_info_native_mixer, \
2162   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2163   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2164 }
2165
2166 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2167 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2168   .info = snd_cmipci_info_native_mixer, \
2169   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2170   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2171 }
2172
2173 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2174 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2175   .info = snd_cmipci_info_native_mixer, \
2176   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2177   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2178 }
2179
2180 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2181                                         struct snd_ctl_elem_info *uinfo)
2182 {
2183         struct cmipci_sb_reg reg;
2184
2185         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2186         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2187         uinfo->count = reg.stereo + 1;
2188         uinfo->value.integer.min = 0;
2189         uinfo->value.integer.max = reg.mask;
2190         return 0;
2191
2192 }
2193
2194 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2195                                        struct snd_ctl_elem_value *ucontrol)
2196 {
2197         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2198         struct cmipci_sb_reg reg;
2199         unsigned char oreg, val;
2200
2201         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2202         spin_lock_irq(&cm->reg_lock);
2203         oreg = inb(cm->iobase + reg.left_reg);
2204         val = (oreg >> reg.left_shift) & reg.mask;
2205         if (reg.invert)
2206                 val = reg.mask - val;
2207         ucontrol->value.integer.value[0] = val;
2208         if (reg.stereo) {
2209                 val = (oreg >> reg.right_shift) & reg.mask;
2210                 if (reg.invert)
2211                         val = reg.mask - val;
2212                 ucontrol->value.integer.value[1] = val;
2213         }
2214         spin_unlock_irq(&cm->reg_lock);
2215         return 0;
2216 }
2217
2218 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2219                                        struct snd_ctl_elem_value *ucontrol)
2220 {
2221         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2222         struct cmipci_sb_reg reg;
2223         unsigned char oreg, nreg, val;
2224
2225         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2226         spin_lock_irq(&cm->reg_lock);
2227         oreg = inb(cm->iobase + reg.left_reg);
2228         val = ucontrol->value.integer.value[0] & reg.mask;
2229         if (reg.invert)
2230                 val = reg.mask - val;
2231         nreg = oreg & ~(reg.mask << reg.left_shift);
2232         nreg |= (val << reg.left_shift);
2233         if (reg.stereo) {
2234                 val = ucontrol->value.integer.value[1] & reg.mask;
2235                 if (reg.invert)
2236                         val = reg.mask - val;
2237                 nreg &= ~(reg.mask << reg.right_shift);
2238                 nreg |= (val << reg.right_shift);
2239         }
2240         outb(nreg, cm->iobase + reg.left_reg);
2241         spin_unlock_irq(&cm->reg_lock);
2242         return (nreg != oreg);
2243 }
2244
2245 /*
2246  * special case - check mixer sensitivity
2247  */
2248 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2249                                                  struct snd_ctl_elem_value *ucontrol)
2250 {
2251         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2252         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2253 }
2254
2255 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2256                                                  struct snd_ctl_elem_value *ucontrol)
2257 {
2258         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2259         if (cm->mixer_insensitive) {
2260                 /* ignored */
2261                 return 0;
2262         }
2263         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2264 }
2265
2266
2267 static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2268         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2269         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2270         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2271         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2272         { /* switch with sensitivity */
2273                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2274                 .name = "PCM Playback Switch",
2275                 .info = snd_cmipci_info_native_mixer,
2276                 .get = snd_cmipci_get_native_mixer_sensitive,
2277                 .put = snd_cmipci_put_native_mixer_sensitive,
2278                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2279         },
2280         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2281         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2282         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2283         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2284         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2285         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2286         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2287         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2288         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2289         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2290         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2291         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2292         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2293         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2294         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2295         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2296         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2297         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2298         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2299         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2300         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2301         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2302         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2303 };
2304
2305 /*
2306  * other switches
2307  */
2308
2309 struct cmipci_switch_args {
2310         int reg;                /* register index */
2311         unsigned int mask;      /* mask bits */
2312         unsigned int mask_on;   /* mask bits to turn on */
2313         unsigned int is_byte: 1;                /* byte access? */
2314         unsigned int ac3_sensitive: 1;  /* access forbidden during
2315                                          * non-audio operation?
2316                                          */
2317 };
2318
2319 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2320
2321 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2322                                    struct snd_ctl_elem_value *ucontrol,
2323                                    struct cmipci_switch_args *args)
2324 {
2325         unsigned int val;
2326         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2327
2328         spin_lock_irq(&cm->reg_lock);
2329         if (args->ac3_sensitive && cm->mixer_insensitive) {
2330                 ucontrol->value.integer.value[0] = 0;
2331                 spin_unlock_irq(&cm->reg_lock);
2332                 return 0;
2333         }
2334         if (args->is_byte)
2335                 val = inb(cm->iobase + args->reg);
2336         else
2337                 val = snd_cmipci_read(cm, args->reg);
2338         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2339         spin_unlock_irq(&cm->reg_lock);
2340         return 0;
2341 }
2342
2343 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2344                                   struct snd_ctl_elem_value *ucontrol)
2345 {
2346         struct cmipci_switch_args *args;
2347         args = (struct cmipci_switch_args *)kcontrol->private_value;
2348         if (snd_BUG_ON(!args))
2349                 return -EINVAL;
2350         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2351 }
2352
2353 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2354                                    struct snd_ctl_elem_value *ucontrol,
2355                                    struct cmipci_switch_args *args)
2356 {
2357         unsigned int val;
2358         int change;
2359         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2360
2361         spin_lock_irq(&cm->reg_lock);
2362         if (args->ac3_sensitive && cm->mixer_insensitive) {
2363                 /* ignored */
2364                 spin_unlock_irq(&cm->reg_lock);
2365                 return 0;
2366         }
2367         if (args->is_byte)
2368                 val = inb(cm->iobase + args->reg);
2369         else
2370                 val = snd_cmipci_read(cm, args->reg);
2371         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2372                         args->mask_on : (args->mask & ~args->mask_on));
2373         if (change) {
2374                 val &= ~args->mask;
2375                 if (ucontrol->value.integer.value[0])
2376                         val |= args->mask_on;
2377                 else
2378                         val |= (args->mask & ~args->mask_on);
2379                 if (args->is_byte)
2380                         outb((unsigned char)val, cm->iobase + args->reg);
2381                 else
2382                         snd_cmipci_write(cm, args->reg, val);
2383         }
2384         spin_unlock_irq(&cm->reg_lock);
2385         return change;
2386 }
2387
2388 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2389                                   struct snd_ctl_elem_value *ucontrol)
2390 {
2391         struct cmipci_switch_args *args;
2392         args = (struct cmipci_switch_args *)kcontrol->private_value;
2393         if (snd_BUG_ON(!args))
2394                 return -EINVAL;
2395         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2396 }
2397
2398 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2399 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2400   .reg = xreg, \
2401   .mask = xmask, \
2402   .mask_on = xmask_on, \
2403   .is_byte = xis_byte, \
2404   .ac3_sensitive = xac3, \
2405 }
2406
2407 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2408         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2409
2410 #if 0 /* these will be controlled in pcm device */
2411 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2412 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2413 #endif
2414 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2415 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2417 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2418 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2419 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2420 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2421 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2422 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2423 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2424 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2425 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2426 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2427 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2428 #if CM_CH_PLAY == 1
2429 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2430 #else
2431 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2432 #endif
2433 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2434 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2435 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2436 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2437 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2438
2439 #define DEFINE_SWITCH(sname, stype, sarg) \
2440 { .name = sname, \
2441   .iface = stype, \
2442   .info = snd_cmipci_uswitch_info, \
2443   .get = snd_cmipci_uswitch_get, \
2444   .put = snd_cmipci_uswitch_put, \
2445   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2446 }
2447
2448 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2449 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2450
2451
2452 /*
2453  * callbacks for spdif output switch
2454  * needs toggle two registers..
2455  */
2456 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2457                                         struct snd_ctl_elem_value *ucontrol)
2458 {
2459         int changed;
2460         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2461         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2462         return changed;
2463 }
2464
2465 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2466                                         struct snd_ctl_elem_value *ucontrol)
2467 {
2468         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2469         int changed;
2470         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2471         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2472         if (changed) {
2473                 if (ucontrol->value.integer.value[0]) {
2474                         if (chip->spdif_playback_avail)
2475                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2476                 } else {
2477                         if (chip->spdif_playback_avail)
2478                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2479                 }
2480         }
2481         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2482         return changed;
2483 }
2484
2485
2486 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2487                                         struct snd_ctl_elem_info *uinfo)
2488 {
2489         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2490         static const char *const texts[3] = {
2491                 "Line-In", "Rear Output", "Bass Output"
2492         };
2493
2494         return snd_ctl_enum_info(uinfo, 1,
2495                                  cm->chip_version >= 39 ? 3 : 2, texts);
2496 }
2497
2498 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2499 {
2500         unsigned int val;
2501         if (cm->chip_version >= 39) {
2502                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2503                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2504                         return 2;
2505         }
2506         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2507         if (val & CM_REAR2LIN)
2508                 return 1;
2509         return 0;
2510 }
2511
2512 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2513                                        struct snd_ctl_elem_value *ucontrol)
2514 {
2515         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2516
2517         spin_lock_irq(&cm->reg_lock);
2518         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2519         spin_unlock_irq(&cm->reg_lock);
2520         return 0;
2521 }
2522
2523 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2524                                        struct snd_ctl_elem_value *ucontrol)
2525 {
2526         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2527         int change;
2528
2529         spin_lock_irq(&cm->reg_lock);
2530         if (ucontrol->value.enumerated.item[0] == 2)
2531                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2532         else
2533                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2534         if (ucontrol->value.enumerated.item[0] == 1)
2535                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2536         else
2537                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2538         spin_unlock_irq(&cm->reg_lock);
2539         return change;
2540 }
2541
2542 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2543                                        struct snd_ctl_elem_info *uinfo)
2544 {
2545         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2546
2547         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2548 }
2549
2550 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2551                                       struct snd_ctl_elem_value *ucontrol)
2552 {
2553         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2554         /* same bit as spdi_phase */
2555         spin_lock_irq(&cm->reg_lock);
2556         ucontrol->value.enumerated.item[0] =
2557                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2558         spin_unlock_irq(&cm->reg_lock);
2559         return 0;
2560 }
2561
2562 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2563                                       struct snd_ctl_elem_value *ucontrol)
2564 {
2565         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2566         int change;
2567
2568         spin_lock_irq(&cm->reg_lock);
2569         if (ucontrol->value.enumerated.item[0])
2570                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2571         else
2572                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2573         spin_unlock_irq(&cm->reg_lock);
2574         return change;
2575 }
2576
2577 /* both for CM8338/8738 */
2578 static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2579         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2580         {
2581                 .name = "Line-In Mode",
2582                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2583                 .info = snd_cmipci_line_in_mode_info,
2584                 .get = snd_cmipci_line_in_mode_get,
2585                 .put = snd_cmipci_line_in_mode_put,
2586         },
2587 };
2588
2589 /* for non-multichannel chips */
2590 static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2591 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2592
2593 /* only for CM8738 */
2594 static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2595 #if 0 /* controlled in pcm device */
2596         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2597         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2598         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2599 #endif
2600         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2601         { .name = "IEC958 Output Switch",
2602           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2603           .info = snd_cmipci_uswitch_info,
2604           .get = snd_cmipci_spdout_enable_get,
2605           .put = snd_cmipci_spdout_enable_put,
2606         },
2607         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2608         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2609         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2610 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2611         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2612         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2613 };
2614
2615 /* only for model 033/037 */
2616 static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2617         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2618         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2619         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2620 };
2621
2622 /* only for model 039 or later */
2623 static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2624         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2625         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2626         {
2627                 .name = "Mic-In Mode",
2628                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2629                 .info = snd_cmipci_mic_in_mode_info,
2630                 .get = snd_cmipci_mic_in_mode_get,
2631                 .put = snd_cmipci_mic_in_mode_put,
2632         }
2633 };
2634
2635 /* card control switches */
2636 static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2637 DEFINE_CARD_SWITCH("Modem", modem);
2638
2639
2640 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2641 {
2642         struct snd_card *card;
2643         const struct snd_kcontrol_new *sw;
2644         struct snd_kcontrol *kctl;
2645         unsigned int idx;
2646         int err;
2647
2648         if (snd_BUG_ON(!cm || !cm->card))
2649                 return -EINVAL;
2650
2651         card = cm->card;
2652
2653         strcpy(card->mixername, "CMedia PCI");
2654
2655         spin_lock_irq(&cm->reg_lock);
2656         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2657         spin_unlock_irq(&cm->reg_lock);
2658
2659         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2660                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2661                         if (!strcmp(snd_cmipci_mixers[idx].name,
2662                                 "PCM Playback Volume"))
2663                                 continue;
2664                 }
2665                 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2666                 if (err < 0)
2667                         return err;
2668         }
2669
2670         /* mixer switches */
2671         sw = snd_cmipci_mixer_switches;
2672         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2673                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2674                 if (err < 0)
2675                         return err;
2676         }
2677         if (! cm->can_multi_ch) {
2678                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2679                 if (err < 0)
2680                         return err;
2681         }
2682         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2683             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2684                 sw = snd_cmipci_8738_mixer_switches;
2685                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2686                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2687                         if (err < 0)
2688                                 return err;
2689                 }
2690                 if (cm->can_ac3_hw) {
2691                         kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2692                         err = snd_ctl_add(card, kctl);
2693                         if (err < 0)
2694                                 return err;
2695                         kctl->id.device = pcm_spdif_device;
2696                         kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2697                         err = snd_ctl_add(card, kctl);
2698                         if (err < 0)
2699                                 return err;
2700                         kctl->id.device = pcm_spdif_device;
2701                         kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2702                         err = snd_ctl_add(card, kctl);
2703                         if (err < 0)
2704                                 return err;
2705                         kctl->id.device = pcm_spdif_device;
2706                 }
2707                 if (cm->chip_version <= 37) {
2708                         sw = snd_cmipci_old_mixer_switches;
2709                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2710                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2711                                 if (err < 0)
2712                                         return err;
2713                         }
2714                 }
2715         }
2716         if (cm->chip_version >= 39) {
2717                 sw = snd_cmipci_extra_mixer_switches;
2718                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2719                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2720                         if (err < 0)
2721                                 return err;
2722                 }
2723         }
2724
2725         /* card switches */
2726         /*
2727          * newer chips don't have the register bits to force modem link
2728          * detection; the bit that was FLINKON now mutes CH1
2729          */
2730         if (cm->chip_version < 39) {
2731                 err = snd_ctl_add(cm->card,
2732                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2733                 if (err < 0)
2734                         return err;
2735         }
2736
2737         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2738                 struct snd_ctl_elem_id elem_id;
2739                 struct snd_kcontrol *ctl;
2740                 memset(&elem_id, 0, sizeof(elem_id));
2741                 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2742                 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2743                 ctl = snd_ctl_find_id(cm->card, &elem_id);
2744                 if (ctl)
2745                         cm->mixer_res_ctl[idx] = ctl;
2746         }
2747
2748         return 0;
2749 }
2750
2751
2752 /*
2753  * proc interface
2754  */
2755
2756 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2757                                  struct snd_info_buffer *buffer)
2758 {
2759         struct cmipci *cm = entry->private_data;
2760         int i, v;
2761
2762         snd_iprintf(buffer, "%s\n", cm->card->longname);
2763         for (i = 0; i < 0x94; i++) {
2764                 if (i == 0x28)
2765                         i = 0x90;
2766                 v = inb(cm->iobase + i);
2767                 if (i % 4 == 0)
2768                         snd_iprintf(buffer, "\n%02x:", i);
2769                 snd_iprintf(buffer, " %02x", v);
2770         }
2771         snd_iprintf(buffer, "\n");
2772 }
2773
2774 static void snd_cmipci_proc_init(struct cmipci *cm)
2775 {
2776         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2777 }
2778
2779 static const struct pci_device_id snd_cmipci_ids[] = {
2780         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2781         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2782         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2783         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2784         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2785         {0,},
2786 };
2787
2788
2789 /*
2790  * check chip version and capabilities
2791  * driver name is modified according to the chip model
2792  */
2793 static void query_chip(struct cmipci *cm)
2794 {
2795         unsigned int detect;
2796
2797         /* check reg 0Ch, bit 24-31 */
2798         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2799         if (! detect) {
2800                 /* check reg 08h, bit 24-28 */
2801                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2802                 switch (detect) {
2803                 case 0:
2804                         cm->chip_version = 33;
2805                         if (cm->do_soft_ac3)
2806                                 cm->can_ac3_sw = 1;
2807                         else
2808                                 cm->can_ac3_hw = 1;
2809                         break;
2810                 case CM_CHIP_037:
2811                         cm->chip_version = 37;
2812                         cm->can_ac3_hw = 1;
2813                         break;
2814                 default:
2815                         cm->chip_version = 39;
2816                         cm->can_ac3_hw = 1;
2817                         break;
2818                 }
2819                 cm->max_channels = 2;
2820         } else {
2821                 if (detect & CM_CHIP_039) {
2822                         cm->chip_version = 39;
2823                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2824                                 cm->max_channels = 6;
2825                         else
2826                                 cm->max_channels = 4;
2827                 } else if (detect & CM_CHIP_8768) {
2828                         cm->chip_version = 68;
2829                         cm->max_channels = 8;
2830                         cm->can_96k = 1;
2831                 } else {
2832                         cm->chip_version = 55;
2833                         cm->max_channels = 6;
2834                         cm->can_96k = 1;
2835                 }
2836                 cm->can_ac3_hw = 1;
2837                 cm->can_multi_ch = 1;
2838         }
2839 }
2840
2841 #ifdef SUPPORT_JOYSTICK
2842 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2843 {
2844         static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2845         struct gameport *gp;
2846         struct resource *r = NULL;
2847         int i, io_port = 0;
2848
2849         if (joystick_port[dev] == 0)
2850                 return -ENODEV;
2851
2852         if (joystick_port[dev] == 1) { /* auto-detect */
2853                 for (i = 0; ports[i]; i++) {
2854                         io_port = ports[i];
2855                         r = devm_request_region(&cm->pci->dev, io_port, 1,
2856                                                 "CMIPCI gameport");
2857                         if (r)
2858                                 break;
2859                 }
2860         } else {
2861                 io_port = joystick_port[dev];
2862                 r = devm_request_region(&cm->pci->dev, io_port, 1,
2863                                         "CMIPCI gameport");
2864         }
2865
2866         if (!r) {
2867                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2868                 return -EBUSY;
2869         }
2870
2871         cm->gameport = gp = gameport_allocate_port();
2872         if (!gp) {
2873                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2874                 return -ENOMEM;
2875         }
2876         gameport_set_name(gp, "C-Media Gameport");
2877         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2878         gameport_set_dev_parent(gp, &cm->pci->dev);
2879         gp->io = io_port;
2880
2881         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2882
2883         gameport_register_port(cm->gameport);
2884
2885         return 0;
2886 }
2887
2888 static void snd_cmipci_free_gameport(struct cmipci *cm)
2889 {
2890         if (cm->gameport) {
2891                 gameport_unregister_port(cm->gameport);
2892                 cm->gameport = NULL;
2893
2894                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2895         }
2896 }
2897 #else
2898 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2899 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2900 #endif
2901
2902 static void snd_cmipci_free(struct snd_card *card)
2903 {
2904         struct cmipci *cm = card->private_data;
2905
2906         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2907         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2908         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2909         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2910         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2911         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2912         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2913
2914         /* reset mixer */
2915         snd_cmipci_mixer_write(cm, 0, 0);
2916
2917         snd_cmipci_free_gameport(cm);
2918 }
2919
2920 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2921 {
2922         long iosynth;
2923         unsigned int val;
2924         struct snd_opl3 *opl3;
2925         int err;
2926
2927         if (!fm_port)
2928                 goto disable_fm;
2929
2930         if (cm->chip_version >= 39) {
2931                 /* first try FM regs in PCI port range */
2932                 iosynth = cm->iobase + CM_REG_FM_PCI;
2933                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2934                                       OPL3_HW_OPL3, 1, &opl3);
2935         } else {
2936                 err = -EIO;
2937         }
2938         if (err < 0) {
2939                 /* then try legacy ports */
2940                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2941                 iosynth = fm_port;
2942                 switch (iosynth) {
2943                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2944                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2945                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2946                 case 0x388: val |= CM_FMSEL_388; break;
2947                 default:
2948                         goto disable_fm;
2949                 }
2950                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2951                 /* enable FM */
2952                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2953
2954                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2955                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2956                         dev_err(cm->card->dev,
2957                                 "no OPL device at %#lx, skipping...\n",
2958                                 iosynth);
2959                         goto disable_fm;
2960                 }
2961         }
2962         err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2963         if (err < 0) {
2964                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2965                 return err;
2966         }
2967         return 0;
2968
2969  disable_fm:
2970         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2971         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2972         return 0;
2973 }
2974
2975 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2976                              int dev)
2977 {
2978         struct cmipci *cm = card->private_data;
2979         int err;
2980         unsigned int val;
2981         long iomidi = 0;
2982         int integrated_midi = 0;
2983         char modelstr[16];
2984         int pcm_index, pcm_spdif_index;
2985         static const struct pci_device_id intel_82437vx[] = {
2986                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2987                 { },
2988         };
2989
2990         err = pcim_enable_device(pci);
2991         if (err < 0)
2992                 return err;
2993
2994         spin_lock_init(&cm->reg_lock);
2995         mutex_init(&cm->open_mutex);
2996         cm->device = pci->device;
2997         cm->card = card;
2998         cm->pci = pci;
2999         cm->irq = -1;
3000         cm->channel[0].ch = 0;
3001         cm->channel[1].ch = 1;
3002         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3003
3004         err = pci_request_regions(pci, card->driver);
3005         if (err < 0)
3006                 return err;
3007         cm->iobase = pci_resource_start(pci, 0);
3008
3009         if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt,
3010                              IRQF_SHARED, KBUILD_MODNAME, cm)) {
3011                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3012                 return -EBUSY;
3013         }
3014         cm->irq = pci->irq;
3015         card->sync_irq = cm->irq;
3016         card->private_free = snd_cmipci_free;
3017
3018         pci_set_master(cm->pci);
3019
3020         /*
3021          * check chip version, max channels and capabilities
3022          */
3023
3024         cm->chip_version = 0;
3025         cm->max_channels = 2;
3026         cm->do_soft_ac3 = soft_ac3[dev];
3027
3028         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3029             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3030                 query_chip(cm);
3031         /* added -MCx suffix for chip supporting multi-channels */
3032         if (cm->can_multi_ch)
3033                 sprintf(cm->card->driver + strlen(cm->card->driver),
3034                         "-MC%d", cm->max_channels);
3035         else if (cm->can_ac3_sw)
3036                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3037
3038         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3039         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3040
3041 #if CM_CH_PLAY == 1
3042         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3043 #else
3044         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3045 #endif
3046
3047         /* initialize codec registers */
3048         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3049         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3050         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3051         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3052         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3053         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3054         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3055
3056         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3057         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3058 #if CM_CH_PLAY == 1
3059         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3060 #else
3061         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3062 #endif
3063         if (cm->chip_version) {
3064                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3065                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3066         }
3067         /* Set Bus Master Request */
3068         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3069
3070         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3071         switch (pci->device) {
3072         case PCI_DEVICE_ID_CMEDIA_CM8738:
3073         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3074                 if (!pci_dev_present(intel_82437vx))
3075                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3076                 break;
3077         default:
3078                 break;
3079         }
3080
3081         if (cm->chip_version < 68) {
3082                 val = pci->device < 0x110 ? 8338 : 8738;
3083         } else {
3084                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3085                 case 0:
3086                         val = 8769;
3087                         break;
3088                 case 2:
3089                         val = 8762;
3090                         break;
3091                 default:
3092                         switch ((pci->subsystem_vendor << 16) |
3093                                 pci->subsystem_device) {
3094                         case 0x13f69761:
3095                         case 0x584d3741:
3096                         case 0x584d3751:
3097                         case 0x584d3761:
3098                         case 0x584d3771:
3099                         case 0x72848384:
3100                                 val = 8770;
3101                                 break;
3102                         default:
3103                                 val = 8768;
3104                                 break;
3105                         }
3106                 }
3107         }
3108         sprintf(card->shortname, "C-Media CMI%d", val);
3109         if (cm->chip_version < 68)
3110                 sprintf(modelstr, " (model %d)", cm->chip_version);
3111         else
3112                 modelstr[0] = '\0';
3113         sprintf(card->longname, "%s%s at %#lx, irq %i",
3114                 card->shortname, modelstr, cm->iobase, cm->irq);
3115
3116         if (cm->chip_version >= 39) {
3117                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3118                 if (val != 0x00 && val != 0xff) {
3119                         if (mpu_port[dev])
3120                                 iomidi = cm->iobase + CM_REG_MPU_PCI;
3121                         integrated_midi = 1;
3122                 }
3123         }
3124         if (!integrated_midi) {
3125                 val = 0;
3126                 iomidi = mpu_port[dev];
3127                 switch (iomidi) {
3128                 case 0x320: val = CM_VMPU_320; break;
3129                 case 0x310: val = CM_VMPU_310; break;
3130                 case 0x300: val = CM_VMPU_300; break;
3131                 case 0x330: val = CM_VMPU_330; break;
3132                 default:
3133                             iomidi = 0; break;
3134                 }
3135                 if (iomidi > 0) {
3136                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3137                         /* enable UART */
3138                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3139                         if (inb(iomidi + 1) == 0xff) {
3140                                 dev_err(cm->card->dev,
3141                                         "cannot enable MPU-401 port at %#lx\n",
3142                                         iomidi);
3143                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3144                                                      CM_UART_EN);
3145                                 iomidi = 0;
3146                         }
3147                 }
3148         }
3149
3150         if (cm->chip_version < 68) {
3151                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3152                 if (err < 0)
3153                         return err;
3154         }
3155
3156         /* reset mixer */
3157         snd_cmipci_mixer_write(cm, 0, 0);
3158
3159         snd_cmipci_proc_init(cm);
3160
3161         /* create pcm devices */
3162         pcm_index = pcm_spdif_index = 0;
3163         err = snd_cmipci_pcm_new(cm, pcm_index);
3164         if (err < 0)
3165                 return err;
3166         pcm_index++;
3167         err = snd_cmipci_pcm2_new(cm, pcm_index);
3168         if (err < 0)
3169                 return err;
3170         pcm_index++;
3171         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3172                 pcm_spdif_index = pcm_index;
3173                 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3174                 if (err < 0)
3175                         return err;
3176         }
3177
3178         /* create mixer interface & switches */
3179         err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3180         if (err < 0)
3181                 return err;
3182
3183         if (iomidi > 0) {
3184                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3185                                           iomidi,
3186                                           (integrated_midi ?
3187                                            MPU401_INFO_INTEGRATED : 0) |
3188                                           MPU401_INFO_IRQ_HOOK,
3189                                           -1, &cm->rmidi);
3190                 if (err < 0)
3191                         dev_err(cm->card->dev,
3192                                 "no UART401 device at 0x%lx\n", iomidi);
3193         }
3194
3195 #ifdef USE_VAR48KRATE
3196         for (val = 0; val < ARRAY_SIZE(rates); val++)
3197                 snd_cmipci_set_pll(cm, rates[val], val);
3198
3199         /*
3200          * (Re-)Enable external switch spdo_48k
3201          */
3202         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3203 #endif /* USE_VAR48KRATE */
3204
3205         if (snd_cmipci_create_gameport(cm, dev) < 0)
3206                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3207
3208         return 0;
3209 }
3210
3211 /*
3212  */
3213
3214 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3215
3216 static int snd_cmipci_probe(struct pci_dev *pci,
3217                             const struct pci_device_id *pci_id)
3218 {
3219         static int dev;
3220         struct snd_card *card;
3221         struct cmipci *cm;
3222         int err;
3223
3224         if (dev >= SNDRV_CARDS)
3225                 return -ENODEV;
3226         if (! enable[dev]) {
3227                 dev++;
3228                 return -ENOENT;
3229         }
3230
3231         err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3232                                 sizeof(*cm), &card);
3233         if (err < 0)
3234                 return err;
3235         cm = card->private_data;
3236
3237         switch (pci->device) {
3238         case PCI_DEVICE_ID_CMEDIA_CM8738:
3239         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3240                 strcpy(card->driver, "CMI8738");
3241                 break;
3242         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3243         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3244                 strcpy(card->driver, "CMI8338");
3245                 break;
3246         default:
3247                 strcpy(card->driver, "CMIPCI");
3248                 break;
3249         }
3250
3251         err = snd_cmipci_create(card, pci, dev);
3252         if (err < 0)
3253                 return err;
3254
3255         err = snd_card_register(card);
3256         if (err < 0)
3257                 return err;
3258
3259         pci_set_drvdata(pci, card);
3260         dev++;
3261         return 0;
3262 }
3263
3264 #ifdef CONFIG_PM_SLEEP
3265 /*
3266  * power management
3267  */
3268 static const unsigned char saved_regs[] = {
3269         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3270         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3271         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3272         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3273         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3274 };
3275
3276 static const unsigned char saved_mixers[] = {
3277         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3278         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3279         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3280         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3281         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3282         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3283         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3284         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3285 };
3286
3287 static int snd_cmipci_suspend(struct device *dev)
3288 {
3289         struct snd_card *card = dev_get_drvdata(dev);
3290         struct cmipci *cm = card->private_data;
3291         int i;
3292
3293         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3294
3295         /* save registers */
3296         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3297                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3298         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3299                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3300
3301         /* disable ints */
3302         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3303         return 0;
3304 }
3305
3306 static int snd_cmipci_resume(struct device *dev)
3307 {
3308         struct snd_card *card = dev_get_drvdata(dev);
3309         struct cmipci *cm = card->private_data;
3310         int i;
3311
3312         /* reset / initialize to a sane state */
3313         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3314         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3315         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3316         snd_cmipci_mixer_write(cm, 0, 0);
3317
3318         /* restore registers */
3319         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3320                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3321         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3322                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3323
3324         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3325         return 0;
3326 }
3327
3328 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3329 #define SND_CMIPCI_PM_OPS       &snd_cmipci_pm
3330 #else
3331 #define SND_CMIPCI_PM_OPS       NULL
3332 #endif /* CONFIG_PM_SLEEP */
3333
3334 static struct pci_driver cmipci_driver = {
3335         .name = KBUILD_MODNAME,
3336         .id_table = snd_cmipci_ids,
3337         .probe = snd_cmipci_probe,
3338         .driver = {
3339                 .pm = SND_CMIPCI_PM_OPS,
3340         },
3341 };
3342
3343 module_pci_driver(cmipci_driver);