sound/mips/hal2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Driver for A2 audio system used in SGI machines
   4  *  Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
   5  *
   6  *  Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
   7  *  was based on code from Ulf Carlsson
   8  */
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/module.h>
  17
  18 #include <asm/sgi/hpc3.h>
  19 #include <asm/sgi/ip22.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/control.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm-indirect.h>
  25 #include <sound/initval.h>
  26
  27 #include "hal2.h"
  28
  29 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  30 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  31
  32 module_param(index, int, 0444);
  33 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
  34 module_param(id, charp, 0444);
  35 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
  36 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
  37 MODULE_AUTHOR("Thomas Bogendoerfer");
  38 MODULE_LICENSE("GPL");
  39
  40
  41 #define H2_BLOCK_SIZE   1024
  42 #define H2_BUF_SIZE     16384
  43
  44 struct hal2_pbus {
  45         struct hpc3_pbus_dmacregs *pbus;
  46         int pbusnr;
  47         unsigned int ctrl;              /* Current state of pbus->pbdma_ctrl */
  48 };
  49
  50 struct hal2_desc {
  51         struct hpc_dma_desc desc;
  52         u32 pad;                        /* padding */
  53 };
  54
  55 struct hal2_codec {
  56         struct snd_pcm_indirect pcm_indirect;
  57         struct snd_pcm_substream *substream;
  58
  59         unsigned char *buffer;
  60         dma_addr_t buffer_dma;
  61         struct hal2_desc *desc;
  62         dma_addr_t desc_dma;
  63         int desc_count;
  64         struct hal2_pbus pbus;
  65         int voices;                     /* mono/stereo */
  66         unsigned int sample_rate;
  67         unsigned int master;            /* Master frequency */
  68         unsigned short mod;             /* MOD value */
  69         unsigned short inc;             /* INC value */
  70 };
  71
  72 #define H2_MIX_OUTPUT_ATT       0
  73 #define H2_MIX_INPUT_GAIN       1
  74
  75 struct snd_hal2 {
  76         struct snd_card *card;
  77
  78         struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
  79         struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
  80         struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
  81         struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
  82
  83         struct hal2_codec dac;
  84         struct hal2_codec adc;
  85 };
  86
  87 #define H2_INDIRECT_WAIT(regs)  while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
  88
  89 #define H2_READ_ADDR(addr)      (addr | (1<<7))
  90 #define H2_WRITE_ADDR(addr)     (addr)
  91
  92 static inline u32 hal2_read(u32 *reg)
  93 {
  94         return __raw_readl(reg);
  95 }
  96
  97 static inline void hal2_write(u32 val, u32 *reg)
  98 {
  99         __raw_writel(val, reg);
 100 }
 101
 102
 103 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
 104 {
 105         u32 ret;
 106         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 107
 108         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 109         H2_INDIRECT_WAIT(regs);
 110         ret = hal2_read(&regs->idr0) & 0xffff;
 111         hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
 112         H2_INDIRECT_WAIT(regs);
 113         ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
 114         return ret;
 115 }
 116
 117 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
 118 {
 119         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 120
 121         hal2_write(val, &regs->idr0);
 122         hal2_write(0, &regs->idr1);
 123         hal2_write(0, &regs->idr2);
 124         hal2_write(0, &regs->idr3);
 125         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 126         H2_INDIRECT_WAIT(regs);
 127 }
 128
 129 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
 130 {
 131         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 132
 133         hal2_write(val & 0xffff, &regs->idr0);
 134         hal2_write(val >> 16, &regs->idr1);
 135         hal2_write(0, &regs->idr2);
 136         hal2_write(0, &regs->idr3);
 137         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 138         H2_INDIRECT_WAIT(regs);
 139 }
 140
 141 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
 142 {
 143         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 144
 145         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 146         H2_INDIRECT_WAIT(regs);
 147         hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
 148         hal2_write(0, &regs->idr1);
 149         hal2_write(0, &regs->idr2);
 150         hal2_write(0, &regs->idr3);
 151         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 152         H2_INDIRECT_WAIT(regs);
 153 }
 154
 155 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
 156 {
 157         struct hal2_ctl_regs *regs = hal2->ctl_regs;
 158
 159         hal2_write(H2_READ_ADDR(addr), &regs->iar);
 160         H2_INDIRECT_WAIT(regs);
 161         hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
 162         hal2_write(0, &regs->idr1);
 163         hal2_write(0, &regs->idr2);
 164         hal2_write(0, &regs->idr3);
 165         hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
 166         H2_INDIRECT_WAIT(regs);
 167 }
 168
 169 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
 170                                struct snd_ctl_elem_info *uinfo)
 171 {
 172         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 173         uinfo->count = 2;
 174         uinfo->value.integer.min = 0;
 175         switch ((int)kcontrol->private_value) {
 176         case H2_MIX_OUTPUT_ATT:
 177                 uinfo->value.integer.max = 31;
 178                 break;
 179         case H2_MIX_INPUT_GAIN:
 180                 uinfo->value.integer.max = 15;
 181                 break;
 182         }
 183         return 0;
 184 }
 185
 186 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
 187                                struct snd_ctl_elem_value *ucontrol)
 188 {
 189         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
 190         u32 tmp;
 191         int l, r;
 192
 193         switch ((int)kcontrol->private_value) {
 194         case H2_MIX_OUTPUT_ATT:
 195                 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
 196                 if (tmp & H2I_C2_MUTE) {
 197                         l = 0;
 198                         r = 0;
 199                 } else {
 200                         l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
 201                         r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
 202                 }
 203                 break;
 204         case H2_MIX_INPUT_GAIN:
 205                 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
 206                 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
 207                 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
 208                 break;
 209         default:
 210                 return -EINVAL;
 211         }
 212         ucontrol->value.integer.value[0] = l;
 213         ucontrol->value.integer.value[1] = r;
 214
 215         return 0;
 216 }
 217
 218 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
 219                          struct snd_ctl_elem_value *ucontrol)
 220 {
 221         struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
 222         u32 old, new;
 223         int l, r;
 224
 225         l = ucontrol->value.integer.value[0];
 226         r = ucontrol->value.integer.value[1];
 227
 228         switch ((int)kcontrol->private_value) {
 229         case H2_MIX_OUTPUT_ATT:
 230                 old = hal2_i_read32(hal2, H2I_DAC_C2);
 231                 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
 232                 if (l | r) {
 233                         l = 31 - l;
 234                         r = 31 - r;
 235                         new |= (l << H2I_C2_L_ATT_SHIFT);
 236                         new |= (r << H2I_C2_R_ATT_SHIFT);
 237                 } else
 238                         new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
 239                 hal2_i_write32(hal2, H2I_DAC_C2, new);
 240                 break;
 241         case H2_MIX_INPUT_GAIN:
 242                 old = hal2_i_read32(hal2, H2I_ADC_C2);
 243                 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
 244                 new |= (l << H2I_C2_L_GAIN_SHIFT);
 245                 new |= (r << H2I_C2_R_GAIN_SHIFT);
 246                 hal2_i_write32(hal2, H2I_ADC_C2, new);
 247                 break;
 248         default:
 249                 return -EINVAL;
 250         }
 251         return old != new;
 252 }
 253
 254 static const struct snd_kcontrol_new hal2_ctrl_headphone = {
 255         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
 256         .name           = "Headphone Playback Volume",
 257         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 258         .private_value  = H2_MIX_OUTPUT_ATT,
 259         .info           = hal2_gain_info,
 260         .get            = hal2_gain_get,
 261         .put            = hal2_gain_put,
 262 };
 263
 264 static const struct snd_kcontrol_new hal2_ctrl_mic = {
 265         .iface          = SNDRV_CTL_ELEM_IFACE_MIXER,
 266         .name           = "Mic Capture Volume",
 267         .access         = SNDRV_CTL_ELEM_ACCESS_READWRITE,
 268         .private_value  = H2_MIX_INPUT_GAIN,
 269         .info           = hal2_gain_info,
 270         .get            = hal2_gain_get,
 271         .put            = hal2_gain_put,
 272 };
 273
 274 static int hal2_mixer_create(struct snd_hal2 *hal2)
 275 {
 276         int err;
 277
 278         /* mute DAC */
 279         hal2_i_write32(hal2, H2I_DAC_C2,
 280                        H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
 281         /* mute ADC */
 282         hal2_i_write32(hal2, H2I_ADC_C2, 0);
 283
 284         err = snd_ctl_add(hal2->card,
 285                           snd_ctl_new1(&hal2_ctrl_headphone, hal2));
 286         if (err < 0)
 287                 return err;
 288
 289         err = snd_ctl_add(hal2->card,
 290                           snd_ctl_new1(&hal2_ctrl_mic, hal2));
 291         if (err < 0)
 292                 return err;
 293
 294         return 0;
 295 }
 296
 297 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
 298 {
 299         struct snd_hal2 *hal2 = dev_id;
 300         irqreturn_t ret = IRQ_NONE;
 301
 302         /* decide what caused this interrupt */
 303         if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
 304                 snd_pcm_period_elapsed(hal2->dac.substream);
 305                 ret = IRQ_HANDLED;
 306         }
 307         if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
 308                 snd_pcm_period_elapsed(hal2->adc.substream);
 309                 ret = IRQ_HANDLED;
 310         }
 311         return ret;
 312 }
 313
 314 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
 315 {
 316         unsigned short mod;
 317
 318         if (44100 % rate < 48000 % rate) {
 319                 mod = 4 * 44100 / rate;
 320                 codec->master = 44100;
 321         } else {
 322                 mod = 4 * 48000 / rate;
 323                 codec->master = 48000;
 324         }
 325
 326         codec->inc = 4;
 327         codec->mod = mod;
 328         rate = 4 * codec->master / mod;
 329
 330         return rate;
 331 }
 332
 333 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
 334 {
 335         unsigned int master = hal2->dac.master;
 336         int inc = hal2->dac.inc;
 337         int mod = hal2->dac.mod;
 338
 339         hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
 340         hal2_i_write32(hal2, H2I_BRES1_C2,
 341                        ((0xffff & (inc - mod - 1)) << 16) | inc);
 342 }
 343
 344 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
 345 {
 346         unsigned int master = hal2->adc.master;
 347         int inc = hal2->adc.inc;
 348         int mod = hal2->adc.mod;
 349
 350         hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
 351         hal2_i_write32(hal2, H2I_BRES2_C2,
 352                        ((0xffff & (inc - mod - 1)) << 16) | inc);
 353 }
 354
 355 static void hal2_setup_dac(struct snd_hal2 *hal2)
 356 {
 357         unsigned int fifobeg, fifoend, highwater, sample_size;
 358         struct hal2_pbus *pbus = &hal2->dac.pbus;
 359
 360         /* Now we set up some PBUS information. The PBUS needs information about
 361          * what portion of the fifo it will use. If it's receiving or
 362          * transmitting, and finally whether the stream is little endian or big
 363          * endian. The information is written later, on the start call.
 364          */
 365         sample_size = 2 * hal2->dac.voices;
 366         /* Fifo should be set to hold exactly four samples. Highwater mark
 367          * should be set to two samples. */
 368         highwater = (sample_size * 2) >> 1;     /* halfwords */
 369         fifobeg = 0;                            /* playback is first */
 370         fifoend = (sample_size * 4) >> 3;       /* doublewords */
 371         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
 372                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
 373         /* We disable everything before we do anything at all */
 374         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 375         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
 376         /* Setup the HAL2 for playback */
 377         hal2_set_dac_rate(hal2);
 378         /* Set endianess */
 379         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
 380         /* Set DMA bus */
 381         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
 382         /* We are using 1st Bresenham clock generator for playback */
 383         hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
 384                         | (1 << H2I_C1_CLKID_SHIFT)
 385                         | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
 386 }
 387
 388 static void hal2_setup_adc(struct snd_hal2 *hal2)
 389 {
 390         unsigned int fifobeg, fifoend, highwater, sample_size;
 391         struct hal2_pbus *pbus = &hal2->adc.pbus;
 392
 393         sample_size = 2 * hal2->adc.voices;
 394         highwater = (sample_size * 2) >> 1;             /* halfwords */
 395         fifobeg = (4 * 4) >> 3;                         /* record is second */
 396         fifoend = (4 * 4 + sample_size * 4) >> 3;       /* doublewords */
 397         pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
 398                      (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
 399         pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 400         hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
 401         /* Setup the HAL2 for record */
 402         hal2_set_adc_rate(hal2);
 403         /* Set endianess */
 404         hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
 405         /* Set DMA bus */
 406         hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
 407         /* We are using 2nd Bresenham clock generator for record */
 408         hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
 409                         | (2 << H2I_C1_CLKID_SHIFT)
 410                         | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
 411 }
 412
 413 static void hal2_start_dac(struct snd_hal2 *hal2)
 414 {
 415         struct hal2_pbus *pbus = &hal2->dac.pbus;
 416
 417         pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
 418         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
 419         /* enable DAC */
 420         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
 421 }
 422
 423 static void hal2_start_adc(struct snd_hal2 *hal2)
 424 {
 425         struct hal2_pbus *pbus = &hal2->adc.pbus;
 426
 427         pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
 428         pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
 429         /* enable ADC */
 430         hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
 431 }
 432
 433 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
 434 {
 435         hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 436         /* The HAL2 itself may remain enabled safely */
 437 }
 438
 439 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
 440 {
 441         hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
 442 }
 443
 444 static int hal2_alloc_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec,
 445                 enum dma_data_direction buffer_dir)
 446 {
 447         struct device *dev = hal2->card->dev;
 448         struct hal2_desc *desc;
 449         dma_addr_t desc_dma, buffer_dma;
 450         int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
 451         int i;
 452
 453         codec->buffer = dma_alloc_noncoherent(dev, H2_BUF_SIZE, &buffer_dma,
 454                                         buffer_dir, GFP_KERNEL);
 455         if (!codec->buffer)
 456                 return -ENOMEM;
 457         desc = dma_alloc_noncoherent(dev, count * sizeof(struct hal2_desc),
 458                         &desc_dma, DMA_BIDIRECTIONAL, GFP_KERNEL);
 459         if (!desc) {
 460                 dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, buffer_dma,
 461                                 buffer_dir);
 462                 return -ENOMEM;
 463         }
 464         codec->buffer_dma = buffer_dma;
 465         codec->desc_dma = desc_dma;
 466         codec->desc = desc;
 467         for (i = 0; i < count; i++) {
 468                 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
 469                 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
 470                 desc->desc.pnext = (i == count - 1) ?
 471                       desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
 472                 desc++;
 473         }
 474         dma_sync_single_for_device(dev, codec->desc_dma,
 475                                    count * sizeof(struct hal2_desc),
 476                                    DMA_BIDIRECTIONAL);
 477         codec->desc_count = count;
 478         return 0;
 479 }
 480
 481 static void hal2_free_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec,
 482                 enum dma_data_direction buffer_dir)
 483 {
 484         struct device *dev = hal2->card->dev;
 485
 486         dma_free_noncoherent(dev, codec->desc_count * sizeof(struct hal2_desc),
 487                        codec->desc, codec->desc_dma, DMA_BIDIRECTIONAL);
 488         dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, codec->buffer_dma,
 489                         buffer_dir);
 490 }
 491
 492 static const struct snd_pcm_hardware hal2_pcm_hw = {
 493         .info = (SNDRV_PCM_INFO_MMAP |
 494                  SNDRV_PCM_INFO_MMAP_VALID |
 495                  SNDRV_PCM_INFO_INTERLEAVED |
 496                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 497                  SNDRV_PCM_INFO_SYNC_APPLPTR),
 498         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 499         .rates =            SNDRV_PCM_RATE_8000_48000,
 500         .rate_min =         8000,
 501         .rate_max =         48000,
 502         .channels_min =     2,
 503         .channels_max =     2,
 504         .buffer_bytes_max = 65536,
 505         .period_bytes_min = 1024,
 506         .period_bytes_max = 65536,
 507         .periods_min =      2,
 508         .periods_max =      1024,
 509 };
 510
 511 static int hal2_playback_open(struct snd_pcm_substream *substream)
 512 {
 513         struct snd_pcm_runtime *runtime = substream->runtime;
 514         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 515
 516         runtime->hw = hal2_pcm_hw;
 517         return hal2_alloc_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE);
 518 }
 519
 520 static int hal2_playback_close(struct snd_pcm_substream *substream)
 521 {
 522         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 523
 524         hal2_free_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE);
 525         return 0;
 526 }
 527
 528 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
 529 {
 530         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 531         struct snd_pcm_runtime *runtime = substream->runtime;
 532         struct hal2_codec *dac = &hal2->dac;
 533
 534         dac->voices = runtime->channels;
 535         dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
 536         memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
 537         dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
 538         dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
 539         dac->pcm_indirect.hw_io = dac->buffer_dma;
 540         dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
 541         dac->substream = substream;
 542         hal2_setup_dac(hal2);
 543         return 0;
 544 }
 545
 546 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
 547 {
 548         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 549
 550         switch (cmd) {
 551         case SNDRV_PCM_TRIGGER_START:
 552                 hal2_start_dac(hal2);
 553                 break;
 554         case SNDRV_PCM_TRIGGER_STOP:
 555                 hal2_stop_dac(hal2);
 556                 break;
 557         default:
 558                 return -EINVAL;
 559         }
 560         return 0;
 561 }
 562
 563 static snd_pcm_uframes_t
 564 hal2_playback_pointer(struct snd_pcm_substream *substream)
 565 {
 566         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 567         struct hal2_codec *dac = &hal2->dac;
 568
 569         return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
 570                                                  dac->pbus.pbus->pbdma_bptr);
 571 }
 572
 573 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
 574                                    struct snd_pcm_indirect *rec, size_t bytes)
 575 {
 576         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 577         unsigned char *buf = hal2->dac.buffer + rec->hw_data;
 578
 579         memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
 580         dma_sync_single_for_device(hal2->card->dev,
 581                         hal2->dac.buffer_dma + rec->hw_data, bytes,
 582                         DMA_TO_DEVICE);
 583
 584 }
 585
 586 static int hal2_playback_ack(struct snd_pcm_substream *substream)
 587 {
 588         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 589         struct hal2_codec *dac = &hal2->dac;
 590
 591         return snd_pcm_indirect_playback_transfer(substream,
 592                                                   &dac->pcm_indirect,
 593                                                   hal2_playback_transfer);
 594 }
 595
 596 static int hal2_capture_open(struct snd_pcm_substream *substream)
 597 {
 598         struct snd_pcm_runtime *runtime = substream->runtime;
 599         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 600
 601         runtime->hw = hal2_pcm_hw;
 602         return hal2_alloc_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE);
 603 }
 604
 605 static int hal2_capture_close(struct snd_pcm_substream *substream)
 606 {
 607         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 608
 609         hal2_free_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE);
 610         return 0;
 611 }
 612
 613 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
 614 {
 615         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 616         struct snd_pcm_runtime *runtime = substream->runtime;
 617         struct hal2_codec *adc = &hal2->adc;
 618
 619         adc->voices = runtime->channels;
 620         adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
 621         memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
 622         adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
 623         adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
 624         adc->pcm_indirect.hw_io = adc->buffer_dma;
 625         adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
 626         adc->substream = substream;
 627         hal2_setup_adc(hal2);
 628         return 0;
 629 }
 630
 631 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
 632 {
 633         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 634
 635         switch (cmd) {
 636         case SNDRV_PCM_TRIGGER_START:
 637                 hal2_start_adc(hal2);
 638                 break;
 639         case SNDRV_PCM_TRIGGER_STOP:
 640                 hal2_stop_adc(hal2);
 641                 break;
 642         default:
 643                 return -EINVAL;
 644         }
 645         return 0;
 646 }
 647
 648 static snd_pcm_uframes_t
 649 hal2_capture_pointer(struct snd_pcm_substream *substream)
 650 {
 651         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 652         struct hal2_codec *adc = &hal2->adc;
 653
 654         return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
 655                                                 adc->pbus.pbus->pbdma_bptr);
 656 }
 657
 658 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
 659                                   struct snd_pcm_indirect *rec, size_t bytes)
 660 {
 661         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 662         unsigned char *buf = hal2->adc.buffer + rec->hw_data;
 663
 664         dma_sync_single_for_cpu(hal2->card->dev,
 665                         hal2->adc.buffer_dma + rec->hw_data, bytes,
 666                         DMA_FROM_DEVICE);
 667         memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
 668 }
 669
 670 static int hal2_capture_ack(struct snd_pcm_substream *substream)
 671 {
 672         struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
 673         struct hal2_codec *adc = &hal2->adc;
 674
 675         return snd_pcm_indirect_capture_transfer(substream,
 676                                                  &adc->pcm_indirect,
 677                                                  hal2_capture_transfer);
 678 }
 679
 680 static const struct snd_pcm_ops hal2_playback_ops = {
 681         .open =        hal2_playback_open,
 682         .close =       hal2_playback_close,
 683         .prepare =     hal2_playback_prepare,
 684         .trigger =     hal2_playback_trigger,
 685         .pointer =     hal2_playback_pointer,
 686         .ack =         hal2_playback_ack,
 687 };
 688
 689 static const struct snd_pcm_ops hal2_capture_ops = {
 690         .open =        hal2_capture_open,
 691         .close =       hal2_capture_close,
 692         .prepare =     hal2_capture_prepare,
 693         .trigger =     hal2_capture_trigger,
 694         .pointer =     hal2_capture_pointer,
 695         .ack =         hal2_capture_ack,
 696 };
 697
 698 static int hal2_pcm_create(struct snd_hal2 *hal2)
 699 {
 700         struct snd_pcm *pcm;
 701         int err;
 702
 703         /* create first pcm device with one outputs and one input */
 704         err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
 705         if (err < 0)
 706                 return err;
 707
 708         pcm->private_data = hal2;
 709         strcpy(pcm->name, "SGI HAL2");
 710
 711         /* set operators */
 712         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 713                         &hal2_playback_ops);
 714         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 715                         &hal2_capture_ops);
 716         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
 717                                        NULL, 0, 1024 * 1024);
 718
 719         return 0;
 720 }
 721
 722 static int hal2_dev_free(struct snd_device *device)
 723 {
 724         struct snd_hal2 *hal2 = device->device_data;
 725
 726         free_irq(SGI_HPCDMA_IRQ, hal2);
 727         kfree(hal2);
 728         return 0;
 729 }
 730
 731 static const struct snd_device_ops hal2_ops = {
 732         .dev_free = hal2_dev_free,
 733 };
 734
 735 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
 736                             int index)
 737 {
 738         codec->pbus.pbusnr = index;
 739         codec->pbus.pbus = &hpc3->pbdma[index];
 740 }
 741
 742 static int hal2_detect(struct snd_hal2 *hal2)
 743 {
 744         unsigned short board, major, minor;
 745         unsigned short rev;
 746
 747         /* reset HAL2 */
 748         hal2_write(0, &hal2->ctl_regs->isr);
 749
 750         /* release reset */
 751         hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
 752                    &hal2->ctl_regs->isr);
 753
 754
 755         hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
 756         rev = hal2_read(&hal2->ctl_regs->rev);
 757         if (rev & H2_REV_AUDIO_PRESENT)
 758                 return -ENODEV;
 759
 760         board = (rev & H2_REV_BOARD_M) >> 12;
 761         major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
 762         minor = (rev & H2_REV_MINOR_CHIP_M);
 763
 764         printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
 765                board, major, minor);
 766
 767         return 0;
 768 }
 769
 770 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
 771 {
 772         struct snd_hal2 *hal2;
 773         struct hpc3_regs *hpc3 = hpc3c0;
 774         int err;
 775
 776         hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
 777         if (!hal2)
 778                 return -ENOMEM;
 779
 780         hal2->card = card;
 781
 782         if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
 783                         "SGI HAL2", hal2)) {
 784                 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
 785                 kfree(hal2);
 786                 return -EAGAIN;
 787         }
 788
 789         hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
 790         hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
 791         hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
 792         hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
 793
 794         if (hal2_detect(hal2) < 0) {
 795                 kfree(hal2);
 796                 return -ENODEV;
 797         }
 798
 799         hal2_init_codec(&hal2->dac, hpc3, 0);
 800         hal2_init_codec(&hal2->adc, hpc3, 1);
 801
 802         /*
 803          * All DMA channel interfaces in HAL2 are designed to operate with
 804          * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
 805          * in D5. HAL2 is a 16-bit device which can accept both big and little
 806          * endian format. It assumes that even address bytes are on high
 807          * portion of PBUS (15:8) and assumes that HPC3 is programmed to
 808          * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
 809          */
 810 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
 811                           (2 << HPC3_DMACFG_D4R_SHIFT) | \
 812                           (2 << HPC3_DMACFG_D5R_SHIFT) | \
 813                           (0 << HPC3_DMACFG_D3W_SHIFT) | \
 814                           (2 << HPC3_DMACFG_D4W_SHIFT) | \
 815                           (2 << HPC3_DMACFG_D5W_SHIFT) | \
 816                                 HPC3_DMACFG_DS16 | \
 817                                 HPC3_DMACFG_EVENHI | \
 818                                 HPC3_DMACFG_RTIME | \
 819                           (8 << HPC3_DMACFG_BURST_SHIFT) | \
 820                                 HPC3_DMACFG_DRQLIVE)
 821         /*
 822          * Ignore what's mentioned in the specification and write value which
 823          * works in The Real World (TM)
 824          */
 825         hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
 826         hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
 827
 828         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
 829         if (err < 0) {
 830                 free_irq(SGI_HPCDMA_IRQ, hal2);
 831                 kfree(hal2);
 832                 return err;
 833         }
 834         *rchip = hal2;
 835         return 0;
 836 }
 837
 838 static int hal2_probe(struct platform_device *pdev)
 839 {
 840         struct snd_card *card;
 841         struct snd_hal2 *chip;
 842         int err;
 843
 844         err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
 845         if (err < 0)
 846                 return err;
 847
 848         err = hal2_create(card, &chip);
 849         if (err < 0) {
 850                 snd_card_free(card);
 851                 return err;
 852         }
 853
 854         err = hal2_pcm_create(chip);
 855         if (err < 0) {
 856                 snd_card_free(card);
 857                 return err;
 858         }
 859         err = hal2_mixer_create(chip);
 860         if (err < 0) {
 861                 snd_card_free(card);
 862                 return err;
 863         }
 864
 865         strcpy(card->driver, "SGI HAL2 Audio");
 866         strcpy(card->shortname, "SGI HAL2 Audio");
 867         sprintf(card->longname, "%s irq %i",
 868                 card->shortname,
 869                 SGI_HPCDMA_IRQ);
 870
 871         err = snd_card_register(card);
 872         if (err < 0) {
 873                 snd_card_free(card);
 874                 return err;
 875         }
 876         platform_set_drvdata(pdev, card);
 877         return 0;
 878 }
 879
 880 static int hal2_remove(struct platform_device *pdev)
 881 {
 882         struct snd_card *card = platform_get_drvdata(pdev);
 883
 884         snd_card_free(card);
 885         return 0;
 886 }
 887
 888 static struct platform_driver hal2_driver = {
 889         .probe  = hal2_probe,
 890         .remove = hal2_remove,
 891         .driver = {
 892                 .name   = "sgihal2",
 893         }
 894 };
 895
 896 module_platform_driver(hal2_driver);