sound/firewire/amdtp-stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
   4  * with Common Isochronous Packet (IEC 61883-1) headers
   5  *
   6  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/err.h>
  11 #include <linux/firewire.h>
  12 #include <linux/firewire-constants.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include "amdtp-stream.h"
  18
  19 #define TICKS_PER_CYCLE         3072
  20 #define CYCLES_PER_SECOND       8000
  21 #define TICKS_PER_SECOND        (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
  22
  23 #define OHCI_MAX_SECOND         8
  24
  25 /* Always support Linux tracing subsystem. */
  26 #define CREATE_TRACE_POINTS
  27 #include "amdtp-stream-trace.h"
  28
  29 #define TRANSFER_DELAY_TICKS    0x2e00 /* 479.17 microseconds */
  30
  31 /* isochronous header parameters */
  32 #define ISO_DATA_LENGTH_SHIFT   16
  33 #define TAG_NO_CIP_HEADER       0
  34 #define TAG_CIP                 1
  35
  36 /* common isochronous packet header parameters */
  37 #define CIP_EOH_SHIFT           31
  38 #define CIP_EOH                 (1u << CIP_EOH_SHIFT)
  39 #define CIP_EOH_MASK            0x80000000
  40 #define CIP_SID_SHIFT           24
  41 #define CIP_SID_MASK            0x3f000000
  42 #define CIP_DBS_MASK            0x00ff0000
  43 #define CIP_DBS_SHIFT           16
  44 #define CIP_SPH_MASK            0x00000400
  45 #define CIP_SPH_SHIFT           10
  46 #define CIP_DBC_MASK            0x000000ff
  47 #define CIP_FMT_SHIFT           24
  48 #define CIP_FMT_MASK            0x3f000000
  49 #define CIP_FDF_MASK            0x00ff0000
  50 #define CIP_FDF_SHIFT           16
  51 #define CIP_SYT_MASK            0x0000ffff
  52 #define CIP_SYT_NO_INFO         0xffff
  53
  54 /* Audio and Music transfer protocol specific parameters */
  55 #define CIP_FMT_AM              0x10
  56 #define AMDTP_FDF_NO_DATA       0xff
  57
  58 // For iso header, tstamp and 2 CIP header.
  59 #define IR_CTX_HEADER_SIZE_CIP          16
  60 // For iso header and tstamp.
  61 #define IR_CTX_HEADER_SIZE_NO_CIP       8
  62 #define HEADER_TSTAMP_MASK      0x0000ffff
  63
  64 #define IT_PKT_HEADER_SIZE_CIP          8 // For 2 CIP header.
  65 #define IT_PKT_HEADER_SIZE_NO_CIP       0 // Nothing.
  66
  67 static void pcm_period_work(struct work_struct *work);
  68
  69 /**
  70  * amdtp_stream_init - initialize an AMDTP stream structure
  71  * @s: the AMDTP stream to initialize
  72  * @unit: the target of the stream
  73  * @dir: the direction of stream
  74  * @flags: the packet transmission method to use
  75  * @fmt: the value of fmt field in CIP header
  76  * @process_ctx_payloads: callback handler to process payloads of isoc context
  77  * @protocol_size: the size to allocate newly for protocol
  78  */
  79 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
  80                       enum amdtp_stream_direction dir, enum cip_flags flags,
  81                       unsigned int fmt,
  82                       amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
  83                       unsigned int protocol_size)
  84 {
  85         if (process_ctx_payloads == NULL)
  86                 return -EINVAL;
  87
  88         s->protocol = kzalloc(protocol_size, GFP_KERNEL);
  89         if (!s->protocol)
  90                 return -ENOMEM;
  91
  92         s->unit = unit;
  93         s->direction = dir;
  94         s->flags = flags;
  95         s->context = ERR_PTR(-1);
  96         mutex_init(&s->mutex);
  97         INIT_WORK(&s->period_work, pcm_period_work);
  98         s->packet_index = 0;
  99
 100         init_waitqueue_head(&s->callback_wait);
 101         s->callbacked = false;
 102
 103         s->fmt = fmt;
 104         s->process_ctx_payloads = process_ctx_payloads;
 105
 106         if (dir == AMDTP_OUT_STREAM)
 107                 s->ctx_data.rx.syt_override = -1;
 108
 109         return 0;
 110 }
 111 EXPORT_SYMBOL(amdtp_stream_init);
 112
 113 /**
 114  * amdtp_stream_destroy - free stream resources
 115  * @s: the AMDTP stream to destroy
 116  */
 117 void amdtp_stream_destroy(struct amdtp_stream *s)
 118 {
 119         /* Not initialized. */
 120         if (s->protocol == NULL)
 121                 return;
 122
 123         WARN_ON(amdtp_stream_running(s));
 124         kfree(s->protocol);
 125         mutex_destroy(&s->mutex);
 126 }
 127 EXPORT_SYMBOL(amdtp_stream_destroy);
 128
 129 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
 130         [CIP_SFC_32000]  =  8,
 131         [CIP_SFC_44100]  =  8,
 132         [CIP_SFC_48000]  =  8,
 133         [CIP_SFC_88200]  = 16,
 134         [CIP_SFC_96000]  = 16,
 135         [CIP_SFC_176400] = 32,
 136         [CIP_SFC_192000] = 32,
 137 };
 138 EXPORT_SYMBOL(amdtp_syt_intervals);
 139
 140 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
 141         [CIP_SFC_32000]  =  32000,
 142         [CIP_SFC_44100]  =  44100,
 143         [CIP_SFC_48000]  =  48000,
 144         [CIP_SFC_88200]  =  88200,
 145         [CIP_SFC_96000]  =  96000,
 146         [CIP_SFC_176400] = 176400,
 147         [CIP_SFC_192000] = 192000,
 148 };
 149 EXPORT_SYMBOL(amdtp_rate_table);
 150
 151 static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
 152                                     struct snd_pcm_hw_rule *rule)
 153 {
 154         struct snd_interval *s = hw_param_interval(params, rule->var);
 155         const struct snd_interval *r =
 156                 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
 157         struct snd_interval t = {0};
 158         unsigned int step = 0;
 159         int i;
 160
 161         for (i = 0; i < CIP_SFC_COUNT; ++i) {
 162                 if (snd_interval_test(r, amdtp_rate_table[i]))
 163                         step = max(step, amdtp_syt_intervals[i]);
 164         }
 165
 166         t.min = roundup(s->min, step);
 167         t.max = rounddown(s->max, step);
 168         t.integer = 1;
 169
 170         return snd_interval_refine(s, &t);
 171 }
 172
 173 /**
 174  * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
 175  * @s:          the AMDTP stream, which must be initialized.
 176  * @runtime:    the PCM substream runtime
 177  */
 178 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
 179                                         struct snd_pcm_runtime *runtime)
 180 {
 181         struct snd_pcm_hardware *hw = &runtime->hw;
 182         unsigned int ctx_header_size;
 183         unsigned int maximum_usec_per_period;
 184         int err;
 185
 186         hw->info = SNDRV_PCM_INFO_BATCH |
 187                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
 188                    SNDRV_PCM_INFO_INTERLEAVED |
 189                    SNDRV_PCM_INFO_JOINT_DUPLEX |
 190                    SNDRV_PCM_INFO_MMAP |
 191                    SNDRV_PCM_INFO_MMAP_VALID;
 192
 193         /* SNDRV_PCM_INFO_BATCH */
 194         hw->periods_min = 2;
 195         hw->periods_max = UINT_MAX;
 196
 197         /* bytes for a frame */
 198         hw->period_bytes_min = 4 * hw->channels_max;
 199
 200         /* Just to prevent from allocating much pages. */
 201         hw->period_bytes_max = hw->period_bytes_min * 2048;
 202         hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
 203
 204         // Linux driver for 1394 OHCI controller voluntarily flushes isoc
 205         // context when total size of accumulated context header reaches
 206         // PAGE_SIZE. This kicks work for the isoc context and brings
 207         // callback in the middle of scheduled interrupts.
 208         // Although AMDTP streams in the same domain use the same events per
 209         // IRQ, use the largest size of context header between IT/IR contexts.
 210         // Here, use the value of context header in IR context is for both
 211         // contexts.
 212         if (!(s->flags & CIP_NO_HEADER))
 213                 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
 214         else
 215                 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
 216         maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
 217                                   CYCLES_PER_SECOND / ctx_header_size;
 218
 219         // In IEC 61883-6, one isoc packet can transfer events up to the value
 220         // of syt interval. This comes from the interval of isoc cycle. As 1394
 221         // OHCI controller can generate hardware IRQ per isoc packet, the
 222         // interval is 125 usec.
 223         // However, there are two ways of transmission in IEC 61883-6; blocking
 224         // and non-blocking modes. In blocking mode, the sequence of isoc packet
 225         // includes 'empty' or 'NODATA' packets which include no event. In
 226         // non-blocking mode, the number of events per packet is variable up to
 227         // the syt interval.
 228         // Due to the above protocol design, the minimum PCM frames per
 229         // interrupt should be double of the value of syt interval, thus it is
 230         // 250 usec.
 231         err = snd_pcm_hw_constraint_minmax(runtime,
 232                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 233                                            250, maximum_usec_per_period);
 234         if (err < 0)
 235                 goto end;
 236
 237         /* Non-Blocking stream has no more constraints */
 238         if (!(s->flags & CIP_BLOCKING))
 239                 goto end;
 240
 241         /*
 242          * One AMDTP packet can include some frames. In blocking mode, the
 243          * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
 244          * depending on its sampling rate. For accurate period interrupt, it's
 245          * preferrable to align period/buffer sizes to current SYT_INTERVAL.
 246          */
 247         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 248                                   apply_constraint_to_size, NULL,
 249                                   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 250                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 251         if (err < 0)
 252                 goto end;
 253         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 254                                   apply_constraint_to_size, NULL,
 255                                   SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 256                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 257         if (err < 0)
 258                 goto end;
 259 end:
 260         return err;
 261 }
 262 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
 263
 264 /**
 265  * amdtp_stream_set_parameters - set stream parameters
 266  * @s: the AMDTP stream to configure
 267  * @rate: the sample rate
 268  * @data_block_quadlets: the size of a data block in quadlet unit
 269  *
 270  * The parameters must be set before the stream is started, and must not be
 271  * changed while the stream is running.
 272  */
 273 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
 274                                 unsigned int data_block_quadlets)
 275 {
 276         unsigned int sfc;
 277
 278         for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
 279                 if (amdtp_rate_table[sfc] == rate)
 280                         break;
 281         }
 282         if (sfc == ARRAY_SIZE(amdtp_rate_table))
 283                 return -EINVAL;
 284
 285         s->sfc = sfc;
 286         s->data_block_quadlets = data_block_quadlets;
 287         s->syt_interval = amdtp_syt_intervals[sfc];
 288
 289         // default buffering in the device.
 290         if (s->direction == AMDTP_OUT_STREAM) {
 291                 s->ctx_data.rx.transfer_delay =
 292                                         TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
 293
 294                 if (s->flags & CIP_BLOCKING) {
 295                         // additional buffering needed to adjust for no-data
 296                         // packets.
 297                         s->ctx_data.rx.transfer_delay +=
 298                                 TICKS_PER_SECOND * s->syt_interval / rate;
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304 EXPORT_SYMBOL(amdtp_stream_set_parameters);
 305
 306 /**
 307  * amdtp_stream_get_max_payload - get the stream's packet size
 308  * @s: the AMDTP stream
 309  *
 310  * This function must not be called before the stream has been configured
 311  * with amdtp_stream_set_parameters().
 312  */
 313 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
 314 {
 315         unsigned int multiplier = 1;
 316         unsigned int cip_header_size = 0;
 317
 318         if (s->flags & CIP_JUMBO_PAYLOAD)
 319                 multiplier = 5;
 320         if (!(s->flags & CIP_NO_HEADER))
 321                 cip_header_size = sizeof(__be32) * 2;
 322
 323         return cip_header_size +
 324                 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
 325 }
 326 EXPORT_SYMBOL(amdtp_stream_get_max_payload);
 327
 328 /**
 329  * amdtp_stream_pcm_prepare - prepare PCM device for running
 330  * @s: the AMDTP stream
 331  *
 332  * This function should be called from the PCM device's .prepare callback.
 333  */
 334 void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
 335 {
 336         cancel_work_sync(&s->period_work);
 337         s->pcm_buffer_pointer = 0;
 338         s->pcm_period_pointer = 0;
 339 }
 340 EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
 341
 342 static unsigned int calculate_data_blocks(unsigned int *data_block_state,
 343                                 bool is_blocking, bool is_no_info,
 344                                 unsigned int syt_interval, enum cip_sfc sfc)
 345 {
 346         unsigned int data_blocks;
 347
 348         /* Blocking mode. */
 349         if (is_blocking) {
 350                 /* This module generate empty packet for 'no data'. */
 351                 if (is_no_info)
 352                         data_blocks = 0;
 353                 else
 354                         data_blocks = syt_interval;
 355         /* Non-blocking mode. */
 356         } else {
 357                 if (!cip_sfc_is_base_44100(sfc)) {
 358                         // Sample_rate / 8000 is an integer, and precomputed.
 359                         data_blocks = *data_block_state;
 360                 } else {
 361                         unsigned int phase = *data_block_state;
 362
 363                 /*
 364                  * This calculates the number of data blocks per packet so that
 365                  * 1) the overall rate is correct and exactly synchronized to
 366                  *    the bus clock, and
 367                  * 2) packets with a rounded-up number of blocks occur as early
 368                  *    as possible in the sequence (to prevent underruns of the
 369                  *    device's buffer).
 370                  */
 371                         if (sfc == CIP_SFC_44100)
 372                                 /* 6 6 5 6 5 6 5 ... */
 373                                 data_blocks = 5 + ((phase & 1) ^
 374                                                    (phase == 0 || phase >= 40));
 375                         else
 376                                 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
 377                                 data_blocks = 11 * (sfc >> 1) + (phase == 0);
 378                         if (++phase >= (80 >> (sfc >> 1)))
 379                                 phase = 0;
 380                         *data_block_state = phase;
 381                 }
 382         }
 383
 384         return data_blocks;
 385 }
 386
 387 static unsigned int calculate_syt_offset(unsigned int *last_syt_offset,
 388                         unsigned int *syt_offset_state, enum cip_sfc sfc)
 389 {
 390         unsigned int syt_offset;
 391
 392         if (*last_syt_offset < TICKS_PER_CYCLE) {
 393                 if (!cip_sfc_is_base_44100(sfc))
 394                         syt_offset = *last_syt_offset + *syt_offset_state;
 395                 else {
 396                 /*
 397                  * The time, in ticks, of the n'th SYT_INTERVAL sample is:
 398                  *   n * SYT_INTERVAL * 24576000 / sample_rate
 399                  * Modulo TICKS_PER_CYCLE, the difference between successive
 400                  * elements is about 1386.23.  Rounding the results of this
 401                  * formula to the SYT precision results in a sequence of
 402                  * differences that begins with:
 403                  *   1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
 404                  * This code generates _exactly_ the same sequence.
 405                  */
 406                         unsigned int phase = *syt_offset_state;
 407                         unsigned int index = phase % 13;
 408
 409                         syt_offset = *last_syt_offset;
 410                         syt_offset += 1386 + ((index && !(index & 3)) ||
 411                                               phase == 146);
 412                         if (++phase >= 147)
 413                                 phase = 0;
 414                         *syt_offset_state = phase;
 415                 }
 416         } else
 417                 syt_offset = *last_syt_offset - TICKS_PER_CYCLE;
 418         *last_syt_offset = syt_offset;
 419
 420         if (syt_offset >= TICKS_PER_CYCLE)
 421                 syt_offset = CIP_SYT_NO_INFO;
 422
 423         return syt_offset;
 424 }
 425
 426 static void update_pcm_pointers(struct amdtp_stream *s,
 427                                 struct snd_pcm_substream *pcm,
 428                                 unsigned int frames)
 429 {
 430         unsigned int ptr;
 431
 432         ptr = s->pcm_buffer_pointer + frames;
 433         if (ptr >= pcm->runtime->buffer_size)
 434                 ptr -= pcm->runtime->buffer_size;
 435         WRITE_ONCE(s->pcm_buffer_pointer, ptr);
 436
 437         s->pcm_period_pointer += frames;
 438         if (s->pcm_period_pointer >= pcm->runtime->period_size) {
 439                 s->pcm_period_pointer -= pcm->runtime->period_size;
 440                 queue_work(system_highpri_wq, &s->period_work);
 441         }
 442 }
 443
 444 static void pcm_period_work(struct work_struct *work)
 445 {
 446         struct amdtp_stream *s = container_of(work, struct amdtp_stream,
 447                                               period_work);
 448         struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
 449
 450         if (pcm)
 451                 snd_pcm_period_elapsed(pcm);
 452 }
 453
 454 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
 455                         bool sched_irq)
 456 {
 457         int err;
 458
 459         params->interrupt = sched_irq;
 460         params->tag = s->tag;
 461         params->sy = 0;
 462
 463         err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
 464                                    s->buffer.packets[s->packet_index].offset);
 465         if (err < 0) {
 466                 dev_err(&s->unit->device, "queueing error: %d\n", err);
 467                 goto end;
 468         }
 469
 470         if (++s->packet_index >= s->queue_size)
 471                 s->packet_index = 0;
 472 end:
 473         return err;
 474 }
 475
 476 static inline int queue_out_packet(struct amdtp_stream *s,
 477                                    struct fw_iso_packet *params, bool sched_irq)
 478 {
 479         params->skip =
 480                 !!(params->header_length == 0 && params->payload_length == 0);
 481         return queue_packet(s, params, sched_irq);
 482 }
 483
 484 static inline int queue_in_packet(struct amdtp_stream *s,
 485                                   struct fw_iso_packet *params)
 486 {
 487         // Queue one packet for IR context.
 488         params->header_length = s->ctx_data.tx.ctx_header_size;
 489         params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
 490         params->skip = false;
 491         return queue_packet(s, params, false);
 492 }
 493
 494 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
 495                         unsigned int data_block_counter, unsigned int syt)
 496 {
 497         cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
 498                                 (s->data_block_quadlets << CIP_DBS_SHIFT) |
 499                                 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
 500                                 data_block_counter);
 501         cip_header[1] = cpu_to_be32(CIP_EOH |
 502                         ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
 503                         ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
 504                         (syt & CIP_SYT_MASK));
 505 }
 506
 507 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
 508                                 struct fw_iso_packet *params,
 509                                 unsigned int data_blocks,
 510                                 unsigned int data_block_counter,
 511                                 unsigned int syt, unsigned int index)
 512 {
 513         unsigned int payload_length;
 514         __be32 *cip_header;
 515
 516         payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
 517         params->payload_length = payload_length;
 518
 519         if (!(s->flags & CIP_NO_HEADER)) {
 520                 cip_header = (__be32 *)params->header;
 521                 generate_cip_header(s, cip_header, data_block_counter, syt);
 522                 params->header_length = 2 * sizeof(__be32);
 523                 payload_length += params->header_length;
 524         } else {
 525                 cip_header = NULL;
 526         }
 527
 528         trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks,
 529                            data_block_counter, index);
 530 }
 531
 532 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
 533                             unsigned int payload_length,
 534                             unsigned int *data_blocks,
 535                             unsigned int *data_block_counter, unsigned int *syt)
 536 {
 537         u32 cip_header[2];
 538         unsigned int sph;
 539         unsigned int fmt;
 540         unsigned int fdf;
 541         unsigned int dbc;
 542         bool lost;
 543
 544         cip_header[0] = be32_to_cpu(buf[0]);
 545         cip_header[1] = be32_to_cpu(buf[1]);
 546
 547         /*
 548          * This module supports 'Two-quadlet CIP header with SYT field'.
 549          * For convenience, also check FMT field is AM824 or not.
 550          */
 551         if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
 552              ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
 553             (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
 554                 dev_info_ratelimited(&s->unit->device,
 555                                 "Invalid CIP header for AMDTP: %08X:%08X\n",
 556                                 cip_header[0], cip_header[1]);
 557                 return -EAGAIN;
 558         }
 559
 560         /* Check valid protocol or not. */
 561         sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
 562         fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
 563         if (sph != s->sph || fmt != s->fmt) {
 564                 dev_info_ratelimited(&s->unit->device,
 565                                      "Detect unexpected protocol: %08x %08x\n",
 566                                      cip_header[0], cip_header[1]);
 567                 return -EAGAIN;
 568         }
 569
 570         /* Calculate data blocks */
 571         fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
 572         if (payload_length < sizeof(__be32) * 2 ||
 573             (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
 574                 *data_blocks = 0;
 575         } else {
 576                 unsigned int data_block_quadlets =
 577                                 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
 578                 /* avoid division by zero */
 579                 if (data_block_quadlets == 0) {
 580                         dev_err(&s->unit->device,
 581                                 "Detect invalid value in dbs field: %08X\n",
 582                                 cip_header[0]);
 583                         return -EPROTO;
 584                 }
 585                 if (s->flags & CIP_WRONG_DBS)
 586                         data_block_quadlets = s->data_block_quadlets;
 587
 588                 *data_blocks = (payload_length / sizeof(__be32) - 2) /
 589                                                         data_block_quadlets;
 590         }
 591
 592         /* Check data block counter continuity */
 593         dbc = cip_header[0] & CIP_DBC_MASK;
 594         if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
 595             *data_block_counter != UINT_MAX)
 596                 dbc = *data_block_counter;
 597
 598         if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
 599             *data_block_counter == UINT_MAX) {
 600                 lost = false;
 601         } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
 602                 lost = dbc != *data_block_counter;
 603         } else {
 604                 unsigned int dbc_interval;
 605
 606                 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
 607                         dbc_interval = s->ctx_data.tx.dbc_interval;
 608                 else
 609                         dbc_interval = *data_blocks;
 610
 611                 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
 612         }
 613
 614         if (lost) {
 615                 dev_err(&s->unit->device,
 616                         "Detect discontinuity of CIP: %02X %02X\n",
 617                         *data_block_counter, dbc);
 618                 return -EIO;
 619         }
 620
 621         *data_block_counter = dbc;
 622
 623         *syt = cip_header[1] & CIP_SYT_MASK;
 624
 625         return 0;
 626 }
 627
 628 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
 629                                const __be32 *ctx_header,
 630                                unsigned int *payload_length,
 631                                unsigned int *data_blocks,
 632                                unsigned int *data_block_counter,
 633                                unsigned int *syt, unsigned int index)
 634 {
 635         const __be32 *cip_header;
 636         unsigned int cip_header_size;
 637         int err;
 638
 639         *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
 640
 641         if (!(s->flags & CIP_NO_HEADER))
 642                 cip_header_size = 8;
 643         else
 644                 cip_header_size = 0;
 645
 646         if (*payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
 647                 dev_err(&s->unit->device,
 648                         "Detect jumbo payload: %04x %04x\n",
 649                         *payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
 650                 return -EIO;
 651         }
 652
 653         if (cip_header_size > 0) {
 654                 cip_header = ctx_header + 2;
 655                 err = check_cip_header(s, cip_header, *payload_length,
 656                                        data_blocks, data_block_counter, syt);
 657                 if (err < 0)
 658                         return err;
 659         } else {
 660                 cip_header = NULL;
 661                 err = 0;
 662                 *data_blocks = *payload_length / sizeof(__be32) /
 663                                s->data_block_quadlets;
 664                 *syt = 0;
 665
 666                 if (*data_block_counter == UINT_MAX)
 667                         *data_block_counter = 0;
 668         }
 669
 670         trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks,
 671                            *data_block_counter, index);
 672
 673         return err;
 674 }
 675
 676 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
 677 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
 678 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
 679 static inline u32 compute_cycle_count(__be32 ctx_header_tstamp)
 680 {
 681         u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
 682         return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
 683 }
 684
 685 static inline u32 increment_cycle_count(u32 cycle, unsigned int addend)
 686 {
 687         cycle += addend;
 688         if (cycle >= OHCI_MAX_SECOND * CYCLES_PER_SECOND)
 689                 cycle -= OHCI_MAX_SECOND * CYCLES_PER_SECOND;
 690         return cycle;
 691 }
 692
 693 // Align to actual cycle count for the packet which is going to be scheduled.
 694 // This module queued the same number of isochronous cycle as the size of queue
 695 // to kip isochronous cycle, therefore it's OK to just increment the cycle by
 696 // the size of queue for scheduled cycle.
 697 static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp,
 698                                    unsigned int queue_size)
 699 {
 700         u32 cycle = compute_cycle_count(ctx_header_tstamp);
 701         return increment_cycle_count(cycle, queue_size);
 702 }
 703
 704 static int generate_device_pkt_descs(struct amdtp_stream *s,
 705                                      struct pkt_desc *descs,
 706                                      const __be32 *ctx_header,
 707                                      unsigned int packets)
 708 {
 709         unsigned int dbc = s->data_block_counter;
 710         int i;
 711         int err;
 712
 713         for (i = 0; i < packets; ++i) {
 714                 struct pkt_desc *desc = descs + i;
 715                 unsigned int index = (s->packet_index + i) % s->queue_size;
 716                 unsigned int cycle;
 717                 unsigned int payload_length;
 718                 unsigned int data_blocks;
 719                 unsigned int syt;
 720
 721                 cycle = compute_cycle_count(ctx_header[1]);
 722
 723                 err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length,
 724                                           &data_blocks, &dbc, &syt, i);
 725                 if (err < 0)
 726                         return err;
 727
 728                 desc->cycle = cycle;
 729                 desc->syt = syt;
 730                 desc->data_blocks = data_blocks;
 731                 desc->data_block_counter = dbc;
 732                 desc->ctx_payload = s->buffer.packets[index].buffer;
 733
 734                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 735                         dbc = (dbc + desc->data_blocks) & 0xff;
 736
 737                 ctx_header +=
 738                         s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
 739         }
 740
 741         s->data_block_counter = dbc;
 742
 743         return 0;
 744 }
 745
 746 static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle,
 747                                 unsigned int transfer_delay)
 748 {
 749         unsigned int syt;
 750
 751         syt_offset += transfer_delay;
 752         syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) |
 753               (syt_offset % TICKS_PER_CYCLE);
 754         return syt & CIP_SYT_MASK;
 755 }
 756
 757 static void generate_pkt_descs(struct amdtp_stream *s, struct pkt_desc *descs,
 758                                const __be32 *ctx_header, unsigned int packets,
 759                                const struct seq_desc *seq_descs,
 760                                unsigned int seq_size)
 761 {
 762         unsigned int dbc = s->data_block_counter;
 763         unsigned int seq_index = s->ctx_data.rx.seq_index;
 764         int i;
 765
 766         for (i = 0; i < packets; ++i) {
 767                 struct pkt_desc *desc = descs + i;
 768                 unsigned int index = (s->packet_index + i) % s->queue_size;
 769                 const struct seq_desc *seq = seq_descs + seq_index;
 770                 unsigned int syt;
 771
 772                 desc->cycle = compute_it_cycle(*ctx_header, s->queue_size);
 773
 774                 syt = seq->syt_offset;
 775                 if (syt != CIP_SYT_NO_INFO) {
 776                         syt = compute_syt(syt, desc->cycle,
 777                                           s->ctx_data.rx.transfer_delay);
 778                 }
 779                 desc->syt = syt;
 780                 desc->data_blocks = seq->data_blocks;
 781
 782                 if (s->flags & CIP_DBC_IS_END_EVENT)
 783                         dbc = (dbc + desc->data_blocks) & 0xff;
 784
 785                 desc->data_block_counter = dbc;
 786
 787                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 788                         dbc = (dbc + desc->data_blocks) & 0xff;
 789
 790                 desc->ctx_payload = s->buffer.packets[index].buffer;
 791
 792                 seq_index = (seq_index + 1) % seq_size;
 793
 794                 ++ctx_header;
 795         }
 796
 797         s->data_block_counter = dbc;
 798         s->ctx_data.rx.seq_index = seq_index;
 799 }
 800
 801 static inline void cancel_stream(struct amdtp_stream *s)
 802 {
 803         s->packet_index = -1;
 804         if (current_work() == &s->period_work)
 805                 amdtp_stream_pcm_abort(s);
 806         WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
 807 }
 808
 809 static void process_ctx_payloads(struct amdtp_stream *s,
 810                                  const struct pkt_desc *descs,
 811                                  unsigned int packets)
 812 {
 813         struct snd_pcm_substream *pcm;
 814         unsigned int pcm_frames;
 815
 816         pcm = READ_ONCE(s->pcm);
 817         pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm);
 818         if (pcm)
 819                 update_pcm_pointers(s, pcm, pcm_frames);
 820 }
 821
 822 static void out_stream_callback(struct fw_iso_context *context, u32 tstamp,
 823                                 size_t header_length, void *header,
 824                                 void *private_data)
 825 {
 826         struct amdtp_stream *s = private_data;
 827         const struct amdtp_domain *d = s->domain;
 828         const __be32 *ctx_header = header;
 829         unsigned int events_per_period = s->ctx_data.rx.events_per_period;
 830         unsigned int event_count = s->ctx_data.rx.event_count;
 831         unsigned int packets;
 832         int i;
 833
 834         if (s->packet_index < 0)
 835                 return;
 836
 837         // Calculate the number of packets in buffer and check XRUN.
 838         packets = header_length / sizeof(*ctx_header);
 839
 840         generate_pkt_descs(s, s->pkt_descs, ctx_header, packets, d->seq_descs,
 841                            d->seq_size);
 842
 843         process_ctx_payloads(s, s->pkt_descs, packets);
 844
 845         for (i = 0; i < packets; ++i) {
 846                 const struct pkt_desc *desc = s->pkt_descs + i;
 847                 unsigned int syt;
 848                 struct {
 849                         struct fw_iso_packet params;
 850                         __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)];
 851                 } template = { {0}, {0} };
 852                 bool sched_irq = false;
 853
 854                 if (s->ctx_data.rx.syt_override < 0)
 855                         syt = desc->syt;
 856                 else
 857                         syt = s->ctx_data.rx.syt_override;
 858
 859                 build_it_pkt_header(s, desc->cycle, &template.params,
 860                                     desc->data_blocks, desc->data_block_counter,
 861                                     syt, i);
 862
 863                 if (s == s->domain->irq_target) {
 864                         event_count += desc->data_blocks;
 865                         if (event_count >= events_per_period) {
 866                                 event_count -= events_per_period;
 867                                 sched_irq = true;
 868                         }
 869                 }
 870
 871                 if (queue_out_packet(s, &template.params, sched_irq) < 0) {
 872                         cancel_stream(s);
 873                         return;
 874                 }
 875         }
 876
 877         s->ctx_data.rx.event_count = event_count;
 878 }
 879
 880 static void in_stream_callback(struct fw_iso_context *context, u32 tstamp,
 881                                size_t header_length, void *header,
 882                                void *private_data)
 883 {
 884         struct amdtp_stream *s = private_data;
 885         __be32 *ctx_header = header;
 886         unsigned int packets;
 887         int i;
 888         int err;
 889
 890         if (s->packet_index < 0)
 891                 return;
 892
 893         // Calculate the number of packets in buffer and check XRUN.
 894         packets = header_length / s->ctx_data.tx.ctx_header_size;
 895
 896         err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets);
 897         if (err < 0) {
 898                 if (err != -EAGAIN) {
 899                         cancel_stream(s);
 900                         return;
 901                 }
 902         } else {
 903                 process_ctx_payloads(s, s->pkt_descs, packets);
 904         }
 905
 906         for (i = 0; i < packets; ++i) {
 907                 struct fw_iso_packet params = {0};
 908
 909                 if (queue_in_packet(s, &params) < 0) {
 910                         cancel_stream(s);
 911                         return;
 912                 }
 913         }
 914 }
 915
 916 static void pool_ideal_seq_descs(struct amdtp_domain *d, unsigned int packets)
 917 {
 918         struct amdtp_stream *irq_target = d->irq_target;
 919         unsigned int seq_tail = d->seq_tail;
 920         unsigned int seq_size = d->seq_size;
 921         unsigned int min_avail;
 922         struct amdtp_stream *s;
 923
 924         min_avail = d->seq_size;
 925         list_for_each_entry(s, &d->streams, list) {
 926                 unsigned int seq_index;
 927                 unsigned int avail;
 928
 929                 if (s->direction == AMDTP_IN_STREAM)
 930                         continue;
 931
 932                 seq_index = s->ctx_data.rx.seq_index;
 933                 avail = d->seq_tail;
 934                 if (seq_index > avail)
 935                         avail += d->seq_size;
 936                 avail -= seq_index;
 937
 938                 if (avail < min_avail)
 939                         min_avail = avail;
 940         }
 941
 942         while (min_avail < packets) {
 943                 struct seq_desc *desc = d->seq_descs + seq_tail;
 944
 945                 desc->syt_offset = calculate_syt_offset(&d->last_syt_offset,
 946                                         &d->syt_offset_state, irq_target->sfc);
 947                 desc->data_blocks = calculate_data_blocks(&d->data_block_state,
 948                                 !!(irq_target->flags & CIP_BLOCKING),
 949                                 desc->syt_offset == CIP_SYT_NO_INFO,
 950                                 irq_target->syt_interval, irq_target->sfc);
 951
 952                 ++seq_tail;
 953                 seq_tail %= seq_size;
 954
 955                 ++min_avail;
 956         }
 957
 958         d->seq_tail = seq_tail;
 959 }
 960
 961 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp,
 962                                 size_t header_length, void *header,
 963                                 void *private_data)
 964 {
 965         struct amdtp_stream *irq_target = private_data;
 966         struct amdtp_domain *d = irq_target->domain;
 967         unsigned int packets = header_length / sizeof(__be32);
 968         struct amdtp_stream *s;
 969
 970         // Record enough entries with extra 3 cycles at least.
 971         pool_ideal_seq_descs(d, packets + 3);
 972
 973         out_stream_callback(context, tstamp, header_length, header, irq_target);
 974         if (amdtp_streaming_error(irq_target))
 975                 goto error;
 976
 977         list_for_each_entry(s, &d->streams, list) {
 978                 if (s != irq_target && amdtp_stream_running(s)) {
 979                         fw_iso_context_flush_completions(s->context);
 980                         if (amdtp_streaming_error(s))
 981                                 goto error;
 982                 }
 983         }
 984
 985         return;
 986 error:
 987         if (amdtp_stream_running(irq_target))
 988                 cancel_stream(irq_target);
 989
 990         list_for_each_entry(s, &d->streams, list) {
 991                 if (amdtp_stream_running(s))
 992                         cancel_stream(s);
 993         }
 994 }
 995
 996 // this is executed one time.
 997 static void amdtp_stream_first_callback(struct fw_iso_context *context,
 998                                         u32 tstamp, size_t header_length,
 999                                         void *header, void *private_data)
1000 {
1001         struct amdtp_stream *s = private_data;
1002         const __be32 *ctx_header = header;
1003         u32 cycle;
1004
1005         /*
1006          * For in-stream, first packet has come.
1007          * For out-stream, prepared to transmit first packet
1008          */
1009         s->callbacked = true;
1010         wake_up(&s->callback_wait);
1011
1012         if (s->direction == AMDTP_IN_STREAM) {
1013                 cycle = compute_cycle_count(ctx_header[1]);
1014
1015                 context->callback.sc = in_stream_callback;
1016         } else {
1017                 cycle = compute_it_cycle(*ctx_header, s->queue_size);
1018
1019                 if (s == s->domain->irq_target)
1020                         context->callback.sc = irq_target_callback;
1021                 else
1022                         context->callback.sc = out_stream_callback;
1023         }
1024
1025         s->start_cycle = cycle;
1026
1027         context->callback.sc(context, tstamp, header_length, header, s);
1028 }
1029
1030 /**
1031  * amdtp_stream_start - start transferring packets
1032  * @s: the AMDTP stream to start
1033  * @channel: the isochronous channel on the bus
1034  * @speed: firewire speed code
1035  * @start_cycle: the isochronous cycle to start the context. Start immediately
1036  *               if negative value is given.
1037  * @queue_size: The number of packets in the queue.
1038  * @idle_irq_interval: the interval to queue packet during initial state.
1039  *
1040  * The stream cannot be started until it has been configured with
1041  * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
1042  * device can be started.
1043  */
1044 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
1045                               int start_cycle, unsigned int queue_size,
1046                               unsigned int idle_irq_interval)
1047 {
1048         bool is_irq_target = (s == s->domain->irq_target);
1049         unsigned int ctx_header_size;
1050         unsigned int max_ctx_payload_size;
1051         enum dma_data_direction dir;
1052         int type, tag, err;
1053
1054         mutex_lock(&s->mutex);
1055
1056         if (WARN_ON(amdtp_stream_running(s) ||
1057                     (s->data_block_quadlets < 1))) {
1058                 err = -EBADFD;
1059                 goto err_unlock;
1060         }
1061
1062         if (s->direction == AMDTP_IN_STREAM) {
1063                 // NOTE: IT context should be used for constant IRQ.
1064                 if (is_irq_target) {
1065                         err = -EINVAL;
1066                         goto err_unlock;
1067                 }
1068
1069                 s->data_block_counter = UINT_MAX;
1070         } else {
1071                 s->data_block_counter = 0;
1072         }
1073
1074         /* initialize packet buffer */
1075         if (s->direction == AMDTP_IN_STREAM) {
1076                 dir = DMA_FROM_DEVICE;
1077                 type = FW_ISO_CONTEXT_RECEIVE;
1078                 if (!(s->flags & CIP_NO_HEADER))
1079                         ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
1080                 else
1081                         ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
1082
1083                 max_ctx_payload_size = amdtp_stream_get_max_payload(s) -
1084                                        ctx_header_size;
1085         } else {
1086                 dir = DMA_TO_DEVICE;
1087                 type = FW_ISO_CONTEXT_TRANSMIT;
1088                 ctx_header_size = 0;    // No effect for IT context.
1089
1090                 max_ctx_payload_size = amdtp_stream_get_max_payload(s);
1091                 if (!(s->flags & CIP_NO_HEADER))
1092                         max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP;
1093         }
1094
1095         err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size,
1096                                       max_ctx_payload_size, dir);
1097         if (err < 0)
1098                 goto err_unlock;
1099         s->queue_size = queue_size;
1100
1101         s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1102                                           type, channel, speed, ctx_header_size,
1103                                           amdtp_stream_first_callback, s);
1104         if (IS_ERR(s->context)) {
1105                 err = PTR_ERR(s->context);
1106                 if (err == -EBUSY)
1107                         dev_err(&s->unit->device,
1108                                 "no free stream on this controller\n");
1109                 goto err_buffer;
1110         }
1111
1112         amdtp_stream_update(s);
1113
1114         if (s->direction == AMDTP_IN_STREAM) {
1115                 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1116                 s->ctx_data.tx.ctx_header_size = ctx_header_size;
1117         }
1118
1119         if (s->flags & CIP_NO_HEADER)
1120                 s->tag = TAG_NO_CIP_HEADER;
1121         else
1122                 s->tag = TAG_CIP;
1123
1124         s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs),
1125                                GFP_KERNEL);
1126         if (!s->pkt_descs) {
1127                 err = -ENOMEM;
1128                 goto err_context;
1129         }
1130
1131         s->packet_index = 0;
1132         do {
1133                 struct fw_iso_packet params;
1134
1135                 if (s->direction == AMDTP_IN_STREAM) {
1136                         err = queue_in_packet(s, &params);
1137                 } else {
1138                         bool sched_irq = false;
1139
1140                         params.header_length = 0;
1141                         params.payload_length = 0;
1142
1143                         if (is_irq_target) {
1144                                 sched_irq = !((s->packet_index + 1) %
1145                                               idle_irq_interval);
1146                         }
1147
1148                         err = queue_out_packet(s, &params, sched_irq);
1149                 }
1150                 if (err < 0)
1151                         goto err_pkt_descs;
1152         } while (s->packet_index > 0);
1153
1154         /* NOTE: TAG1 matches CIP. This just affects in stream. */
1155         tag = FW_ISO_CONTEXT_MATCH_TAG1;
1156         if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1157                 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1158
1159         s->callbacked = false;
1160         err = fw_iso_context_start(s->context, start_cycle, 0, tag);
1161         if (err < 0)
1162                 goto err_pkt_descs;
1163
1164         mutex_unlock(&s->mutex);
1165
1166         return 0;
1167 err_pkt_descs:
1168         kfree(s->pkt_descs);
1169 err_context:
1170         fw_iso_context_destroy(s->context);
1171         s->context = ERR_PTR(-1);
1172 err_buffer:
1173         iso_packets_buffer_destroy(&s->buffer, s->unit);
1174 err_unlock:
1175         mutex_unlock(&s->mutex);
1176
1177         return err;
1178 }
1179
1180 /**
1181  * amdtp_domain_stream_pcm_pointer - get the PCM buffer position
1182  * @d: the AMDTP domain.
1183  * @s: the AMDTP stream that transports the PCM data
1184  *
1185  * Returns the current buffer position, in frames.
1186  */
1187 unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
1188                                               struct amdtp_stream *s)
1189 {
1190         struct amdtp_stream *irq_target = d->irq_target;
1191
1192         if (irq_target && amdtp_stream_running(irq_target)) {
1193                 // This function is called in software IRQ context of
1194                 // period_work or process context.
1195                 //
1196                 // When the software IRQ context was scheduled by software IRQ
1197                 // context of IT contexts, queued packets were already handled.
1198                 // Therefore, no need to flush the queue in buffer furthermore.
1199                 //
1200                 // When the process context reach here, some packets will be
1201                 // already queued in the buffer. These packets should be handled
1202                 // immediately to keep better granularity of PCM pointer.
1203                 //
1204                 // Later, the process context will sometimes schedules software
1205                 // IRQ context of the period_work. Then, no need to flush the
1206                 // queue by the same reason as described in the above
1207                 if (current_work() != &s->period_work) {
1208                         // Queued packet should be processed without any kernel
1209                         // preemption to keep latency against bus cycle.
1210                         preempt_disable();
1211                         fw_iso_context_flush_completions(irq_target->context);
1212                         preempt_enable();
1213                 }
1214         }
1215
1216         return READ_ONCE(s->pcm_buffer_pointer);
1217 }
1218 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer);
1219
1220 /**
1221  * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames
1222  * @d: the AMDTP domain.
1223  * @s: the AMDTP stream that transfers the PCM frames
1224  *
1225  * Returns zero always.
1226  */
1227 int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s)
1228 {
1229         struct amdtp_stream *irq_target = d->irq_target;
1230
1231         // Process isochronous packets for recent isochronous cycle to handle
1232         // queued PCM frames.
1233         if (irq_target && amdtp_stream_running(irq_target)) {
1234                 // Queued packet should be processed without any kernel
1235                 // preemption to keep latency against bus cycle.
1236                 preempt_disable();
1237                 fw_iso_context_flush_completions(irq_target->context);
1238                 preempt_enable();
1239         }
1240
1241         return 0;
1242 }
1243 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack);
1244
1245 /**
1246  * amdtp_stream_update - update the stream after a bus reset
1247  * @s: the AMDTP stream
1248  */
1249 void amdtp_stream_update(struct amdtp_stream *s)
1250 {
1251         /* Precomputing. */
1252         WRITE_ONCE(s->source_node_id_field,
1253                    (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
1254 }
1255 EXPORT_SYMBOL(amdtp_stream_update);
1256
1257 /**
1258  * amdtp_stream_stop - stop sending packets
1259  * @s: the AMDTP stream to stop
1260  *
1261  * All PCM and MIDI devices of the stream must be stopped before the stream
1262  * itself can be stopped.
1263  */
1264 static void amdtp_stream_stop(struct amdtp_stream *s)
1265 {
1266         mutex_lock(&s->mutex);
1267
1268         if (!amdtp_stream_running(s)) {
1269                 mutex_unlock(&s->mutex);
1270                 return;
1271         }
1272
1273         cancel_work_sync(&s->period_work);
1274         fw_iso_context_stop(s->context);
1275         fw_iso_context_destroy(s->context);
1276         s->context = ERR_PTR(-1);
1277         iso_packets_buffer_destroy(&s->buffer, s->unit);
1278         kfree(s->pkt_descs);
1279
1280         s->callbacked = false;
1281
1282         mutex_unlock(&s->mutex);
1283 }
1284
1285 /**
1286  * amdtp_stream_pcm_abort - abort the running PCM device
1287  * @s: the AMDTP stream about to be stopped
1288  *
1289  * If the isochronous stream needs to be stopped asynchronously, call this
1290  * function first to stop the PCM device.
1291  */
1292 void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1293 {
1294         struct snd_pcm_substream *pcm;
1295
1296         pcm = READ_ONCE(s->pcm);
1297         if (pcm)
1298                 snd_pcm_stop_xrun(pcm);
1299 }
1300 EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1301
1302 /**
1303  * amdtp_domain_init - initialize an AMDTP domain structure
1304  * @d: the AMDTP domain to initialize.
1305  */
1306 int amdtp_domain_init(struct amdtp_domain *d)
1307 {
1308         INIT_LIST_HEAD(&d->streams);
1309
1310         d->events_per_period = 0;
1311
1312         d->seq_descs = NULL;
1313
1314         return 0;
1315 }
1316 EXPORT_SYMBOL_GPL(amdtp_domain_init);
1317
1318 /**
1319  * amdtp_domain_destroy - destroy an AMDTP domain structure
1320  * @d: the AMDTP domain to destroy.
1321  */
1322 void amdtp_domain_destroy(struct amdtp_domain *d)
1323 {
1324         // At present nothing to do.
1325         return;
1326 }
1327 EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1328
1329 /**
1330  * amdtp_domain_add_stream - register isoc context into the domain.
1331  * @d: the AMDTP domain.
1332  * @s: the AMDTP stream.
1333  * @channel: the isochronous channel on the bus.
1334  * @speed: firewire speed code.
1335  */
1336 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1337                             int channel, int speed)
1338 {
1339         struct amdtp_stream *tmp;
1340
1341         list_for_each_entry(tmp, &d->streams, list) {
1342                 if (s == tmp)
1343                         return -EBUSY;
1344         }
1345
1346         list_add(&s->list, &d->streams);
1347
1348         s->channel = channel;
1349         s->speed = speed;
1350         s->domain = d;
1351
1352         return 0;
1353 }
1354 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1355
1356 static int get_current_cycle_time(struct fw_card *fw_card, int *cur_cycle)
1357 {
1358         int generation;
1359         int rcode;
1360         __be32 reg;
1361         u32 data;
1362
1363         // This is a request to local 1394 OHCI controller and expected to
1364         // complete without any event waiting.
1365         generation = fw_card->generation;
1366         smp_rmb();      // node_id vs. generation.
1367         rcode = fw_run_transaction(fw_card, TCODE_READ_QUADLET_REQUEST,
1368                                    fw_card->node_id, generation, SCODE_100,
1369                                    CSR_REGISTER_BASE + CSR_CYCLE_TIME,
1370                                    &reg, sizeof(reg));
1371         if (rcode != RCODE_COMPLETE)
1372                 return -EIO;
1373
1374         data = be32_to_cpu(reg);
1375         *cur_cycle = data >> 12;
1376
1377         return 0;
1378 }
1379
1380 /**
1381  * amdtp_domain_start - start sending packets for isoc context in the domain.
1382  * @d: the AMDTP domain.
1383  * @ir_delay_cycle: the cycle delay to start all IR contexts.
1384  */
1385 int amdtp_domain_start(struct amdtp_domain *d, unsigned int ir_delay_cycle)
1386 {
1387         static const struct {
1388                 unsigned int data_block;
1389                 unsigned int syt_offset;
1390         } *entry, initial_state[] = {
1391                 [CIP_SFC_32000]  = {  4, 3072 },
1392                 [CIP_SFC_48000]  = {  6, 1024 },
1393                 [CIP_SFC_96000]  = { 12, 1024 },
1394                 [CIP_SFC_192000] = { 24, 1024 },
1395                 [CIP_SFC_44100]  = {  0,   67 },
1396                 [CIP_SFC_88200]  = {  0,   67 },
1397                 [CIP_SFC_176400] = {  0,   67 },
1398         };
1399         unsigned int events_per_buffer = d->events_per_buffer;
1400         unsigned int events_per_period = d->events_per_period;
1401         unsigned int idle_irq_interval;
1402         unsigned int queue_size;
1403         struct amdtp_stream *s;
1404         int cycle;
1405         int err;
1406
1407         // Select an IT context as IRQ target.
1408         list_for_each_entry(s, &d->streams, list) {
1409                 if (s->direction == AMDTP_OUT_STREAM)
1410                         break;
1411         }
1412         if (!s)
1413                 return -ENXIO;
1414         d->irq_target = s;
1415
1416         // This is a case that AMDTP streams in domain run just for MIDI
1417         // substream. Use the number of events equivalent to 10 msec as
1418         // interval of hardware IRQ.
1419         if (events_per_period == 0)
1420                 events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100;
1421         if (events_per_buffer == 0)
1422                 events_per_buffer = events_per_period * 3;
1423
1424         queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
1425                                   amdtp_rate_table[d->irq_target->sfc]);
1426
1427         d->seq_descs = kcalloc(queue_size, sizeof(*d->seq_descs), GFP_KERNEL);
1428         if (!d->seq_descs)
1429                 return -ENOMEM;
1430         d->seq_size = queue_size;
1431         d->seq_tail = 0;
1432
1433         entry = &initial_state[s->sfc];
1434         d->data_block_state = entry->data_block;
1435         d->syt_offset_state = entry->syt_offset;
1436         d->last_syt_offset = TICKS_PER_CYCLE;
1437
1438         if (ir_delay_cycle > 0) {
1439                 struct fw_card *fw_card = fw_parent_device(s->unit)->card;
1440
1441                 err = get_current_cycle_time(fw_card, &cycle);
1442                 if (err < 0)
1443                         goto error;
1444
1445                 // No need to care overflow in cycle field because of enough
1446                 // width.
1447                 cycle += ir_delay_cycle;
1448
1449                 // Round up to sec field.
1450                 if ((cycle & 0x00001fff) >= CYCLES_PER_SECOND) {
1451                         unsigned int sec;
1452
1453                         // The sec field can overflow.
1454                         sec = (cycle & 0xffffe000) >> 13;
1455                         cycle = (++sec << 13) |
1456                                 ((cycle & 0x00001fff) / CYCLES_PER_SECOND);
1457                 }
1458
1459                 // In OHCI 1394 specification, lower 2 bits are available for
1460                 // sec field.
1461                 cycle &= 0x00007fff;
1462         } else {
1463                 cycle = -1;
1464         }
1465
1466         list_for_each_entry(s, &d->streams, list) {
1467                 int cycle_match;
1468
1469                 if (s->direction == AMDTP_IN_STREAM) {
1470                         cycle_match = cycle;
1471                 } else {
1472                         // IT context starts immediately.
1473                         cycle_match = -1;
1474                         s->ctx_data.rx.seq_index = 0;
1475                 }
1476
1477                 if (s != d->irq_target) {
1478                         err = amdtp_stream_start(s, s->channel, s->speed,
1479                                                  cycle_match, queue_size, 0);
1480                         if (err < 0)
1481                                 goto error;
1482                 }
1483         }
1484
1485         s = d->irq_target;
1486         s->ctx_data.rx.events_per_period = events_per_period;
1487         s->ctx_data.rx.event_count = 0;
1488         s->ctx_data.rx.seq_index = 0;
1489
1490         idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
1491                                          amdtp_rate_table[d->irq_target->sfc]);
1492         err = amdtp_stream_start(s, s->channel, s->speed, -1, queue_size,
1493                                  idle_irq_interval);
1494         if (err < 0)
1495                 goto error;
1496
1497         return 0;
1498 error:
1499         list_for_each_entry(s, &d->streams, list)
1500                 amdtp_stream_stop(s);
1501         kfree(d->seq_descs);
1502         d->seq_descs = NULL;
1503         return err;
1504 }
1505 EXPORT_SYMBOL_GPL(amdtp_domain_start);
1506
1507 /**
1508  * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
1509  * @d: the AMDTP domain to which the isoc contexts belong.
1510  */
1511 void amdtp_domain_stop(struct amdtp_domain *d)
1512 {
1513         struct amdtp_stream *s, *next;
1514
1515         if (d->irq_target)
1516                 amdtp_stream_stop(d->irq_target);
1517
1518         list_for_each_entry_safe(s, next, &d->streams, list) {
1519                 list_del(&s->list);
1520
1521                 if (s != d->irq_target)
1522                         amdtp_stream_stop(s);
1523         }
1524
1525         d->events_per_period = 0;
1526         d->irq_target = NULL;
1527
1528         kfree(d->seq_descs);
1529         d->seq_descs = NULL;
1530 }
1531 EXPORT_SYMBOL_GPL(amdtp_domain_stop);