1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Intel Corp.
4 * Author: Jiang Liu <jiang.liu@linux.intel.com>
6 * This file is licensed under GPLv2.
8 * This file contains common code to support Message Signaled Interrupts for
9 * PCI compatible and non PCI compatible devices.
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/msi.h>
16 #include <linux/slab.h>
18 #include "internals.h"
21 * alloc_msi_entry - Allocate an initialized msi_desc
22 * @dev: Pointer to the device for which this is allocated
23 * @nvec: The number of vectors used in this entry
24 * @affinity: Optional pointer to an affinity mask array size of @nvec
26 * If @affinity is not %NULL then an affinity array[@nvec] is allocated
27 * and the affinity masks and flags from @affinity are copied.
29 * Return: pointer to allocated &msi_desc on success or %NULL on failure
31 struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
32 const struct irq_affinity_desc *affinity)
34 struct msi_desc *desc;
36 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
40 INIT_LIST_HEAD(&desc->list);
42 desc->nvec_used = nvec;
44 desc->affinity = kmemdup(affinity,
45 nvec * sizeof(*desc->affinity), GFP_KERNEL);
46 if (!desc->affinity) {
55 void free_msi_entry(struct msi_desc *entry)
57 kfree(entry->affinity);
61 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
66 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
68 struct msi_desc *entry = irq_get_msi_desc(irq);
70 __get_cached_msi_msg(entry, msg);
72 EXPORT_SYMBOL_GPL(get_cached_msi_msg);
74 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
75 static inline void irq_chip_write_msi_msg(struct irq_data *data,
78 data->chip->irq_write_msi_msg(data, msg);
81 static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
83 struct msi_domain_info *info = domain->host_data;
86 * If the MSI provider has messed with the second message and
87 * not advertized that it is level-capable, signal the breakage.
89 WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
90 (info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
91 (msg[1].address_lo || msg[1].address_hi || msg[1].data));
95 * msi_domain_set_affinity - Generic affinity setter function for MSI domains
96 * @irq_data: The irq data associated to the interrupt
97 * @mask: The affinity mask to set
98 * @force: Flag to enforce setting (disable online checks)
100 * Intended to be used by MSI interrupt controllers which are
101 * implemented with hierarchical domains.
103 * Return: IRQ_SET_MASK_* result code
105 int msi_domain_set_affinity(struct irq_data *irq_data,
106 const struct cpumask *mask, bool force)
108 struct irq_data *parent = irq_data->parent_data;
109 struct msi_msg msg[2] = { [1] = { }, };
112 ret = parent->chip->irq_set_affinity(parent, mask, force);
113 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
114 BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
115 msi_check_level(irq_data->domain, msg);
116 irq_chip_write_msi_msg(irq_data, msg);
122 static int msi_domain_activate(struct irq_domain *domain,
123 struct irq_data *irq_data, bool early)
125 struct msi_msg msg[2] = { [1] = { }, };
127 BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
128 msi_check_level(irq_data->domain, msg);
129 irq_chip_write_msi_msg(irq_data, msg);
133 static void msi_domain_deactivate(struct irq_domain *domain,
134 struct irq_data *irq_data)
136 struct msi_msg msg[2];
138 memset(msg, 0, sizeof(msg));
139 irq_chip_write_msi_msg(irq_data, msg);
142 static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
143 unsigned int nr_irqs, void *arg)
145 struct msi_domain_info *info = domain->host_data;
146 struct msi_domain_ops *ops = info->ops;
147 irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
150 if (irq_find_mapping(domain, hwirq) > 0)
153 if (domain->parent) {
154 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
159 for (i = 0; i < nr_irqs; i++) {
160 ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
163 for (i--; i > 0; i--)
164 ops->msi_free(domain, info, virq + i);
166 irq_domain_free_irqs_top(domain, virq, nr_irqs);
174 static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
175 unsigned int nr_irqs)
177 struct msi_domain_info *info = domain->host_data;
180 if (info->ops->msi_free) {
181 for (i = 0; i < nr_irqs; i++)
182 info->ops->msi_free(domain, info, virq + i);
184 irq_domain_free_irqs_top(domain, virq, nr_irqs);
187 static const struct irq_domain_ops msi_domain_ops = {
188 .alloc = msi_domain_alloc,
189 .free = msi_domain_free,
190 .activate = msi_domain_activate,
191 .deactivate = msi_domain_deactivate,
194 static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
195 msi_alloc_info_t *arg)
200 static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
201 int nvec, msi_alloc_info_t *arg)
203 memset(arg, 0, sizeof(*arg));
207 static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
208 struct msi_desc *desc)
213 static int msi_domain_ops_init(struct irq_domain *domain,
214 struct msi_domain_info *info,
215 unsigned int virq, irq_hw_number_t hwirq,
216 msi_alloc_info_t *arg)
218 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
220 if (info->handler && info->handler_name) {
221 __irq_set_handler(virq, info->handler, 0, info->handler_name);
222 if (info->handler_data)
223 irq_set_handler_data(virq, info->handler_data);
228 static int msi_domain_ops_check(struct irq_domain *domain,
229 struct msi_domain_info *info,
235 static struct msi_domain_ops msi_domain_ops_default = {
236 .get_hwirq = msi_domain_ops_get_hwirq,
237 .msi_init = msi_domain_ops_init,
238 .msi_check = msi_domain_ops_check,
239 .msi_prepare = msi_domain_ops_prepare,
240 .set_desc = msi_domain_ops_set_desc,
241 .domain_alloc_irqs = __msi_domain_alloc_irqs,
242 .domain_free_irqs = __msi_domain_free_irqs,
245 static void msi_domain_update_dom_ops(struct msi_domain_info *info)
247 struct msi_domain_ops *ops = info->ops;
250 info->ops = &msi_domain_ops_default;
254 if (ops->domain_alloc_irqs == NULL)
255 ops->domain_alloc_irqs = msi_domain_ops_default.domain_alloc_irqs;
256 if (ops->domain_free_irqs == NULL)
257 ops->domain_free_irqs = msi_domain_ops_default.domain_free_irqs;
259 if (!(info->flags & MSI_FLAG_USE_DEF_DOM_OPS))
262 if (ops->get_hwirq == NULL)
263 ops->get_hwirq = msi_domain_ops_default.get_hwirq;
264 if (ops->msi_init == NULL)
265 ops->msi_init = msi_domain_ops_default.msi_init;
266 if (ops->msi_check == NULL)
267 ops->msi_check = msi_domain_ops_default.msi_check;
268 if (ops->msi_prepare == NULL)
269 ops->msi_prepare = msi_domain_ops_default.msi_prepare;
270 if (ops->set_desc == NULL)
271 ops->set_desc = msi_domain_ops_default.set_desc;
274 static void msi_domain_update_chip_ops(struct msi_domain_info *info)
276 struct irq_chip *chip = info->chip;
278 BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
279 if (!chip->irq_set_affinity)
280 chip->irq_set_affinity = msi_domain_set_affinity;
284 * msi_create_irq_domain - Create an MSI interrupt domain
285 * @fwnode: Optional fwnode of the interrupt controller
286 * @info: MSI domain info
287 * @parent: Parent irq domain
289 * Return: pointer to the created &struct irq_domain or %NULL on failure
291 struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
292 struct msi_domain_info *info,
293 struct irq_domain *parent)
295 struct irq_domain *domain;
297 msi_domain_update_dom_ops(info);
298 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
299 msi_domain_update_chip_ops(info);
301 domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
302 fwnode, &msi_domain_ops, info);
304 if (domain && !domain->name && info->chip)
305 domain->name = info->chip->name;
310 int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
311 int nvec, msi_alloc_info_t *arg)
313 struct msi_domain_info *info = domain->host_data;
314 struct msi_domain_ops *ops = info->ops;
317 ret = ops->msi_check(domain, info, dev);
319 ret = ops->msi_prepare(domain, dev, nvec, arg);
324 int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
325 int virq, int nvec, msi_alloc_info_t *arg)
327 struct msi_domain_info *info = domain->host_data;
328 struct msi_domain_ops *ops = info->ops;
329 struct msi_desc *desc;
332 for_each_msi_entry(desc, dev) {
333 /* Don't even try the multi-MSI brain damage. */
334 if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
339 if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
342 ops->set_desc(arg, desc);
343 /* Assumes the domain mutex is held! */
344 ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
349 irq_set_msi_desc_off(desc->irq, 0, desc);
353 /* Mop up the damage */
354 for_each_msi_entry(desc, dev) {
355 if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
358 irq_domain_free_irqs_common(domain, desc->irq, 1);
366 * Carefully check whether the device can use reservation mode. If
367 * reservation mode is enabled then the early activation will assign a
368 * dummy vector to the device. If the PCI/MSI device does not support
369 * masking of the entry then this can result in spurious interrupts when
370 * the device driver is not absolutely careful. But even then a malfunction
371 * of the hardware could result in a spurious interrupt on the dummy vector
372 * and render the device unusable. If the entry can be masked then the core
373 * logic will prevent the spurious interrupt and reservation mode can be
374 * used. For now reservation mode is restricted to PCI/MSI.
376 static bool msi_check_reservation_mode(struct irq_domain *domain,
377 struct msi_domain_info *info,
380 struct msi_desc *desc;
382 switch(domain->bus_token) {
383 case DOMAIN_BUS_PCI_MSI:
384 case DOMAIN_BUS_VMD_MSI:
390 if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
393 if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
397 * Checking the first MSI descriptor is sufficient. MSIX supports
398 * masking and MSI does so when the maskbit is set.
400 desc = first_msi_entry(dev);
401 return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit;
404 int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
407 struct msi_domain_info *info = domain->host_data;
408 struct msi_domain_ops *ops = info->ops;
409 struct irq_data *irq_data;
410 struct msi_desc *desc;
411 msi_alloc_info_t arg = { };
415 ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
419 for_each_msi_entry(desc, dev) {
420 ops->set_desc(&arg, desc);
422 virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
423 dev_to_node(dev), &arg, false,
427 if (ops->handle_error)
428 ret = ops->handle_error(domain, desc, ret);
430 ops->msi_finish(&arg, ret);
434 for (i = 0; i < desc->nvec_used; i++) {
435 irq_set_msi_desc_off(virq, i, desc);
436 irq_debugfs_copy_devname(virq + i, dev);
441 ops->msi_finish(&arg, 0);
443 can_reserve = msi_check_reservation_mode(domain, info, dev);
446 * This flag is set by the PCI layer as we need to activate
447 * the MSI entries before the PCI layer enables MSI in the
448 * card. Otherwise the card latches a random msi message.
450 if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
453 for_each_msi_vector(desc, i, dev) {
454 if (desc->irq == i) {
456 dev_dbg(dev, "irq [%d-%d] for MSI\n",
457 virq, virq + desc->nvec_used - 1);
460 irq_data = irq_domain_get_irq_data(domain, i);
462 irqd_clr_can_reserve(irq_data);
463 if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK)
464 irqd_set_msi_nomask_quirk(irq_data);
466 ret = irq_domain_activate_irq(irq_data, can_reserve);
473 * If these interrupts use reservation mode, clear the activated bit
474 * so request_irq() will assign the final vector.
477 for_each_msi_vector(desc, i, dev) {
478 irq_data = irq_domain_get_irq_data(domain, i);
479 irqd_clr_activated(irq_data);
485 for_each_msi_vector(desc, i, dev) {
486 irq_data = irq_domain_get_irq_data(domain, i);
487 if (irqd_is_activated(irq_data))
488 irq_domain_deactivate_irq(irq_data);
490 msi_domain_free_irqs(domain, dev);
495 * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
496 * @domain: The domain to allocate from
497 * @dev: Pointer to device struct of the device for which the interrupts
499 * @nvec: The number of interrupts to allocate
501 * Return: %0 on success or an error code.
503 int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
506 struct msi_domain_info *info = domain->host_data;
507 struct msi_domain_ops *ops = info->ops;
509 return ops->domain_alloc_irqs(domain, dev, nvec);
512 void __msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
514 struct msi_desc *desc;
516 for_each_msi_entry(desc, dev) {
518 * We might have failed to allocate an MSI early
519 * enough that there is no IRQ associated to this
520 * entry. If that's the case, don't do anything.
523 irq_domain_free_irqs(desc->irq, desc->nvec_used);
530 * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated to @dev
531 * @domain: The domain to managing the interrupts
532 * @dev: Pointer to device struct of the device for which the interrupts
535 void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
537 struct msi_domain_info *info = domain->host_data;
538 struct msi_domain_ops *ops = info->ops;
540 return ops->domain_free_irqs(domain, dev);
544 * msi_get_domain_info - Get the MSI interrupt domain info for @domain
545 * @domain: The interrupt domain to retrieve data from
547 * Return: the pointer to the msi_domain_info stored in @domain->host_data.
549 struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
551 return (struct msi_domain_info *)domain->host_data;
554 #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */