1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2020 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/ioctl.h>
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
22 * 128 SOBs reserved for collective wait
23 * 16 SOBs reserved for sync stream
25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
28 * 64 monitors reserved for collective wait
29 * 8 monitors reserved for sync stream
31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
34 * Goya queue Numbering
36 * The external queues (PCI DMA channels) MUST be before the internal queues
37 * and each group (PCI DMA channels and internal) must be contiguous inside
38 * itself but there can be a gap between the two groups (although not
43 GOYA_QUEUE_ID_DMA_0 = 0,
44 GOYA_QUEUE_ID_DMA_1 = 1,
45 GOYA_QUEUE_ID_DMA_2 = 2,
46 GOYA_QUEUE_ID_DMA_3 = 3,
47 GOYA_QUEUE_ID_DMA_4 = 4,
48 GOYA_QUEUE_ID_CPU_PQ = 5,
49 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
50 GOYA_QUEUE_ID_TPC0 = 7,
51 GOYA_QUEUE_ID_TPC1 = 8,
52 GOYA_QUEUE_ID_TPC2 = 9,
53 GOYA_QUEUE_ID_TPC3 = 10,
54 GOYA_QUEUE_ID_TPC4 = 11,
55 GOYA_QUEUE_ID_TPC5 = 12,
56 GOYA_QUEUE_ID_TPC6 = 13,
57 GOYA_QUEUE_ID_TPC7 = 14,
62 * Gaudi queue Numbering
63 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*.
64 * Except one CPU queue, all the rest are internal queues.
68 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */
69 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */
70 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */
71 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */
72 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */
73 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */
74 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */
75 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */
76 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */
77 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
78 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
79 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
80 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */
81 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */
82 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */
83 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */
84 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */
85 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */
86 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */
87 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */
88 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */
89 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */
90 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */
91 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */
92 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */
93 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */
94 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */
95 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */
96 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */
97 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */
98 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */
99 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */
100 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */
101 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */
102 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */
103 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */
104 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */
105 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */
106 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */
107 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */
108 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */
109 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */
110 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */
111 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */
112 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */
113 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */
114 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */
115 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */
116 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */
117 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */
118 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */
119 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */
120 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */
121 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */
122 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */
123 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */
124 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */
125 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */
126 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */
127 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */
128 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */
129 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */
130 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */
131 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */
132 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */
133 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */
134 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */
135 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */
136 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */
137 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */
138 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */
139 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */
140 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */
141 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */
142 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */
143 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */
144 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */
145 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */
146 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */
147 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */
148 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */
149 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */
150 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */
151 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */
152 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */
153 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */
154 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */
155 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */
156 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */
157 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */
158 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */
159 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */
160 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */
161 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */
162 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */
163 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */
164 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */
165 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */
166 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */
167 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */
168 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */
169 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */
170 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */
171 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */
172 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */
173 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */
174 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */
175 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */
176 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */
177 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */
178 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */
179 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */
180 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */
187 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle'
190 enum goya_engine_id {
191 GOYA_ENGINE_ID_DMA_0 = 0,
192 GOYA_ENGINE_ID_DMA_1,
193 GOYA_ENGINE_ID_DMA_2,
194 GOYA_ENGINE_ID_DMA_3,
195 GOYA_ENGINE_ID_DMA_4,
196 GOYA_ENGINE_ID_MME_0,
197 GOYA_ENGINE_ID_TPC_0,
198 GOYA_ENGINE_ID_TPC_1,
199 GOYA_ENGINE_ID_TPC_2,
200 GOYA_ENGINE_ID_TPC_3,
201 GOYA_ENGINE_ID_TPC_4,
202 GOYA_ENGINE_ID_TPC_5,
203 GOYA_ENGINE_ID_TPC_6,
204 GOYA_ENGINE_ID_TPC_7,
208 enum gaudi_engine_id {
209 GAUDI_ENGINE_ID_DMA_0 = 0,
210 GAUDI_ENGINE_ID_DMA_1,
211 GAUDI_ENGINE_ID_DMA_2,
212 GAUDI_ENGINE_ID_DMA_3,
213 GAUDI_ENGINE_ID_DMA_4,
214 GAUDI_ENGINE_ID_DMA_5,
215 GAUDI_ENGINE_ID_DMA_6,
216 GAUDI_ENGINE_ID_DMA_7,
217 GAUDI_ENGINE_ID_MME_0,
218 GAUDI_ENGINE_ID_MME_1,
219 GAUDI_ENGINE_ID_MME_2,
220 GAUDI_ENGINE_ID_MME_3,
221 GAUDI_ENGINE_ID_TPC_0,
222 GAUDI_ENGINE_ID_TPC_1,
223 GAUDI_ENGINE_ID_TPC_2,
224 GAUDI_ENGINE_ID_TPC_3,
225 GAUDI_ENGINE_ID_TPC_4,
226 GAUDI_ENGINE_ID_TPC_5,
227 GAUDI_ENGINE_ID_TPC_6,
228 GAUDI_ENGINE_ID_TPC_7,
229 GAUDI_ENGINE_ID_NIC_0,
230 GAUDI_ENGINE_ID_NIC_1,
231 GAUDI_ENGINE_ID_NIC_2,
232 GAUDI_ENGINE_ID_NIC_3,
233 GAUDI_ENGINE_ID_NIC_4,
234 GAUDI_ENGINE_ID_NIC_5,
235 GAUDI_ENGINE_ID_NIC_6,
236 GAUDI_ENGINE_ID_NIC_7,
237 GAUDI_ENGINE_ID_NIC_8,
238 GAUDI_ENGINE_ID_NIC_9,
243 * ASIC specific PLL index
245 * Used to retrieve in frequency info of different IPs via
246 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be
247 * used as an index in struct hl_pll_frequency_info
250 enum hl_goya_pll_index {
261 enum hl_gaudi_pll_index {
262 HL_GAUDI_CPU_PLL = 0,
275 enum hl_device_status {
276 HL_DEVICE_STATUS_OPERATIONAL,
277 HL_DEVICE_STATUS_IN_RESET,
278 HL_DEVICE_STATUS_MALFUNCTION,
279 HL_DEVICE_STATUS_NEEDS_RESET
282 /* Opcode for management ioctl
284 * HW_IP_INFO - Receive information about different IP blocks in the
286 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event
287 * occurred since the last hard reset.
288 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the
289 * specific context. This is relevant only for devices
290 * where the dram is managed by the kernel driver
291 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each
293 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
294 * require an open context.
295 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
296 * over the last period specified by the user.
297 * The period can be between 100ms to 1s, in
298 * resolution of 100ms. The return value is a
299 * percentage of the utilization rate.
300 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
301 * event occurred since the driver was loaded.
302 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate
303 * of the device in MHz. The maximum clock rate is
304 * configurable via sysfs parameter
305 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset
306 * operations performed on the device since the last
307 * time the driver was loaded.
308 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time
309 * for synchronization.
310 * HL_INFO_CS_COUNTERS - Retrieve command submission counters
311 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters
312 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
313 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore
314 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption
315 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
316 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls
318 #define HL_INFO_HW_IP_INFO 0
319 #define HL_INFO_HW_EVENTS 1
320 #define HL_INFO_DRAM_USAGE 2
321 #define HL_INFO_HW_IDLE 3
322 #define HL_INFO_DEVICE_STATUS 4
323 #define HL_INFO_DEVICE_UTILIZATION 6
324 #define HL_INFO_HW_EVENTS_AGGREGATE 7
325 #define HL_INFO_CLK_RATE 8
326 #define HL_INFO_RESET_COUNT 9
327 #define HL_INFO_TIME_SYNC 10
328 #define HL_INFO_CS_COUNTERS 11
329 #define HL_INFO_PCI_COUNTERS 12
330 #define HL_INFO_CLK_THROTTLE_REASON 13
331 #define HL_INFO_SYNC_MANAGER 14
332 #define HL_INFO_TOTAL_ENERGY 15
333 #define HL_INFO_PLL_FREQUENCY 16
334 #define HL_INFO_POWER 17
335 #define HL_INFO_OPEN_STATS 18
337 #define HL_INFO_VERSION_MAX_LEN 128
338 #define HL_INFO_CARD_NAME_MAX_LEN 16
340 struct hl_info_hw_ip_info {
341 __u64 sram_base_address;
342 __u64 dram_base_address;
346 __u32 device_id; /* PCI Device ID */
347 __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */
349 __u16 first_available_interrupt_id;
352 __u32 psoc_pci_pll_nr;
353 __u32 psoc_pci_pll_nf;
354 __u32 psoc_pci_pll_od;
355 __u32 psoc_pci_pll_div_factor;
356 __u8 tpc_enabled_mask;
359 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
360 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
362 __u64 dram_page_size;
365 struct hl_info_dram_usage {
370 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2
372 struct hl_info_hw_idle {
375 * Bitmask of busy engines.
376 * Bits definition is according to `enum <chip>_enging_id'.
378 __u32 busy_engines_mask;
381 * Extended Bitmask of busy engines.
382 * Bits definition is according to `enum <chip>_enging_id'.
384 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
387 struct hl_info_device_status {
392 struct hl_info_device_utilization {
397 struct hl_info_clk_rate {
398 __u32 cur_clk_rate_mhz;
399 __u32 max_clk_rate_mhz;
402 struct hl_info_reset_count {
403 __u32 hard_reset_cnt;
404 __u32 soft_reset_cnt;
407 struct hl_info_time_sync {
413 * struct hl_info_pci_counters - pci counters
414 * @rx_throughput: PCI rx throughput KBps
415 * @tx_throughput: PCI tx throughput KBps
416 * @replay_cnt: PCI replay counter
418 struct hl_info_pci_counters {
424 #define HL_CLK_THROTTLE_POWER 0x1
425 #define HL_CLK_THROTTLE_THERMAL 0x2
428 * struct hl_info_clk_throttle - clock throttling reason
429 * @clk_throttling_reason: each bit represents a clk throttling reason
431 struct hl_info_clk_throttle {
432 __u32 clk_throttling_reason;
436 * struct hl_info_energy - device energy information
437 * @total_energy_consumption: total device energy consumption
439 struct hl_info_energy {
440 __u64 total_energy_consumption;
443 #define HL_PLL_NUM_OUTPUTS 4
445 struct hl_pll_frequency_info {
446 __u16 output[HL_PLL_NUM_OUTPUTS];
450 * struct hl_open_stats_info - device open statistics information
451 * @open_counter: ever growing counter, increased on each successful dev open
452 * @last_open_period_ms: duration (ms) device was open last time
454 struct hl_open_stats_info {
456 __u64 last_open_period_ms;
460 * struct hl_power_info - power information
461 * @power: power consumption
463 struct hl_power_info {
468 * struct hl_info_sync_manager - sync manager information
469 * @first_available_sync_object: first available sob
470 * @first_available_monitor: first available monitor
471 * @first_available_cq: first available cq
473 struct hl_info_sync_manager {
474 __u32 first_available_sync_object;
475 __u32 first_available_monitor;
476 __u32 first_available_cq;
481 * struct hl_info_cs_counters - command submission counters
482 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue
483 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue
484 * @total_parsing_drop_cnt: total dropped due to error in packet parsing
485 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing
486 * @total_queue_full_drop_cnt: total dropped due to queue full
487 * @ctx_queue_full_drop_cnt: context dropped due to queue full
488 * @total_device_in_reset_drop_cnt: total dropped due to device in reset
489 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
490 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
491 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
492 * @total_validation_drop_cnt: total dropped due to validation error
493 * @ctx_validation_drop_cnt: context dropped due to validation error
495 struct hl_info_cs_counters {
496 __u64 total_out_of_mem_drop_cnt;
497 __u64 ctx_out_of_mem_drop_cnt;
498 __u64 total_parsing_drop_cnt;
499 __u64 ctx_parsing_drop_cnt;
500 __u64 total_queue_full_drop_cnt;
501 __u64 ctx_queue_full_drop_cnt;
502 __u64 total_device_in_reset_drop_cnt;
503 __u64 ctx_device_in_reset_drop_cnt;
504 __u64 total_max_cs_in_flight_drop_cnt;
505 __u64 ctx_max_cs_in_flight_drop_cnt;
506 __u64 total_validation_drop_cnt;
507 __u64 ctx_validation_drop_cnt;
517 struct hl_info_args {
518 /* Location of relevant struct in userspace */
519 __u64 return_pointer;
521 * The size of the return value. Just like "size" in "snprintf",
522 * it limits how many bytes the kernel can write
524 * For hw_events array, the size should be
525 * hl_info_hw_ip_info.num_of_events * sizeof(__u32)
533 /* Dcore id for which the information is relevant.
534 * For Gaudi refer to 'enum gaudi_dcores'
537 /* Context ID - Currently not in use */
539 /* Period value for utilization rate (100ms - 1000ms, in 100ms
543 /* PLL frequency retrieval */
550 /* Opcode to create a new command buffer */
551 #define HL_CB_OP_CREATE 0
552 /* Opcode to destroy previously created command buffer */
553 #define HL_CB_OP_DESTROY 1
554 /* Opcode to retrieve information about a command buffer */
555 #define HL_CB_OP_INFO 2
557 /* 2MB minus 32 bytes for 2xMSG_PROT */
558 #define HL_MAX_CB_SIZE (0x200000 - 32)
560 /* Indicates whether the command buffer should be mapped to the device's MMU */
561 #define HL_CB_FLAGS_MAP 0x1
564 /* Handle of CB or 0 if we want to create one */
568 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
569 * will be allocated, regardless of this parameter's value, is PAGE_SIZE
572 /* Context ID - Currently not in use */
583 /* Information about CB */
585 /* Usage count of CB */
594 struct hl_cb_out out;
597 /* HL_CS_CHUNK_FLAGS_ values
599 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
600 * Indicates if the CB was allocated and mapped by userspace.
601 * User allocated CB is a command buffer allocated by the user, via malloc
602 * (or similar). After allocating the CB, the user invokes “memory ioctl”
603 * to map the user memory into a device virtual address. The user provides
604 * this address via the cb_handle field. The interface provides the
605 * ability to create a large CBs, Which aren’t limited to
606 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues
607 * throughput. This CB allocation method also reduces the use of Linux
608 * DMA-able memory pool. Which are limited and used by other Linux
611 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
614 * This structure size must always be fixed to 64-bytes for backward
619 /* For external queue, this represents a Handle of CB on the
621 * For internal queue in Goya, this represents an SRAM or
622 * a DRAM address of the internal CB. In Gaudi, this might also
623 * represent a mapped host address of the CB.
625 * A mapped host address is in the device address space, after
626 * a host address was mapped by the device MMU.
630 /* Relevant only when HL_CS_FLAGS_WAIT or
631 * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
632 * This holds address of array of u64 values that contain
633 * signal CS sequence numbers. The wait described by this job
634 * will listen on all those signals (wait event per signal)
636 __u64 signal_seq_arr;
639 /* Index of queue to put the CB on */
644 * Size of command buffer with valid packets
645 * Can be smaller then actual CB size
649 /* Relevant only when HL_CS_FLAGS_WAIT or
650 * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
651 * Number of entries in signal_seq_arr
653 __u32 num_signal_seq_arr;
656 /* HL_CS_CHUNK_FLAGS_* */
657 __u32 cs_chunk_flags;
659 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set.
660 * This holds the collective engine ID. The wait described by this job
661 * will sync with this engine and with all NICs before completion.
663 __u32 collective_engine_id;
665 /* Align structure to 64 bytes */
669 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
670 #define HL_CS_FLAGS_FORCE_RESTORE 0x1
671 #define HL_CS_FLAGS_SIGNAL 0x2
672 #define HL_CS_FLAGS_WAIT 0x4
673 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
674 #define HL_CS_FLAGS_TIMESTAMP 0x20
675 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
676 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
677 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
678 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
679 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
681 #define HL_CS_STATUS_SUCCESS 0
683 #define HL_MAX_JOBS_PER_CS 512
687 /* this holds address of array of hl_cs_chunk for restore phase */
688 __u64 chunks_restore;
690 /* holds address of array of hl_cs_chunk for execution phase */
691 __u64 chunks_execute;
693 /* Sequence number of a staged submission CS
694 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set
698 /* Number of chunks in restore phase array. Maximum number is
701 __u32 num_chunks_restore;
703 /* Number of chunks in execution array. Maximum number is
706 __u32 num_chunks_execute;
708 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT
716 /* Context ID - Currently not in use */
722 * seq holds the sequence number of the CS to pass to wait ioctl. All
723 * values are valid except for 0 and ULLONG_MAX
733 struct hl_cs_out out;
736 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
737 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
739 struct hl_wait_cs_in {
742 /* Command submission sequence number */
744 /* Absolute timeout to wait for command submission
751 /* User address for completion comparison.
752 * upon interrupt, driver will compare the value pointed
753 * by this address with the supplied target value.
754 * in order not to perform any comparison, set address
756 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
759 /* Target value for completion comparison */
761 /* Absolute timeout to wait for interrupt
764 __u32 interrupt_timeout_us;
768 /* Context ID - Currently not in use */
770 /* HL_WAIT_CS_FLAGS_*
771 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include
772 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order
773 * not to specify an interrupt id ,set mask to all 1s.
778 #define HL_WAIT_CS_STATUS_COMPLETED 0
779 #define HL_WAIT_CS_STATUS_BUSY 1
780 #define HL_WAIT_CS_STATUS_TIMEDOUT 2
781 #define HL_WAIT_CS_STATUS_ABORTED 3
782 #define HL_WAIT_CS_STATUS_INTERRUPTED 4
784 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
785 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
787 struct hl_wait_cs_out {
788 /* HL_WAIT_CS_STATUS_* */
790 /* HL_WAIT_CS_STATUS_FLAG* */
792 /* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set */
793 __s64 timestamp_nsec;
796 union hl_wait_cs_args {
797 struct hl_wait_cs_in in;
798 struct hl_wait_cs_out out;
801 /* Opcode to allocate device memory */
802 #define HL_MEM_OP_ALLOC 0
803 /* Opcode to free previously allocated device memory */
804 #define HL_MEM_OP_FREE 1
805 /* Opcode to map host and device memory */
806 #define HL_MEM_OP_MAP 2
807 /* Opcode to unmap previously mapped host and device memory */
808 #define HL_MEM_OP_UNMAP 3
809 /* Opcode to map a hw block */
810 #define HL_MEM_OP_MAP_BLOCK 4
813 #define HL_MEM_CONTIGUOUS 0x1
814 #define HL_MEM_SHARED 0x2
815 #define HL_MEM_USERPTR 0x4
819 /* HL_MEM_OP_ALLOC- allocate device memory */
825 /* HL_MEM_OP_FREE - free device memory */
827 /* Handle returned from HL_MEM_OP_ALLOC */
831 /* HL_MEM_OP_MAP - map device memory */
834 * Requested virtual address of mapped memory.
835 * The driver will try to map the requested region to
836 * this hint address, as long as the address is valid
837 * and not already mapped. The user should check the
838 * returned address of the IOCTL to make sure he got
839 * the hint address. Passing 0 here means that the
840 * driver will choose the address itself.
843 /* Handle returned from HL_MEM_OP_ALLOC */
847 /* HL_MEM_OP_MAP - map host memory */
849 /* Address of allocated host memory */
850 __u64 host_virt_addr;
852 * Requested virtual address of mapped memory.
853 * The driver will try to map the requested region to
854 * this hint address, as long as the address is valid
855 * and not already mapped. The user should check the
856 * returned address of the IOCTL to make sure he got
857 * the hint address. Passing 0 here means that the
858 * driver will choose the address itself.
861 /* Size of allocated host memory */
865 /* HL_MEM_OP_MAP_BLOCK - map a hw block */
868 * HW block address to map, a handle and size will be
869 * returned to the user and will be used to mmap the
870 * relevant block. Only addresses from configuration
876 /* HL_MEM_OP_UNMAP - unmap host memory */
878 /* Virtual address returned from HL_MEM_OP_MAP */
879 __u64 device_virt_addr;
887 /* Context ID - Currently not in use */
895 * Used for HL_MEM_OP_MAP as the virtual address that was
896 * assigned in the device VA space.
897 * A value of 0 means the requested operation failed.
899 __u64 device_virt_addr;
902 * Used in HL_MEM_OP_ALLOC
903 * This is the assigned handle for the allocated memory
909 * Used in HL_MEM_OP_MAP_BLOCK.
910 * This is the assigned handle for the mapped block
915 * Used in HL_MEM_OP_MAP_BLOCK
916 * This is the size of the mapped block
927 struct hl_mem_out out;
930 #define HL_DEBUG_MAX_AUX_VALUES 10
932 struct hl_debug_params_etr {
933 /* Address in memory to allocate buffer */
934 __u64 buffer_address;
936 /* Size of buffer to allocate */
939 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
944 struct hl_debug_params_etf {
945 /* Address in memory to allocate buffer */
946 __u64 buffer_address;
948 /* Size of buffer to allocate */
951 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
956 struct hl_debug_params_stm {
957 /* Two bit masks for HW event and Stimulus Port */
961 /* Trace source ID */
964 /* Frequency for the timestamp register */
968 struct hl_debug_params_bmon {
969 /* Two address ranges that the user can request to filter */
976 /* Capture window configuration */
980 /* Trace source ID */
985 struct hl_debug_params_spmu {
986 /* Event types selection */
987 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
989 /* Number of event types selection */
990 __u32 event_types_num;
994 /* Opcode for ETR component */
995 #define HL_DEBUG_OP_ETR 0
996 /* Opcode for ETF component */
997 #define HL_DEBUG_OP_ETF 1
998 /* Opcode for STM component */
999 #define HL_DEBUG_OP_STM 2
1000 /* Opcode for FUNNEL component */
1001 #define HL_DEBUG_OP_FUNNEL 3
1002 /* Opcode for BMON component */
1003 #define HL_DEBUG_OP_BMON 4
1004 /* Opcode for SPMU component */
1005 #define HL_DEBUG_OP_SPMU 5
1006 /* Opcode for timestamp (deprecated) */
1007 #define HL_DEBUG_OP_TIMESTAMP 6
1008 /* Opcode for setting the device into or out of debug mode. The enable
1009 * variable should be 1 for enabling debug mode and 0 for disabling it
1011 #define HL_DEBUG_OP_SET_MODE 7
1013 struct hl_debug_args {
1015 * Pointer to user input structure.
1016 * This field is relevant to specific opcodes.
1019 /* Pointer to user output structure */
1021 /* Size of user input structure */
1023 /* Size of user output structure */
1028 * Register index in the component, taken from the debug_regs_index enum
1029 * in the various ASIC header files
1032 /* Enable/disable */
1034 /* Context ID - Currently not in use */
1039 * Various information operations such as:
1040 * - H/W IP information
1041 * - Current dram usage
1043 * The user calls this IOCTL with an opcode that describes the required
1044 * information. The user should supply a pointer to a user-allocated memory
1045 * chunk, which will be filled by the driver with the requested information.
1047 * The user supplies the maximum amount of size to copy into the user's memory,
1048 * in order to prevent data corruption in case of differences between the
1049 * definitions of structures in kernel and userspace, e.g. in case of old
1050 * userspace and new kernel driver
1052 #define HL_IOCTL_INFO \
1053 _IOWR('H', 0x01, struct hl_info_args)
1057 * - Request a Command Buffer
1058 * - Destroy a Command Buffer
1060 * The command buffers are memory blocks that reside in DMA-able address
1061 * space and are physically contiguous so they can be accessed by the device
1062 * directly. They are allocated using the coherent DMA API.
1064 * When creating a new CB, the IOCTL returns a handle of it, and the user-space
1065 * process needs to use that handle to mmap the buffer so it can access them.
1067 * In some instances, the device must access the command buffer through the
1068 * device's MMU, and thus its memory should be mapped. In these cases, user can
1069 * indicate the driver that such a mapping is required.
1070 * The resulting device virtual address will be used internally by the driver,
1071 * and won't be returned to user.
1074 #define HL_IOCTL_CB \
1075 _IOWR('H', 0x02, union hl_cb_args)
1078 * Command Submission
1080 * To submit work to the device, the user need to call this IOCTL with a set
1081 * of JOBS. That set of JOBS constitutes a CS object.
1082 * Each JOB will be enqueued on a specific queue, according to the user's input.
1083 * There can be more then one JOB per queue.
1085 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase
1086 * and a second set is for "execution" phase.
1087 * The JOBS on the "restore" phase are enqueued only after context-switch
1088 * (or if its the first CS for this context). The user can also order the
1089 * driver to run the "restore" phase explicitly
1091 * There are two types of queues - external and internal. External queues
1092 * are DMA queues which transfer data from/to the Host. All other queues are
1093 * internal. The driver will get completion notifications from the device only
1094 * on JOBS which are enqueued in the external queues.
1096 * For jobs on external queues, the user needs to create command buffers
1097 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
1098 * internal queues, the user needs to prepare a "command buffer" with packets
1099 * on either the device SRAM/DRAM or the host, and give the device address of
1100 * that buffer to the CS ioctl.
1102 * This IOCTL is asynchronous in regard to the actual execution of the CS. This
1103 * means it returns immediately after ALL the JOBS were enqueued on their
1104 * relevant queues. Therefore, the user mustn't assume the CS has been completed
1105 * or has even started to execute.
1107 * Upon successful enqueue, the IOCTL returns a sequence number which the user
1108 * can use with the "Wait for CS" IOCTL to check whether the handle's CS
1109 * external JOBS have been completed. Note that if the CS has internal JOBS
1110 * which can execute AFTER the external JOBS have finished, the driver might
1111 * report that the CS has finished executing BEFORE the internal JOBS have
1112 * actually finished executing.
1114 * Even though the sequence number increments per CS, the user can NOT
1115 * automatically assume that if CS with sequence number N finished, then CS
1116 * with sequence number N-1 also finished. The user can make this assumption if
1117 * and only if CS N and CS N-1 are exactly the same (same CBs for the same
1120 #define HL_IOCTL_CS \
1121 _IOWR('H', 0x03, union hl_cs_args)
1124 * Wait for Command Submission
1126 * The user can call this IOCTL with a handle it received from the CS IOCTL
1127 * to wait until the handle's CS has finished executing. The user will wait
1128 * inside the kernel until the CS has finished or until the user-requested
1129 * timeout has expired.
1131 * If the timeout value is 0, the driver won't sleep at all. It will check
1132 * the status of the CS and return immediately
1134 * The return value of the IOCTL is a standard Linux error code. The possible
1137 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal
1138 * that the user process received
1139 * ETIMEDOUT - The CS has caused a timeout on the device
1140 * EIO - The CS was aborted (usually because the device was reset)
1141 * ENODEV - The device wants to do hard-reset (so user need to close FD)
1143 * The driver also returns a custom define inside the IOCTL which can be:
1145 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0)
1146 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0)
1147 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device
1149 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the
1150 * device was reset (EIO)
1151 * HL_WAIT_CS_STATUS_INTERRUPTED - Waiting for the CS was interrupted (EINTR)
1155 #define HL_IOCTL_WAIT_CS \
1156 _IOWR('H', 0x04, union hl_wait_cs_args)
1160 * - Map host memory to device MMU
1161 * - Unmap host memory from device MMU
1163 * This IOCTL allows the user to map host memory to the device MMU
1165 * For host memory, the IOCTL doesn't allocate memory. The user is supposed
1166 * to allocate the memory in user-space (malloc/new). The driver pins the
1167 * physical pages (up to the allowed limit by the OS), assigns a virtual
1168 * address in the device VA space and initializes the device MMU.
1170 * There is an option for the user to specify the requested virtual address.
1173 #define HL_IOCTL_MEMORY \
1174 _IOWR('H', 0x05, union hl_mem_args)
1178 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces
1180 * This IOCTL allows the user to get debug traces from the chip.
1182 * Before the user can send configuration requests of the various
1183 * debug/profile engines, it needs to set the device into debug mode.
1184 * This is because the debug/profile infrastructure is shared component in the
1185 * device and we can't allow multiple users to access it at the same time.
1187 * Once a user set the device into debug mode, the driver won't allow other
1188 * users to "work" with the device, i.e. open a FD. If there are multiple users
1189 * opened on the device, the driver won't allow any user to debug the device.
1191 * For each configuration request, the user needs to provide the register index
1192 * and essential data such as buffer address and size.
1194 * Once the user has finished using the debug/profile engines, he should
1195 * set the device into non-debug mode, i.e. disable debug mode.
1197 * The driver can decide to "kick out" the user if he abuses this interface.
1200 #define HL_IOCTL_DEBUG \
1201 _IOWR('H', 0x06, struct hl_debug_args)
1203 #define HL_COMMAND_START 0x01
1204 #define HL_COMMAND_END 0x07
1206 #endif /* HABANALABS_H_ */