1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
7 #include <linux/types.h>
12 /* Driver command error status */
14 IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
24 IDXD_SCMD_PERCPU_ERR = 0x80090000,
25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
26 IDXD_SCMD_CDEV_ERR = 0x800b0000,
27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
33 #define IDXD_SCMD_SOFTERR_MASK 0x80000000
34 #define IDXD_SCMD_SOFTERR_SHIFT 16
36 /* Descriptor flags */
37 #define IDXD_OP_FLAG_FENCE 0x0001
38 #define IDXD_OP_FLAG_BOF 0x0002
39 #define IDXD_OP_FLAG_CRAV 0x0004
40 #define IDXD_OP_FLAG_RCR 0x0008
41 #define IDXD_OP_FLAG_RCI 0x0010
42 #define IDXD_OP_FLAG_CRSTS 0x0020
43 #define IDXD_OP_FLAG_CR 0x0080
44 #define IDXD_OP_FLAG_CC 0x0100
45 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200
46 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400
47 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800
48 #define IDXD_OP_FLAG_CR_TCS 0x1000
49 #define IDXD_OP_FLAG_STORD 0x2000
50 #define IDXD_OP_FLAG_DRDBK 0x4000
51 #define IDXD_OP_FLAG_DSTS 0x8000
54 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
68 DSA_OPCODE_CRCGEN = 0x10,
74 DSA_OPCODE_CFLUSH = 0x20,
81 IAX_OPCODE_DECOMPRESS = 0x42,
85 /* Completion record status */
86 enum dsa_completion_status {
89 DSA_COMP_SUCCESS_PRED,
90 DSA_COMP_PAGE_FAULT_NOBOF,
91 DSA_COMP_PAGE_FAULT_IR,
93 DSA_COMP_BATCH_PAGE_FAULT,
94 DSA_COMP_DR_OFFSET_NOINC,
95 DSA_COMP_DR_OFFSET_ERANGE,
97 DSA_COMP_BAD_OPCODE = 0x10,
98 DSA_COMP_INVALID_FLAGS,
99 DSA_COMP_NOZERO_RESERVE,
100 DSA_COMP_XFER_ERANGE,
101 DSA_COMP_DESC_CNT_ERANGE,
103 DSA_COMP_OVERLAP_BUFFERS,
105 DSA_COMP_DESCLIST_ALIGN,
106 DSA_COMP_INT_HANDLE_INVAL,
111 DSA_COMP_TRAFFIC_CLASS_CONF,
112 DSA_COMP_PFAULT_RDBA,
115 DSA_COMP_TRANSLATION_FAIL,
118 enum iax_completion_status {
121 IAX_COMP_PAGE_FAULT_IR = 0x04,
122 IAX_COMP_OUTBUF_OVERFLOW,
123 IAX_COMP_BAD_OPCODE = 0x10,
124 IAX_COMP_INVALID_FLAGS,
125 IAX_COMP_NOZERO_RESERVE,
126 IAX_COMP_INVALID_SIZE,
127 IAX_COMP_OVERLAP_BUFFERS = 0x16,
128 IAX_COMP_INT_HANDLE_INVAL = 0x19,
133 IAX_COMP_TRAFFIC_CLASS_CONF,
134 IAX_COMP_PFAULT_RDBA,
137 IAX_COMP_TRANSLATION_FAIL,
138 IAX_COMP_PRS_TIMEOUT,
140 IAX_COMP_INVALID_COMP_FLAG = 0x30,
141 IAX_COMP_INVALID_FILTER_FLAG,
142 IAX_COMP_INVALID_NUM_ELEMS = 0x33,
145 #define DSA_COMP_STATUS_MASK 0x7f
146 #define DSA_COMP_STATUS_WRITE 0x80
154 uint64_t completion_addr;
157 uint64_t rdback_addr;
159 uint64_t desc_list_addr;
163 uint64_t rdback_addr2;
165 uint64_t comp_pattern;
174 uint8_t expected_res;
175 /* create delta record */
178 uint32_t max_delta_size;
180 uint8_t expected_res_mask;
182 uint32_t delta_rec_size;
190 /* DIF check or strip */
192 uint8_t src_dif_flags;
194 uint8_t dif_chk_flags;
195 uint8_t dif_chk_res2[5];
196 uint32_t chk_ref_tag_seed;
197 uint16_t chk_app_tag_mask;
198 uint16_t chk_app_tag_seed;
203 uint8_t dest_dif_flag;
204 uint8_t dif_ins_flags;
205 uint8_t dif_ins_res2[13];
206 uint32_t ins_ref_tag_seed;
207 uint16_t ins_app_tag_mask;
208 uint16_t ins_app_tag_seed;
212 uint8_t src_upd_flags;
213 uint8_t upd_dest_flags;
214 uint8_t dif_upd_flags;
215 uint8_t dif_upd_res[5];
216 uint32_t src_ref_tag_seed;
217 uint16_t src_app_tag_mask;
218 uint16_t src_app_tag_seed;
219 uint32_t dest_ref_tag_seed;
220 uint16_t dest_app_tag_mask;
221 uint16_t dest_app_tag_seed;
224 uint8_t op_specific[24];
226 } __attribute__((packed));
234 uint64_t completion_addr;
240 uint16_t compr_flags;
241 uint16_t decompr_flags;
244 uint32_t max_dst_size;
246 uint32_t filter_flags;
248 } __attribute__((packed));
250 struct dsa_raw_desc {
252 } __attribute__((packed));
255 * The status field will be modified by hardware, therefore it should be
256 * volatile and prevent the compiler from optimize the read.
258 struct dsa_completion_record {
259 volatile uint8_t status;
265 uint32_t bytes_completed;
270 uint32_t invalid_flags:24;
274 uint32_t delta_rec_size;
277 /* DIF check & strip */
279 uint32_t dif_chk_ref_tag;
280 uint16_t dif_chk_app_tag_mask;
281 uint16_t dif_chk_app_tag;
286 uint64_t dif_ins_res;
287 uint32_t dif_ins_ref_tag;
288 uint16_t dif_ins_app_tag_mask;
289 uint16_t dif_ins_app_tag;
294 uint32_t dif_upd_src_ref_tag;
295 uint16_t dif_upd_src_app_tag_mask;
296 uint16_t dif_upd_src_app_tag;
297 uint32_t dif_upd_dest_ref_tag;
298 uint16_t dif_upd_dest_app_tag_mask;
299 uint16_t dif_upd_dest_app_tag;
302 uint8_t op_specific[16];
304 } __attribute__((packed));
306 struct dsa_raw_completion_record {
308 } __attribute__((packed));
310 struct iax_completion_record {
311 volatile uint8_t status;
314 uint32_t bytes_completed;
316 uint32_t invalid_flags;
318 uint32_t output_size;
323 } __attribute__((packed));
325 struct iax_raw_completion_record {
327 } __attribute__((packed));