include/linux/mfd/ti-lmu-register.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * TI LMU (Lighting Management Unit) Device Register Map
   4  *
   5  * Copyright 2017 Texas Instruments
   6  *
   7  * Author: Milo Kim <milo.kim@ti.com>
   8  */
   9
  10 #ifndef __MFD_TI_LMU_REGISTER_H__
  11 #define __MFD_TI_LMU_REGISTER_H__
  12
  13 #include <linux/bitops.h>
  14
  15 /* LM3631 */
  16 #define LM3631_REG_DEVCTRL                      0x00
  17 #define LM3631_LCD_EN_MASK                      BIT(1)
  18 #define LM3631_BL_EN_MASK                       BIT(0)
  19
  20 #define LM3631_REG_BRT_LSB                      0x01
  21 #define LM3631_REG_BRT_MSB                      0x02
  22
  23 #define LM3631_REG_BL_CFG                       0x06
  24 #define LM3631_BL_CHANNEL_MASK                  BIT(3)
  25 #define LM3631_BL_DUAL_CHANNEL                  0
  26 #define LM3631_BL_SINGLE_CHANNEL                BIT(3)
  27 #define LM3631_MAP_MASK                         BIT(5)
  28 #define LM3631_EXPONENTIAL_MAP                  0
  29
  30 #define LM3631_REG_BRT_MODE                     0x08
  31 #define LM3631_MODE_MASK                        (BIT(1) | BIT(2) | BIT(3))
  32 #define LM3631_DEFAULT_MODE                     (BIT(1) | BIT(3))
  33
  34 #define LM3631_REG_SLOPE                        0x09
  35 #define LM3631_SLOPE_MASK                       0xF0
  36 #define LM3631_SLOPE_SHIFT                      4
  37
  38 #define LM3631_REG_LDO_CTRL1                    0x0A
  39 #define LM3631_EN_OREF_MASK                     BIT(0)
  40 #define LM3631_EN_VNEG_MASK                     BIT(1)
  41 #define LM3631_EN_VPOS_MASK                     BIT(2)
  42
  43 #define LM3631_REG_LDO_CTRL2                    0x0B
  44 #define LM3631_EN_CONT_MASK                     BIT(0)
  45
  46 #define LM3631_REG_VOUT_CONT                    0x0C
  47 #define LM3631_VOUT_CONT_MASK                   (BIT(6) | BIT(7))
  48
  49 #define LM3631_REG_VOUT_BOOST                   0x0C
  50 #define LM3631_REG_VOUT_POS                     0x0D
  51 #define LM3631_REG_VOUT_NEG                     0x0E
  52 #define LM3631_REG_VOUT_OREF                    0x0F
  53 #define LM3631_VOUT_MASK                        0x3F
  54
  55 #define LM3631_REG_ENTIME_VCONT                 0x0B
  56 #define LM3631_ENTIME_CONT_MASK                 0x70
  57
  58 #define LM3631_REG_ENTIME_VOREF                 0x0F
  59 #define LM3631_REG_ENTIME_VPOS                  0x10
  60 #define LM3631_REG_ENTIME_VNEG                  0x11
  61 #define LM3631_ENTIME_MASK                      0xF0
  62 #define LM3631_ENTIME_SHIFT                     4
  63
  64 #define LM3631_MAX_REG                          0x16
  65
  66 /* LM3632 */
  67 #define LM3632_REG_CONFIG1                      0x02
  68 #define LM3632_OVP_MASK                         (BIT(5) | BIT(6) | BIT(7))
  69 #define LM3632_OVP_25V                          BIT(6)
  70
  71 #define LM3632_REG_CONFIG2                      0x03
  72 #define LM3632_SWFREQ_MASK                      BIT(7)
  73 #define LM3632_SWFREQ_1MHZ                      BIT(7)
  74
  75 #define LM3632_REG_BRT_LSB                      0x04
  76 #define LM3632_REG_BRT_MSB                      0x05
  77
  78 #define LM3632_REG_IO_CTRL                      0x09
  79 #define LM3632_PWM_MASK                         BIT(6)
  80 #define LM3632_I2C_MODE                         0
  81 #define LM3632_PWM_MODE                         BIT(6)
  82
  83 #define LM3632_REG_ENABLE                       0x0A
  84 #define LM3632_BL_EN_MASK                       BIT(0)
  85 #define LM3632_BL_CHANNEL_MASK                  (BIT(3) | BIT(4))
  86 #define LM3632_BL_SINGLE_CHANNEL                        BIT(4)
  87 #define LM3632_BL_DUAL_CHANNEL                  BIT(3)
  88
  89 #define LM3632_REG_BIAS_CONFIG                  0x0C
  90 #define LM3632_EXT_EN_MASK                      BIT(0)
  91 #define LM3632_EN_VNEG_MASK                     BIT(1)
  92 #define LM3632_EN_VPOS_MASK                     BIT(2)
  93
  94 #define LM3632_REG_VOUT_BOOST                   0x0D
  95 #define LM3632_REG_VOUT_POS                     0x0E
  96 #define LM3632_REG_VOUT_NEG                     0x0F
  97 #define LM3632_VOUT_MASK                        0x3F
  98
  99 #define LM3632_MAX_REG                          0x10
 100
 101 /* LM3633 */
 102 #define LM3633_REG_HVLED_OUTPUT_CFG             0x10
 103 #define LM3633_HVLED1_CFG_MASK                  BIT(0)
 104 #define LM3633_HVLED2_CFG_MASK                  BIT(1)
 105 #define LM3633_HVLED3_CFG_MASK                  BIT(2)
 106 #define LM3633_HVLED1_CFG_SHIFT                 0
 107 #define LM3633_HVLED2_CFG_SHIFT                 1
 108 #define LM3633_HVLED3_CFG_SHIFT                 2
 109
 110 #define LM3633_REG_BANK_SEL                     0x11
 111
 112 #define LM3633_REG_BL0_RAMP                     0x12
 113 #define LM3633_REG_BL1_RAMP                     0x13
 114 #define LM3633_BL_RAMPUP_MASK                   0xF0
 115 #define LM3633_BL_RAMPUP_SHIFT                  4
 116 #define LM3633_BL_RAMPDN_MASK                   0x0F
 117 #define LM3633_BL_RAMPDN_SHIFT                  0
 118
 119 #define LM3633_REG_BL_RAMP_CONF                 0x1B
 120 #define LM3633_BL_RAMP_MASK                     0x0F
 121 #define LM3633_BL_RAMP_EACH                     0x05
 122
 123 #define LM3633_REG_PTN0_RAMP                    0x1C
 124 #define LM3633_REG_PTN1_RAMP                    0x1D
 125 #define LM3633_PTN_RAMPUP_MASK                  0x70
 126 #define LM3633_PTN_RAMPUP_SHIFT                 4
 127 #define LM3633_PTN_RAMPDN_MASK                  0x07
 128 #define LM3633_PTN_RAMPDN_SHIFT                 0
 129
 130 #define LM3633_REG_LED_MAPPING_MODE             0x1F
 131 #define LM3633_LED_EXPONENTIAL                  BIT(1)
 132
 133 #define LM3633_REG_IMAX_HVLED_A                 0x20
 134 #define LM3633_REG_IMAX_HVLED_B                 0x21
 135 #define LM3633_REG_IMAX_LVLED_BASE              0x22
 136
 137 #define LM3633_REG_BL_FEEDBACK_ENABLE           0x28
 138
 139 #define LM3633_REG_ENABLE                       0x2B
 140 #define LM3633_LED_BANK_OFFSET                  2
 141
 142 #define LM3633_REG_PATTERN                      0x2C
 143
 144 #define LM3633_REG_BOOST_CFG                    0x2D
 145 #define LM3633_OVP_MASK                         (BIT(1) | BIT(2))
 146 #define LM3633_OVP_40V                          0x6
 147
 148 #define LM3633_REG_PWM_CFG                      0x2F
 149 #define LM3633_PWM_A_MASK                       BIT(0)
 150 #define LM3633_PWM_B_MASK                       BIT(1)
 151
 152 #define LM3633_REG_BRT_HVLED_A_LSB              0x40
 153 #define LM3633_REG_BRT_HVLED_A_MSB              0x41
 154 #define LM3633_REG_BRT_HVLED_B_LSB              0x42
 155 #define LM3633_REG_BRT_HVLED_B_MSB              0x43
 156
 157 #define LM3633_REG_BRT_LVLED_BASE               0x44
 158
 159 #define LM3633_REG_PTN_DELAY                    0x50
 160
 161 #define LM3633_REG_PTN_LOWTIME                  0x51
 162
 163 #define LM3633_REG_PTN_HIGHTIME                 0x52
 164
 165 #define LM3633_REG_PTN_LOWBRT                   0x53
 166
 167 #define LM3633_REG_PTN_HIGHBRT                  LM3633_REG_BRT_LVLED_BASE
 168
 169 #define LM3633_REG_BL_OPEN_FAULT_STATUS         0xB0
 170
 171 #define LM3633_REG_BL_SHORT_FAULT_STATUS        0xB2
 172
 173 #define LM3633_REG_MONITOR_ENABLE               0xB4
 174
 175 #define LM3633_MAX_REG                          0xB4
 176
 177 /* LM3695 */
 178 #define LM3695_REG_GP                           0x10
 179 #define LM3695_BL_CHANNEL_MASK                  BIT(3)
 180 #define LM3695_BL_DUAL_CHANNEL                  0
 181 #define LM3695_BL_SINGLE_CHANNEL                        BIT(3)
 182 #define LM3695_BRT_RW_MASK                      BIT(2)
 183 #define LM3695_BL_EN_MASK                       BIT(0)
 184
 185 #define LM3695_REG_BRT_LSB                      0x13
 186 #define LM3695_REG_BRT_MSB                      0x14
 187
 188 #define LM3695_MAX_REG                          0x14
 189
 190 /* LM36274 */
 191 #define LM36274_REG_REV                         0x01
 192 #define LM36274_REG_BL_CFG_1                    0x02
 193 #define LM36274_REG_BL_CFG_2                    0x03
 194 #define LM36274_REG_BRT_LSB                     0x04
 195 #define LM36274_REG_BRT_MSB                     0x05
 196 #define LM36274_REG_BL_EN                       0x08
 197
 198 #define LM36274_REG_BIAS_CONFIG_1               0x09
 199 #define LM36274_EXT_EN_MASK                     BIT(0)
 200 #define LM36274_EN_VNEG_MASK                    BIT(1)
 201 #define LM36274_EN_VPOS_MASK                    BIT(2)
 202
 203 #define LM36274_REG_BIAS_CONFIG_2               0x0a
 204 #define LM36274_REG_BIAS_CONFIG_3               0x0b
 205 #define LM36274_REG_VOUT_BOOST                  0x0c
 206 #define LM36274_REG_VOUT_POS                    0x0d
 207 #define LM36274_REG_VOUT_NEG                    0x0e
 208 #define LM36274_VOUT_MASK                       0x3F
 209
 210 #define LM36274_MAX_REG                         0x13
 211
 212 #endif