include/linux/mfd/bd9571mwv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * ROHM BD9571MWV-M and BD9574MWF-M driver
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
   6  * Copyright (C) 2020 Renesas Electronics Corporation
   7  *
   8  * Based on the TPS65086 driver
   9  */
  10
  11 #ifndef __LINUX_MFD_BD9571MWV_H
  12 #define __LINUX_MFD_BD9571MWV_H
  13
  14 #include <linux/device.h>
  15 #include <linux/regmap.h>
  16
  17 /* List of registers for BD9571MWV and BD9574MWF */
  18 #define BD9571MWV_VENDOR_CODE                   0x00
  19 #define BD9571MWV_VENDOR_CODE_VAL               0xdb
  20 #define BD9571MWV_PRODUCT_CODE                  0x01
  21 #define BD9571MWV_PRODUCT_CODE_BD9571MWV        0x60
  22 #define BD9571MWV_PRODUCT_CODE_BD9574MWF        0x74
  23 #define BD9571MWV_PRODUCT_REVISION              0x02
  24
  25 #define BD9571MWV_I2C_FUSA_MODE                 0x10
  26 #define BD9571MWV_I2C_MD2_E1_BIT_1              0x11
  27 #define BD9571MWV_I2C_MD2_E1_BIT_2              0x12
  28
  29 #define BD9571MWV_BKUP_MODE_CNT                 0x20
  30 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK     GENMASK(3, 0)
  31 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0     BIT(0)
  32 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1     BIT(1)
  33 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C    BIT(2)
  34 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C    BIT(3)
  35 #define BD9571MWV_BKUP_MODE_STATUS              0x21
  36 #define BD9571MWV_BKUP_RECOVERY_CNT             0x22
  37 #define BD9571MWV_BKUP_CTRL_TIM_CNT             0x23
  38 #define BD9571MWV_WAITBKUP_WDT_CNT              0x24
  39 #define BD9571MWV_128H_TIM_CNT                  0x26
  40 #define BD9571MWV_QLLM_CNT                      0x27
  41
  42 #define BD9571MWV_AVS_SET_MONI                  0x31
  43 #define BD9571MWV_AVS_SET_MONI_MASK             0x3
  44 #define BD9571MWV_AVS_VD09_VID(n)               (0x32 + (n))
  45 #define BD9571MWV_AVS_DVFS_VID(n)               (0x36 + (n))
  46
  47 #define BD9571MWV_VD18_VID                      0x42
  48 #define BD9571MWV_VD25_VID                      0x43
  49 #define BD9571MWV_VD33_VID                      0x44
  50
  51 #define BD9571MWV_DVFS_VINIT                    0x50
  52 #define BD9574MWF_VD09_VINIT                    0x51
  53 #define BD9571MWV_DVFS_SETVMAX                  0x52
  54 #define BD9571MWV_DVFS_BOOSTVID                 0x53
  55 #define BD9571MWV_DVFS_SETVID                   0x54
  56 #define BD9571MWV_DVFS_MONIVDAC                 0x55
  57 #define BD9571MWV_DVFS_PGD_CNT                  0x56
  58
  59 #define BD9571MWV_GPIO_DIR                      0x60
  60 #define BD9571MWV_GPIO_OUT                      0x61
  61 #define BD9571MWV_GPIO_IN                       0x62
  62 #define BD9571MWV_GPIO_DEB                      0x63
  63 #define BD9571MWV_GPIO_INT_SET                  0x64
  64 #define BD9571MWV_GPIO_INT                      0x65
  65 #define BD9571MWV_GPIO_INTMASK                  0x66
  66 #define BD9574MWF_GPIO_MUX                      0x67
  67
  68 #define BD9571MWV_REG_KEEP(n)                   (0x70 + (n))
  69
  70 #define BD9571MWV_PMIC_INTERNAL_STATUS          0x80
  71 #define BD9571MWV_PROT_ERROR_STATUS0            0x81
  72 #define BD9571MWV_PROT_ERROR_STATUS1            0x82
  73 #define BD9571MWV_PROT_ERROR_STATUS2            0x83
  74 #define BD9571MWV_PROT_ERROR_STATUS3            0x84
  75 #define BD9571MWV_PROT_ERROR_STATUS4            0x85
  76 #define BD9574MWF_PROT_ERROR_STATUS5            0x86
  77 #define BD9574MWF_SYSTEM_ERROR_STATUS           0x87
  78
  79 #define BD9571MWV_INT_INTREQ                    0x90
  80 #define BD9571MWV_INT_INTREQ_MD1_INT            BIT(0)
  81 #define BD9571MWV_INT_INTREQ_MD2_E1_INT         BIT(1)
  82 #define BD9571MWV_INT_INTREQ_MD2_E2_INT         BIT(2)
  83 #define BD9571MWV_INT_INTREQ_PROT_ERR_INT       BIT(3)
  84 #define BD9571MWV_INT_INTREQ_GP_INT             BIT(4)
  85 #define BD9571MWV_INT_INTREQ_128H_OF_INT        BIT(5)
  86 #define BD9571MWV_INT_INTREQ_WDT_OF_INT         BIT(6)
  87 #define BD9571MWV_INT_INTREQ_BKUP_TRG_INT       BIT(7)
  88 #define BD9571MWV_INT_INTMASK                   0x91
  89
  90 #define BD9574MWF_SSCG_CNT                      0xA0
  91 #define BD9574MWF_POFFB_MRB                     0xA1
  92 #define BD9574MWF_SMRB_WR_PROT                  0xA2
  93 #define BD9574MWF_SMRB_ASSERT                   0xA3
  94 #define BD9574MWF_SMRB_STATUS                   0xA4
  95
  96 #define BD9571MWV_ACCESS_KEY                    0xff
  97
  98 /* Define the BD9571MWV IRQ numbers */
  99 enum bd9571mwv_irqs {
 100         BD9571MWV_IRQ_MD1,
 101         BD9571MWV_IRQ_MD2_E1,
 102         BD9571MWV_IRQ_MD2_E2,
 103         BD9571MWV_IRQ_PROT_ERR,
 104         BD9571MWV_IRQ_GP,
 105         BD9571MWV_IRQ_128H_OF,  /* BKUP_HOLD on BD9574MWF */
 106         BD9571MWV_IRQ_WDT_OF,
 107         BD9571MWV_IRQ_BKUP_TRG,
 108 };
 109 #endif /* __LINUX_MFD_BD9571MWV_H */