include/linux/mailbox/mtk-cmdq-mailbox.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  *
   5  */
   6
   7 #ifndef __MTK_CMDQ_MAILBOX_H__
   8 #define __MTK_CMDQ_MAILBOX_H__
   9
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12 #include <linux/types.h>
  13
  14 #define CMDQ_INST_SIZE                  8 /* instruction is 64-bit */
  15 #define CMDQ_SUBSYS_SHIFT               16
  16 #define CMDQ_OP_CODE_SHIFT              24
  17 #define CMDQ_JUMP_PASS                  CMDQ_INST_SIZE
  18
  19 #define CMDQ_WFE_UPDATE                 BIT(31)
  20 #define CMDQ_WFE_UPDATE_VALUE           BIT(16)
  21 #define CMDQ_WFE_WAIT                   BIT(15)
  22 #define CMDQ_WFE_WAIT_VALUE             0x1
  23
  24 /*
  25  * WFE arg_b
  26  * bit 0-11: wait value
  27  * bit 15: 1 - wait, 0 - no wait
  28  * bit 16-27: update value
  29  * bit 31: 1 - update, 0 - no update
  30  */
  31 #define CMDQ_WFE_OPTION                 (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
  32                                         CMDQ_WFE_WAIT_VALUE)
  33
  34 /** cmdq event maximum */
  35 #define CMDQ_MAX_EVENT                  0x3ff
  36
  37 /*
  38  * CMDQ_CODE_MASK:
  39  *   set write mask
  40  *   format: op mask
  41  * CMDQ_CODE_WRITE:
  42  *   write value into target register
  43  *   format: op subsys address value
  44  * CMDQ_CODE_JUMP:
  45  *   jump by offset
  46  *   format: op offset
  47  * CMDQ_CODE_WFE:
  48  *   wait for event and clear
  49  *   it is just clear if no wait
  50  *   format: [wait]  op event update:1 to_wait:1 wait:1
  51  *           [clear] op event update:1 to_wait:0 wait:0
  52  * CMDQ_CODE_EOC:
  53  *   end of command
  54  *   format: op irq_flag
  55  */
  56 enum cmdq_code {
  57         CMDQ_CODE_MASK = 0x02,
  58         CMDQ_CODE_WRITE = 0x04,
  59         CMDQ_CODE_POLL = 0x08,
  60         CMDQ_CODE_JUMP = 0x10,
  61         CMDQ_CODE_WFE = 0x20,
  62         CMDQ_CODE_EOC = 0x40,
  63         CMDQ_CODE_LOGIC = 0xa0,
  64 };
  65
  66 enum cmdq_cb_status {
  67         CMDQ_CB_NORMAL = 0,
  68         CMDQ_CB_ERROR
  69 };
  70
  71 struct cmdq_cb_data {
  72         enum cmdq_cb_status     sta;
  73         void                    *data;
  74 };
  75
  76 typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
  77
  78 struct cmdq_task_cb {
  79         cmdq_async_flush_cb     cb;
  80         void                    *data;
  81 };
  82
  83 struct cmdq_pkt {
  84         void                    *va_base;
  85         dma_addr_t              pa_base;
  86         size_t                  cmd_buf_size; /* command occupied size */
  87         size_t                  buf_size; /* real buffer size */
  88         struct cmdq_task_cb     cb;
  89         struct cmdq_task_cb     async_cb;
  90         void                    *cl;
  91 };
  92
  93 #endif /* __MTK_CMDQ_MAILBOX_H__ */