1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
21 enum gpio_lookup_flags;
25 #define GPIO_LINE_DIRECTION_IN 1
26 #define GPIO_LINE_DIRECTION_OUT 0
29 * struct gpio_irq_chip - GPIO interrupt controller
31 struct gpio_irq_chip {
35 * GPIO IRQ chip implementation, provided by GPIO driver.
37 struct irq_chip *chip;
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
45 struct irq_domain *domain;
50 * Table of interrupt domain operations for this IRQ chip.
52 const struct irq_domain_ops *domain_ops;
54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
61 struct fwnode_handle *fwnode;
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
71 struct irq_domain *parent_domain;
74 * @child_to_parent_hwirq:
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
97 * @populate_parent_alloc_arg :
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
110 * @child_offset_to_irq:
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
121 * @child_irq_domain_ops:
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
128 struct irq_domain_ops child_irq_domain_ops;
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
137 irq_flow_handler_t handler;
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
145 unsigned int default_type;
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 struct lock_class_key *lock_key;
157 * Per GPIO IRQ chip lockdep class for IRQ request.
159 struct lock_class_key *request_key;
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
167 irq_flow_handler_t parent_handler;
170 * @parent_handler_data:
172 * Data associated, and passed to, the handler for the parent
175 void *parent_handler_data;
180 * The number of interrupt parents of a GPIO chip.
182 unsigned int num_parents;
187 * A list of interrupt parents of a GPIO chip. This is owned by the
188 * driver, so the core will only reference this list, not modify it.
190 unsigned int *parents;
195 * A list of interrupt parents for each line of a GPIO chip.
202 * True if set the interrupt handling uses nested threads.
207 * @init_hw: optional routine to initialize hardware before
208 * an IRQ chip will be added. This is quite useful when
209 * a particular driver wants to clear IRQ related registers
210 * in order to avoid undesired events.
212 int (*init_hw)(struct gpio_chip *gc);
215 * @init_valid_mask: optional routine to initialize @valid_mask, to be
216 * used if not all GPIO lines are valid interrupts. Sometimes some
217 * lines just cannot fire interrupts, and this routine, when defined,
218 * is passed a bitmap in "valid_mask" and it will have ngpios
219 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
220 * then directly set some bits to "0" if they cannot be used for
223 void (*init_valid_mask)(struct gpio_chip *gc,
224 unsigned long *valid_mask,
225 unsigned int ngpios);
230 * If not %NULL, holds bitmask of GPIOs which are valid to be included
231 * in IRQ domain of the chip.
233 unsigned long *valid_mask;
238 * Required for static IRQ allocation. If set, irq_domain_add_simple()
239 * will allocate and map all IRQs during initialization.
246 * Store old irq_chip irq_enable callback
248 void (*irq_enable)(struct irq_data *data);
253 * Store old irq_chip irq_disable callback
255 void (*irq_disable)(struct irq_data *data);
259 * Store old irq_chip irq_unmask callback
261 void (*irq_unmask)(struct irq_data *data);
266 * Store old irq_chip irq_mask callback
268 void (*irq_mask)(struct irq_data *data);
272 * struct gpio_chip - abstract a GPIO controller
273 * @label: a functional name for the GPIO device, such as a part
274 * number or the name of the SoC IP-block implementing it.
275 * @gpiodev: the internal state holder, opaque struct
276 * @parent: optional parent device providing the GPIOs
277 * @owner: helps prevent removal of modules exporting active GPIOs
278 * @request: optional hook for chip-specific activation, such as
279 * enabling module power and clock; may sleep
280 * @free: optional hook for chip-specific deactivation, such as
281 * disabling module power and clock; may sleep
282 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
283 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
284 * or negative error. It is recommended to always implement this
285 * function, even on input-only or output-only gpio chips.
286 * @direction_input: configures signal "offset" as input, or returns error
287 * This can be omitted on input-only or output-only gpio chips.
288 * @direction_output: configures signal "offset" as output, or returns error
289 * This can be omitted on input-only or output-only gpio chips.
290 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
291 * @get_multiple: reads values for multiple signals defined by "mask" and
292 * stores them in "bits", returns 0 on success or negative error
293 * @set: assigns output value for signal "offset"
294 * @set_multiple: assigns output values for multiple signals defined by "mask"
295 * @set_config: optional hook for all kinds of settings. Uses the same
296 * packed config format as generic pinconf.
297 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
298 * implementation may not sleep
299 * @dbg_show: optional routine to show contents in debugfs; default code
300 * will be used when this is omitted, but custom code can show extra
301 * state (such as pullup/pulldown configuration).
302 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
303 * not all GPIOs are valid.
304 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
305 * requires special mapping of the pins that provides GPIO functionality.
306 * It is called after adding GPIO chip and before adding IRQ chip.
307 * @base: identifies the first GPIO number handled by this chip;
308 * or, if negative during registration, requests dynamic ID allocation.
309 * DEPRECATION: providing anything non-negative and nailing the base
310 * offset of GPIO chips is deprecated. Please pass -1 as base to
311 * let gpiolib select the chip base in all possible cases. We want to
312 * get rid of the static GPIO number space in the long run.
313 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
314 * handled is (base + ngpio - 1).
315 * @offset: when multiple gpio chips belong to the same device this
316 * can be used as offset within the device so friendly names can
317 * be properly assigned.
318 * @names: if set, must be an array of strings to use as alternative
319 * names for the GPIOs in this chip. Any entry in the array
320 * may be NULL if there is no alias for the GPIO, however the
321 * array must be @ngpio entries long. A name can include a single printk
322 * format specifier for an unsigned int. It is substituted by the actual
323 * number of the gpio.
324 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
325 * must while accessing GPIO expander chips over I2C or SPI. This
326 * implies that if the chip supports IRQs, these IRQs need to be threaded
327 * as the chip access may sleep when e.g. reading out the IRQ status
329 * @read_reg: reader function for generic GPIO
330 * @write_reg: writer function for generic GPIO
331 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
332 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
333 * generic GPIO core. It is for internal housekeeping only.
334 * @reg_dat: data (in) register for generic GPIO
335 * @reg_set: output set register (out=high) for generic GPIO
336 * @reg_clr: output clear register (out=low) for generic GPIO
337 * @reg_dir_out: direction out setting register for generic GPIO
338 * @reg_dir_in: direction in setting register for generic GPIO
339 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
340 * be read and we need to rely on out internal state tracking.
341 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
342 * <register width> * 8
343 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
344 * shadowed and real data registers writes together.
345 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
347 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
348 * direction safely. A "1" in this word means the line is set as
351 * A gpio_chip can help platforms abstract various sources of GPIOs so
352 * they can all be accessed through a common programming interface.
353 * Example sources would be SOC controllers, FPGAs, multifunction
354 * chips, dedicated GPIO expanders, and so on.
356 * Each chip controls a number of signals, identified in method calls
357 * by "offset" values in the range 0..(@ngpio - 1). When those signals
358 * are referenced through calls like gpio_get_value(gpio), the offset
359 * is calculated by subtracting @base from the gpio number.
363 struct gpio_device *gpiodev;
364 struct device *parent;
365 struct module *owner;
367 int (*request)(struct gpio_chip *gc,
368 unsigned int offset);
369 void (*free)(struct gpio_chip *gc,
370 unsigned int offset);
371 int (*get_direction)(struct gpio_chip *gc,
372 unsigned int offset);
373 int (*direction_input)(struct gpio_chip *gc,
374 unsigned int offset);
375 int (*direction_output)(struct gpio_chip *gc,
376 unsigned int offset, int value);
377 int (*get)(struct gpio_chip *gc,
378 unsigned int offset);
379 int (*get_multiple)(struct gpio_chip *gc,
381 unsigned long *bits);
382 void (*set)(struct gpio_chip *gc,
383 unsigned int offset, int value);
384 void (*set_multiple)(struct gpio_chip *gc,
386 unsigned long *bits);
387 int (*set_config)(struct gpio_chip *gc,
389 unsigned long config);
390 int (*to_irq)(struct gpio_chip *gc,
391 unsigned int offset);
393 void (*dbg_show)(struct seq_file *s,
394 struct gpio_chip *gc);
396 int (*init_valid_mask)(struct gpio_chip *gc,
397 unsigned long *valid_mask,
398 unsigned int ngpios);
400 int (*add_pin_ranges)(struct gpio_chip *gc);
405 const char *const *names;
408 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
409 unsigned long (*read_reg)(void __iomem *reg);
410 void (*write_reg)(void __iomem *reg, unsigned long data);
412 void __iomem *reg_dat;
413 void __iomem *reg_set;
414 void __iomem *reg_clr;
415 void __iomem *reg_dir_out;
416 void __iomem *reg_dir_in;
417 bool bgpio_dir_unreadable;
419 spinlock_t bgpio_lock;
420 unsigned long bgpio_data;
421 unsigned long bgpio_dir;
422 #endif /* CONFIG_GPIO_GENERIC */
424 #ifdef CONFIG_GPIOLIB_IRQCHIP
426 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
427 * to handle IRQs for most practical cases.
433 * Integrates interrupt chip functionality with the GPIO chip. Can be
434 * used to handle IRQs for most practical cases.
436 struct gpio_irq_chip irq;
437 #endif /* CONFIG_GPIOLIB_IRQCHIP */
442 * If not %NULL, holds bitmask of GPIOs which are valid to be used
445 unsigned long *valid_mask;
447 #if defined(CONFIG_OF_GPIO)
449 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
450 * the device tree automatically may have an OF translation
456 * Pointer to a device tree node representing this GPIO controller.
458 struct device_node *of_node;
463 * Number of cells used to form the GPIO specifier.
465 unsigned int of_gpio_n_cells;
470 * Callback to translate a device tree GPIO specifier into a chip-
471 * relative GPIO number and flags.
473 int (*of_xlate)(struct gpio_chip *gc,
474 const struct of_phandle_args *gpiospec, u32 *flags);
475 #endif /* CONFIG_OF_GPIO */
478 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
479 unsigned int offset);
482 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
483 * @chip: the chip to query
485 * @base: first GPIO in the range
486 * @size: amount of GPIOs to check starting from @base
487 * @label: label of current GPIO
489 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
490 for (i = 0; i < size; i++) \
491 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
493 /* Iterates over all requested GPIO of the given @chip */
494 #define for_each_requested_gpio(chip, i, label) \
495 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
497 /* add/remove chips */
498 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
499 struct lock_class_key *lock_key,
500 struct lock_class_key *request_key);
503 * gpiochip_add_data() - register a gpio_chip
504 * @gc: the chip to register, with gc->base initialized
505 * @data: driver-private data associated with this chip
507 * Context: potentially before irqs will work
509 * When gpiochip_add_data() is called very early during boot, so that GPIOs
510 * can be freely used, the gc->parent device must be registered before
511 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
512 * for GPIOs will fail rudely.
514 * gpiochip_add_data() must only be called after gpiolib initialization,
515 * i.e. after core_initcall().
517 * If gc->base is negative, this requests dynamic assignment of
518 * a range of valid GPIOs.
521 * A negative errno if the chip can't be registered, such as because the
522 * gc->base is invalid or already associated with a different chip.
523 * Otherwise it returns zero as a success code.
525 #ifdef CONFIG_LOCKDEP
526 #define gpiochip_add_data(gc, data) ({ \
527 static struct lock_class_key lock_key; \
528 static struct lock_class_key request_key; \
529 gpiochip_add_data_with_key(gc, data, &lock_key, \
532 #define devm_gpiochip_add_data(dev, gc, data) ({ \
533 static struct lock_class_key lock_key; \
534 static struct lock_class_key request_key; \
535 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
539 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
540 #define devm_gpiochip_add_data(dev, gc, data) \
541 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
542 #endif /* CONFIG_LOCKDEP */
544 static inline int gpiochip_add(struct gpio_chip *gc)
546 return gpiochip_add_data(gc, NULL);
548 extern void gpiochip_remove(struct gpio_chip *gc);
549 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
550 struct lock_class_key *lock_key,
551 struct lock_class_key *request_key);
553 extern struct gpio_chip *gpiochip_find(void *data,
554 int (*match)(struct gpio_chip *gc, void *data));
556 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
557 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
558 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
559 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
560 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
562 /* Line status inquiry for drivers */
563 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
564 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
566 /* Sleep persistence inquiry for drivers */
567 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
568 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
570 /* get driver data */
571 void *gpiochip_get_data(struct gpio_chip *gc);
579 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
581 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
582 unsigned int parent_hwirq,
583 unsigned int parent_type);
584 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
585 unsigned int parent_hwirq,
586 unsigned int parent_type);
590 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
591 unsigned int parent_hwirq,
592 unsigned int parent_type)
597 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
598 unsigned int parent_hwirq,
599 unsigned int parent_type)
604 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
606 int bgpio_init(struct gpio_chip *gc, struct device *dev,
607 unsigned long sz, void __iomem *dat, void __iomem *set,
608 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
609 unsigned long flags);
611 #define BGPIOF_BIG_ENDIAN BIT(0)
612 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
613 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
614 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
615 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
616 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
617 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
619 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
620 irq_hw_number_t hwirq);
621 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
623 int gpiochip_irq_domain_activate(struct irq_domain *domain,
624 struct irq_data *data, bool reserve);
625 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
626 struct irq_data *data);
628 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
629 unsigned int offset);
631 #ifdef CONFIG_GPIOLIB_IRQCHIP
632 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
633 struct irq_domain *domain);
635 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
636 struct irq_domain *domain)
643 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
644 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
645 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
646 unsigned long config);
649 * struct gpio_pin_range - pin range controlled by a gpio chip
650 * @node: list for maintaining set of pin ranges, used internally
651 * @pctldev: pinctrl device which handles corresponding pins
652 * @range: actual range of pins controlled by a gpio controller
654 struct gpio_pin_range {
655 struct list_head node;
656 struct pinctrl_dev *pctldev;
657 struct pinctrl_gpio_range range;
660 #ifdef CONFIG_PINCTRL
662 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
663 unsigned int gpio_offset, unsigned int pin_offset,
665 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
666 struct pinctrl_dev *pctldev,
667 unsigned int gpio_offset, const char *pin_group);
668 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
670 #else /* ! CONFIG_PINCTRL */
673 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
674 unsigned int gpio_offset, unsigned int pin_offset,
680 gpiochip_add_pingroup_range(struct gpio_chip *gc,
681 struct pinctrl_dev *pctldev,
682 unsigned int gpio_offset, const char *pin_group)
688 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
692 #endif /* CONFIG_PINCTRL */
694 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
697 enum gpio_lookup_flags lflags,
698 enum gpiod_flags dflags);
699 void gpiochip_free_own_desc(struct gpio_desc *desc);
701 #ifdef CONFIG_GPIOLIB
703 /* lock/unlock as IRQ */
704 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
705 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
708 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
710 #else /* CONFIG_GPIOLIB */
712 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
714 /* GPIO can never have been requested */
716 return ERR_PTR(-ENODEV);
719 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
726 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
731 #endif /* CONFIG_GPIOLIB */
733 #endif /* __LINUX_GPIO_DRIVER_H */