include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #include <linux/err.h>
  17
  18 #define ZYNQMP_PM_VERSION_MAJOR 1
  19 #define ZYNQMP_PM_VERSION_MINOR 0
  20
  21 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  22                                         ZYNQMP_PM_VERSION_MINOR)
  23
  24 #define ZYNQMP_TZ_VERSION_MAJOR 1
  25 #define ZYNQMP_TZ_VERSION_MINOR 0
  26
  27 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  28                                         ZYNQMP_TZ_VERSION_MINOR)
  29
  30 /* SMC SIP service Call Function Identifier Prefix */
  31 #define PM_SIP_SVC                      0xC2000000
  32 #define PM_GET_TRUSTZONE_VERSION        0xa03
  33 #define PM_SET_SUSPEND_MODE             0xa02
  34 #define GET_CALLBACK_DATA               0xa01
  35
  36 /* Number of 32bits values in payload */
  37 #define PAYLOAD_ARG_CNT 4U
  38
  39 /* Number of arguments for a callback */
  40 #define CB_ARG_CNT     4
  41
  42 /* Payload size (consists of callback API ID + arguments) */
  43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  44
  45 #define ZYNQMP_PM_MAX_QOS               100U
  46
  47 #define GSS_NUM_REGS    (4)
  48
  49 /* Node capabilities */
  50 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  51 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  52 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  53 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  54
  55 /* Loader commands */
  56 #define PM_LOAD_PDI     0x701
  57 #define PDI_SRC_DDR     0xF
  58
  59 /*
  60  * Firmware FPGA Manager flags
  61  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  62  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  63  */
  64 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  65 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  66
  67 /*
  68  * Node IDs for the Error Events.
  69  */
  70 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
  71 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
  72 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
  73 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
  74
  75 enum pm_api_cb_id {
  76         PM_INIT_SUSPEND_CB = 30,
  77         PM_ACKNOWLEDGE_CB = 31,
  78         PM_NOTIFY_CB = 32,
  79 };
  80
  81 enum pm_api_id {
  82         PM_GET_API_VERSION = 1,
  83         PM_REGISTER_NOTIFIER = 5,
  84         PM_SYSTEM_SHUTDOWN = 12,
  85         PM_REQUEST_NODE = 13,
  86         PM_RELEASE_NODE = 14,
  87         PM_SET_REQUIREMENT = 15,
  88         PM_RESET_ASSERT = 17,
  89         PM_RESET_GET_STATUS = 18,
  90         PM_MMIO_WRITE = 19,
  91         PM_MMIO_READ = 20,
  92         PM_PM_INIT_FINALIZE = 21,
  93         PM_FPGA_LOAD = 22,
  94         PM_FPGA_GET_STATUS = 23,
  95         PM_GET_CHIPID = 24,
  96         PM_SECURE_SHA = 26,
  97         PM_PINCTRL_REQUEST = 28,
  98         PM_PINCTRL_RELEASE = 29,
  99         PM_PINCTRL_GET_FUNCTION = 30,
 100         PM_PINCTRL_SET_FUNCTION = 31,
 101         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 102         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 103         PM_IOCTL = 34,
 104         PM_QUERY_DATA = 35,
 105         PM_CLOCK_ENABLE = 36,
 106         PM_CLOCK_DISABLE = 37,
 107         PM_CLOCK_GETSTATE = 38,
 108         PM_CLOCK_SETDIVIDER = 39,
 109         PM_CLOCK_GETDIVIDER = 40,
 110         PM_CLOCK_SETRATE = 41,
 111         PM_CLOCK_GETRATE = 42,
 112         PM_CLOCK_SETPARENT = 43,
 113         PM_CLOCK_GETPARENT = 44,
 114         PM_SECURE_AES = 47,
 115         PM_FEATURE_CHECK = 63,
 116 };
 117
 118 /* PMU-FW return status codes */
 119 enum pm_ret_status {
 120         XST_PM_SUCCESS = 0,
 121         XST_PM_NO_FEATURE = 19,
 122         XST_PM_INTERNAL = 2000,
 123         XST_PM_CONFLICT = 2001,
 124         XST_PM_NO_ACCESS = 2002,
 125         XST_PM_INVALID_NODE = 2003,
 126         XST_PM_DOUBLE_REQ = 2004,
 127         XST_PM_ABORT_SUSPEND = 2005,
 128         XST_PM_MULT_USER = 2008,
 129 };
 130
 131 enum pm_ioctl_id {
 132         IOCTL_SD_DLL_RESET = 6,
 133         IOCTL_SET_SD_TAPDELAY = 7,
 134         IOCTL_SET_PLL_FRAC_MODE = 8,
 135         IOCTL_GET_PLL_FRAC_MODE = 9,
 136         IOCTL_SET_PLL_FRAC_DATA = 10,
 137         IOCTL_GET_PLL_FRAC_DATA = 11,
 138         IOCTL_WRITE_GGS = 12,
 139         IOCTL_READ_GGS = 13,
 140         IOCTL_WRITE_PGGS = 14,
 141         IOCTL_READ_PGGS = 15,
 142         /* Set healthy bit value */
 143         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 144         IOCTL_OSPI_MUX_SELECT = 21,
 145         /* Register SGI to ATF */
 146         IOCTL_REGISTER_SGI = 25,
 147         /* Runtime feature configuration */
 148         IOCTL_SET_FEATURE_CONFIG = 26,
 149         IOCTL_GET_FEATURE_CONFIG = 27,
 150 };
 151
 152 enum pm_query_id {
 153         PM_QID_INVALID = 0,
 154         PM_QID_CLOCK_GET_NAME = 1,
 155         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 156         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 157         PM_QID_CLOCK_GET_PARENTS = 4,
 158         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 159         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 160         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 161         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 162         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 163         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 164         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 165         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 166         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 167 };
 168
 169 enum zynqmp_pm_reset_action {
 170         PM_RESET_ACTION_RELEASE = 0,
 171         PM_RESET_ACTION_ASSERT = 1,
 172         PM_RESET_ACTION_PULSE = 2,
 173 };
 174
 175 enum zynqmp_pm_reset {
 176         ZYNQMP_PM_RESET_START = 1000,
 177         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 178         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 179         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 180         ZYNQMP_PM_RESET_DP = 1003,
 181         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 182         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 183         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 184         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 185         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 186         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 187         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 188         ZYNQMP_PM_RESET_GDMA = 1011,
 189         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 190         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 191         ZYNQMP_PM_RESET_GPU = 1014,
 192         ZYNQMP_PM_RESET_GT = 1015,
 193         ZYNQMP_PM_RESET_SATA = 1016,
 194         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 195         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 196         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 197         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 198         ZYNQMP_PM_RESET_APU_L2 = 1021,
 199         ZYNQMP_PM_RESET_ACPU3 = 1022,
 200         ZYNQMP_PM_RESET_ACPU2 = 1023,
 201         ZYNQMP_PM_RESET_ACPU1 = 1024,
 202         ZYNQMP_PM_RESET_ACPU0 = 1025,
 203         ZYNQMP_PM_RESET_DDR = 1026,
 204         ZYNQMP_PM_RESET_APM_FPD = 1027,
 205         ZYNQMP_PM_RESET_SOFT = 1028,
 206         ZYNQMP_PM_RESET_GEM0 = 1029,
 207         ZYNQMP_PM_RESET_GEM1 = 1030,
 208         ZYNQMP_PM_RESET_GEM2 = 1031,
 209         ZYNQMP_PM_RESET_GEM3 = 1032,
 210         ZYNQMP_PM_RESET_QSPI = 1033,
 211         ZYNQMP_PM_RESET_UART0 = 1034,
 212         ZYNQMP_PM_RESET_UART1 = 1035,
 213         ZYNQMP_PM_RESET_SPI0 = 1036,
 214         ZYNQMP_PM_RESET_SPI1 = 1037,
 215         ZYNQMP_PM_RESET_SDIO0 = 1038,
 216         ZYNQMP_PM_RESET_SDIO1 = 1039,
 217         ZYNQMP_PM_RESET_CAN0 = 1040,
 218         ZYNQMP_PM_RESET_CAN1 = 1041,
 219         ZYNQMP_PM_RESET_I2C0 = 1042,
 220         ZYNQMP_PM_RESET_I2C1 = 1043,
 221         ZYNQMP_PM_RESET_TTC0 = 1044,
 222         ZYNQMP_PM_RESET_TTC1 = 1045,
 223         ZYNQMP_PM_RESET_TTC2 = 1046,
 224         ZYNQMP_PM_RESET_TTC3 = 1047,
 225         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 226         ZYNQMP_PM_RESET_NAND = 1049,
 227         ZYNQMP_PM_RESET_ADMA = 1050,
 228         ZYNQMP_PM_RESET_GPIO = 1051,
 229         ZYNQMP_PM_RESET_IOU_CC = 1052,
 230         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 231         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 232         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 233         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 234         ZYNQMP_PM_RESET_OCM = 1057,
 235         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 236         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 237         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 238         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 239         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 240         ZYNQMP_PM_RESET_USB0_APB = 1063,
 241         ZYNQMP_PM_RESET_USB1_APB = 1064,
 242         ZYNQMP_PM_RESET_IPI = 1065,
 243         ZYNQMP_PM_RESET_APM_LPD = 1066,
 244         ZYNQMP_PM_RESET_RTC = 1067,
 245         ZYNQMP_PM_RESET_SYSMON = 1068,
 246         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 247         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 248         ZYNQMP_PM_RESET_FPD = 1071,
 249         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 250         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 251         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 252         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 253         ZYNQMP_PM_RESET_APLL = 1076,
 254         ZYNQMP_PM_RESET_DPLL = 1077,
 255         ZYNQMP_PM_RESET_VPLL = 1078,
 256         ZYNQMP_PM_RESET_IOPLL = 1079,
 257         ZYNQMP_PM_RESET_RPLL = 1080,
 258         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 259         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 260         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 261         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 262         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 263         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 264         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 265         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 266         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 267         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 268         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 269         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 270         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 271         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 272         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 273         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 274         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 275         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 276         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 277         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 278         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 279         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 280         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 281         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 282         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 283         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 284         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 285         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 286         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 287         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 288         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 289         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 290         ZYNQMP_PM_RESET_RPU_LS = 1113,
 291         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 292         ZYNQMP_PM_RESET_PL = 1115,
 293         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 294         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 295         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 296         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 297         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 298 };
 299
 300 enum zynqmp_pm_suspend_reason {
 301         SUSPEND_POWER_REQUEST = 201,
 302         SUSPEND_ALERT = 202,
 303         SUSPEND_SYSTEM_SHUTDOWN = 203,
 304 };
 305
 306 enum zynqmp_pm_request_ack {
 307         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 308         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 309         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 310 };
 311
 312 enum pm_node_id {
 313         NODE_SD_0 = 39,
 314         NODE_SD_1 = 40,
 315 };
 316
 317 enum tap_delay_type {
 318         PM_TAPDELAY_INPUT = 0,
 319         PM_TAPDELAY_OUTPUT = 1,
 320 };
 321
 322 enum dll_reset_type {
 323         PM_DLL_RESET_ASSERT = 0,
 324         PM_DLL_RESET_RELEASE = 1,
 325         PM_DLL_RESET_PULSE = 2,
 326 };
 327
 328 enum pm_pinctrl_config_param {
 329         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 330         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 331         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 332         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 333         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 334         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 335         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 336         PM_PINCTRL_CONFIG_MAX = 7,
 337 };
 338
 339 enum pm_pinctrl_slew_rate {
 340         PM_PINCTRL_SLEW_RATE_FAST = 0,
 341         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 342 };
 343
 344 enum pm_pinctrl_bias_status {
 345         PM_PINCTRL_BIAS_DISABLE = 0,
 346         PM_PINCTRL_BIAS_ENABLE = 1,
 347 };
 348
 349 enum pm_pinctrl_pull_ctrl {
 350         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 351         PM_PINCTRL_BIAS_PULL_UP = 1,
 352 };
 353
 354 enum pm_pinctrl_schmitt_cmos {
 355         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 356         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 357 };
 358
 359 enum pm_pinctrl_drive_strength {
 360         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 361         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 362         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 363         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 364 };
 365
 366 enum zynqmp_pm_shutdown_type {
 367         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 368         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 369         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 370 };
 371
 372 enum zynqmp_pm_shutdown_subtype {
 373         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 374         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 375         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 376 };
 377
 378 enum ospi_mux_select_type {
 379         PM_OSPI_MUX_SEL_DMA = 0,
 380         PM_OSPI_MUX_SEL_LINEAR = 1,
 381 };
 382
 383 enum pm_feature_config_id {
 384         PM_FEATURE_INVALID = 0,
 385         PM_FEATURE_OVERTEMP_STATUS = 1,
 386         PM_FEATURE_OVERTEMP_VALUE = 2,
 387         PM_FEATURE_EXTWDT_STATUS = 3,
 388         PM_FEATURE_EXTWDT_VALUE = 4,
 389 };
 390
 391 /**
 392  * struct zynqmp_pm_query_data - PM query data
 393  * @qid:        query ID
 394  * @arg1:       Argument 1 of query data
 395  * @arg2:       Argument 2 of query data
 396  * @arg3:       Argument 3 of query data
 397  */
 398 struct zynqmp_pm_query_data {
 399         u32 qid;
 400         u32 arg1;
 401         u32 arg2;
 402         u32 arg3;
 403 };
 404
 405 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 406                         u32 arg2, u32 arg3, u32 *ret_payload);
 407
 408 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 409 int zynqmp_pm_get_api_version(u32 *version);
 410 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 411 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 412 int zynqmp_pm_clock_enable(u32 clock_id);
 413 int zynqmp_pm_clock_disable(u32 clock_id);
 414 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 415 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 416 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 417 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 418 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 419 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 420 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 421 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 422 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 423 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 424 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 425 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 426 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 427 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 428 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 429                            const enum zynqmp_pm_reset_action assert_flag);
 430 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 431 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 432 int zynqmp_pm_bootmode_write(u32 ps_mode);
 433 int zynqmp_pm_init_finalize(void);
 434 int zynqmp_pm_set_suspend_mode(u32 mode);
 435 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 436                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 437 int zynqmp_pm_release_node(const u32 node);
 438 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 439                               const u32 qos,
 440                               const enum zynqmp_pm_request_ack ack);
 441 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 442 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 443 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 444 int zynqmp_pm_fpga_get_status(u32 *value);
 445 int zynqmp_pm_write_ggs(u32 index, u32 value);
 446 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 447 int zynqmp_pm_write_pggs(u32 index, u32 value);
 448 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 449 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 450 int zynqmp_pm_set_boot_health_status(u32 value);
 451 int zynqmp_pm_pinctrl_request(const u32 pin);
 452 int zynqmp_pm_pinctrl_release(const u32 pin);
 453 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 454 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 455 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 456                                  u32 *value);
 457 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 458                                  u32 value);
 459 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 460 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 461                                 const u32 wake, const u32 enable);
 462 int zynqmp_pm_feature(const u32 api_id);
 463 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 464 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 465 #else
 466 static inline int zynqmp_pm_get_api_version(u32 *version)
 467 {
 468         return -ENODEV;
 469 }
 470
 471 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 472 {
 473         return -ENODEV;
 474 }
 475
 476 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 477                                        u32 *out)
 478 {
 479         return -ENODEV;
 480 }
 481
 482 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 483 {
 484         return -ENODEV;
 485 }
 486
 487 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 488 {
 489         return -ENODEV;
 490 }
 491
 492 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 493 {
 494         return -ENODEV;
 495 }
 496
 497 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 498 {
 499         return -ENODEV;
 500 }
 501
 502 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 503 {
 504         return -ENODEV;
 505 }
 506
 507 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 508 {
 509         return -ENODEV;
 510 }
 511
 512 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 513 {
 514         return -ENODEV;
 515 }
 516
 517 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 518 {
 519         return -ENODEV;
 520 }
 521
 522 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 523 {
 524         return -ENODEV;
 525 }
 526
 527 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 528 {
 529         return -ENODEV;
 530 }
 531
 532 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 533 {
 534         return -ENODEV;
 535 }
 536
 537 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 538 {
 539         return -ENODEV;
 540 }
 541
 542 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 543 {
 544         return -ENODEV;
 545 }
 546
 547 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 548 {
 549         return -ENODEV;
 550 }
 551
 552 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 553 {
 554         return -ENODEV;
 555 }
 556
 557 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 558 {
 559         return -ENODEV;
 560 }
 561
 562 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 563                                          const enum zynqmp_pm_reset_action assert_flag)
 564 {
 565         return -ENODEV;
 566 }
 567
 568 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 569                                              u32 *status)
 570 {
 571         return -ENODEV;
 572 }
 573
 574 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 575 {
 576         return -ENODEV;
 577 }
 578
 579 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 580 {
 581         return -ENODEV;
 582 }
 583
 584 static inline int zynqmp_pm_init_finalize(void)
 585 {
 586         return -ENODEV;
 587 }
 588
 589 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 590 {
 591         return -ENODEV;
 592 }
 593
 594 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 595                                          const u32 qos,
 596                                          const enum zynqmp_pm_request_ack ack)
 597 {
 598         return -ENODEV;
 599 }
 600
 601 static inline int zynqmp_pm_release_node(const u32 node)
 602 {
 603         return -ENODEV;
 604 }
 605
 606 static inline int zynqmp_pm_set_requirement(const u32 node,
 607                                             const u32 capabilities,
 608                                             const u32 qos,
 609                                             const enum zynqmp_pm_request_ack ack)
 610 {
 611         return -ENODEV;
 612 }
 613
 614 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 615 {
 616         return -ENODEV;
 617 }
 618
 619 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 620                                      const u32 flags)
 621 {
 622         return -ENODEV;
 623 }
 624
 625 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 626                                       const u32 flags)
 627 {
 628         return -ENODEV;
 629 }
 630
 631 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 632 {
 633         return -ENODEV;
 634 }
 635
 636 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 637 {
 638         return -ENODEV;
 639 }
 640
 641 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 642 {
 643         return -ENODEV;
 644 }
 645
 646 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 647 {
 648         return -ENODEV;
 649 }
 650
 651 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 652 {
 653         return -ENODEV;
 654 }
 655
 656 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 657 {
 658         return -ENODEV;
 659 }
 660
 661 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 662 {
 663         return -ENODEV;
 664 }
 665
 666 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 667 {
 668         return -ENODEV;
 669 }
 670
 671 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 672 {
 673         return -ENODEV;
 674 }
 675
 676 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 677 {
 678         return -ENODEV;
 679 }
 680
 681 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 682 {
 683         return -ENODEV;
 684 }
 685
 686 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 687                                                u32 *value)
 688 {
 689         return -ENODEV;
 690 }
 691
 692 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 693                                                u32 value)
 694 {
 695         return -ENODEV;
 696 }
 697
 698 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 699 {
 700         return -ENODEV;
 701 }
 702
 703 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 704                                               const u32 wake, const u32 enable)
 705 {
 706         return -ENODEV;
 707 }
 708
 709 static inline int zynqmp_pm_feature(const u32 api_id)
 710 {
 711         return -ENODEV;
 712 }
 713
 714 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 715                                                u32 value)
 716 {
 717         return -ENODEV;
 718 }
 719
 720 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 721                                                u32 *payload)
 722 {
 723         return -ENODEV;
 724 }
 725 #endif
 726
 727 #endif /* __FIRMWARE_ZYNQMP_H__ */