1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define QCA_HDR_VERSION 0x2
9 #define QCA_HDR_RECV_VERSION GENMASK(15, 14)
10 #define QCA_HDR_RECV_PRIORITY GENMASK(13, 11)
11 #define QCA_HDR_RECV_TYPE GENMASK(10, 6)
12 #define QCA_HDR_RECV_FRAME_IS_TAGGED BIT(3)
13 #define QCA_HDR_RECV_SOURCE_PORT GENMASK(2, 0)
15 /* Packet type for recv */
16 #define QCA_HDR_RECV_TYPE_NORMAL 0x0
17 #define QCA_HDR_RECV_TYPE_MIB 0x1
18 #define QCA_HDR_RECV_TYPE_RW_REG_ACK 0x2
20 #define QCA_HDR_XMIT_VERSION GENMASK(15, 14)
21 #define QCA_HDR_XMIT_PRIORITY GENMASK(13, 11)
22 #define QCA_HDR_XMIT_CONTROL GENMASK(10, 8)
23 #define QCA_HDR_XMIT_FROM_CPU BIT(7)
24 #define QCA_HDR_XMIT_DP_BIT GENMASK(6, 0)
26 /* Packet type for xmit */
27 #define QCA_HDR_XMIT_TYPE_NORMAL 0x0
28 #define QCA_HDR_XMIT_TYPE_RW_REG 0x1
30 /* Check code for a valid mgmt packet. Switch will ignore the packet
33 #define QCA_HDR_MGMT_CHECK_CODE_VAL 0x5
35 /* Specific define for in-band MDIO read/write with Ethernet packet */
36 #define QCA_HDR_MGMT_SEQ_LEN 4 /* 4 byte for the seq */
37 #define QCA_HDR_MGMT_COMMAND_LEN 4 /* 4 byte for the command */
38 #define QCA_HDR_MGMT_DATA1_LEN 4 /* First 4 byte for the mdio data */
39 #define QCA_HDR_MGMT_HEADER_LEN (QCA_HDR_MGMT_SEQ_LEN + \
40 QCA_HDR_MGMT_COMMAND_LEN + \
41 QCA_HDR_MGMT_DATA1_LEN)
43 #define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */
44 #define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */
46 #define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \
48 QCA_HDR_MGMT_DATA2_LEN + \
49 QCA_HDR_MGMT_PADDING_LEN)
51 #define QCA_HDR_MGMT_SEQ_NUM GENMASK(31, 0) /* 63, 32 */
52 #define QCA_HDR_MGMT_CHECK_CODE GENMASK(31, 29) /* 31, 29 */
53 #define QCA_HDR_MGMT_CMD BIT(28) /* 28 */
54 #define QCA_HDR_MGMT_LENGTH GENMASK(23, 20) /* 23, 20 */
55 #define QCA_HDR_MGMT_ADDR GENMASK(18, 0) /* 18, 0 */
57 /* Special struct emulating a Ethernet header */
58 struct qca_mgmt_ethhdr {
59 u32 command; /* command bit 31:0 */
60 u32 seq; /* seq 63:32 */
61 u32 mdio_data; /* first 4byte mdio */
62 __be16 hdr; /* qca hdr */
71 u32 data[3]; /* first 3 mib counter */
72 __be16 hdr; /* qca hdr */
75 struct qca_tagger_data {
76 void (*rw_reg_ack_handler)(struct dsa_switch *ds,
78 void (*mib_autocast_handler)(struct dsa_switch *ds,
82 #endif /* __TAG_QCA_H */