drivers/watchdog/octeon-wdt-main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Octeon Watchdog driver
   4  *
   5  * Copyright (C) 2007-2017 Cavium, Inc.
   6  *
   7  * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
   8  *
   9  * Some parts derived from wdt.c
  10  *
  11  *      (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
  12  *                                              All Rights Reserved.
  13  *
  14  *      Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
  15  *      warranty for any of this software. This material is provided
  16  *      "AS-IS" and at no charge.
  17  *
  18  *      (c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
  19  *
  20  * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
  21  * For most systems this is less than 10 seconds, so to allow for
  22  * software to request longer watchdog heartbeats, we maintain software
  23  * counters to count multiples of the base rate.  If the system locks
  24  * up in such a manner that we can not run the software counters, the
  25  * only result is a watchdog reset sooner than was requested.  But
  26  * that is OK, because in this case userspace would likely not be able
  27  * to do anything anyhow.
  28  *
  29  * The hardware watchdog interval we call the period.  The OCTEON
  30  * watchdog goes through several stages, after the first period an
  31  * irq is asserted, then if it is not reset, after the next period NMI
  32  * is asserted, then after an additional period a chip wide soft reset.
  33  * So for the software counters, we reset watchdog after each period
  34  * and decrement the counter.  But for the last two periods we need to
  35  * let the watchdog progress to the NMI stage so we disable the irq
  36  * and let it proceed.  Once in the NMI, we print the register state
  37  * to the serial port and then wait for the reset.
  38  *
  39  * A watchdog is maintained for each CPU in the system, that way if
  40  * one CPU suffers a lockup, we also get a register dump and reset.
  41  * The userspace ping resets the watchdog on all CPUs.
  42  *
  43  * Before userspace opens the watchdog device, we still run the
  44  * watchdogs to catch any lockups that may be kernel related.
  45  *
  46  */
  47
  48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  49
  50 #include <linux/interrupt.h>
  51 #include <linux/watchdog.h>
  52 #include <linux/cpumask.h>
  53 #include <linux/module.h>
  54 #include <linux/delay.h>
  55 #include <linux/cpu.h>
  56 #include <linux/irq.h>
  57
  58 #include <asm/mipsregs.h>
  59 #include <asm/uasm.h>
  60
  61 #include <asm/octeon/octeon.h>
  62 #include <asm/octeon/cvmx-boot-vector.h>
  63 #include <asm/octeon/cvmx-ciu2-defs.h>
  64 #include <asm/octeon/cvmx-rst-defs.h>
  65
  66 /* Watchdog interrupt major block number (8 MSBs of intsn) */
  67 #define WD_BLOCK_NUMBER         0x01
  68
  69 static int divisor;
  70
  71 /* The count needed to achieve timeout_sec. */
  72 static unsigned int timeout_cnt;
  73
  74 /* The maximum period supported. */
  75 static unsigned int max_timeout_sec;
  76
  77 /* The current period.  */
  78 static unsigned int timeout_sec;
  79
  80 /* Set to non-zero when userspace countdown mode active */
  81 static bool do_countdown;
  82 static unsigned int countdown_reset;
  83 static unsigned int per_cpu_countdown[NR_CPUS];
  84
  85 static cpumask_t irq_enabled_cpus;
  86
  87 #define WD_TIMO 60                      /* Default heartbeat = 60 seconds */
  88
  89 #define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
  90
  91 static int heartbeat = WD_TIMO;
  92 module_param(heartbeat, int, 0444);
  93 MODULE_PARM_DESC(heartbeat,
  94         "Watchdog heartbeat in seconds. (0 < heartbeat, default="
  95                                 __MODULE_STRING(WD_TIMO) ")");
  96
  97 static bool nowayout = WATCHDOG_NOWAYOUT;
  98 module_param(nowayout, bool, 0444);
  99 MODULE_PARM_DESC(nowayout,
 100         "Watchdog cannot be stopped once started (default="
 101                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 102
 103 static int disable;
 104 module_param(disable, int, 0444);
 105 MODULE_PARM_DESC(disable,
 106         "Disable the watchdog entirely (default=0)");
 107
 108 static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
 109
 110 void octeon_wdt_nmi_stage2(void);
 111
 112 static int cpu2core(int cpu)
 113 {
 114 #ifdef CONFIG_SMP
 115         return cpu_logical_map(cpu) & 0x3f;
 116 #else
 117         return cvmx_get_core_num();
 118 #endif
 119 }
 120
 121 /**
 122  * octeon_wdt_poke_irq - Poke the watchdog when an interrupt is received
 123  *
 124  * @cpl:
 125  * @dev_id:
 126  *
 127  * Returns
 128  */
 129 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
 130 {
 131         int cpu = raw_smp_processor_id();
 132         unsigned int core = cpu2core(cpu);
 133         int node = cpu_to_node(cpu);
 134
 135         if (do_countdown) {
 136                 if (per_cpu_countdown[cpu] > 0) {
 137                         /* We're alive, poke the watchdog */
 138                         cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 139                         per_cpu_countdown[cpu]--;
 140                 } else {
 141                         /* Bad news, you are about to reboot. */
 142                         disable_irq_nosync(cpl);
 143                         cpumask_clear_cpu(cpu, &irq_enabled_cpus);
 144                 }
 145         } else {
 146                 /* Not open, just ping away... */
 147                 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 148         }
 149         return IRQ_HANDLED;
 150 }
 151
 152 /* From setup.c */
 153 extern int prom_putchar(char c);
 154
 155 /**
 156  * octeon_wdt_write_string - Write a string to the uart
 157  *
 158  * @str:        String to write
 159  */
 160 static void octeon_wdt_write_string(const char *str)
 161 {
 162         /* Just loop writing one byte at a time */
 163         while (*str)
 164                 prom_putchar(*str++);
 165 }
 166
 167 /**
 168  * octeon_wdt_write_hex() - Write a hex number out of the uart
 169  *
 170  * @value:      Number to display
 171  * @digits:     Number of digits to print (1 to 16)
 172  */
 173 static void octeon_wdt_write_hex(u64 value, int digits)
 174 {
 175         int d;
 176         int v;
 177
 178         for (d = 0; d < digits; d++) {
 179                 v = (value >> ((digits - d - 1) * 4)) & 0xf;
 180                 if (v >= 10)
 181                         prom_putchar('a' + v - 10);
 182                 else
 183                         prom_putchar('0' + v);
 184         }
 185 }
 186
 187 static const char reg_name[][3] = {
 188         "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
 189         "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
 190         "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
 191         "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
 192 };
 193
 194 /**
 195  * octeon_wdt_nmi_stage3:
 196  *
 197  * NMI stage 3 handler. NMIs are handled in the following manner:
 198  * 1) The first NMI handler enables CVMSEG and transfers from
 199  * the bootbus region into normal memory. It is careful to not
 200  * destroy any registers.
 201  * 2) The second stage handler uses CVMSEG to save the registers
 202  * and create a stack for C code. It then calls the third level
 203  * handler with one argument, a pointer to the register values.
 204  * 3) The third, and final, level handler is the following C
 205  * function that prints out some useful infomration.
 206  *
 207  * @reg:    Pointer to register state before the NMI
 208  */
 209 void octeon_wdt_nmi_stage3(u64 reg[32])
 210 {
 211         u64 i;
 212
 213         unsigned int coreid = cvmx_get_core_num();
 214         /*
 215          * Save status and cause early to get them before any changes
 216          * might happen.
 217          */
 218         u64 cp0_cause = read_c0_cause();
 219         u64 cp0_status = read_c0_status();
 220         u64 cp0_error_epc = read_c0_errorepc();
 221         u64 cp0_epc = read_c0_epc();
 222
 223         /* Delay so output from all cores output is not jumbled together. */
 224         udelay(85000 * coreid);
 225
 226         octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
 227         octeon_wdt_write_hex(coreid, 2);
 228         octeon_wdt_write_string(" ***\r\n");
 229         for (i = 0; i < 32; i++) {
 230                 octeon_wdt_write_string("\t");
 231                 octeon_wdt_write_string(reg_name[i]);
 232                 octeon_wdt_write_string("\t0x");
 233                 octeon_wdt_write_hex(reg[i], 16);
 234                 if (i & 1)
 235                         octeon_wdt_write_string("\r\n");
 236         }
 237         octeon_wdt_write_string("\terr_epc\t0x");
 238         octeon_wdt_write_hex(cp0_error_epc, 16);
 239
 240         octeon_wdt_write_string("\tepc\t0x");
 241         octeon_wdt_write_hex(cp0_epc, 16);
 242         octeon_wdt_write_string("\r\n");
 243
 244         octeon_wdt_write_string("\tstatus\t0x");
 245         octeon_wdt_write_hex(cp0_status, 16);
 246         octeon_wdt_write_string("\tcause\t0x");
 247         octeon_wdt_write_hex(cp0_cause, 16);
 248         octeon_wdt_write_string("\r\n");
 249
 250         /* The CIU register is different for each Octeon model. */
 251         if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
 252                 octeon_wdt_write_string("\tsrc_wd\t0x");
 253                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
 254                 octeon_wdt_write_string("\ten_wd\t0x");
 255                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
 256                 octeon_wdt_write_string("\r\n");
 257                 octeon_wdt_write_string("\tsrc_rml\t0x");
 258                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
 259                 octeon_wdt_write_string("\ten_rml\t0x");
 260                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
 261                 octeon_wdt_write_string("\r\n");
 262                 octeon_wdt_write_string("\tsum\t0x");
 263                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
 264                 octeon_wdt_write_string("\r\n");
 265         } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
 266                 octeon_wdt_write_string("\tsum0\t0x");
 267                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
 268                 octeon_wdt_write_string("\ten0\t0x");
 269                 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
 270                 octeon_wdt_write_string("\r\n");
 271         }
 272
 273         octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
 274
 275         /*
 276          * G-30204: We must trigger a soft reset before watchdog
 277          * does an incomplete job of doing it.
 278          */
 279         if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
 280                 u64 scr;
 281                 unsigned int node = cvmx_get_node_num();
 282                 unsigned int lcore = cvmx_get_local_core_num();
 283                 union cvmx_ciu_wdogx ciu_wdog;
 284
 285                 /*
 286                  * Wait for other cores to print out information, but
 287                  * not too long.  Do the soft reset before watchdog
 288                  * can trigger it.
 289                  */
 290                 do {
 291                         ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
 292                 } while (ciu_wdog.s.cnt > 0x10000);
 293
 294                 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
 295                 scr |= 1 << 11; /* Indicate watchdog in bit 11 */
 296                 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
 297                 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
 298         }
 299 }
 300
 301 static int octeon_wdt_cpu_to_irq(int cpu)
 302 {
 303         unsigned int coreid;
 304         int node;
 305         int irq;
 306
 307         coreid = cpu2core(cpu);
 308         node = cpu_to_node(cpu);
 309
 310         if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
 311                 struct irq_domain *domain;
 312                 int hwirq;
 313
 314                 domain = octeon_irq_get_block_domain(node,
 315                                                      WD_BLOCK_NUMBER);
 316                 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
 317                 irq = irq_find_mapping(domain, hwirq);
 318         } else {
 319                 irq = OCTEON_IRQ_WDOG0 + coreid;
 320         }
 321         return irq;
 322 }
 323
 324 static int octeon_wdt_cpu_pre_down(unsigned int cpu)
 325 {
 326         unsigned int core;
 327         int node;
 328         union cvmx_ciu_wdogx ciu_wdog;
 329
 330         core = cpu2core(cpu);
 331
 332         node = cpu_to_node(cpu);
 333
 334         /* Poke the watchdog to clear out its state */
 335         cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 336
 337         /* Disable the hardware. */
 338         ciu_wdog.u64 = 0;
 339         cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 340
 341         free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
 342         return 0;
 343 }
 344
 345 static int octeon_wdt_cpu_online(unsigned int cpu)
 346 {
 347         unsigned int core;
 348         unsigned int irq;
 349         union cvmx_ciu_wdogx ciu_wdog;
 350         int node;
 351         struct irq_domain *domain;
 352         int hwirq;
 353
 354         core = cpu2core(cpu);
 355         node = cpu_to_node(cpu);
 356
 357         octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
 358
 359         /* Disable it before doing anything with the interrupts. */
 360         ciu_wdog.u64 = 0;
 361         cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 362
 363         per_cpu_countdown[cpu] = countdown_reset;
 364
 365         if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
 366                 /* Must get the domain for the watchdog block */
 367                 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
 368
 369                 /* Get a irq for the wd intsn (hardware interrupt) */
 370                 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
 371                 irq = irq_create_mapping(domain, hwirq);
 372                 irqd_set_trigger_type(irq_get_irq_data(irq),
 373                                       IRQ_TYPE_EDGE_RISING);
 374         } else
 375                 irq = OCTEON_IRQ_WDOG0 + core;
 376
 377         if (request_irq(irq, octeon_wdt_poke_irq,
 378                         IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
 379                 panic("octeon_wdt: Couldn't obtain irq %d", irq);
 380
 381         /* Must set the irq affinity here */
 382         if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
 383                 cpumask_t mask;
 384
 385                 cpumask_clear(&mask);
 386                 cpumask_set_cpu(cpu, &mask);
 387                 irq_set_affinity(irq, &mask);
 388         }
 389
 390         cpumask_set_cpu(cpu, &irq_enabled_cpus);
 391
 392         /* Poke the watchdog to clear out its state */
 393         cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 394
 395         /* Finally enable the watchdog now that all handlers are installed */
 396         ciu_wdog.u64 = 0;
 397         ciu_wdog.s.len = timeout_cnt;
 398         ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
 399         cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 400
 401         return 0;
 402 }
 403
 404 static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
 405 {
 406         int cpu;
 407         int coreid;
 408         int node;
 409
 410         if (disable)
 411                 return 0;
 412
 413         for_each_online_cpu(cpu) {
 414                 coreid = cpu2core(cpu);
 415                 node = cpu_to_node(cpu);
 416                 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
 417                 per_cpu_countdown[cpu] = countdown_reset;
 418                 if ((countdown_reset || !do_countdown) &&
 419                     !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
 420                         /* We have to enable the irq */
 421                         enable_irq(octeon_wdt_cpu_to_irq(cpu));
 422                         cpumask_set_cpu(cpu, &irq_enabled_cpus);
 423                 }
 424         }
 425         return 0;
 426 }
 427
 428 static void octeon_wdt_calc_parameters(int t)
 429 {
 430         unsigned int periods;
 431
 432         timeout_sec = max_timeout_sec;
 433
 434
 435         /*
 436          * Find the largest interrupt period, that can evenly divide
 437          * the requested heartbeat time.
 438          */
 439         while ((t % timeout_sec) != 0)
 440                 timeout_sec--;
 441
 442         periods = t / timeout_sec;
 443
 444         /*
 445          * The last two periods are after the irq is disabled, and
 446          * then to the nmi, so we subtract them off.
 447          */
 448
 449         countdown_reset = periods > 2 ? periods - 2 : 0;
 450         heartbeat = t;
 451         timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
 452 }
 453
 454 static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
 455                                   unsigned int t)
 456 {
 457         int cpu;
 458         int coreid;
 459         union cvmx_ciu_wdogx ciu_wdog;
 460         int node;
 461
 462         if (t <= 0)
 463                 return -1;
 464
 465         octeon_wdt_calc_parameters(t);
 466
 467         if (disable)
 468                 return 0;
 469
 470         for_each_online_cpu(cpu) {
 471                 coreid = cpu2core(cpu);
 472                 node = cpu_to_node(cpu);
 473                 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
 474                 ciu_wdog.u64 = 0;
 475                 ciu_wdog.s.len = timeout_cnt;
 476                 ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
 477                 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
 478                 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
 479         }
 480         octeon_wdt_ping(wdog); /* Get the irqs back on. */
 481         return 0;
 482 }
 483
 484 static int octeon_wdt_start(struct watchdog_device *wdog)
 485 {
 486         octeon_wdt_ping(wdog);
 487         do_countdown = 1;
 488         return 0;
 489 }
 490
 491 static int octeon_wdt_stop(struct watchdog_device *wdog)
 492 {
 493         do_countdown = 0;
 494         octeon_wdt_ping(wdog);
 495         return 0;
 496 }
 497
 498 static const struct watchdog_info octeon_wdt_info = {
 499         .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
 500         .identity = "OCTEON",
 501 };
 502
 503 static const struct watchdog_ops octeon_wdt_ops = {
 504         .owner          = THIS_MODULE,
 505         .start          = octeon_wdt_start,
 506         .stop           = octeon_wdt_stop,
 507         .ping           = octeon_wdt_ping,
 508         .set_timeout    = octeon_wdt_set_timeout,
 509 };
 510
 511 static struct watchdog_device octeon_wdt = {
 512         .info   = &octeon_wdt_info,
 513         .ops    = &octeon_wdt_ops,
 514 };
 515
 516 static enum cpuhp_state octeon_wdt_online;
 517 /**
 518  * octeon_wdt_init - Module/ driver initialization.
 519  *
 520  * Returns Zero on success
 521  */
 522 static int __init octeon_wdt_init(void)
 523 {
 524         int ret;
 525
 526         octeon_wdt_bootvector = cvmx_boot_vector_get();
 527         if (!octeon_wdt_bootvector) {
 528                 pr_err("Error: Cannot allocate boot vector.\n");
 529                 return -ENOMEM;
 530         }
 531
 532         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 533                 divisor = 0x200;
 534         else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
 535                 divisor = 0x400;
 536         else
 537                 divisor = 0x100;
 538
 539         /*
 540          * Watchdog time expiration length = The 16 bits of LEN
 541          * represent the most significant bits of a 24 bit decrementer
 542          * that decrements every divisor cycle.
 543          *
 544          * Try for a timeout of 5 sec, if that fails a smaller number
 545          * of even seconds,
 546          */
 547         max_timeout_sec = 6;
 548         do {
 549                 max_timeout_sec--;
 550                 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
 551         } while (timeout_cnt > 65535);
 552
 553         BUG_ON(timeout_cnt == 0);
 554
 555         octeon_wdt_calc_parameters(heartbeat);
 556
 557         pr_info("Initial granularity %d Sec\n", timeout_sec);
 558
 559         octeon_wdt.timeout      = timeout_sec;
 560         octeon_wdt.max_timeout  = UINT_MAX;
 561
 562         watchdog_set_nowayout(&octeon_wdt, nowayout);
 563
 564         ret = watchdog_register_device(&octeon_wdt);
 565         if (ret) {
 566                 pr_err("watchdog_register_device() failed: %d\n", ret);
 567                 return ret;
 568         }
 569
 570         if (disable) {
 571                 pr_notice("disabled\n");
 572                 return 0;
 573         }
 574
 575         cpumask_clear(&irq_enabled_cpus);
 576
 577         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
 578                                 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
 579         if (ret < 0)
 580                 goto err;
 581         octeon_wdt_online = ret;
 582         return 0;
 583 err:
 584         cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
 585         watchdog_unregister_device(&octeon_wdt);
 586         return ret;
 587 }
 588
 589 /**
 590  * octeon_wdt_cleanup - Module / driver shutdown
 591  */
 592 static void __exit octeon_wdt_cleanup(void)
 593 {
 594         watchdog_unregister_device(&octeon_wdt);
 595
 596         if (disable)
 597                 return;
 598
 599         cpuhp_remove_state(octeon_wdt_online);
 600
 601         /*
 602          * Disable the boot-bus memory, the code it points to is soon
 603          * to go missing.
 604          */
 605         cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
 606 }
 607
 608 MODULE_LICENSE("GPL");
 609 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
 610 MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
 611 module_init(octeon_wdt_init);
 612 module_exit(octeon_wdt_cleanup);