drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  34
  35 #define PCI_VENDOR_ID_ETRON             0x1b6f
  36 #define PCI_DEVICE_ID_EJ168             0x7023
  37
  38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  46 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI        0x15c1
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  56 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  57 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  58 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI            0x1138
  60 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI             0x461e
  61
  62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  66 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  67 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  68 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  69 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  70 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI                 0x3242
  71
  72 static const char hcd_name[] = "xhci_hcd";
  73
  74 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  75
  76 static int xhci_pci_setup(struct usb_hcd *hcd);
  77
  78 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  79         .reset = xhci_pci_setup,
  80 };
  81
  82 /* called after powerup, by probe or system-pm "wakeup" */
  83 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  84 {
  85         /*
  86          * TODO: Implement finding debug ports later.
  87          * TODO: see if there are any quirks that need to be added to handle
  88          * new extended capabilities.
  89          */
  90
  91         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  92         if (!pci_set_mwi(pdev))
  93                 xhci_dbg(xhci, "MWI active\n");
  94
  95         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  96         return 0;
  97 }
  98
  99 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 100 {
 101         struct pci_dev                  *pdev = to_pci_dev(dev);
 102         struct xhci_driver_data         *driver_data;
 103         const struct pci_device_id      *id;
 104
 105         id = pci_match_id(pdev->driver->id_table, pdev);
 106
 107         if (id && id->driver_data) {
 108                 driver_data = (struct xhci_driver_data *)id->driver_data;
 109                 xhci->quirks |= driver_data->quirks;
 110         }
 111
 112         /* Look for vendor-specific quirks */
 113         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 114                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 115                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 116                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 117                                 pdev->revision == 0x0) {
 118                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 119                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 120                                 "QUIRK: Fresco Logic xHC needs configure"
 121                                 " endpoint cmd after reset endpoint");
 122                 }
 123                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 124                                 pdev->revision == 0x4) {
 125                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 126                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 127                                 "QUIRK: Fresco Logic xHC revision %u"
 128                                 "must be suspended extra slowly",
 129                                 pdev->revision);
 130                 }
 131                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 132                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 133                 /* Fresco Logic confirms: all revisions of this chip do not
 134                  * support MSI, even though some of them claim to in their PCI
 135                  * capabilities.
 136                  */
 137                 xhci->quirks |= XHCI_BROKEN_MSI;
 138                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 139                                 "QUIRK: Fresco Logic revision %u "
 140                                 "has broken MSI implementation",
 141                                 pdev->revision);
 142                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 143         }
 144
 145         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 146                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 147                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 148
 149         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 150                 xhci->quirks |= XHCI_NEC_HOST;
 151
 152         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 153                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 154
 155         /* AMD PLL quirk */
 156         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 157                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 158
 159         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 160                 (pdev->device == 0x145c ||
 161                  pdev->device == 0x15e0 ||
 162                  pdev->device == 0x15e1 ||
 163                  pdev->device == 0x43bb))
 164                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 165
 166         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 167             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 168                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 169
 170         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
 171                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 172                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 173         }
 174
 175         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 176                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 177
 178         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 179                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 180                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 181                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 182                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 183                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 184
 185         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 186                 xhci->quirks |= XHCI_LPM_SUPPORT;
 187                 xhci->quirks |= XHCI_INTEL_HOST;
 188                 xhci->quirks |= XHCI_AVOID_BEI;
 189         }
 190         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 191                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 192                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 193                 xhci->limit_active_eps = 64;
 194                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 195                 /*
 196                  * PPT desktop boards DH77EB and DH77DF will power back on after
 197                  * a few seconds of being shutdown.  The fix for this is to
 198                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 199                  * DMI information to find those particular boards (since each
 200                  * vendor will change the board name), so we have to key off all
 201                  * PPT chipsets.
 202                  */
 203                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 204         }
 205         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 206                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 207                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 208                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 209                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 210         }
 211         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 212                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 213                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 214                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 215                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 216                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 217                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 218                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 219                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 220                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 221         }
 222         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 223             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 224                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 225         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 226             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 227              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 228              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 229                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 230         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 231             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 232              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 233              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 234              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 235              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 236                 xhci->quirks |= XHCI_MISSING_CAS;
 237
 238         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 239             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 240              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 241              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
 242              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 243              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 244              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 245              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 246              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 247              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 248              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
 249              pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
 250              pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
 251                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 252
 253         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 254                         pdev->device == PCI_DEVICE_ID_EJ168) {
 255                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 256                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 257                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 258         }
 259         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 260             pdev->device == 0x0014) {
 261                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 262                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 263         }
 264         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 265             pdev->device == 0x0015) {
 266                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 267                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 268         }
 269         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 270                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 271
 272         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 273         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 274                         pdev->device == 0x3432)
 275                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 276
 277         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
 278                 xhci->quirks |= XHCI_LPM_SUPPORT;
 279
 280         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 281                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 282                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 283         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 284                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
 285                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 286                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 287         }
 288         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 289             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 290              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
 291              pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 292                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 293
 294         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 295                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 296                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 297
 298         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 299                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 300
 301         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 302              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 303              pdev->device == 0x9026)
 304                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 305
 306         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 307             (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
 308              pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
 309                 xhci->quirks |= XHCI_NO_SOFT_RETRY;
 310
 311         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 312                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 313                                 "QUIRK: Resetting on resume");
 314 }
 315
 316 #ifdef CONFIG_ACPI
 317 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 318 {
 319         static const guid_t intel_dsm_guid =
 320                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 321                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 322         union acpi_object *obj;
 323
 324         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 325                                 NULL);
 326         ACPI_FREE(obj);
 327 }
 328 #else
 329 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 330 #endif /* CONFIG_ACPI */
 331
 332 /* called during probe() after chip reset completes */
 333 static int xhci_pci_setup(struct usb_hcd *hcd)
 334 {
 335         struct xhci_hcd         *xhci;
 336         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 337         int                     retval;
 338
 339         xhci = hcd_to_xhci(hcd);
 340         if (!xhci->sbrn)
 341                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 342
 343         /* imod_interval is the interrupt moderation value in nanoseconds. */
 344         xhci->imod_interval = 40000;
 345
 346         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 347         if (retval)
 348                 return retval;
 349
 350         if (!usb_hcd_is_primary_hcd(hcd))
 351                 return 0;
 352
 353         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 354                 xhci_pme_acpi_rtd3_enable(pdev);
 355
 356         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 357
 358         /* Find any debug ports */
 359         return xhci_pci_reinit(xhci, pdev);
 360 }
 361
 362 /*
 363  * We need to register our own PCI probe function (instead of the USB core's
 364  * function) in order to create a second roothub under xHCI.
 365  */
 366 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 367 {
 368         int retval;
 369         struct xhci_hcd *xhci;
 370         struct usb_hcd *hcd;
 371         struct xhci_driver_data *driver_data;
 372         struct reset_control *reset;
 373
 374         driver_data = (struct xhci_driver_data *)id->driver_data;
 375         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 376                 retval = renesas_xhci_check_request_fw(dev, id);
 377                 if (retval)
 378                         return retval;
 379         }
 380
 381         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 382         if (IS_ERR(reset))
 383                 return PTR_ERR(reset);
 384         reset_control_reset(reset);
 385
 386         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 387         pm_runtime_get_noresume(&dev->dev);
 388
 389         /* Register the USB 2.0 roothub.
 390          * FIXME: USB core must know to register the USB 2.0 roothub first.
 391          * This is sort of silly, because we could just set the HCD driver flags
 392          * to say USB 2.0, but I'm not sure what the implications would be in
 393          * the other parts of the HCD code.
 394          */
 395         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 396
 397         if (retval)
 398                 goto put_runtime_pm;
 399
 400         /* USB 2.0 roothub is stored in the PCI device now. */
 401         hcd = dev_get_drvdata(&dev->dev);
 402         xhci = hcd_to_xhci(hcd);
 403         xhci->reset = reset;
 404         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 405                                                  pci_name(dev), hcd);
 406         if (!xhci->shared_hcd) {
 407                 retval = -ENOMEM;
 408                 goto dealloc_usb2_hcd;
 409         }
 410
 411         retval = xhci_ext_cap_init(xhci);
 412         if (retval)
 413                 goto put_usb3_hcd;
 414
 415         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 416                         IRQF_SHARED);
 417         if (retval)
 418                 goto put_usb3_hcd;
 419         /* Roothub already marked as USB 3.0 speed */
 420
 421         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 422                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 423                 xhci->shared_hcd->can_do_streams = 1;
 424
 425         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 426         pm_runtime_put_noidle(&dev->dev);
 427
 428         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 429                 pm_runtime_allow(&dev->dev);
 430
 431         return 0;
 432
 433 put_usb3_hcd:
 434         usb_put_hcd(xhci->shared_hcd);
 435 dealloc_usb2_hcd:
 436         usb_hcd_pci_remove(dev);
 437 put_runtime_pm:
 438         pm_runtime_put_noidle(&dev->dev);
 439         return retval;
 440 }
 441
 442 static void xhci_pci_remove(struct pci_dev *dev)
 443 {
 444         struct xhci_hcd *xhci;
 445
 446         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 447         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 448                 renesas_xhci_pci_exit(dev);
 449
 450         xhci->xhc_state |= XHCI_STATE_REMOVING;
 451
 452         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 453                 pm_runtime_forbid(&dev->dev);
 454
 455         if (xhci->shared_hcd) {
 456                 usb_remove_hcd(xhci->shared_hcd);
 457                 usb_put_hcd(xhci->shared_hcd);
 458                 xhci->shared_hcd = NULL;
 459         }
 460
 461         /* Workaround for spurious wakeups at shutdown with HSW */
 462         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 463                 pci_set_power_state(dev, PCI_D3hot);
 464
 465         usb_hcd_pci_remove(dev);
 466 }
 467
 468 #ifdef CONFIG_PM
 469 /*
 470  * In some Intel xHCI controllers, in order to get D3 working,
 471  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 472  * SSIC PORT need to be marked as "unused" before putting xHCI
 473  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 474  * Without this change, xHCI might not enter D3 state.
 475  */
 476 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 477 {
 478         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 479         u32 val;
 480         void __iomem *reg;
 481         int i;
 482
 483         for (i = 0; i < SSIC_PORT_NUM; i++) {
 484                 reg = (void __iomem *) xhci->cap_regs +
 485                                 SSIC_PORT_CFG2 +
 486                                 i * SSIC_PORT_CFG2_OFFSET;
 487
 488                 /* Notify SSIC that SSIC profile programming is not done. */
 489                 val = readl(reg) & ~PROG_DONE;
 490                 writel(val, reg);
 491
 492                 /* Mark SSIC port as unused(suspend) or used(resume) */
 493                 val = readl(reg);
 494                 if (suspend)
 495                         val |= SSIC_PORT_UNUSED;
 496                 else
 497                         val &= ~SSIC_PORT_UNUSED;
 498                 writel(val, reg);
 499
 500                 /* Notify SSIC that SSIC profile programming is done */
 501                 val = readl(reg) | PROG_DONE;
 502                 writel(val, reg);
 503                 readl(reg);
 504         }
 505 }
 506
 507 /*
 508  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 509  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 510  */
 511 static void xhci_pme_quirk(struct usb_hcd *hcd)
 512 {
 513         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 514         void __iomem *reg;
 515         u32 val;
 516
 517         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 518         val = readl(reg);
 519         writel(val | BIT(28), reg);
 520         readl(reg);
 521 }
 522
 523 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 524 {
 525         u32 reg;
 526
 527         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 528         reg &= ~BIT(SPARSE_DISABLE_BIT);
 529         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 530 }
 531
 532 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 533 {
 534         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 535         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 536         int                     ret;
 537
 538         /*
 539          * Systems with the TI redriver that loses port status change events
 540          * need to have the registers polled during D3, so avoid D3cold.
 541          */
 542         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 543                 pci_d3cold_disable(pdev);
 544
 545         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 546                 xhci_pme_quirk(hcd);
 547
 548         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 549                 xhci_ssic_port_unused_quirk(hcd, true);
 550
 551         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 552                 xhci_sparse_control_quirk(hcd);
 553
 554         ret = xhci_suspend(xhci, do_wakeup);
 555         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 556                 xhci_ssic_port_unused_quirk(hcd, false);
 557
 558         return ret;
 559 }
 560
 561 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 562 {
 563         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 564         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 565         int                     retval = 0;
 566
 567         reset_control_reset(xhci->reset);
 568
 569         /* The BIOS on systems with the Intel Panther Point chipset may or may
 570          * not support xHCI natively.  That means that during system resume, it
 571          * may switch the ports back to EHCI so that users can use their
 572          * keyboard to select a kernel from GRUB after resume from hibernate.
 573          *
 574          * The BIOS is supposed to remember whether the OS had xHCI ports
 575          * enabled before resume, and switch the ports back to xHCI when the
 576          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 577          * writers.
 578          *
 579          * Unconditionally switch the ports back to xHCI after a system resume.
 580          * It should not matter whether the EHCI or xHCI controller is
 581          * resumed first. It's enough to do the switchover in xHCI because
 582          * USB core won't notice anything as the hub driver doesn't start
 583          * running again until after all the devices (including both EHCI and
 584          * xHCI host controllers) have been resumed.
 585          */
 586
 587         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 588                 usb_enable_intel_xhci_ports(pdev);
 589
 590         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 591                 xhci_ssic_port_unused_quirk(hcd, false);
 592
 593         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 594                 xhci_pme_quirk(hcd);
 595
 596         retval = xhci_resume(xhci, hibernated);
 597         return retval;
 598 }
 599
 600 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 601 {
 602         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 603         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 604
 605         xhci_shutdown(hcd);
 606
 607         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 608         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 609                 pci_set_power_state(pdev, PCI_D3hot);
 610 }
 611 #endif /* CONFIG_PM */
 612
 613 /*-------------------------------------------------------------------------*/
 614
 615 static const struct xhci_driver_data reneses_data = {
 616         .quirks  = XHCI_RENESAS_FW_QUIRK,
 617         .firmware = "renesas_usb_fw.mem",
 618 };
 619
 620 /* PCI driver selection metadata; PCI hotplugging uses this */
 621 static const struct pci_device_id pci_ids[] = {
 622         { PCI_DEVICE(0x1912, 0x0014),
 623                 .driver_data =  (unsigned long)&reneses_data,
 624         },
 625         { PCI_DEVICE(0x1912, 0x0015),
 626                 .driver_data =  (unsigned long)&reneses_data,
 627         },
 628         /* handle any USB 3.0 xHCI controller */
 629         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 630         },
 631         { /* end: all zeroes */ }
 632 };
 633 MODULE_DEVICE_TABLE(pci, pci_ids);
 634 MODULE_FIRMWARE("renesas_usb_fw.mem");
 635
 636 /* pci driver glue; this is a "new style" PCI driver module */
 637 static struct pci_driver xhci_pci_driver = {
 638         .name =         hcd_name,
 639         .id_table =     pci_ids,
 640
 641         .probe =        xhci_pci_probe,
 642         .remove =       xhci_pci_remove,
 643         /* suspend and resume implemented later */
 644
 645         .shutdown =     usb_hcd_pci_shutdown,
 646 #ifdef CONFIG_PM
 647         .driver = {
 648                 .pm = &usb_hcd_pci_pm_ops
 649         },
 650 #endif
 651 };
 652
 653 static int __init xhci_pci_init(void)
 654 {
 655         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 656 #ifdef CONFIG_PM
 657         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 658         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 659         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 660 #endif
 661         return pci_register_driver(&xhci_pci_driver);
 662 }
 663 module_init(xhci_pci_init);
 664
 665 static void __exit xhci_pci_exit(void)
 666 {
 667         pci_unregister_driver(&xhci_pci_driver);
 668 }
 669 module_exit(xhci_pci_exit);
 670
 671 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 672 MODULE_LICENSE("GPL");