drivers/usb/gadget/udc/fsl_udc_core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  * Author: Li Yang <leoli@freescale.com>
   7  *         Jiang Bo <tanya.jiang@freescale.com>
   8  *
   9  * Description:
  10  * Freescale high-speed USB SOC DR module device controller driver.
  11  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  12  * The driver is previously named as mpc_udc.  Based on bare board
  13  * code from Dave Liu and Shlomi Gridish.
  14  */
  15
  16 #undef VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/mm.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/device.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38 #include <linux/dmapool.h>
  39 #include <linux/delay.h>
  40 #include <linux/of_device.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45 #include <asm/dma.h>
  46
  47 #include "fsl_usb2_udc.h"
  48
  49 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  50 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  51 #define DRIVER_VERSION  "Apr 20, 2007"
  52
  53 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  54
  55 static const char driver_name[] = "fsl-usb2-udc";
  56
  57 static struct usb_dr_device __iomem *dr_regs;
  58
  59 static struct usb_sys_interface __iomem *usb_sys_regs;
  60
  61 /* it is initialized in probe()  */
  62 static struct fsl_udc *udc_controller = NULL;
  63
  64 static const struct usb_endpoint_descriptor
  65 fsl_ep0_desc = {
  66         .bLength =              USB_DT_ENDPOINT_SIZE,
  67         .bDescriptorType =      USB_DT_ENDPOINT,
  68         .bEndpointAddress =     0,
  69         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  70         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  71 };
  72
  73 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  74
  75 #ifdef CONFIG_PPC32
  76 /*
  77  * On some SoCs, the USB controller registers can be big or little endian,
  78  * depending on the version of the chip. In order to be able to run the
  79  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  80  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  81  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  82  * call through those pointers. Platform code for SoCs that have BE USB
  83  * registers should set pdata->big_endian_mmio flag.
  84  *
  85  * This also applies to controller-to-cpu accessors for the USB descriptors,
  86  * since their endianness is also SoC dependant. Platform code for SoCs that
  87  * have BE USB descriptors should set pdata->big_endian_desc flag.
  88  */
  89 static u32 _fsl_readl_be(const unsigned __iomem *p)
  90 {
  91         return in_be32(p);
  92 }
  93
  94 static u32 _fsl_readl_le(const unsigned __iomem *p)
  95 {
  96         return in_le32(p);
  97 }
  98
  99 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 100 {
 101         out_be32(p, v);
 102 }
 103
 104 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 105 {
 106         out_le32(p, v);
 107 }
 108
 109 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 110 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 111
 112 #define fsl_readl(p)            (*_fsl_readl)((p))
 113 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 114
 115 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 116 {
 117         if (pdata->big_endian_mmio) {
 118                 _fsl_readl = _fsl_readl_be;
 119                 _fsl_writel = _fsl_writel_be;
 120         } else {
 121                 _fsl_readl = _fsl_readl_le;
 122                 _fsl_writel = _fsl_writel_le;
 123         }
 124 }
 125
 126 static inline u32 cpu_to_hc32(const u32 x)
 127 {
 128         return udc_controller->pdata->big_endian_desc
 129                 ? (__force u32)cpu_to_be32(x)
 130                 : (__force u32)cpu_to_le32(x);
 131 }
 132
 133 static inline u32 hc32_to_cpu(const u32 x)
 134 {
 135         return udc_controller->pdata->big_endian_desc
 136                 ? be32_to_cpu((__force __be32)x)
 137                 : le32_to_cpu((__force __le32)x);
 138 }
 139 #else /* !CONFIG_PPC32 */
 140 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 141
 142 #define fsl_readl(addr)         readl(addr)
 143 #define fsl_writel(val32, addr) writel(val32, addr)
 144 #define cpu_to_hc32(x)          cpu_to_le32(x)
 145 #define hc32_to_cpu(x)          le32_to_cpu(x)
 146 #endif /* CONFIG_PPC32 */
 147
 148 /********************************************************************
 149  *      Internal Used Function
 150 ********************************************************************/
 151 /*-----------------------------------------------------------------
 152  * done() - retire a request; caller blocked irqs
 153  * @status : request status to be set, only works when
 154  *      request is still in progress.
 155  *--------------------------------------------------------------*/
 156 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 157 __releases(ep->udc->lock)
 158 __acquires(ep->udc->lock)
 159 {
 160         struct fsl_udc *udc = NULL;
 161         unsigned char stopped = ep->stopped;
 162         struct ep_td_struct *curr_td, *next_td;
 163         int j;
 164
 165         udc = (struct fsl_udc *)ep->udc;
 166         /* Removed the req from fsl_ep->queue */
 167         list_del_init(&req->queue);
 168
 169         /* req.status should be set as -EINPROGRESS in ep_queue() */
 170         if (req->req.status == -EINPROGRESS)
 171                 req->req.status = status;
 172         else
 173                 status = req->req.status;
 174
 175         /* Free dtd for the request */
 176         next_td = req->head;
 177         for (j = 0; j < req->dtd_count; j++) {
 178                 curr_td = next_td;
 179                 if (j != req->dtd_count - 1) {
 180                         next_td = curr_td->next_td_virt;
 181                 }
 182                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 183         }
 184
 185         usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 186
 187         if (status && (status != -ESHUTDOWN))
 188                 VDBG("complete %s req %p stat %d len %u/%u",
 189                         ep->ep.name, &req->req, status,
 190                         req->req.actual, req->req.length);
 191
 192         ep->stopped = 1;
 193
 194         spin_unlock(&ep->udc->lock);
 195
 196         usb_gadget_giveback_request(&ep->ep, &req->req);
 197
 198         spin_lock(&ep->udc->lock);
 199         ep->stopped = stopped;
 200 }
 201
 202 /*-----------------------------------------------------------------
 203  * nuke(): delete all requests related to this ep
 204  * called with spinlock held
 205  *--------------------------------------------------------------*/
 206 static void nuke(struct fsl_ep *ep, int status)
 207 {
 208         ep->stopped = 1;
 209
 210         /* Flush fifo */
 211         fsl_ep_fifo_flush(&ep->ep);
 212
 213         /* Whether this eq has request linked */
 214         while (!list_empty(&ep->queue)) {
 215                 struct fsl_req *req = NULL;
 216
 217                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 218                 done(ep, req, status);
 219         }
 220 }
 221
 222 /*------------------------------------------------------------------
 223         Internal Hardware related function
 224  ------------------------------------------------------------------*/
 225
 226 static int dr_controller_setup(struct fsl_udc *udc)
 227 {
 228         unsigned int tmp, portctrl, ep_num;
 229         unsigned int max_no_of_ep;
 230         unsigned int ctrl;
 231         unsigned long timeout;
 232
 233 #define FSL_UDC_RESET_TIMEOUT 1000
 234
 235         /* Config PHY interface */
 236         portctrl = fsl_readl(&dr_regs->portsc1);
 237         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 238         switch (udc->phy_mode) {
 239         case FSL_USB2_PHY_ULPI:
 240                 if (udc->pdata->have_sysif_regs) {
 241                         if (udc->pdata->controller_ver) {
 242                                 /* controller version 1.6 or above */
 243                                 ctrl = __raw_readl(&usb_sys_regs->control);
 244                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 245                                 ctrl |= USB_CTRL_USB_EN;
 246                                 __raw_writel(ctrl, &usb_sys_regs->control);
 247                         }
 248                 }
 249                 portctrl |= PORTSCX_PTS_ULPI;
 250                 break;
 251         case FSL_USB2_PHY_UTMI_WIDE:
 252                 portctrl |= PORTSCX_PTW_16BIT;
 253                 fallthrough;
 254         case FSL_USB2_PHY_UTMI:
 255         case FSL_USB2_PHY_UTMI_DUAL:
 256                 if (udc->pdata->have_sysif_regs) {
 257                         if (udc->pdata->controller_ver) {
 258                                 /* controller version 1.6 or above */
 259                                 ctrl = __raw_readl(&usb_sys_regs->control);
 260                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 261                                         USB_CTRL_USB_EN);
 262                                 __raw_writel(ctrl, &usb_sys_regs->control);
 263                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 264                                         PHY CLK to become stable - 10ms*/
 265                         }
 266                 }
 267                 portctrl |= PORTSCX_PTS_UTMI;
 268                 break;
 269         case FSL_USB2_PHY_SERIAL:
 270                 portctrl |= PORTSCX_PTS_FSLS;
 271                 break;
 272         default:
 273                 return -EINVAL;
 274         }
 275         fsl_writel(portctrl, &dr_regs->portsc1);
 276
 277         /* Stop and reset the usb controller */
 278         tmp = fsl_readl(&dr_regs->usbcmd);
 279         tmp &= ~USB_CMD_RUN_STOP;
 280         fsl_writel(tmp, &dr_regs->usbcmd);
 281
 282         tmp = fsl_readl(&dr_regs->usbcmd);
 283         tmp |= USB_CMD_CTRL_RESET;
 284         fsl_writel(tmp, &dr_regs->usbcmd);
 285
 286         /* Wait for reset to complete */
 287         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 288         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 289                 if (time_after(jiffies, timeout)) {
 290                         ERR("udc reset timeout!\n");
 291                         return -ETIMEDOUT;
 292                 }
 293                 cpu_relax();
 294         }
 295
 296         /* Set the controller as device mode */
 297         tmp = fsl_readl(&dr_regs->usbmode);
 298         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 299         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 300         /* Disable Setup Lockout */
 301         tmp |= USB_MODE_SETUP_LOCK_OFF;
 302         if (udc->pdata->es)
 303                 tmp |= USB_MODE_ES;
 304         fsl_writel(tmp, &dr_regs->usbmode);
 305
 306         /* Clear the setup status */
 307         fsl_writel(0, &dr_regs->usbsts);
 308
 309         tmp = udc->ep_qh_dma;
 310         tmp &= USB_EP_LIST_ADDRESS_MASK;
 311         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 312
 313         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 314                 udc->ep_qh, (int)tmp,
 315                 fsl_readl(&dr_regs->endpointlistaddr));
 316
 317         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 318         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 319                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 320                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 321                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 322                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 323                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 324         }
 325         /* Config control enable i/o output, cpu endian register */
 326 #ifndef CONFIG_ARCH_MXC
 327         if (udc->pdata->have_sysif_regs) {
 328                 ctrl = __raw_readl(&usb_sys_regs->control);
 329                 ctrl |= USB_CTRL_IOENB;
 330                 __raw_writel(ctrl, &usb_sys_regs->control);
 331         }
 332 #endif
 333
 334 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 335         /* Turn on cache snooping hardware, since some PowerPC platforms
 336          * wholly rely on hardware to deal with cache coherent. */
 337
 338         if (udc->pdata->have_sysif_regs) {
 339                 /* Setup Snooping for all the 4GB space */
 340                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 341                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 342                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 343                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 344         }
 345 #endif
 346
 347         return 0;
 348 }
 349
 350 /* Enable DR irq and set controller to run state */
 351 static void dr_controller_run(struct fsl_udc *udc)
 352 {
 353         u32 temp;
 354
 355         /* Enable DR irq reg */
 356         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 357                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 358                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 359
 360         fsl_writel(temp, &dr_regs->usbintr);
 361
 362         /* Clear stopped bit */
 363         udc->stopped = 0;
 364
 365         /* Set the controller as device mode */
 366         temp = fsl_readl(&dr_regs->usbmode);
 367         temp |= USB_MODE_CTRL_MODE_DEVICE;
 368         fsl_writel(temp, &dr_regs->usbmode);
 369
 370         /* Set controller to Run */
 371         temp = fsl_readl(&dr_regs->usbcmd);
 372         temp |= USB_CMD_RUN_STOP;
 373         fsl_writel(temp, &dr_regs->usbcmd);
 374 }
 375
 376 static void dr_controller_stop(struct fsl_udc *udc)
 377 {
 378         unsigned int tmp;
 379
 380         pr_debug("%s\n", __func__);
 381
 382         /* if we're in OTG mode, and the Host is currently using the port,
 383          * stop now and don't rip the controller out from under the
 384          * ehci driver
 385          */
 386         if (udc->gadget.is_otg) {
 387                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 388                         pr_debug("udc: Leaving early\n");
 389                         return;
 390                 }
 391         }
 392
 393         /* disable all INTR */
 394         fsl_writel(0, &dr_regs->usbintr);
 395
 396         /* Set stopped bit for isr */
 397         udc->stopped = 1;
 398
 399         /* disable IO output */
 400 /*      usb_sys_regs->control = 0; */
 401
 402         /* set controller to Stop */
 403         tmp = fsl_readl(&dr_regs->usbcmd);
 404         tmp &= ~USB_CMD_RUN_STOP;
 405         fsl_writel(tmp, &dr_regs->usbcmd);
 406 }
 407
 408 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 409                         unsigned char ep_type)
 410 {
 411         unsigned int tmp_epctrl = 0;
 412
 413         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 414         if (dir) {
 415                 if (ep_num)
 416                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 417                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 418                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 419                 tmp_epctrl |= ((unsigned int)(ep_type)
 420                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 421         } else {
 422                 if (ep_num)
 423                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 424                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 425                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 426                 tmp_epctrl |= ((unsigned int)(ep_type)
 427                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 428         }
 429
 430         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 431 }
 432
 433 static void
 434 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 435 {
 436         u32 tmp_epctrl = 0;
 437
 438         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 439
 440         if (value) {
 441                 /* set the stall bit */
 442                 if (dir)
 443                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 444                 else
 445                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 446         } else {
 447                 /* clear the stall bit and reset data toggle */
 448                 if (dir) {
 449                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 450                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 451                 } else {
 452                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 453                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 454                 }
 455         }
 456         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 457 }
 458
 459 /* Get stall status of a specific ep
 460    Return: 0: not stalled; 1:stalled */
 461 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 462 {
 463         u32 epctrl;
 464
 465         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 466         if (dir)
 467                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 468         else
 469                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 470 }
 471
 472 /********************************************************************
 473         Internal Structure Build up functions
 474 ********************************************************************/
 475
 476 /*------------------------------------------------------------------
 477 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 478  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 479  * @mult: Mult field
 480  ------------------------------------------------------------------*/
 481 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 482                 unsigned char dir, unsigned char ep_type,
 483                 unsigned int max_pkt_len,
 484                 unsigned int zlt, unsigned char mult)
 485 {
 486         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 487         unsigned int tmp = 0;
 488
 489         /* set the Endpoint Capabilites in QH */
 490         switch (ep_type) {
 491         case USB_ENDPOINT_XFER_CONTROL:
 492                 /* Interrupt On Setup (IOS). for control ep  */
 493                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 494                         | EP_QUEUE_HEAD_IOS;
 495                 break;
 496         case USB_ENDPOINT_XFER_ISOC:
 497                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 498                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 499                 break;
 500         case USB_ENDPOINT_XFER_BULK:
 501         case USB_ENDPOINT_XFER_INT:
 502                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 503                 break;
 504         default:
 505                 VDBG("error ep type is %d", ep_type);
 506                 return;
 507         }
 508         if (zlt)
 509                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 510
 511         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 512         p_QH->next_dtd_ptr = 1;
 513         p_QH->size_ioc_int_sts = 0;
 514 }
 515
 516 /* Setup qh structure and ep register for ep0. */
 517 static void ep0_setup(struct fsl_udc *udc)
 518 {
 519         /* the initialization of an ep includes: fields in QH, Regs,
 520          * fsl_ep struct */
 521         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 522                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 523         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 524                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 525         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 526         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 527
 528         return;
 529
 530 }
 531
 532 /***********************************************************************
 533                 Endpoint Management Functions
 534 ***********************************************************************/
 535
 536 /*-------------------------------------------------------------------------
 537  * when configurations are set, or when interface settings change
 538  * for example the do_set_interface() in gadget layer,
 539  * the driver will enable or disable the relevant endpoints
 540  * ep0 doesn't use this routine. It is always enabled.
 541 -------------------------------------------------------------------------*/
 542 static int fsl_ep_enable(struct usb_ep *_ep,
 543                 const struct usb_endpoint_descriptor *desc)
 544 {
 545         struct fsl_udc *udc = NULL;
 546         struct fsl_ep *ep = NULL;
 547         unsigned short max = 0;
 548         unsigned char mult = 0, zlt;
 549         int retval = -EINVAL;
 550         unsigned long flags = 0;
 551
 552         ep = container_of(_ep, struct fsl_ep, ep);
 553
 554         /* catch various bogus parameters */
 555         if (!_ep || !desc
 556                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 557                 return -EINVAL;
 558
 559         udc = ep->udc;
 560
 561         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 562                 return -ESHUTDOWN;
 563
 564         max = usb_endpoint_maxp(desc);
 565
 566         /* Disable automatic zlp generation.  Driver is responsible to indicate
 567          * explicitly through req->req.zero.  This is needed to enable multi-td
 568          * request. */
 569         zlt = 1;
 570
 571         /* Assume the max packet size from gadget is always correct */
 572         switch (desc->bmAttributes & 0x03) {
 573         case USB_ENDPOINT_XFER_CONTROL:
 574         case USB_ENDPOINT_XFER_BULK:
 575         case USB_ENDPOINT_XFER_INT:
 576                 /* mult = 0.  Execute N Transactions as demonstrated by
 577                  * the USB variable length packet protocol where N is
 578                  * computed using the Maximum Packet Length (dQH) and
 579                  * the Total Bytes field (dTD) */
 580                 mult = 0;
 581                 break;
 582         case USB_ENDPOINT_XFER_ISOC:
 583                 /* Calculate transactions needed for high bandwidth iso */
 584                 mult = usb_endpoint_maxp_mult(desc);
 585                 /* 3 transactions at most */
 586                 if (mult > 3)
 587                         goto en_done;
 588                 break;
 589         default:
 590                 goto en_done;
 591         }
 592
 593         spin_lock_irqsave(&udc->lock, flags);
 594         ep->ep.maxpacket = max;
 595         ep->ep.desc = desc;
 596         ep->stopped = 0;
 597
 598         /* Controller related setup */
 599         /* Init EPx Queue Head (Ep Capabilites field in QH
 600          * according to max, zlt, mult) */
 601         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 602                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 603                                         ?  USB_SEND : USB_RECV),
 604                         (unsigned char) (desc->bmAttributes
 605                                         & USB_ENDPOINT_XFERTYPE_MASK),
 606                         max, zlt, mult);
 607
 608         /* Init endpoint ctrl register */
 609         dr_ep_setup((unsigned char) ep_index(ep),
 610                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 611                                         ? USB_SEND : USB_RECV),
 612                         (unsigned char) (desc->bmAttributes
 613                                         & USB_ENDPOINT_XFERTYPE_MASK));
 614
 615         spin_unlock_irqrestore(&udc->lock, flags);
 616         retval = 0;
 617
 618         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 619                         ep->ep.desc->bEndpointAddress & 0x0f,
 620                         (desc->bEndpointAddress & USB_DIR_IN)
 621                                 ? "in" : "out", max);
 622 en_done:
 623         return retval;
 624 }
 625
 626 /*---------------------------------------------------------------------
 627  * @ep : the ep being unconfigured. May not be ep0
 628  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 629 *---------------------------------------------------------------------*/
 630 static int fsl_ep_disable(struct usb_ep *_ep)
 631 {
 632         struct fsl_udc *udc = NULL;
 633         struct fsl_ep *ep = NULL;
 634         unsigned long flags = 0;
 635         u32 epctrl;
 636         int ep_num;
 637
 638         ep = container_of(_ep, struct fsl_ep, ep);
 639         if (!_ep || !ep->ep.desc) {
 640                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 641                 return -EINVAL;
 642         }
 643
 644         /* disable ep on controller */
 645         ep_num = ep_index(ep);
 646         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 647         if (ep_is_in(ep)) {
 648                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 649                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 650         } else {
 651                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 652                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 653         }
 654         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 655
 656         udc = (struct fsl_udc *)ep->udc;
 657         spin_lock_irqsave(&udc->lock, flags);
 658
 659         /* nuke all pending requests (does flush) */
 660         nuke(ep, -ESHUTDOWN);
 661
 662         ep->ep.desc = NULL;
 663         ep->stopped = 1;
 664         spin_unlock_irqrestore(&udc->lock, flags);
 665
 666         VDBG("disabled %s OK", _ep->name);
 667         return 0;
 668 }
 669
 670 /*---------------------------------------------------------------------
 671  * allocate a request object used by this endpoint
 672  * the main operation is to insert the req->queue to the eq->queue
 673  * Returns the request, or null if one could not be allocated
 674 *---------------------------------------------------------------------*/
 675 static struct usb_request *
 676 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 677 {
 678         struct fsl_req *req = NULL;
 679
 680         req = kzalloc(sizeof *req, gfp_flags);
 681         if (!req)
 682                 return NULL;
 683
 684         req->req.dma = DMA_ADDR_INVALID;
 685         INIT_LIST_HEAD(&req->queue);
 686
 687         return &req->req;
 688 }
 689
 690 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 691 {
 692         struct fsl_req *req = NULL;
 693
 694         req = container_of(_req, struct fsl_req, req);
 695
 696         if (_req)
 697                 kfree(req);
 698 }
 699
 700 /* Actually add a dTD chain to an empty dQH and let go */
 701 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 702 {
 703         struct ep_queue_head *qh = get_qh_by_ep(ep);
 704
 705         /* Write dQH next pointer and terminate bit to 0 */
 706         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 707                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 708
 709         /* Clear active and halt bit */
 710         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 711                                         | EP_QUEUE_HEAD_STATUS_HALT));
 712
 713         /* Ensure that updates to the QH will occur before priming. */
 714         wmb();
 715
 716         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 717         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 718                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 719 }
 720
 721 /* Add dTD chain to the dQH of an EP */
 722 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 723 {
 724         u32 temp, bitmask, tmp_stat;
 725
 726         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 727         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 728
 729         bitmask = ep_is_in(ep)
 730                 ? (1 << (ep_index(ep) + 16))
 731                 : (1 << (ep_index(ep)));
 732
 733         /* check if the pipe is empty */
 734         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
 735                 /* Add td to the end */
 736                 struct fsl_req *lastreq;
 737                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 738                 lastreq->tail->next_td_ptr =
 739                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 740                 /* Ensure dTD's next dtd pointer to be updated */
 741                 wmb();
 742                 /* Read prime bit, if 1 goto done */
 743                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 744                         return;
 745
 746                 do {
 747                         /* Set ATDTW bit in USBCMD */
 748                         temp = fsl_readl(&dr_regs->usbcmd);
 749                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 750
 751                         /* Read correct status bit */
 752                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 753
 754                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 755
 756                 /* Write ATDTW bit to 0 */
 757                 temp = fsl_readl(&dr_regs->usbcmd);
 758                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 759
 760                 if (tmp_stat)
 761                         return;
 762         }
 763
 764         fsl_prime_ep(ep, req->head);
 765 }
 766
 767 /* Fill in the dTD structure
 768  * @req: request that the transfer belongs to
 769  * @length: return actually data length of the dTD
 770  * @dma: return dma address of the dTD
 771  * @is_last: return flag if it is the last dTD of the request
 772  * return: pointer to the built dTD */
 773 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 774                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 775 {
 776         u32 swap_temp;
 777         struct ep_td_struct *dtd;
 778
 779         /* how big will this transfer be? */
 780         *length = min(req->req.length - req->req.actual,
 781                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 782
 783         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 784         if (dtd == NULL)
 785                 return dtd;
 786
 787         dtd->td_dma = *dma;
 788         /* Clear reserved field */
 789         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 790         swap_temp &= ~DTD_RESERVED_FIELDS;
 791         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 792
 793         /* Init all of buffer page pointers */
 794         swap_temp = (u32) (req->req.dma + req->req.actual);
 795         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 796         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 797         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 798         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 799         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 800
 801         req->req.actual += *length;
 802
 803         /* zlp is needed if req->req.zero is set */
 804         if (req->req.zero) {
 805                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 806                         *is_last = 1;
 807                 else
 808                         *is_last = 0;
 809         } else if (req->req.length == req->req.actual)
 810                 *is_last = 1;
 811         else
 812                 *is_last = 0;
 813
 814         if ((*is_last) == 0)
 815                 VDBG("multi-dtd request!");
 816         /* Fill in the transfer size; set active bit */
 817         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 818
 819         /* Enable interrupt for the last dtd of a request */
 820         if (*is_last && !req->req.no_interrupt)
 821                 swap_temp |= DTD_IOC;
 822
 823         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 824
 825         mb();
 826
 827         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 828
 829         return dtd;
 830 }
 831
 832 /* Generate dtd chain for a request */
 833 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 834 {
 835         unsigned        count;
 836         int             is_last;
 837         int             is_first =1;
 838         struct ep_td_struct     *last_dtd = NULL, *dtd;
 839         dma_addr_t dma;
 840
 841         do {
 842                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 843                 if (dtd == NULL)
 844                         return -ENOMEM;
 845
 846                 if (is_first) {
 847                         is_first = 0;
 848                         req->head = dtd;
 849                 } else {
 850                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 851                         last_dtd->next_td_virt = dtd;
 852                 }
 853                 last_dtd = dtd;
 854
 855                 req->dtd_count++;
 856         } while (!is_last);
 857
 858         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 859
 860         req->tail = dtd;
 861
 862         return 0;
 863 }
 864
 865 /* queues (submits) an I/O request to an endpoint */
 866 static int
 867 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 868 {
 869         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 870         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 871         struct fsl_udc *udc;
 872         unsigned long flags;
 873         int ret;
 874
 875         /* catch various bogus parameters */
 876         if (!_req || !req->req.complete || !req->req.buf
 877                         || !list_empty(&req->queue)) {
 878                 VDBG("%s, bad params", __func__);
 879                 return -EINVAL;
 880         }
 881         if (unlikely(!_ep || !ep->ep.desc)) {
 882                 VDBG("%s, bad ep", __func__);
 883                 return -EINVAL;
 884         }
 885         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
 886                 if (req->req.length > ep->ep.maxpacket)
 887                         return -EMSGSIZE;
 888         }
 889
 890         udc = ep->udc;
 891         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 892                 return -ESHUTDOWN;
 893
 894         req->ep = ep;
 895
 896         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 897         if (ret)
 898                 return ret;
 899
 900         req->req.status = -EINPROGRESS;
 901         req->req.actual = 0;
 902         req->dtd_count = 0;
 903
 904         /* build dtds and push them to device queue */
 905         if (!fsl_req_to_dtd(req, gfp_flags)) {
 906                 spin_lock_irqsave(&udc->lock, flags);
 907                 fsl_queue_td(ep, req);
 908         } else {
 909                 return -ENOMEM;
 910         }
 911
 912         /* irq handler advances the queue */
 913         if (req != NULL)
 914                 list_add_tail(&req->queue, &ep->queue);
 915         spin_unlock_irqrestore(&udc->lock, flags);
 916
 917         return 0;
 918 }
 919
 920 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 921 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 922 {
 923         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 924         struct fsl_req *req;
 925         unsigned long flags;
 926         int ep_num, stopped, ret = 0;
 927         u32 epctrl;
 928
 929         if (!_ep || !_req)
 930                 return -EINVAL;
 931
 932         spin_lock_irqsave(&ep->udc->lock, flags);
 933         stopped = ep->stopped;
 934
 935         /* Stop the ep before we deal with the queue */
 936         ep->stopped = 1;
 937         ep_num = ep_index(ep);
 938         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 939         if (ep_is_in(ep))
 940                 epctrl &= ~EPCTRL_TX_ENABLE;
 941         else
 942                 epctrl &= ~EPCTRL_RX_ENABLE;
 943         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 944
 945         /* make sure it's actually queued on this endpoint */
 946         list_for_each_entry(req, &ep->queue, queue) {
 947                 if (&req->req == _req)
 948                         break;
 949         }
 950         if (&req->req != _req) {
 951                 ret = -EINVAL;
 952                 goto out;
 953         }
 954
 955         /* The request is in progress, or completed but not dequeued */
 956         if (ep->queue.next == &req->queue) {
 957                 _req->status = -ECONNRESET;
 958                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 959
 960                 /* The request isn't the last request in this ep queue */
 961                 if (req->queue.next != &ep->queue) {
 962                         struct fsl_req *next_req;
 963
 964                         next_req = list_entry(req->queue.next, struct fsl_req,
 965                                         queue);
 966
 967                         /* prime with dTD of next request */
 968                         fsl_prime_ep(ep, next_req->head);
 969                 }
 970         /* The request hasn't been processed, patch up the TD chain */
 971         } else {
 972                 struct fsl_req *prev_req;
 973
 974                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 975                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 976         }
 977
 978         done(ep, req, -ECONNRESET);
 979
 980         /* Enable EP */
 981 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 982         if (ep_is_in(ep))
 983                 epctrl |= EPCTRL_TX_ENABLE;
 984         else
 985                 epctrl |= EPCTRL_RX_ENABLE;
 986         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 987         ep->stopped = stopped;
 988
 989         spin_unlock_irqrestore(&ep->udc->lock, flags);
 990         return ret;
 991 }
 992
 993 /*-------------------------------------------------------------------------*/
 994
 995 /*-----------------------------------------------------------------
 996  * modify the endpoint halt feature
 997  * @ep: the non-isochronous endpoint being stalled
 998  * @value: 1--set halt  0--clear halt
 999  * Returns zero, or a negative error code.
1000 *----------------------------------------------------------------*/
1001 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1002 {
1003         struct fsl_ep *ep = NULL;
1004         unsigned long flags = 0;
1005         int status = -EOPNOTSUPP;       /* operation not supported */
1006         unsigned char ep_dir = 0, ep_num = 0;
1007         struct fsl_udc *udc = NULL;
1008
1009         ep = container_of(_ep, struct fsl_ep, ep);
1010         udc = ep->udc;
1011         if (!_ep || !ep->ep.desc) {
1012                 status = -EINVAL;
1013                 goto out;
1014         }
1015
1016         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1017                 status = -EOPNOTSUPP;
1018                 goto out;
1019         }
1020
1021         /* Attempt to halt IN ep will fail if any transfer requests
1022          * are still queue */
1023         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1024                 status = -EAGAIN;
1025                 goto out;
1026         }
1027
1028         status = 0;
1029         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1030         ep_num = (unsigned char)(ep_index(ep));
1031         spin_lock_irqsave(&ep->udc->lock, flags);
1032         dr_ep_change_stall(ep_num, ep_dir, value);
1033         spin_unlock_irqrestore(&ep->udc->lock, flags);
1034
1035         if (ep_index(ep) == 0) {
1036                 udc->ep0_state = WAIT_FOR_SETUP;
1037                 udc->ep0_dir = 0;
1038         }
1039 out:
1040         VDBG(" %s %s halt stat %d", ep->ep.name,
1041                         value ?  "set" : "clear", status);
1042
1043         return status;
1044 }
1045
1046 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1047 {
1048         struct fsl_ep *ep;
1049         struct fsl_udc *udc;
1050         int size = 0;
1051         u32 bitmask;
1052         struct ep_queue_head *qh;
1053
1054         if (!_ep || _ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1055                 return -ENODEV;
1056
1057         ep = container_of(_ep, struct fsl_ep, ep);
1058
1059         udc = (struct fsl_udc *)ep->udc;
1060
1061         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1062                 return -ESHUTDOWN;
1063
1064         qh = get_qh_by_ep(ep);
1065
1066         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1067             (1 << (ep_index(ep)));
1068
1069         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1070                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1071                     >> DTD_LENGTH_BIT_POS;
1072
1073         pr_debug("%s %u\n", __func__, size);
1074         return size;
1075 }
1076
1077 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1078 {
1079         struct fsl_ep *ep;
1080         int ep_num, ep_dir;
1081         u32 bits;
1082         unsigned long timeout;
1083 #define FSL_UDC_FLUSH_TIMEOUT 1000
1084
1085         if (!_ep) {
1086                 return;
1087         } else {
1088                 ep = container_of(_ep, struct fsl_ep, ep);
1089                 if (!ep->ep.desc)
1090                         return;
1091         }
1092         ep_num = ep_index(ep);
1093         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1094
1095         if (ep_num == 0)
1096                 bits = (1 << 16) | 1;
1097         else if (ep_dir == USB_SEND)
1098                 bits = 1 << (16 + ep_num);
1099         else
1100                 bits = 1 << ep_num;
1101
1102         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1103         do {
1104                 fsl_writel(bits, &dr_regs->endptflush);
1105
1106                 /* Wait until flush complete */
1107                 while (fsl_readl(&dr_regs->endptflush)) {
1108                         if (time_after(jiffies, timeout)) {
1109                                 ERR("ep flush timeout\n");
1110                                 return;
1111                         }
1112                         cpu_relax();
1113                 }
1114                 /* See if we need to flush again */
1115         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1116 }
1117
1118 static const struct usb_ep_ops fsl_ep_ops = {
1119         .enable = fsl_ep_enable,
1120         .disable = fsl_ep_disable,
1121
1122         .alloc_request = fsl_alloc_request,
1123         .free_request = fsl_free_request,
1124
1125         .queue = fsl_ep_queue,
1126         .dequeue = fsl_ep_dequeue,
1127
1128         .set_halt = fsl_ep_set_halt,
1129         .fifo_status = fsl_ep_fifo_status,
1130         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1131 };
1132
1133 /*-------------------------------------------------------------------------
1134                 Gadget Driver Layer Operations
1135 -------------------------------------------------------------------------*/
1136
1137 /*----------------------------------------------------------------------
1138  * Get the current frame number (from DR frame_index Reg )
1139  *----------------------------------------------------------------------*/
1140 static int fsl_get_frame(struct usb_gadget *gadget)
1141 {
1142         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1143 }
1144
1145 /*-----------------------------------------------------------------------
1146  * Tries to wake up the host connected to this gadget
1147  -----------------------------------------------------------------------*/
1148 static int fsl_wakeup(struct usb_gadget *gadget)
1149 {
1150         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1151         u32 portsc;
1152
1153         /* Remote wakeup feature not enabled by host */
1154         if (!udc->remote_wakeup)
1155                 return -ENOTSUPP;
1156
1157         portsc = fsl_readl(&dr_regs->portsc1);
1158         /* not suspended? */
1159         if (!(portsc & PORTSCX_PORT_SUSPEND))
1160                 return 0;
1161         /* trigger force resume */
1162         portsc |= PORTSCX_PORT_FORCE_RESUME;
1163         fsl_writel(portsc, &dr_regs->portsc1);
1164         return 0;
1165 }
1166
1167 static int can_pullup(struct fsl_udc *udc)
1168 {
1169         return udc->driver && udc->softconnect && udc->vbus_active;
1170 }
1171
1172 /* Notify controller that VBUS is powered, Called by whatever
1173    detects VBUS sessions */
1174 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1175 {
1176         struct fsl_udc  *udc;
1177         unsigned long   flags;
1178
1179         udc = container_of(gadget, struct fsl_udc, gadget);
1180         spin_lock_irqsave(&udc->lock, flags);
1181         VDBG("VBUS %s", is_active ? "on" : "off");
1182         udc->vbus_active = (is_active != 0);
1183         if (can_pullup(udc))
1184                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1185                                 &dr_regs->usbcmd);
1186         else
1187                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1188                                 &dr_regs->usbcmd);
1189         spin_unlock_irqrestore(&udc->lock, flags);
1190         return 0;
1191 }
1192
1193 /* constrain controller's VBUS power usage
1194  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1195  * reporting how much power the device may consume.  For example, this
1196  * could affect how quickly batteries are recharged.
1197  *
1198  * Returns zero on success, else negative errno.
1199  */
1200 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1201 {
1202         struct fsl_udc *udc;
1203
1204         udc = container_of(gadget, struct fsl_udc, gadget);
1205         if (!IS_ERR_OR_NULL(udc->transceiver))
1206                 return usb_phy_set_power(udc->transceiver, mA);
1207         return -ENOTSUPP;
1208 }
1209
1210 /* Change Data+ pullup status
1211  * this func is used by usb_gadget_connect/disconnect
1212  */
1213 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1214 {
1215         struct fsl_udc *udc;
1216
1217         udc = container_of(gadget, struct fsl_udc, gadget);
1218
1219         if (!udc->vbus_active)
1220                 return -EOPNOTSUPP;
1221
1222         udc->softconnect = (is_on != 0);
1223         if (can_pullup(udc))
1224                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1225                                 &dr_regs->usbcmd);
1226         else
1227                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1228                                 &dr_regs->usbcmd);
1229
1230         return 0;
1231 }
1232
1233 static int fsl_udc_start(struct usb_gadget *g,
1234                 struct usb_gadget_driver *driver);
1235 static int fsl_udc_stop(struct usb_gadget *g);
1236
1237 static const struct usb_gadget_ops fsl_gadget_ops = {
1238         .get_frame = fsl_get_frame,
1239         .wakeup = fsl_wakeup,
1240 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1241         .vbus_session = fsl_vbus_session,
1242         .vbus_draw = fsl_vbus_draw,
1243         .pullup = fsl_pullup,
1244         .udc_start = fsl_udc_start,
1245         .udc_stop = fsl_udc_stop,
1246 };
1247
1248 /*
1249  * Empty complete function used by this driver to fill in the req->complete
1250  * field when creating a request since the complete field is mandatory.
1251  */
1252 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1253
1254 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1255    on new transaction */
1256 static void ep0stall(struct fsl_udc *udc)
1257 {
1258         u32 tmp;
1259
1260         /* must set tx and rx to stall at the same time */
1261         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1262         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1263         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1264         udc->ep0_state = WAIT_FOR_SETUP;
1265         udc->ep0_dir = 0;
1266 }
1267
1268 /* Prime a status phase for ep0 */
1269 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1270 {
1271         struct fsl_req *req = udc->status_req;
1272         struct fsl_ep *ep;
1273         int ret;
1274
1275         if (direction == EP_DIR_IN)
1276                 udc->ep0_dir = USB_DIR_IN;
1277         else
1278                 udc->ep0_dir = USB_DIR_OUT;
1279
1280         ep = &udc->eps[0];
1281         if (udc->ep0_state != DATA_STATE_XMIT)
1282                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1283
1284         req->ep = ep;
1285         req->req.length = 0;
1286         req->req.status = -EINPROGRESS;
1287         req->req.actual = 0;
1288         req->req.complete = fsl_noop_complete;
1289         req->dtd_count = 0;
1290
1291         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1292         if (ret)
1293                 return ret;
1294
1295         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1296                 fsl_queue_td(ep, req);
1297         else
1298                 return -ENOMEM;
1299
1300         list_add_tail(&req->queue, &ep->queue);
1301
1302         return 0;
1303 }
1304
1305 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1306 {
1307         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1308
1309         if (ep->ep.name)
1310                 nuke(ep, -ESHUTDOWN);
1311 }
1312
1313 /*
1314  * ch9 Set address
1315  */
1316 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1317 {
1318         /* Save the new address to device struct */
1319         udc->device_address = (u8) value;
1320         /* Update usb state */
1321         udc->usb_state = USB_STATE_ADDRESS;
1322         /* Status phase */
1323         if (ep0_prime_status(udc, EP_DIR_IN))
1324                 ep0stall(udc);
1325 }
1326
1327 /*
1328  * ch9 Get status
1329  */
1330 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1331                 u16 index, u16 length)
1332 {
1333         u16 tmp = 0;            /* Status, cpu endian */
1334         struct fsl_req *req;
1335         struct fsl_ep *ep;
1336         int ret;
1337
1338         ep = &udc->eps[0];
1339
1340         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1341                 /* Get device status */
1342                 tmp = udc->gadget.is_selfpowered;
1343                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1344         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1345                 /* Get interface status */
1346                 /* We don't have interface information in udc driver */
1347                 tmp = 0;
1348         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1349                 /* Get endpoint status */
1350                 struct fsl_ep *target_ep;
1351
1352                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1353
1354                 /* stall if endpoint doesn't exist */
1355                 if (!target_ep->ep.desc)
1356                         goto stall;
1357                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1358                                 << USB_ENDPOINT_HALT;
1359         }
1360
1361         udc->ep0_dir = USB_DIR_IN;
1362         /* Borrow the per device status_req */
1363         req = udc->status_req;
1364         /* Fill in the reqest structure */
1365         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1366
1367         req->ep = ep;
1368         req->req.length = 2;
1369         req->req.status = -EINPROGRESS;
1370         req->req.actual = 0;
1371         req->req.complete = fsl_noop_complete;
1372         req->dtd_count = 0;
1373
1374         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1375         if (ret)
1376                 goto stall;
1377
1378         /* prime the data phase */
1379         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1380                 fsl_queue_td(ep, req);
1381         else                    /* no mem */
1382                 goto stall;
1383
1384         list_add_tail(&req->queue, &ep->queue);
1385         udc->ep0_state = DATA_STATE_XMIT;
1386         if (ep0_prime_status(udc, EP_DIR_OUT))
1387                 ep0stall(udc);
1388
1389         return;
1390 stall:
1391         ep0stall(udc);
1392 }
1393
1394 static void setup_received_irq(struct fsl_udc *udc,
1395                 struct usb_ctrlrequest *setup)
1396 __releases(udc->lock)
1397 __acquires(udc->lock)
1398 {
1399         u16 wValue = le16_to_cpu(setup->wValue);
1400         u16 wIndex = le16_to_cpu(setup->wIndex);
1401         u16 wLength = le16_to_cpu(setup->wLength);
1402
1403         udc_reset_ep_queue(udc, 0);
1404
1405         /* We process some stardard setup requests here */
1406         switch (setup->bRequest) {
1407         case USB_REQ_GET_STATUS:
1408                 /* Data+Status phase from udc */
1409                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1410                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1411                         break;
1412                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1413                 return;
1414
1415         case USB_REQ_SET_ADDRESS:
1416                 /* Status phase from udc */
1417                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1418                                                 | USB_RECIP_DEVICE))
1419                         break;
1420                 ch9setaddress(udc, wValue, wIndex, wLength);
1421                 return;
1422
1423         case USB_REQ_CLEAR_FEATURE:
1424         case USB_REQ_SET_FEATURE:
1425                 /* Status phase from udc */
1426         {
1427                 int rc = -EOPNOTSUPP;
1428                 u16 ptc = 0;
1429
1430                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1431                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1432                         int pipe = get_pipe_by_windex(wIndex);
1433                         struct fsl_ep *ep;
1434
1435                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1436                                 break;
1437                         ep = get_ep_by_pipe(udc, pipe);
1438
1439                         spin_unlock(&udc->lock);
1440                         rc = fsl_ep_set_halt(&ep->ep,
1441                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1442                                                 ? 1 : 0);
1443                         spin_lock(&udc->lock);
1444
1445                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1446                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1447                                 | USB_TYPE_STANDARD)) {
1448                         /* Note: The driver has not include OTG support yet.
1449                          * This will be set when OTG support is added */
1450                         if (wValue == USB_DEVICE_TEST_MODE)
1451                                 ptc = wIndex >> 8;
1452                         else if (gadget_is_otg(&udc->gadget)) {
1453                                 if (setup->bRequest ==
1454                                     USB_DEVICE_B_HNP_ENABLE)
1455                                         udc->gadget.b_hnp_enable = 1;
1456                                 else if (setup->bRequest ==
1457                                          USB_DEVICE_A_HNP_SUPPORT)
1458                                         udc->gadget.a_hnp_support = 1;
1459                                 else if (setup->bRequest ==
1460                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1461                                         udc->gadget.a_alt_hnp_support = 1;
1462                         }
1463                         rc = 0;
1464                 } else
1465                         break;
1466
1467                 if (rc == 0) {
1468                         if (ep0_prime_status(udc, EP_DIR_IN))
1469                                 ep0stall(udc);
1470                 }
1471                 if (ptc) {
1472                         u32 tmp;
1473
1474                         mdelay(10);
1475                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1476                         fsl_writel(tmp, &dr_regs->portsc1);
1477                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1478                 }
1479
1480                 return;
1481         }
1482
1483         default:
1484                 break;
1485         }
1486
1487         /* Requests handled by gadget */
1488         if (wLength) {
1489                 /* Data phase from gadget, status phase from udc */
1490                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1491                                 ?  USB_DIR_IN : USB_DIR_OUT;
1492                 spin_unlock(&udc->lock);
1493                 if (udc->driver->setup(&udc->gadget,
1494                                 &udc->local_setup_buff) < 0)
1495                         ep0stall(udc);
1496                 spin_lock(&udc->lock);
1497                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1498                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1499                 /*
1500                  * If the data stage is IN, send status prime immediately.
1501                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1502                  */
1503                 if (udc->ep0_state == DATA_STATE_XMIT)
1504                         if (ep0_prime_status(udc, EP_DIR_OUT))
1505                                 ep0stall(udc);
1506
1507         } else {
1508                 /* No data phase, IN status from gadget */
1509                 udc->ep0_dir = USB_DIR_IN;
1510                 spin_unlock(&udc->lock);
1511                 if (udc->driver->setup(&udc->gadget,
1512                                 &udc->local_setup_buff) < 0)
1513                         ep0stall(udc);
1514                 spin_lock(&udc->lock);
1515                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1516         }
1517 }
1518
1519 /* Process request for Data or Status phase of ep0
1520  * prime status phase if needed */
1521 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1522                 struct fsl_req *req)
1523 {
1524         if (udc->usb_state == USB_STATE_ADDRESS) {
1525                 /* Set the new address */
1526                 u32 new_address = (u32) udc->device_address;
1527                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1528                                 &dr_regs->deviceaddr);
1529         }
1530
1531         done(ep0, req, 0);
1532
1533         switch (udc->ep0_state) {
1534         case DATA_STATE_XMIT:
1535                 /* already primed at setup_received_irq */
1536                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1537                 break;
1538         case DATA_STATE_RECV:
1539                 /* send status phase */
1540                 if (ep0_prime_status(udc, EP_DIR_IN))
1541                         ep0stall(udc);
1542                 break;
1543         case WAIT_FOR_OUT_STATUS:
1544                 udc->ep0_state = WAIT_FOR_SETUP;
1545                 break;
1546         case WAIT_FOR_SETUP:
1547                 ERR("Unexpected ep0 packets\n");
1548                 break;
1549         default:
1550                 ep0stall(udc);
1551                 break;
1552         }
1553 }
1554
1555 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1556  * being corrupted by another incoming setup packet */
1557 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1558 {
1559         u32 temp;
1560         struct ep_queue_head *qh;
1561         struct fsl_usb2_platform_data *pdata = udc->pdata;
1562
1563         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1564
1565         /* Clear bit in ENDPTSETUPSTAT */
1566         temp = fsl_readl(&dr_regs->endptsetupstat);
1567         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1568
1569         /* while a hazard exists when setup package arrives */
1570         do {
1571                 /* Set Setup Tripwire */
1572                 temp = fsl_readl(&dr_regs->usbcmd);
1573                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1574
1575                 /* Copy the setup packet to local buffer */
1576                 if (pdata->le_setup_buf) {
1577                         u32 *p = (u32 *)buffer_ptr;
1578                         u32 *s = (u32 *)qh->setup_buffer;
1579
1580                         /* Convert little endian setup buffer to CPU endian */
1581                         *p++ = le32_to_cpu(*s++);
1582                         *p = le32_to_cpu(*s);
1583                 } else {
1584                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1585                 }
1586         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1587
1588         /* Clear Setup Tripwire */
1589         temp = fsl_readl(&dr_regs->usbcmd);
1590         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1591 }
1592
1593 /* process-ep_req(): free the completed Tds for this req */
1594 static int process_ep_req(struct fsl_udc *udc, int pipe,
1595                 struct fsl_req *curr_req)
1596 {
1597         struct ep_td_struct *curr_td;
1598         int     actual, remaining_length, j, tmp;
1599         int     status = 0;
1600         int     errors = 0;
1601         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1602         int direction = pipe % 2;
1603
1604         curr_td = curr_req->head;
1605         actual = curr_req->req.length;
1606
1607         for (j = 0; j < curr_req->dtd_count; j++) {
1608                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1609                                         & DTD_PACKET_SIZE)
1610                                 >> DTD_LENGTH_BIT_POS;
1611                 actual -= remaining_length;
1612
1613                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1614                 if (errors & DTD_ERROR_MASK) {
1615                         if (errors & DTD_STATUS_HALTED) {
1616                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1617                                 /* Clear the errors and Halt condition */
1618                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1619                                 tmp &= ~errors;
1620                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1621                                 status = -EPIPE;
1622                                 /* FIXME: continue with next queued TD? */
1623
1624                                 break;
1625                         }
1626                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1627                                 VDBG("Transfer overflow");
1628                                 status = -EPROTO;
1629                                 break;
1630                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1631                                 VDBG("ISO error");
1632                                 status = -EILSEQ;
1633                                 break;
1634                         } else
1635                                 ERR("Unknown error has occurred (0x%x)!\n",
1636                                         errors);
1637
1638                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1639                                 & DTD_STATUS_ACTIVE) {
1640                         VDBG("Request not complete");
1641                         status = REQ_UNCOMPLETE;
1642                         return status;
1643                 } else if (remaining_length) {
1644                         if (direction) {
1645                                 VDBG("Transmit dTD remaining length not zero");
1646                                 status = -EPROTO;
1647                                 break;
1648                         } else {
1649                                 break;
1650                         }
1651                 } else {
1652                         VDBG("dTD transmitted successful");
1653                 }
1654
1655                 if (j != curr_req->dtd_count - 1)
1656                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1657         }
1658
1659         if (status)
1660                 return status;
1661
1662         curr_req->req.actual = actual;
1663
1664         return 0;
1665 }
1666
1667 /* Process a DTD completion interrupt */
1668 static void dtd_complete_irq(struct fsl_udc *udc)
1669 {
1670         u32 bit_pos;
1671         int i, ep_num, direction, bit_mask, status;
1672         struct fsl_ep *curr_ep;
1673         struct fsl_req *curr_req, *temp_req;
1674
1675         /* Clear the bits in the register */
1676         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1677         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1678
1679         if (!bit_pos)
1680                 return;
1681
1682         for (i = 0; i < udc->max_ep; i++) {
1683                 ep_num = i >> 1;
1684                 direction = i % 2;
1685
1686                 bit_mask = 1 << (ep_num + 16 * direction);
1687
1688                 if (!(bit_pos & bit_mask))
1689                         continue;
1690
1691                 curr_ep = get_ep_by_pipe(udc, i);
1692
1693                 /* If the ep is configured */
1694                 if (!curr_ep->ep.name) {
1695                         WARNING("Invalid EP?");
1696                         continue;
1697                 }
1698
1699                 /* process the req queue until an uncomplete request */
1700                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1701                                 queue) {
1702                         status = process_ep_req(udc, i, curr_req);
1703
1704                         VDBG("status of process_ep_req= %d, ep = %d",
1705                                         status, ep_num);
1706                         if (status == REQ_UNCOMPLETE)
1707                                 break;
1708                         /* write back status to req */
1709                         curr_req->req.status = status;
1710
1711                         if (ep_num == 0) {
1712                                 ep0_req_complete(udc, curr_ep, curr_req);
1713                                 break;
1714                         } else
1715                                 done(curr_ep, curr_req, status);
1716                 }
1717         }
1718 }
1719
1720 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1721 {
1722         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1723         case PORTSCX_PORT_SPEED_HIGH:
1724                 return USB_SPEED_HIGH;
1725         case PORTSCX_PORT_SPEED_FULL:
1726                 return USB_SPEED_FULL;
1727         case PORTSCX_PORT_SPEED_LOW:
1728                 return USB_SPEED_LOW;
1729         default:
1730                 return USB_SPEED_UNKNOWN;
1731         }
1732 }
1733
1734 /* Process a port change interrupt */
1735 static void port_change_irq(struct fsl_udc *udc)
1736 {
1737         if (udc->bus_reset)
1738                 udc->bus_reset = 0;
1739
1740         /* Bus resetting is finished */
1741         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1742                 /* Get the speed */
1743                 udc->gadget.speed =
1744                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1745
1746         /* Update USB state */
1747         if (!udc->resume_state)
1748                 udc->usb_state = USB_STATE_DEFAULT;
1749 }
1750
1751 /* Process suspend interrupt */
1752 static void suspend_irq(struct fsl_udc *udc)
1753 {
1754         udc->resume_state = udc->usb_state;
1755         udc->usb_state = USB_STATE_SUSPENDED;
1756
1757         /* report suspend to the driver, serial.c does not support this */
1758         if (udc->driver->suspend)
1759                 udc->driver->suspend(&udc->gadget);
1760 }
1761
1762 static void bus_resume(struct fsl_udc *udc)
1763 {
1764         udc->usb_state = udc->resume_state;
1765         udc->resume_state = 0;
1766
1767         /* report resume to the driver, serial.c does not support this */
1768         if (udc->driver->resume)
1769                 udc->driver->resume(&udc->gadget);
1770 }
1771
1772 /* Clear up all ep queues */
1773 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1774 {
1775         u8 pipe;
1776
1777         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1778                 udc_reset_ep_queue(udc, pipe);
1779
1780         /* report disconnect; the driver is already quiesced */
1781         spin_unlock(&udc->lock);
1782         if (bus_reset)
1783                 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1784         else
1785                 udc->driver->disconnect(&udc->gadget);
1786         spin_lock(&udc->lock);
1787
1788         return 0;
1789 }
1790
1791 /* Process reset interrupt */
1792 static void reset_irq(struct fsl_udc *udc)
1793 {
1794         u32 temp;
1795         unsigned long timeout;
1796
1797         /* Clear the device address */
1798         temp = fsl_readl(&dr_regs->deviceaddr);
1799         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1800
1801         udc->device_address = 0;
1802
1803         /* Clear usb state */
1804         udc->resume_state = 0;
1805         udc->ep0_dir = 0;
1806         udc->ep0_state = WAIT_FOR_SETUP;
1807         udc->remote_wakeup = 0; /* default to 0 on reset */
1808         udc->gadget.b_hnp_enable = 0;
1809         udc->gadget.a_hnp_support = 0;
1810         udc->gadget.a_alt_hnp_support = 0;
1811
1812         /* Clear all the setup token semaphores */
1813         temp = fsl_readl(&dr_regs->endptsetupstat);
1814         fsl_writel(temp, &dr_regs->endptsetupstat);
1815
1816         /* Clear all the endpoint complete status bits */
1817         temp = fsl_readl(&dr_regs->endptcomplete);
1818         fsl_writel(temp, &dr_regs->endptcomplete);
1819
1820         timeout = jiffies + 100;
1821         while (fsl_readl(&dr_regs->endpointprime)) {
1822                 /* Wait until all endptprime bits cleared */
1823                 if (time_after(jiffies, timeout)) {
1824                         ERR("Timeout for reset\n");
1825                         break;
1826                 }
1827                 cpu_relax();
1828         }
1829
1830         /* Write 1s to the flush register */
1831         fsl_writel(0xffffffff, &dr_regs->endptflush);
1832
1833         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1834                 VDBG("Bus reset");
1835                 /* Bus is reseting */
1836                 udc->bus_reset = 1;
1837                 /* Reset all the queues, include XD, dTD, EP queue
1838                  * head and TR Queue */
1839                 reset_queues(udc, true);
1840                 udc->usb_state = USB_STATE_DEFAULT;
1841         } else {
1842                 VDBG("Controller reset");
1843                 /* initialize usb hw reg except for regs for EP, not
1844                  * touch usbintr reg */
1845                 dr_controller_setup(udc);
1846
1847                 /* Reset all internal used Queues */
1848                 reset_queues(udc, false);
1849
1850                 ep0_setup(udc);
1851
1852                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1853                 dr_controller_run(udc);
1854                 udc->usb_state = USB_STATE_ATTACHED;
1855         }
1856 }
1857
1858 /*
1859  * USB device controller interrupt handler
1860  */
1861 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1862 {
1863         struct fsl_udc *udc = _udc;
1864         u32 irq_src;
1865         irqreturn_t status = IRQ_NONE;
1866         unsigned long flags;
1867
1868         /* Disable ISR for OTG host mode */
1869         if (udc->stopped)
1870                 return IRQ_NONE;
1871         spin_lock_irqsave(&udc->lock, flags);
1872         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1873         /* Clear notification bits */
1874         fsl_writel(irq_src, &dr_regs->usbsts);
1875
1876         /* VDBG("irq_src [0x%8x]", irq_src); */
1877
1878         /* Need to resume? */
1879         if (udc->usb_state == USB_STATE_SUSPENDED)
1880                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1881                         bus_resume(udc);
1882
1883         /* USB Interrupt */
1884         if (irq_src & USB_STS_INT) {
1885                 VDBG("Packet int");
1886                 /* Setup package, we only support ep0 as control ep */
1887                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1888                         tripwire_handler(udc, 0,
1889                                         (u8 *) (&udc->local_setup_buff));
1890                         setup_received_irq(udc, &udc->local_setup_buff);
1891                         status = IRQ_HANDLED;
1892                 }
1893
1894                 /* completion of dtd */
1895                 if (fsl_readl(&dr_regs->endptcomplete)) {
1896                         dtd_complete_irq(udc);
1897                         status = IRQ_HANDLED;
1898                 }
1899         }
1900
1901         /* SOF (for ISO transfer) */
1902         if (irq_src & USB_STS_SOF) {
1903                 status = IRQ_HANDLED;
1904         }
1905
1906         /* Port Change */
1907         if (irq_src & USB_STS_PORT_CHANGE) {
1908                 port_change_irq(udc);
1909                 status = IRQ_HANDLED;
1910         }
1911
1912         /* Reset Received */
1913         if (irq_src & USB_STS_RESET) {
1914                 VDBG("reset int");
1915                 reset_irq(udc);
1916                 status = IRQ_HANDLED;
1917         }
1918
1919         /* Sleep Enable (Suspend) */
1920         if (irq_src & USB_STS_SUSPEND) {
1921                 suspend_irq(udc);
1922                 status = IRQ_HANDLED;
1923         }
1924
1925         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1926                 VDBG("Error IRQ %x", irq_src);
1927         }
1928
1929         spin_unlock_irqrestore(&udc->lock, flags);
1930         return status;
1931 }
1932
1933 /*----------------------------------------------------------------*
1934  * Hook to gadget drivers
1935  * Called by initialization code of gadget drivers
1936 *----------------------------------------------------------------*/
1937 static int fsl_udc_start(struct usb_gadget *g,
1938                 struct usb_gadget_driver *driver)
1939 {
1940         int retval = 0;
1941         unsigned long flags = 0;
1942
1943         /* lock is needed but whether should use this lock or another */
1944         spin_lock_irqsave(&udc_controller->lock, flags);
1945
1946         driver->driver.bus = NULL;
1947         /* hook up the driver */
1948         udc_controller->driver = driver;
1949         spin_unlock_irqrestore(&udc_controller->lock, flags);
1950         g->is_selfpowered = 1;
1951
1952         if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1953                 /* Suspend the controller until OTG enable it */
1954                 udc_controller->stopped = 1;
1955                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1956
1957                 /* connect to bus through transceiver */
1958                 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1959                         retval = otg_set_peripheral(
1960                                         udc_controller->transceiver->otg,
1961                                                     &udc_controller->gadget);
1962                         if (retval < 0) {
1963                                 ERR("can't bind to transceiver\n");
1964                                 udc_controller->driver = NULL;
1965                                 return retval;
1966                         }
1967                 }
1968         } else {
1969                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1970                 dr_controller_run(udc_controller);
1971                 udc_controller->usb_state = USB_STATE_ATTACHED;
1972                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1973                 udc_controller->ep0_dir = 0;
1974         }
1975
1976         return retval;
1977 }
1978
1979 /* Disconnect from gadget driver */
1980 static int fsl_udc_stop(struct usb_gadget *g)
1981 {
1982         struct fsl_ep *loop_ep;
1983         unsigned long flags;
1984
1985         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1986                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1987
1988         /* stop DR, disable intr */
1989         dr_controller_stop(udc_controller);
1990
1991         /* in fact, no needed */
1992         udc_controller->usb_state = USB_STATE_ATTACHED;
1993         udc_controller->ep0_state = WAIT_FOR_SETUP;
1994         udc_controller->ep0_dir = 0;
1995
1996         /* stand operation */
1997         spin_lock_irqsave(&udc_controller->lock, flags);
1998         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1999         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2000         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2001                         ep.ep_list)
2002                 nuke(loop_ep, -ESHUTDOWN);
2003         spin_unlock_irqrestore(&udc_controller->lock, flags);
2004
2005         udc_controller->driver = NULL;
2006
2007         return 0;
2008 }
2009
2010 /*-------------------------------------------------------------------------
2011                 PROC File System Support
2012 -------------------------------------------------------------------------*/
2013 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2014
2015 #include <linux/seq_file.h>
2016
2017 static const char proc_filename[] = "driver/fsl_usb2_udc";
2018
2019 static int fsl_proc_read(struct seq_file *m, void *v)
2020 {
2021         unsigned long flags;
2022         int i;
2023         u32 tmp_reg;
2024         struct fsl_ep *ep = NULL;
2025         struct fsl_req *req;
2026
2027         struct fsl_udc *udc = udc_controller;
2028
2029         spin_lock_irqsave(&udc->lock, flags);
2030
2031         /* ------basic driver information ---- */
2032         seq_printf(m,
2033                         DRIVER_DESC "\n"
2034                         "%s version: %s\n"
2035                         "Gadget driver: %s\n\n",
2036                         driver_name, DRIVER_VERSION,
2037                         udc->driver ? udc->driver->driver.name : "(none)");
2038
2039         /* ------ DR Registers ----- */
2040         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2041         seq_printf(m,
2042                         "USBCMD reg:\n"
2043                         "SetupTW: %d\n"
2044                         "Run/Stop: %s\n\n",
2045                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2046                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2047
2048         tmp_reg = fsl_readl(&dr_regs->usbsts);
2049         seq_printf(m,
2050                         "USB Status Reg:\n"
2051                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2052                         "USB Error Interrupt: %s\n\n",
2053                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2054                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2055                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2056                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2057
2058         tmp_reg = fsl_readl(&dr_regs->usbintr);
2059         seq_printf(m,
2060                         "USB Interrupt Enable Reg:\n"
2061                         "Sleep Enable: %d SOF Received Enable: %d "
2062                         "Reset Enable: %d\n"
2063                         "System Error Enable: %d "
2064                         "Port Change Dectected Enable: %d\n"
2065                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2066                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2067                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2068                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2069                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2070                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2071                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2072                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2073
2074         tmp_reg = fsl_readl(&dr_regs->frindex);
2075         seq_printf(m,
2076                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2077                         (tmp_reg & USB_FRINDEX_MASKS));
2078
2079         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2080         seq_printf(m,
2081                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2082                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2083
2084         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2085         seq_printf(m,
2086                         "USB Endpoint List Address Reg: "
2087                         "Device Addr is 0x%x\n\n",
2088                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2089
2090         tmp_reg = fsl_readl(&dr_regs->portsc1);
2091         seq_printf(m,
2092                 "USB Port Status&Control Reg:\n"
2093                 "Port Transceiver Type : %s Port Speed: %s\n"
2094                 "PHY Low Power Suspend: %s Port Reset: %s "
2095                 "Port Suspend Mode: %s\n"
2096                 "Over-current Change: %s "
2097                 "Port Enable/Disable Change: %s\n"
2098                 "Port Enabled/Disabled: %s "
2099                 "Current Connect Status: %s\n\n", ( {
2100                         const char *s;
2101                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2102                         case PORTSCX_PTS_UTMI:
2103                                 s = "UTMI"; break;
2104                         case PORTSCX_PTS_ULPI:
2105                                 s = "ULPI "; break;
2106                         case PORTSCX_PTS_FSLS:
2107                                 s = "FS/LS Serial"; break;
2108                         default:
2109                                 s = "None"; break;
2110                         }
2111                         s;} ),
2112                 usb_speed_string(portscx_device_speed(tmp_reg)),
2113                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2114                 "Normal PHY mode" : "Low power mode",
2115                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2116                 "Not in Reset",
2117                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2118                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2119                 "No",
2120                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2121                 "Not change",
2122                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2123                 "Not correct",
2124                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2125                 "Attached" : "Not-Att");
2126
2127         tmp_reg = fsl_readl(&dr_regs->usbmode);
2128         seq_printf(m,
2129                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2130                                 const char *s;
2131                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2132                                 case USB_MODE_CTRL_MODE_IDLE:
2133                                         s = "Idle"; break;
2134                                 case USB_MODE_CTRL_MODE_DEVICE:
2135                                         s = "Device Controller"; break;
2136                                 case USB_MODE_CTRL_MODE_HOST:
2137                                         s = "Host Controller"; break;
2138                                 default:
2139                                         s = "None"; break;
2140                                 }
2141                                 s;
2142                         } ));
2143
2144         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2145         seq_printf(m,
2146                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2147                         (tmp_reg & EP_SETUP_STATUS_MASK));
2148
2149         for (i = 0; i < udc->max_ep / 2; i++) {
2150                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2151                 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2152         }
2153         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2154         seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2155
2156 #ifndef CONFIG_ARCH_MXC
2157         if (udc->pdata->have_sysif_regs) {
2158                 tmp_reg = usb_sys_regs->snoop1;
2159                 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2160
2161                 tmp_reg = usb_sys_regs->control;
2162                 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2163         }
2164 #endif
2165
2166         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2167         ep = &udc->eps[0];
2168         seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2169                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2170
2171         if (list_empty(&ep->queue)) {
2172                 seq_puts(m, "its req queue is empty\n\n");
2173         } else {
2174                 list_for_each_entry(req, &ep->queue, queue) {
2175                         seq_printf(m,
2176                                 "req %p actual 0x%x length 0x%x buf %p\n",
2177                                 &req->req, req->req.actual,
2178                                 req->req.length, req->req.buf);
2179                 }
2180         }
2181         /* other gadget->eplist ep */
2182         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2183                 if (ep->ep.desc) {
2184                         seq_printf(m,
2185                                         "\nFor %s Maxpkt is 0x%x "
2186                                         "index is 0x%x\n",
2187                                         ep->ep.name, ep_maxpacket(ep),
2188                                         ep_index(ep));
2189
2190                         if (list_empty(&ep->queue)) {
2191                                 seq_puts(m, "its req queue is empty\n\n");
2192                         } else {
2193                                 list_for_each_entry(req, &ep->queue, queue) {
2194                                         seq_printf(m,
2195                                                 "req %p actual 0x%x length "
2196                                                 "0x%x  buf %p\n",
2197                                                 &req->req, req->req.actual,
2198                                                 req->req.length, req->req.buf);
2199                                 }       /* end for each_entry of ep req */
2200                         }       /* end for else */
2201                 }       /* end for if(ep->queue) */
2202         }       /* end (ep->desc) */
2203
2204         spin_unlock_irqrestore(&udc->lock, flags);
2205         return 0;
2206 }
2207
2208 #define create_proc_file() \
2209         proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2210 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2211
2212 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2213
2214 #define create_proc_file()      do {} while (0)
2215 #define remove_proc_file()      do {} while (0)
2216
2217 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2218
2219 /*-------------------------------------------------------------------------*/
2220
2221 /* Release udc structures */
2222 static void fsl_udc_release(struct device *dev)
2223 {
2224         complete(udc_controller->done);
2225         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2226                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2227         kfree(udc_controller);
2228 }
2229
2230 /******************************************************************
2231         Internal structure setup functions
2232 *******************************************************************/
2233 /*------------------------------------------------------------------
2234  * init resource for global controller called by fsl_udc_probe()
2235  * On success the udc handle is initialized, on failure it is
2236  * unchanged (reset).
2237  * Return 0 on success and -1 on allocation failure
2238  ------------------------------------------------------------------*/
2239 static int struct_udc_setup(struct fsl_udc *udc,
2240                 struct platform_device *pdev)
2241 {
2242         struct fsl_usb2_platform_data *pdata;
2243         size_t size;
2244
2245         pdata = dev_get_platdata(&pdev->dev);
2246         udc->phy_mode = pdata->phy_mode;
2247
2248         udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2249         if (!udc->eps) {
2250                 ERR("kmalloc udc endpoint status failed\n");
2251                 goto eps_alloc_failed;
2252         }
2253
2254         /* initialized QHs, take care of alignment */
2255         size = udc->max_ep * sizeof(struct ep_queue_head);
2256         if (size < QH_ALIGNMENT)
2257                 size = QH_ALIGNMENT;
2258         else if ((size % QH_ALIGNMENT) != 0) {
2259                 size += QH_ALIGNMENT + 1;
2260                 size &= ~(QH_ALIGNMENT - 1);
2261         }
2262         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2263                                         &udc->ep_qh_dma, GFP_KERNEL);
2264         if (!udc->ep_qh) {
2265                 ERR("malloc QHs for udc failed\n");
2266                 goto ep_queue_alloc_failed;
2267         }
2268
2269         udc->ep_qh_size = size;
2270
2271         /* Initialize ep0 status request structure */
2272         /* FIXME: fsl_alloc_request() ignores ep argument */
2273         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2274                         struct fsl_req, req);
2275         if (!udc->status_req) {
2276                 ERR("kzalloc for udc status request failed\n");
2277                 goto udc_status_alloc_failed;
2278         }
2279
2280         /* allocate a small amount of memory to get valid address */
2281         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2282         if (!udc->status_req->req.buf) {
2283                 ERR("kzalloc for udc request buffer failed\n");
2284                 goto udc_req_buf_alloc_failed;
2285         }
2286
2287         udc->resume_state = USB_STATE_NOTATTACHED;
2288         udc->usb_state = USB_STATE_POWERED;
2289         udc->ep0_dir = 0;
2290         udc->remote_wakeup = 0; /* default to 0 on reset */
2291
2292         return 0;
2293
2294 udc_req_buf_alloc_failed:
2295         kfree(udc->status_req);
2296 udc_status_alloc_failed:
2297         kfree(udc->ep_qh);
2298         udc->ep_qh_size = 0;
2299 ep_queue_alloc_failed:
2300         kfree(udc->eps);
2301 eps_alloc_failed:
2302         udc->phy_mode = 0;
2303         return -1;
2304
2305 }
2306
2307 /*----------------------------------------------------------------
2308  * Setup the fsl_ep struct for eps
2309  * Link fsl_ep->ep to gadget->ep_list
2310  * ep0out is not used so do nothing here
2311  * ep0in should be taken care
2312  *--------------------------------------------------------------*/
2313 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2314                 char *name, int link)
2315 {
2316         struct fsl_ep *ep = &udc->eps[index];
2317
2318         ep->udc = udc;
2319         strcpy(ep->name, name);
2320         ep->ep.name = ep->name;
2321
2322         ep->ep.ops = &fsl_ep_ops;
2323         ep->stopped = 0;
2324
2325         if (index == 0) {
2326                 ep->ep.caps.type_control = true;
2327         } else {
2328                 ep->ep.caps.type_iso = true;
2329                 ep->ep.caps.type_bulk = true;
2330                 ep->ep.caps.type_int = true;
2331         }
2332
2333         if (index & 1)
2334                 ep->ep.caps.dir_in = true;
2335         else
2336                 ep->ep.caps.dir_out = true;
2337
2338         /* for ep0: maxP defined in desc
2339          * for other eps, maxP is set by epautoconfig() called by gadget layer
2340          */
2341         usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2342
2343         /* the queue lists any req for this ep */
2344         INIT_LIST_HEAD(&ep->queue);
2345
2346         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2347         if (link)
2348                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2349         ep->gadget = &udc->gadget;
2350         ep->qh = &udc->ep_qh[index];
2351
2352         return 0;
2353 }
2354
2355 /* Driver probe function
2356  * all initialization operations implemented here except enabling usb_intr reg
2357  * board setup should have been done in the platform code
2358  */
2359 static int fsl_udc_probe(struct platform_device *pdev)
2360 {
2361         struct fsl_usb2_platform_data *pdata;
2362         struct resource *res;
2363         int ret = -ENODEV;
2364         unsigned int i;
2365         u32 dccparams;
2366
2367         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2368         if (udc_controller == NULL)
2369                 return -ENOMEM;
2370
2371         pdata = dev_get_platdata(&pdev->dev);
2372         udc_controller->pdata = pdata;
2373         spin_lock_init(&udc_controller->lock);
2374         udc_controller->stopped = 1;
2375
2376 #ifdef CONFIG_USB_OTG
2377         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2378                 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2379                 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2380                         ERR("Can't find OTG driver!\n");
2381                         ret = -ENODEV;
2382                         goto err_kfree;
2383                 }
2384         }
2385 #endif
2386
2387         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2388         if (!res) {
2389                 ret = -ENXIO;
2390                 goto err_kfree;
2391         }
2392
2393         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2394                 if (!request_mem_region(res->start, resource_size(res),
2395                                         driver_name)) {
2396                         ERR("request mem region for %s failed\n", pdev->name);
2397                         ret = -EBUSY;
2398                         goto err_kfree;
2399                 }
2400         }
2401
2402         dr_regs = ioremap(res->start, resource_size(res));
2403         if (!dr_regs) {
2404                 ret = -ENOMEM;
2405                 goto err_release_mem_region;
2406         }
2407
2408         pdata->regs = (void __iomem *)dr_regs;
2409
2410         /*
2411          * do platform specific init: check the clock, grab/config pins, etc.
2412          */
2413         if (pdata->init && pdata->init(pdev)) {
2414                 ret = -ENODEV;
2415                 goto err_iounmap_noclk;
2416         }
2417
2418         /* Set accessors only after pdata->init() ! */
2419         fsl_set_accessors(pdata);
2420
2421 #ifndef CONFIG_ARCH_MXC
2422         if (pdata->have_sysif_regs)
2423                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2424 #endif
2425
2426         /* Initialize USB clocks */
2427         ret = fsl_udc_clk_init(pdev);
2428         if (ret < 0)
2429                 goto err_iounmap_noclk;
2430
2431         /* Read Device Controller Capability Parameters register */
2432         dccparams = fsl_readl(&dr_regs->dccparams);
2433         if (!(dccparams & DCCPARAMS_DC)) {
2434                 ERR("This SOC doesn't support device role\n");
2435                 ret = -ENODEV;
2436                 goto err_iounmap;
2437         }
2438         /* Get max device endpoints */
2439         /* DEN is bidirectional ep number, max_ep doubles the number */
2440         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2441
2442         udc_controller->irq = platform_get_irq(pdev, 0);
2443         if (udc_controller->irq <= 0) {
2444                 ret = udc_controller->irq ? : -ENODEV;
2445                 goto err_iounmap;
2446         }
2447
2448         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2449                         driver_name, udc_controller);
2450         if (ret != 0) {
2451                 ERR("cannot request irq %d err %d\n",
2452                                 udc_controller->irq, ret);
2453                 goto err_iounmap;
2454         }
2455
2456         /* Initialize the udc structure including QH member and other member */
2457         if (struct_udc_setup(udc_controller, pdev)) {
2458                 ERR("Can't initialize udc data structure\n");
2459                 ret = -ENOMEM;
2460                 goto err_free_irq;
2461         }
2462
2463         if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2464                 /* initialize usb hw reg except for regs for EP,
2465                  * leave usbintr reg untouched */
2466                 dr_controller_setup(udc_controller);
2467         }
2468
2469         ret = fsl_udc_clk_finalize(pdev);
2470         if (ret)
2471                 goto err_free_irq;
2472
2473         /* Setup gadget structure */
2474         udc_controller->gadget.ops = &fsl_gadget_ops;
2475         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2476         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2477         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2478         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2479         udc_controller->gadget.name = driver_name;
2480
2481         /* Setup gadget.dev and register with kernel */
2482         dev_set_name(&udc_controller->gadget.dev, "gadget");
2483         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2484
2485         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2486                 udc_controller->gadget.is_otg = 1;
2487
2488         /* setup QH and epctrl for ep0 */
2489         ep0_setup(udc_controller);
2490
2491         /* setup udc->eps[] for ep0 */
2492         struct_ep_setup(udc_controller, 0, "ep0", 0);
2493         /* for ep0: the desc defined here;
2494          * for other eps, gadget layer called ep_enable with defined desc
2495          */
2496         udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2497         usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2498                                    USB_MAX_CTRL_PAYLOAD);
2499
2500         /* setup the udc->eps[] for non-control endpoints and link
2501          * to gadget.ep_list */
2502         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2503                 char name[14];
2504
2505                 sprintf(name, "ep%dout", i);
2506                 struct_ep_setup(udc_controller, i * 2, name, 1);
2507                 sprintf(name, "ep%din", i);
2508                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2509         }
2510
2511         /* use dma_pool for TD management */
2512         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2513                         sizeof(struct ep_td_struct),
2514                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2515         if (udc_controller->td_pool == NULL) {
2516                 ret = -ENOMEM;
2517                 goto err_free_irq;
2518         }
2519
2520         ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2521                         fsl_udc_release);
2522         if (ret)
2523                 goto err_del_udc;
2524
2525         create_proc_file();
2526         return 0;
2527
2528 err_del_udc:
2529         dma_pool_destroy(udc_controller->td_pool);
2530 err_free_irq:
2531         free_irq(udc_controller->irq, udc_controller);
2532 err_iounmap:
2533         if (pdata->exit)
2534                 pdata->exit(pdev);
2535         fsl_udc_clk_release();
2536 err_iounmap_noclk:
2537         iounmap(dr_regs);
2538 err_release_mem_region:
2539         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2540                 release_mem_region(res->start, resource_size(res));
2541 err_kfree:
2542         kfree(udc_controller);
2543         udc_controller = NULL;
2544         return ret;
2545 }
2546
2547 /* Driver removal function
2548  * Free resources and finish pending transactions
2549  */
2550 static int fsl_udc_remove(struct platform_device *pdev)
2551 {
2552         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2553         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2554
2555         DECLARE_COMPLETION_ONSTACK(done);
2556
2557         if (!udc_controller)
2558                 return -ENODEV;
2559
2560         udc_controller->done = &done;
2561         usb_del_gadget_udc(&udc_controller->gadget);
2562
2563         fsl_udc_clk_release();
2564
2565         /* DR has been stopped in usb_gadget_unregister_driver() */
2566         remove_proc_file();
2567
2568         /* Free allocated memory */
2569         kfree(udc_controller->status_req->req.buf);
2570         kfree(udc_controller->status_req);
2571         kfree(udc_controller->eps);
2572
2573         dma_pool_destroy(udc_controller->td_pool);
2574         free_irq(udc_controller->irq, udc_controller);
2575         iounmap(dr_regs);
2576         if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2577                 release_mem_region(res->start, resource_size(res));
2578
2579         /* free udc --wait for the release() finished */
2580         wait_for_completion(&done);
2581
2582         /*
2583          * do platform specific un-initialization:
2584          * release iomux pins, etc.
2585          */
2586         if (pdata->exit)
2587                 pdata->exit(pdev);
2588
2589         return 0;
2590 }
2591
2592 /*-----------------------------------------------------------------
2593  * Modify Power management attributes
2594  * Used by OTG statemachine to disable gadget temporarily
2595  -----------------------------------------------------------------*/
2596 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2597 {
2598         dr_controller_stop(udc_controller);
2599         return 0;
2600 }
2601
2602 /*-----------------------------------------------------------------
2603  * Invoked on USB resume. May be called in_interrupt.
2604  * Here we start the DR controller and enable the irq
2605  *-----------------------------------------------------------------*/
2606 static int fsl_udc_resume(struct platform_device *pdev)
2607 {
2608         /* Enable DR irq reg and set controller Run */
2609         if (udc_controller->stopped) {
2610                 dr_controller_setup(udc_controller);
2611                 dr_controller_run(udc_controller);
2612         }
2613         udc_controller->usb_state = USB_STATE_ATTACHED;
2614         udc_controller->ep0_state = WAIT_FOR_SETUP;
2615         udc_controller->ep0_dir = 0;
2616         return 0;
2617 }
2618
2619 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2620 {
2621         struct fsl_udc *udc = udc_controller;
2622         u32 mode, usbcmd;
2623
2624         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2625
2626         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2627
2628         /*
2629          * If the controller is already stopped, then this must be a
2630          * PM suspend.  Remember this fact, so that we will leave the
2631          * controller stopped at PM resume time.
2632          */
2633         if (udc->stopped) {
2634                 pr_debug("gadget already stopped, leaving early\n");
2635                 udc->already_stopped = 1;
2636                 return 0;
2637         }
2638
2639         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2640                 pr_debug("gadget not in device mode, leaving early\n");
2641                 return 0;
2642         }
2643
2644         /* stop the controller */
2645         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2646         fsl_writel(usbcmd, &dr_regs->usbcmd);
2647
2648         udc->stopped = 1;
2649
2650         pr_info("USB Gadget suspended\n");
2651
2652         return 0;
2653 }
2654
2655 static int fsl_udc_otg_resume(struct device *dev)
2656 {
2657         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2658                  udc_controller->stopped, udc_controller->already_stopped);
2659
2660         /*
2661          * If the controller was stopped at suspend time, then
2662          * don't resume it now.
2663          */
2664         if (udc_controller->already_stopped) {
2665                 udc_controller->already_stopped = 0;
2666                 pr_debug("gadget was already stopped, leaving early\n");
2667                 return 0;
2668         }
2669
2670         pr_info("USB Gadget resume\n");
2671
2672         return fsl_udc_resume(NULL);
2673 }
2674 /*-------------------------------------------------------------------------
2675         Register entry point for the peripheral controller driver
2676 --------------------------------------------------------------------------*/
2677 static const struct platform_device_id fsl_udc_devtype[] = {
2678         {
2679                 .name = "imx-udc-mx27",
2680         }, {
2681                 .name = "imx-udc-mx51",
2682         }, {
2683                 .name = "fsl-usb2-udc",
2684         }, {
2685                 /* sentinel */
2686         }
2687 };
2688 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2689 static struct platform_driver udc_driver = {
2690         .remove         = fsl_udc_remove,
2691         /* Just for FSL i.mx SoC currently */
2692         .id_table       = fsl_udc_devtype,
2693         /* these suspend and resume are not usb suspend and resume */
2694         .suspend        = fsl_udc_suspend,
2695         .resume         = fsl_udc_resume,
2696         .driver         = {
2697                         .name = driver_name,
2698                         /* udc suspend/resume called from OTG driver */
2699                         .suspend = fsl_udc_otg_suspend,
2700                         .resume  = fsl_udc_otg_resume,
2701         },
2702 };
2703
2704 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2705
2706 MODULE_DESCRIPTION(DRIVER_DESC);
2707 MODULE_AUTHOR(DRIVER_AUTHOR);
2708 MODULE_LICENSE("GPL");
2709 MODULE_ALIAS("platform:fsl-usb2-udc");