drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 #define DWC3_ALIGN_FRAME(d, n)  (((d)->frame_number + ((d)->interval * (n))) \
  31                                         & ~((d)->interval - 1))
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - enables usb2 test modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will return 0 on
  39  * success or -EINVAL if wrong Test Selector is passed.
  40  */
  41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42 {
  43         u32             reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  47
  48         switch (mode) {
  49         case USB_TEST_J:
  50         case USB_TEST_K:
  51         case USB_TEST_SE0_NAK:
  52         case USB_TEST_PACKET:
  53         case USB_TEST_FORCE_ENABLE:
  54                 reg |= mode << 1;
  55                 break;
  56         default:
  57                 return -EINVAL;
  58         }
  59
  60         dwc3_gadget_dctl_write_safe(dwc, reg);
  61
  62         return 0;
  63 }
  64
  65 /**
  66  * dwc3_gadget_get_link_state - gets current state of usb link
  67  * @dwc: pointer to our context structure
  68  *
  69  * Caller should take care of locking. This function will
  70  * return the link state on success (>= 0) or -ETIMEDOUT.
  71  */
  72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  73 {
  74         u32             reg;
  75
  76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  77
  78         return DWC3_DSTS_USBLNKST(reg);
  79 }
  80
  81 /**
  82  * dwc3_gadget_set_link_state - sets usb link to a particular state
  83  * @dwc: pointer to our context structure
  84  * @state: the state to put link into
  85  *
  86  * Caller should take care of locking. This function will
  87  * return 0 on success or -ETIMEDOUT.
  88  */
  89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90 {
  91         int             retries = 10000;
  92         u32             reg;
  93
  94         /*
  95          * Wait until device controller is ready. Only applies to 1.94a and
  96          * later RTL.
  97          */
  98         if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
  99                 while (--retries) {
 100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 101                         if (reg & DWC3_DSTS_DCNRD)
 102                                 udelay(5);
 103                         else
 104                                 break;
 105                 }
 106
 107                 if (retries <= 0)
 108                         return -ETIMEDOUT;
 109         }
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 113
 114         /* set no action before sending new link state change */
 115         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 116
 117         /* set requested state */
 118         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 119         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 120
 121         /*
 122          * The following code is racy when called from dwc3_gadget_wakeup,
 123          * and is not needed, at least on newer versions
 124          */
 125         if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
 126                 return 0;
 127
 128         /* wait for a change in DSTS */
 129         retries = 10000;
 130         while (--retries) {
 131                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 132
 133                 if (DWC3_DSTS_USBLNKST(reg) == state)
 134                         return 0;
 135
 136                 udelay(5);
 137         }
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_ep_inc_trb - increment a trb index.
 144  * @index: Pointer to the TRB index to increment.
 145  *
 146  * The index should never point to the link TRB. After incrementing,
 147  * if it is point to the link TRB, wrap around to the beginning. The
 148  * link TRB is always at the last TRB entry.
 149  */
 150 static void dwc3_ep_inc_trb(u8 *index)
 151 {
 152         (*index)++;
 153         if (*index == (DWC3_TRB_NUM - 1))
 154                 *index = 0;
 155 }
 156
 157 /**
 158  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 159  * @dep: The endpoint whose enqueue pointer we're incrementing
 160  */
 161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 162 {
 163         dwc3_ep_inc_trb(&dep->trb_enqueue);
 164 }
 165
 166 /**
 167  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 168  * @dep: The endpoint whose enqueue pointer we're incrementing
 169  */
 170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 171 {
 172         dwc3_ep_inc_trb(&dep->trb_dequeue);
 173 }
 174
 175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
 176                 struct dwc3_request *req, int status)
 177 {
 178         struct dwc3                     *dwc = dep->dwc;
 179
 180         list_del(&req->list);
 181         req->remaining = 0;
 182         req->needs_extra_trb = false;
 183
 184         if (req->request.status == -EINPROGRESS)
 185                 req->request.status = status;
 186
 187         if (req->trb)
 188                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 189                                 &req->request, req->direction);
 190
 191         req->trb = NULL;
 192         trace_dwc3_gadget_giveback(req);
 193
 194         if (dep->number > 1)
 195                 pm_runtime_put(dwc->dev);
 196 }
 197
 198 /**
 199  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 200  * @dep: The endpoint to whom the request belongs to
 201  * @req: The request we're giving back
 202  * @status: completion code for the request
 203  *
 204  * Must be called with controller's lock held and interrupts disabled. This
 205  * function will unmap @req and call its ->complete() callback to notify upper
 206  * layers that it has completed.
 207  */
 208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 209                 int status)
 210 {
 211         struct dwc3                     *dwc = dep->dwc;
 212
 213         dwc3_gadget_del_and_unmap_request(dep, req, status);
 214         req->status = DWC3_REQUEST_STATUS_COMPLETED;
 215
 216         spin_unlock(&dwc->lock);
 217         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 218         spin_lock(&dwc->lock);
 219 }
 220
 221 /**
 222  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 223  * @dwc: pointer to the controller context
 224  * @cmd: the command to be issued
 225  * @param: command parameter
 226  *
 227  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 228  * and wait for its completion.
 229  */
 230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
 231                 u32 param)
 232 {
 233         u32             timeout = 500;
 234         int             status = 0;
 235         int             ret = 0;
 236         u32             reg;
 237
 238         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 239         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 240
 241         do {
 242                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 243                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 244                         status = DWC3_DGCMD_STATUS(reg);
 245                         if (status)
 246                                 ret = -EINVAL;
 247                         break;
 248                 }
 249         } while (--timeout);
 250
 251         if (!timeout) {
 252                 ret = -ETIMEDOUT;
 253                 status = -ETIMEDOUT;
 254         }
 255
 256         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 257
 258         return ret;
 259 }
 260
 261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 262
 263 /**
 264  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 265  * @dep: the endpoint to which the command is going to be issued
 266  * @cmd: the command to be issued
 267  * @params: parameters to the command
 268  *
 269  * Caller should handle locking. This function will issue @cmd with given
 270  * @params to @dep and wait for its completion.
 271  */
 272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 273                 struct dwc3_gadget_ep_cmd_params *params)
 274 {
 275         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 276         struct dwc3             *dwc = dep->dwc;
 277         u32                     timeout = 5000;
 278         u32                     saved_config = 0;
 279         u32                     reg;
 280
 281         int                     cmd_status = 0;
 282         int                     ret = -EINVAL;
 283
 284         /*
 285          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 286          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 287          * endpoint command.
 288          *
 289          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 290          * settings. Restore them after the command is completed.
 291          *
 292          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 293          */
 294         if (dwc->gadget->speed <= USB_SPEED_HIGH) {
 295                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 296                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 297                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 298                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 299                 }
 300
 301                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 302                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 303                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 304                 }
 305
 306                 if (saved_config)
 307                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 308         }
 309
 310         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 311                 int link_state;
 312
 313                 link_state = dwc3_gadget_get_link_state(dwc);
 314                 if (link_state == DWC3_LINK_STATE_U1 ||
 315                     link_state == DWC3_LINK_STATE_U2 ||
 316                     link_state == DWC3_LINK_STATE_U3) {
 317                         ret = __dwc3_gadget_wakeup(dwc);
 318                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 319                                         ret);
 320                 }
 321         }
 322
 323         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 324         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 325         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 326
 327         /*
 328          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 329          * not relying on XferNotReady, we can make use of a special "No
 330          * Response Update Transfer" command where we should clear both CmdAct
 331          * and CmdIOC bits.
 332          *
 333          * With this, we don't need to wait for command completion and can
 334          * straight away issue further commands to the endpoint.
 335          *
 336          * NOTICE: We're making an assumption that control endpoints will never
 337          * make use of Update Transfer command. This is a safe assumption
 338          * because we can never have more than one request at a time with
 339          * Control Endpoints. If anybody changes that assumption, this chunk
 340          * needs to be updated accordingly.
 341          */
 342         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 343                         !usb_endpoint_xfer_isoc(desc))
 344                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 345         else
 346                 cmd |= DWC3_DEPCMD_CMDACT;
 347
 348         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 349         do {
 350                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 351                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 352                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 353
 354                         switch (cmd_status) {
 355                         case 0:
 356                                 ret = 0;
 357                                 break;
 358                         case DEPEVT_TRANSFER_NO_RESOURCE:
 359                                 dev_WARN(dwc->dev, "No resource for %s\n",
 360                                          dep->name);
 361                                 ret = -EINVAL;
 362                                 break;
 363                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 364                                 /*
 365                                  * SW issues START TRANSFER command to
 366                                  * isochronous ep with future frame interval. If
 367                                  * future interval time has already passed when
 368                                  * core receives the command, it will respond
 369                                  * with an error status of 'Bus Expiry'.
 370                                  *
 371                                  * Instead of always returning -EINVAL, let's
 372                                  * give a hint to the gadget driver that this is
 373                                  * the case by returning -EAGAIN.
 374                                  */
 375                                 ret = -EAGAIN;
 376                                 break;
 377                         default:
 378                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 379                         }
 380
 381                         break;
 382                 }
 383         } while (--timeout);
 384
 385         if (timeout == 0) {
 386                 ret = -ETIMEDOUT;
 387                 cmd_status = -ETIMEDOUT;
 388         }
 389
 390         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 391
 392         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 393                 if (ret == 0)
 394                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 395
 396                 if (ret != -ETIMEDOUT)
 397                         dwc3_gadget_ep_get_transfer_index(dep);
 398         }
 399
 400         if (saved_config) {
 401                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 402                 reg |= saved_config;
 403                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 404         }
 405
 406         return ret;
 407 }
 408
 409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 410 {
 411         struct dwc3 *dwc = dep->dwc;
 412         struct dwc3_gadget_ep_cmd_params params;
 413         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 414
 415         /*
 416          * As of core revision 2.60a the recommended programming model
 417          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 418          * command for IN endpoints. This is to prevent an issue where
 419          * some (non-compliant) hosts may not send ACK TPs for pending
 420          * IN transfers due to a mishandled error condition. Synopsys
 421          * STAR 9000614252.
 422          */
 423         if (dep->direction &&
 424             !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
 425             (dwc->gadget->speed >= USB_SPEED_SUPER))
 426                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 427
 428         memset(&params, 0, sizeof(params));
 429
 430         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 431 }
 432
 433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 434                 struct dwc3_trb *trb)
 435 {
 436         u32             offset = (char *) trb - (char *) dep->trb_pool;
 437
 438         return dep->trb_pool_dma + offset;
 439 }
 440
 441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 442 {
 443         struct dwc3             *dwc = dep->dwc;
 444
 445         if (dep->trb_pool)
 446                 return 0;
 447
 448         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 449                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 450                         &dep->trb_pool_dma, GFP_KERNEL);
 451         if (!dep->trb_pool) {
 452                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 453                                 dep->name);
 454                 return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 461 {
 462         struct dwc3             *dwc = dep->dwc;
 463
 464         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 465                         dep->trb_pool, dep->trb_pool_dma);
 466
 467         dep->trb_pool = NULL;
 468         dep->trb_pool_dma = 0;
 469 }
 470
 471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
 472 {
 473         struct dwc3_gadget_ep_cmd_params params;
 474
 475         memset(&params, 0x00, sizeof(params));
 476
 477         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 478
 479         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 480                         &params);
 481 }
 482
 483 /**
 484  * dwc3_gadget_start_config - configure ep resources
 485  * @dep: endpoint that is being enabled
 486  *
 487  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 488  * completion, it will set Transfer Resource for all available endpoints.
 489  *
 490  * The assignment of transfer resources cannot perfectly follow the data book
 491  * due to the fact that the controller driver does not have all knowledge of the
 492  * configuration in advance. It is given this information piecemeal by the
 493  * composite gadget framework after every SET_CONFIGURATION and
 494  * SET_INTERFACE. Trying to follow the databook programming model in this
 495  * scenario can cause errors. For two reasons:
 496  *
 497  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 498  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 499  * incorrect in the scenario of multiple interfaces.
 500  *
 501  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
 502  * endpoint on alt setting (8.1.6).
 503  *
 504  * The following simplified method is used instead:
 505  *
 506  * All hardware endpoints can be assigned a transfer resource and this setting
 507  * will stay persistent until either a core reset or hibernation. So whenever we
 508  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 509  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
 510  * guaranteed that there are as many transfer resources as endpoints.
 511  *
 512  * This function is called for each endpoint when it is being enabled but is
 513  * triggered only when called for EP0-out, which always happens first, and which
 514  * should only happen in one of the above conditions.
 515  */
 516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519         struct dwc3             *dwc;
 520         u32                     cmd;
 521         int                     i;
 522         int                     ret;
 523
 524         if (dep->number)
 525                 return 0;
 526
 527         memset(&params, 0x00, sizeof(params));
 528         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 529         dwc = dep->dwc;
 530
 531         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 532         if (ret)
 533                 return ret;
 534
 535         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 536                 struct dwc3_ep *dep = dwc->eps[i];
 537
 538                 if (!dep)
 539                         continue;
 540
 541                 ret = dwc3_gadget_set_xfer_resource(dep);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 550 {
 551         const struct usb_ss_ep_comp_descriptor *comp_desc;
 552         const struct usb_endpoint_descriptor *desc;
 553         struct dwc3_gadget_ep_cmd_params params;
 554         struct dwc3 *dwc = dep->dwc;
 555
 556         comp_desc = dep->endpoint.comp_desc;
 557         desc = dep->endpoint.desc;
 558
 559         memset(&params, 0x00, sizeof(params));
 560
 561         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 562                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 563
 564         /* Burst size is only needed in SuperSpeed mode */
 565         if (dwc->gadget->speed >= USB_SPEED_SUPER) {
 566                 u32 burst = dep->endpoint.maxburst;
 567
 568                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 569         }
 570
 571         params.param0 |= action;
 572         if (action == DWC3_DEPCFG_ACTION_RESTORE)
 573                 params.param2 |= dep->saved_state;
 574
 575         if (usb_endpoint_xfer_control(desc))
 576                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 577
 578         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 579                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 580
 581         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 582                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 583                         | DWC3_DEPCFG_XFER_COMPLETE_EN
 584                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 585                 dep->stream_capable = true;
 586         }
 587
 588         if (!usb_endpoint_xfer_control(desc))
 589                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 590
 591         /*
 592          * We are doing 1:1 mapping for endpoints, meaning
 593          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 594          * so on. We consider the direction bit as part of the physical
 595          * endpoint number. So USB endpoint 0x81 is 0x03.
 596          */
 597         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 598
 599         /*
 600          * We must use the lower 16 TX FIFOs even though
 601          * HW might have more
 602          */
 603         if (dep->direction)
 604                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 605
 606         if (desc->bInterval) {
 607                 u8 bInterval_m1;
 608
 609                 /*
 610                  * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
 611                  *
 612                  * NOTE: The programming guide incorrectly stated bInterval_m1
 613                  * must be set to 0 when operating in fullspeed. Internally the
 614                  * controller does not have this limitation. See DWC_usb3x
 615                  * programming guide section 3.2.2.1.
 616                  */
 617                 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
 618
 619                 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
 620                     dwc->gadget->speed == USB_SPEED_FULL)
 621                         dep->interval = desc->bInterval;
 622                 else
 623                         dep->interval = 1 << (desc->bInterval - 1);
 624
 625                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
 626         }
 627
 628         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 629 }
 630
 631 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
 632                 bool interrupt);
 633
 634 /**
 635  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 636  * @dep: endpoint to be initialized
 637  * @action: one of INIT, MODIFY or RESTORE
 638  *
 639  * Caller should take care of locking. Execute all necessary commands to
 640  * initialize a HW endpoint so it can be used by a gadget driver.
 641  */
 642 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 643 {
 644         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 645         struct dwc3             *dwc = dep->dwc;
 646
 647         u32                     reg;
 648         int                     ret;
 649
 650         if (!(dep->flags & DWC3_EP_ENABLED)) {
 651                 ret = dwc3_gadget_start_config(dep);
 652                 if (ret)
 653                         return ret;
 654         }
 655
 656         ret = dwc3_gadget_set_ep_config(dep, action);
 657         if (ret)
 658                 return ret;
 659
 660         if (!(dep->flags & DWC3_EP_ENABLED)) {
 661                 struct dwc3_trb *trb_st_hw;
 662                 struct dwc3_trb *trb_link;
 663
 664                 dep->type = usb_endpoint_type(desc);
 665                 dep->flags |= DWC3_EP_ENABLED;
 666
 667                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 668                 reg |= DWC3_DALEPENA_EP(dep->number);
 669                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 670
 671                 if (usb_endpoint_xfer_control(desc))
 672                         goto out;
 673
 674                 /* Initialize the TRB ring */
 675                 dep->trb_dequeue = 0;
 676                 dep->trb_enqueue = 0;
 677                 memset(dep->trb_pool, 0,
 678                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 679
 680                 /* Link TRB. The HWO bit is never reset */
 681                 trb_st_hw = &dep->trb_pool[0];
 682
 683                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 684                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 685                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 686                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 687                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 688         }
 689
 690         /*
 691          * Issue StartTransfer here with no-op TRB so we can always rely on No
 692          * Response Update Transfer command.
 693          */
 694         if (usb_endpoint_xfer_bulk(desc) ||
 695                         usb_endpoint_xfer_int(desc)) {
 696                 struct dwc3_gadget_ep_cmd_params params;
 697                 struct dwc3_trb *trb;
 698                 dma_addr_t trb_dma;
 699                 u32 cmd;
 700
 701                 memset(&params, 0, sizeof(params));
 702                 trb = &dep->trb_pool[0];
 703                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 704
 705                 params.param0 = upper_32_bits(trb_dma);
 706                 params.param1 = lower_32_bits(trb_dma);
 707
 708                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 709
 710                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 711                 if (ret < 0)
 712                         return ret;
 713
 714                 if (dep->stream_capable) {
 715                         /*
 716                          * For streams, at start, there maybe a race where the
 717                          * host primes the endpoint before the function driver
 718                          * queues a request to initiate a stream. In that case,
 719                          * the controller will not see the prime to generate the
 720                          * ERDY and start stream. To workaround this, issue a
 721                          * no-op TRB as normal, but end it immediately. As a
 722                          * result, when the function driver queues the request,
 723                          * the next START_TRANSFER command will cause the
 724                          * controller to generate an ERDY to initiate the
 725                          * stream.
 726                          */
 727                         dwc3_stop_active_transfer(dep, true, true);
 728
 729                         /*
 730                          * All stream eps will reinitiate stream on NoStream
 731                          * rejection until we can determine that the host can
 732                          * prime after the first transfer.
 733                          *
 734                          * However, if the controller is capable of
 735                          * TXF_FLUSH_BYPASS, then IN direction endpoints will
 736                          * automatically restart the stream without the driver
 737                          * initiation.
 738                          */
 739                         if (!dep->direction ||
 740                             !(dwc->hwparams.hwparams9 &
 741                               DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
 742                                 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
 743                 }
 744         }
 745
 746 out:
 747         trace_dwc3_gadget_ep_enable(dep);
 748
 749         return 0;
 750 }
 751
 752 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 753 {
 754         struct dwc3_request             *req;
 755
 756         dwc3_stop_active_transfer(dep, true, false);
 757
 758         /* - giveback all requests to gadget driver */
 759         while (!list_empty(&dep->started_list)) {
 760                 req = next_request(&dep->started_list);
 761
 762                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 763         }
 764
 765         while (!list_empty(&dep->pending_list)) {
 766                 req = next_request(&dep->pending_list);
 767
 768                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 769         }
 770
 771         while (!list_empty(&dep->cancelled_list)) {
 772                 req = next_request(&dep->cancelled_list);
 773
 774                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 775         }
 776 }
 777
 778 /**
 779  * __dwc3_gadget_ep_disable - disables a hw endpoint
 780  * @dep: the endpoint to disable
 781  *
 782  * This function undoes what __dwc3_gadget_ep_enable did and also removes
 783  * requests which are currently being processed by the hardware and those which
 784  * are not yet scheduled.
 785  *
 786  * Caller should take care of locking.
 787  */
 788 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 789 {
 790         struct dwc3             *dwc = dep->dwc;
 791         u32                     reg;
 792
 793         trace_dwc3_gadget_ep_disable(dep);
 794
 795         /* make sure HW endpoint isn't stalled */
 796         if (dep->flags & DWC3_EP_STALL)
 797                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 798
 799         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 800         reg &= ~DWC3_DALEPENA_EP(dep->number);
 801         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 802
 803         /* Clear out the ep descriptors for non-ep0 */
 804         if (dep->number > 1) {
 805                 dep->endpoint.comp_desc = NULL;
 806                 dep->endpoint.desc = NULL;
 807         }
 808
 809         dwc3_remove_requests(dwc, dep);
 810
 811         dep->stream_capable = false;
 812         dep->type = 0;
 813         dep->flags = 0;
 814
 815         return 0;
 816 }
 817
 818 /* -------------------------------------------------------------------------- */
 819
 820 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 821                 const struct usb_endpoint_descriptor *desc)
 822 {
 823         return -EINVAL;
 824 }
 825
 826 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 827 {
 828         return -EINVAL;
 829 }
 830
 831 /* -------------------------------------------------------------------------- */
 832
 833 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 834                 const struct usb_endpoint_descriptor *desc)
 835 {
 836         struct dwc3_ep                  *dep;
 837         struct dwc3                     *dwc;
 838         unsigned long                   flags;
 839         int                             ret;
 840
 841         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 842                 pr_debug("dwc3: invalid parameters\n");
 843                 return -EINVAL;
 844         }
 845
 846         if (!desc->wMaxPacketSize) {
 847                 pr_debug("dwc3: missing wMaxPacketSize\n");
 848                 return -EINVAL;
 849         }
 850
 851         dep = to_dwc3_ep(ep);
 852         dwc = dep->dwc;
 853
 854         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 855                                         "%s is already enabled\n",
 856                                         dep->name))
 857                 return 0;
 858
 859         spin_lock_irqsave(&dwc->lock, flags);
 860         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
 861         spin_unlock_irqrestore(&dwc->lock, flags);
 862
 863         return ret;
 864 }
 865
 866 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 867 {
 868         struct dwc3_ep                  *dep;
 869         struct dwc3                     *dwc;
 870         unsigned long                   flags;
 871         int                             ret;
 872
 873         if (!ep) {
 874                 pr_debug("dwc3: invalid parameters\n");
 875                 return -EINVAL;
 876         }
 877
 878         dep = to_dwc3_ep(ep);
 879         dwc = dep->dwc;
 880
 881         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 882                                         "%s is already disabled\n",
 883                                         dep->name))
 884                 return 0;
 885
 886         spin_lock_irqsave(&dwc->lock, flags);
 887         ret = __dwc3_gadget_ep_disable(dep);
 888         spin_unlock_irqrestore(&dwc->lock, flags);
 889
 890         return ret;
 891 }
 892
 893 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 894                 gfp_t gfp_flags)
 895 {
 896         struct dwc3_request             *req;
 897         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 898
 899         req = kzalloc(sizeof(*req), gfp_flags);
 900         if (!req)
 901                 return NULL;
 902
 903         req->direction  = dep->direction;
 904         req->epnum      = dep->number;
 905         req->dep        = dep;
 906         req->status     = DWC3_REQUEST_STATUS_UNKNOWN;
 907
 908         trace_dwc3_alloc_request(req);
 909
 910         return &req->request;
 911 }
 912
 913 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 914                 struct usb_request *request)
 915 {
 916         struct dwc3_request             *req = to_dwc3_request(request);
 917
 918         trace_dwc3_free_request(req);
 919         kfree(req);
 920 }
 921
 922 /**
 923  * dwc3_ep_prev_trb - returns the previous TRB in the ring
 924  * @dep: The endpoint with the TRB ring
 925  * @index: The index of the current TRB in the ring
 926  *
 927  * Returns the TRB prior to the one pointed to by the index. If the
 928  * index is 0, we will wrap backwards, skip the link TRB, and return
 929  * the one just before that.
 930  */
 931 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 932 {
 933         u8 tmp = index;
 934
 935         if (!tmp)
 936                 tmp = DWC3_TRB_NUM - 1;
 937
 938         return &dep->trb_pool[tmp - 1];
 939 }
 940
 941 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 942 {
 943         u8                      trbs_left;
 944
 945         /*
 946          * If the enqueue & dequeue are equal then the TRB ring is either full
 947          * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
 948          * pending to be processed by the driver.
 949          */
 950         if (dep->trb_enqueue == dep->trb_dequeue) {
 951                 /*
 952                  * If there is any request remained in the started_list at
 953                  * this point, that means there is no TRB available.
 954                  */
 955                 if (!list_empty(&dep->started_list))
 956                         return 0;
 957
 958                 return DWC3_TRB_NUM - 1;
 959         }
 960
 961         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 962         trbs_left &= (DWC3_TRB_NUM - 1);
 963
 964         if (dep->trb_dequeue < dep->trb_enqueue)
 965                 trbs_left--;
 966
 967         return trbs_left;
 968 }
 969
 970 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
 971                 dma_addr_t dma, unsigned int length, unsigned int chain,
 972                 unsigned int node, unsigned int stream_id,
 973                 unsigned int short_not_ok, unsigned int no_interrupt,
 974                 unsigned int is_last, bool must_interrupt)
 975 {
 976         struct dwc3             *dwc = dep->dwc;
 977         struct usb_gadget       *gadget = dwc->gadget;
 978         enum usb_device_speed   speed = gadget->speed;
 979
 980         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 981         trb->bpl = lower_32_bits(dma);
 982         trb->bph = upper_32_bits(dma);
 983
 984         switch (usb_endpoint_type(dep->endpoint.desc)) {
 985         case USB_ENDPOINT_XFER_CONTROL:
 986                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 987                 break;
 988
 989         case USB_ENDPOINT_XFER_ISOC:
 990                 if (!node) {
 991                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 992
 993                         /*
 994                          * USB Specification 2.0 Section 5.9.2 states that: "If
 995                          * there is only a single transaction in the microframe,
 996                          * only a DATA0 data packet PID is used.  If there are
 997                          * two transactions per microframe, DATA1 is used for
 998                          * the first transaction data packet and DATA0 is used
 999                          * for the second transaction data packet.  If there are
1000                          * three transactions per microframe, DATA2 is used for
1001                          * the first transaction data packet, DATA1 is used for
1002                          * the second, and DATA0 is used for the third."
1003                          *
1004                          * IOW, we should satisfy the following cases:
1005                          *
1006                          * 1) length <= maxpacket
1007                          *      - DATA0
1008                          *
1009                          * 2) maxpacket < length <= (2 * maxpacket)
1010                          *      - DATA1, DATA0
1011                          *
1012                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1013                          *      - DATA2, DATA1, DATA0
1014                          */
1015                         if (speed == USB_SPEED_HIGH) {
1016                                 struct usb_ep *ep = &dep->endpoint;
1017                                 unsigned int mult = 2;
1018                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1019
1020                                 if (length <= (2 * maxp))
1021                                         mult--;
1022
1023                                 if (length <= maxp)
1024                                         mult--;
1025
1026                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1027                         }
1028                 } else {
1029                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1030                 }
1031
1032                 /* always enable Interrupt on Missed ISOC */
1033                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1034                 break;
1035
1036         case USB_ENDPOINT_XFER_BULK:
1037         case USB_ENDPOINT_XFER_INT:
1038                 trb->ctrl = DWC3_TRBCTL_NORMAL;
1039                 break;
1040         default:
1041                 /*
1042                  * This is only possible with faulty memory because we
1043                  * checked it already :)
1044                  */
1045                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1046                                 usb_endpoint_type(dep->endpoint.desc));
1047         }
1048
1049         /*
1050          * Enable Continue on Short Packet
1051          * when endpoint is not a stream capable
1052          */
1053         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1054                 if (!dep->stream_capable)
1055                         trb->ctrl |= DWC3_TRB_CTRL_CSP;
1056
1057                 if (short_not_ok)
1058                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1059         }
1060
1061         if ((!no_interrupt && !chain) || must_interrupt)
1062                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1063
1064         if (chain)
1065                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1066         else if (dep->stream_capable && is_last)
1067                 trb->ctrl |= DWC3_TRB_CTRL_LST;
1068
1069         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1070                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1071
1072         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1073
1074         dwc3_ep_inc_enq(dep);
1075
1076         trace_dwc3_prepare_trb(dep, trb);
1077 }
1078
1079 /**
1080  * dwc3_prepare_one_trb - setup one TRB from one request
1081  * @dep: endpoint for which this request is prepared
1082  * @req: dwc3_request pointer
1083  * @trb_length: buffer size of the TRB
1084  * @chain: should this TRB be chained to the next?
1085  * @node: only for isochronous endpoints. First TRB needs different type.
1086  * @use_bounce_buffer: set to use bounce buffer
1087  * @must_interrupt: set to interrupt on TRB completion
1088  */
1089 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1090                 struct dwc3_request *req, unsigned int trb_length,
1091                 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1092                 bool must_interrupt)
1093 {
1094         struct dwc3_trb         *trb;
1095         dma_addr_t              dma;
1096         unsigned int            stream_id = req->request.stream_id;
1097         unsigned int            short_not_ok = req->request.short_not_ok;
1098         unsigned int            no_interrupt = req->request.no_interrupt;
1099         unsigned int            is_last = req->request.is_last;
1100
1101         if (use_bounce_buffer)
1102                 dma = dep->dwc->bounce_addr;
1103         else if (req->request.num_sgs > 0)
1104                 dma = sg_dma_address(req->start_sg);
1105         else
1106                 dma = req->request.dma;
1107
1108         trb = &dep->trb_pool[dep->trb_enqueue];
1109
1110         if (!req->trb) {
1111                 dwc3_gadget_move_started_request(req);
1112                 req->trb = trb;
1113                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1114         }
1115
1116         req->num_trbs++;
1117
1118         __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1119                         stream_id, short_not_ok, no_interrupt, is_last,
1120                         must_interrupt);
1121 }
1122
1123 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1124 {
1125         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1126         unsigned int rem = req->request.length % maxp;
1127
1128         if ((req->request.length && req->request.zero && !rem &&
1129                         !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1130                         (!req->direction && rem))
1131                 return true;
1132
1133         return false;
1134 }
1135
1136 /**
1137  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1138  * @dep: The endpoint that the request belongs to
1139  * @req: The request to prepare
1140  * @entry_length: The last SG entry size
1141  * @node: Indicates whether this is not the first entry (for isoc only)
1142  *
1143  * Return the number of TRBs prepared.
1144  */
1145 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1146                 struct dwc3_request *req, unsigned int entry_length,
1147                 unsigned int node)
1148 {
1149         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1150         unsigned int rem = req->request.length % maxp;
1151         unsigned int num_trbs = 1;
1152
1153         if (dwc3_needs_extra_trb(dep, req))
1154                 num_trbs++;
1155
1156         if (dwc3_calc_trbs_left(dep) < num_trbs)
1157                 return 0;
1158
1159         req->needs_extra_trb = num_trbs > 1;
1160
1161         /* Prepare a normal TRB */
1162         if (req->direction || req->request.length)
1163                 dwc3_prepare_one_trb(dep, req, entry_length,
1164                                 req->needs_extra_trb, node, false, false);
1165
1166         /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1167         if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1168                 dwc3_prepare_one_trb(dep, req,
1169                                 req->direction ? 0 : maxp - rem,
1170                                 false, 1, true, false);
1171
1172         return num_trbs;
1173 }
1174
1175 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1176                 struct dwc3_request *req)
1177 {
1178         struct scatterlist *sg = req->start_sg;
1179         struct scatterlist *s;
1180         int             i;
1181         unsigned int length = req->request.length;
1182         unsigned int remaining = req->request.num_mapped_sgs
1183                 - req->num_queued_sgs;
1184         unsigned int num_trbs = req->num_trbs;
1185         bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1186
1187         /*
1188          * If we resume preparing the request, then get the remaining length of
1189          * the request and resume where we left off.
1190          */
1191         for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1192                 length -= sg_dma_len(s);
1193
1194         for_each_sg(sg, s, remaining, i) {
1195                 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1196                 unsigned int trb_length;
1197                 bool must_interrupt = false;
1198                 bool last_sg = false;
1199
1200                 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1201
1202                 length -= trb_length;
1203
1204                 /*
1205                  * IOMMU driver is coalescing the list of sgs which shares a
1206                  * page boundary into one and giving it to USB driver. With
1207                  * this the number of sgs mapped is not equal to the number of
1208                  * sgs passed. So mark the chain bit to false if it isthe last
1209                  * mapped sg.
1210                  */
1211                 if ((i == remaining - 1) || !length)
1212                         last_sg = true;
1213
1214                 if (!num_trbs_left)
1215                         break;
1216
1217                 if (last_sg) {
1218                         if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1219                                 break;
1220                 } else {
1221                         /*
1222                          * Look ahead to check if we have enough TRBs for the
1223                          * next SG entry. If not, set interrupt on this TRB to
1224                          * resume preparing the next SG entry when more TRBs are
1225                          * free.
1226                          */
1227                         if (num_trbs_left == 1 || (needs_extra_trb &&
1228                                         num_trbs_left <= 2 &&
1229                                         sg_dma_len(sg_next(s)) >= length))
1230                                 must_interrupt = true;
1231
1232                         dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1233                                         must_interrupt);
1234                 }
1235
1236                 /*
1237                  * There can be a situation where all sgs in sglist are not
1238                  * queued because of insufficient trb number. To handle this
1239                  * case, update start_sg to next sg to be queued, so that
1240                  * we have free trbs we can continue queuing from where we
1241                  * previously stopped
1242                  */
1243                 if (!last_sg)
1244                         req->start_sg = sg_next(s);
1245
1246                 req->num_queued_sgs++;
1247                 req->num_pending_sgs--;
1248
1249                 /*
1250                  * The number of pending SG entries may not correspond to the
1251                  * number of mapped SG entries. If all the data are queued, then
1252                  * don't include unused SG entries.
1253                  */
1254                 if (length == 0) {
1255                         req->num_pending_sgs = 0;
1256                         break;
1257                 }
1258
1259                 if (must_interrupt)
1260                         break;
1261         }
1262
1263         return req->num_trbs - num_trbs;
1264 }
1265
1266 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1267                 struct dwc3_request *req)
1268 {
1269         return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1270 }
1271
1272 /*
1273  * dwc3_prepare_trbs - setup TRBs from requests
1274  * @dep: endpoint for which requests are being prepared
1275  *
1276  * The function goes through the requests list and sets up TRBs for the
1277  * transfers. The function returns once there are no more TRBs available or
1278  * it runs out of requests.
1279  *
1280  * Returns the number of TRBs prepared or negative errno.
1281  */
1282 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1283 {
1284         struct dwc3_request     *req, *n;
1285         int                     ret = 0;
1286
1287         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1288
1289         /*
1290          * We can get in a situation where there's a request in the started list
1291          * but there weren't enough TRBs to fully kick it in the first time
1292          * around, so it has been waiting for more TRBs to be freed up.
1293          *
1294          * In that case, we should check if we have a request with pending_sgs
1295          * in the started list and prepare TRBs for that request first,
1296          * otherwise we will prepare TRBs completely out of order and that will
1297          * break things.
1298          */
1299         list_for_each_entry(req, &dep->started_list, list) {
1300                 if (req->num_pending_sgs > 0) {
1301                         ret = dwc3_prepare_trbs_sg(dep, req);
1302                         if (!ret || req->num_pending_sgs)
1303                                 return ret;
1304                 }
1305
1306                 if (!dwc3_calc_trbs_left(dep))
1307                         return ret;
1308
1309                 /*
1310                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1311                  * burst capability may try to read and use TRBs beyond the
1312                  * active transfer instead of stopping.
1313                  */
1314                 if (dep->stream_capable && req->request.is_last)
1315                         return ret;
1316         }
1317
1318         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1319                 struct dwc3     *dwc = dep->dwc;
1320
1321                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1322                                                     dep->direction);
1323                 if (ret)
1324                         return ret;
1325
1326                 req->sg                 = req->request.sg;
1327                 req->start_sg           = req->sg;
1328                 req->num_queued_sgs     = 0;
1329                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1330
1331                 if (req->num_pending_sgs > 0) {
1332                         ret = dwc3_prepare_trbs_sg(dep, req);
1333                         if (req->num_pending_sgs)
1334                                 return ret;
1335                 } else {
1336                         ret = dwc3_prepare_trbs_linear(dep, req);
1337                 }
1338
1339                 if (!ret || !dwc3_calc_trbs_left(dep))
1340                         return ret;
1341
1342                 /*
1343                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1344                  * burst capability may try to read and use TRBs beyond the
1345                  * active transfer instead of stopping.
1346                  */
1347                 if (dep->stream_capable && req->request.is_last)
1348                         return ret;
1349         }
1350
1351         return ret;
1352 }
1353
1354 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1355
1356 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1357 {
1358         struct dwc3_gadget_ep_cmd_params params;
1359         struct dwc3_request             *req;
1360         int                             starting;
1361         int                             ret;
1362         u32                             cmd;
1363
1364         /*
1365          * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1366          * This happens when we need to stop and restart a transfer such as in
1367          * the case of reinitiating a stream or retrying an isoc transfer.
1368          */
1369         ret = dwc3_prepare_trbs(dep);
1370         if (ret < 0)
1371                 return ret;
1372
1373         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1374
1375         /*
1376          * If there's no new TRB prepared and we don't need to restart a
1377          * transfer, there's no need to update the transfer.
1378          */
1379         if (!ret && !starting)
1380                 return ret;
1381
1382         req = next_request(&dep->started_list);
1383         if (!req) {
1384                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1385                 return 0;
1386         }
1387
1388         memset(&params, 0, sizeof(params));
1389
1390         if (starting) {
1391                 params.param0 = upper_32_bits(req->trb_dma);
1392                 params.param1 = lower_32_bits(req->trb_dma);
1393                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1394
1395                 if (dep->stream_capable)
1396                         cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1397
1398                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1399                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1400         } else {
1401                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1402                         DWC3_DEPCMD_PARAM(dep->resource_index);
1403         }
1404
1405         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1406         if (ret < 0) {
1407                 struct dwc3_request *tmp;
1408
1409                 if (ret == -EAGAIN)
1410                         return ret;
1411
1412                 dwc3_stop_active_transfer(dep, true, true);
1413
1414                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1415                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1416
1417                 /* If ep isn't started, then there's no end transfer pending */
1418                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1419                         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1420
1421                 return ret;
1422         }
1423
1424         if (dep->stream_capable && req->request.is_last)
1425                 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1426
1427         return 0;
1428 }
1429
1430 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1431 {
1432         u32                     reg;
1433
1434         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1435         return DWC3_DSTS_SOFFN(reg);
1436 }
1437
1438 /**
1439  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1440  * @dep: isoc endpoint
1441  *
1442  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1443  * microframe number reported by the XferNotReady event for the future frame
1444  * number to start the isoc transfer.
1445  *
1446  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1447  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1448  * XferNotReady event are invalid. The driver uses this number to schedule the
1449  * isochronous transfer and passes it to the START TRANSFER command. Because
1450  * this number is invalid, the command may fail. If BIT[15:14] matches the
1451  * internal 16-bit microframe, the START TRANSFER command will pass and the
1452  * transfer will start at the scheduled time, if it is off by 1, the command
1453  * will still pass, but the transfer will start 2 seconds in the future. For all
1454  * other conditions, the START TRANSFER command will fail with bus-expiry.
1455  *
1456  * In order to workaround this issue, we can test for the correct combination of
1457  * BIT[15:14] by sending START TRANSFER commands with different values of
1458  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1459  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1460  * As the result, within the 4 possible combinations for BIT[15:14], there will
1461  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1462  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1463  * value is the correct combination.
1464  *
1465  * Since there are only 4 outcomes and the results are ordered, we can simply
1466  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1467  * deduce the smaller successful combination.
1468  *
1469  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1470  * of BIT[15:14]. The correct combination is as follow:
1471  *
1472  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1473  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1474  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1475  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1476  *
1477  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1478  * endpoints.
1479  */
1480 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1481 {
1482         int cmd_status = 0;
1483         bool test0;
1484         bool test1;
1485
1486         while (dep->combo_num < 2) {
1487                 struct dwc3_gadget_ep_cmd_params params;
1488                 u32 test_frame_number;
1489                 u32 cmd;
1490
1491                 /*
1492                  * Check if we can start isoc transfer on the next interval or
1493                  * 4 uframes in the future with BIT[15:14] as dep->combo_num
1494                  */
1495                 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1496                 test_frame_number |= dep->combo_num << 14;
1497                 test_frame_number += max_t(u32, 4, dep->interval);
1498
1499                 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1500                 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1501
1502                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1503                 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1504                 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1505
1506                 /* Redo if some other failure beside bus-expiry is received */
1507                 if (cmd_status && cmd_status != -EAGAIN) {
1508                         dep->start_cmd_status = 0;
1509                         dep->combo_num = 0;
1510                         return 0;
1511                 }
1512
1513                 /* Store the first test status */
1514                 if (dep->combo_num == 0)
1515                         dep->start_cmd_status = cmd_status;
1516
1517                 dep->combo_num++;
1518
1519                 /*
1520                  * End the transfer if the START_TRANSFER command is successful
1521                  * to wait for the next XferNotReady to test the command again
1522                  */
1523                 if (cmd_status == 0) {
1524                         dwc3_stop_active_transfer(dep, true, true);
1525                         return 0;
1526                 }
1527         }
1528
1529         /* test0 and test1 are both completed at this point */
1530         test0 = (dep->start_cmd_status == 0);
1531         test1 = (cmd_status == 0);
1532
1533         if (!test0 && test1)
1534                 dep->combo_num = 1;
1535         else if (!test0 && !test1)
1536                 dep->combo_num = 2;
1537         else if (test0 && !test1)
1538                 dep->combo_num = 3;
1539         else if (test0 && test1)
1540                 dep->combo_num = 0;
1541
1542         dep->frame_number &= DWC3_FRNUMBER_MASK;
1543         dep->frame_number |= dep->combo_num << 14;
1544         dep->frame_number += max_t(u32, 4, dep->interval);
1545
1546         /* Reinitialize test variables */
1547         dep->start_cmd_status = 0;
1548         dep->combo_num = 0;
1549
1550         return __dwc3_gadget_kick_transfer(dep);
1551 }
1552
1553 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1554 {
1555         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1556         struct dwc3 *dwc = dep->dwc;
1557         int ret;
1558         int i;
1559
1560         if (list_empty(&dep->pending_list) &&
1561             list_empty(&dep->started_list)) {
1562                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1563                 return -EAGAIN;
1564         }
1565
1566         if (!dwc->dis_start_transfer_quirk &&
1567             (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1568              DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1569                 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1570                         return dwc3_gadget_start_isoc_quirk(dep);
1571         }
1572
1573         if (desc->bInterval <= 14 &&
1574             dwc->gadget->speed >= USB_SPEED_HIGH) {
1575                 u32 frame = __dwc3_gadget_get_frame(dwc);
1576                 bool rollover = frame <
1577                                 (dep->frame_number & DWC3_FRNUMBER_MASK);
1578
1579                 /*
1580                  * frame_number is set from XferNotReady and may be already
1581                  * out of date. DSTS only provides the lower 14 bit of the
1582                  * current frame number. So add the upper two bits of
1583                  * frame_number and handle a possible rollover.
1584                  * This will provide the correct frame_number unless more than
1585                  * rollover has happened since XferNotReady.
1586                  */
1587
1588                 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1589                                      frame;
1590                 if (rollover)
1591                         dep->frame_number += BIT(14);
1592         }
1593
1594         for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1595                 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1596
1597                 ret = __dwc3_gadget_kick_transfer(dep);
1598                 if (ret != -EAGAIN)
1599                         break;
1600         }
1601
1602         /*
1603          * After a number of unsuccessful start attempts due to bus-expiry
1604          * status, issue END_TRANSFER command and retry on the next XferNotReady
1605          * event.
1606          */
1607         if (ret == -EAGAIN) {
1608                 struct dwc3_gadget_ep_cmd_params params;
1609                 u32 cmd;
1610
1611                 cmd = DWC3_DEPCMD_ENDTRANSFER |
1612                         DWC3_DEPCMD_CMDIOC |
1613                         DWC3_DEPCMD_PARAM(dep->resource_index);
1614
1615                 dep->resource_index = 0;
1616                 memset(&params, 0, sizeof(params));
1617
1618                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1619                 if (!ret)
1620                         dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1621         }
1622
1623         return ret;
1624 }
1625
1626 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1627 {
1628         struct dwc3             *dwc = dep->dwc;
1629
1630         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1631                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1632                                 dep->name);
1633                 return -ESHUTDOWN;
1634         }
1635
1636         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1637                                 &req->request, req->dep->name))
1638                 return -EINVAL;
1639
1640         if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1641                                 "%s: request %pK already in flight\n",
1642                                 dep->name, &req->request))
1643                 return -EINVAL;
1644
1645         pm_runtime_get(dwc->dev);
1646
1647         req->request.actual     = 0;
1648         req->request.status     = -EINPROGRESS;
1649
1650         trace_dwc3_ep_queue(req);
1651
1652         list_add_tail(&req->list, &dep->pending_list);
1653         req->status = DWC3_REQUEST_STATUS_QUEUED;
1654
1655         if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1656                 return 0;
1657
1658         /*
1659          * Start the transfer only after the END_TRANSFER is completed
1660          * and endpoint STALL is cleared.
1661          */
1662         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1663             (dep->flags & DWC3_EP_WEDGE) ||
1664             (dep->flags & DWC3_EP_STALL)) {
1665                 dep->flags |= DWC3_EP_DELAY_START;
1666                 return 0;
1667         }
1668
1669         /*
1670          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1671          * wait for a XferNotReady event so we will know what's the current
1672          * (micro-)frame number.
1673          *
1674          * Without this trick, we are very, very likely gonna get Bus Expiry
1675          * errors which will force us issue EndTransfer command.
1676          */
1677         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1678                 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1679                                 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1680                         return 0;
1681
1682                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1683                         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1684                                 return __dwc3_gadget_start_isoc(dep);
1685                 }
1686         }
1687
1688         __dwc3_gadget_kick_transfer(dep);
1689
1690         return 0;
1691 }
1692
1693 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1694         gfp_t gfp_flags)
1695 {
1696         struct dwc3_request             *req = to_dwc3_request(request);
1697         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1698         struct dwc3                     *dwc = dep->dwc;
1699
1700         unsigned long                   flags;
1701
1702         int                             ret;
1703
1704         spin_lock_irqsave(&dwc->lock, flags);
1705         ret = __dwc3_gadget_ep_queue(dep, req);
1706         spin_unlock_irqrestore(&dwc->lock, flags);
1707
1708         return ret;
1709 }
1710
1711 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1712 {
1713         int i;
1714
1715         /* If req->trb is not set, then the request has not started */
1716         if (!req->trb)
1717                 return;
1718
1719         /*
1720          * If request was already started, this means we had to
1721          * stop the transfer. With that we also need to ignore
1722          * all TRBs used by the request, however TRBs can only
1723          * be modified after completion of END_TRANSFER
1724          * command. So what we do here is that we wait for
1725          * END_TRANSFER completion and only after that, we jump
1726          * over TRBs by clearing HWO and incrementing dequeue
1727          * pointer.
1728          */
1729         for (i = 0; i < req->num_trbs; i++) {
1730                 struct dwc3_trb *trb;
1731
1732                 trb = &dep->trb_pool[dep->trb_dequeue];
1733                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1734                 dwc3_ep_inc_deq(dep);
1735         }
1736
1737         req->num_trbs = 0;
1738 }
1739
1740 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1741 {
1742         struct dwc3_request             *req;
1743         struct dwc3_request             *tmp;
1744         struct dwc3                     *dwc = dep->dwc;
1745
1746         list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1747                 dwc3_gadget_ep_skip_trbs(dep, req);
1748                 switch (req->status) {
1749                 case DWC3_REQUEST_STATUS_DISCONNECTED:
1750                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1751                         break;
1752                 case DWC3_REQUEST_STATUS_DEQUEUED:
1753                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1754                         break;
1755                 case DWC3_REQUEST_STATUS_STALLED:
1756                         dwc3_gadget_giveback(dep, req, -EPIPE);
1757                         break;
1758                 default:
1759                         dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1760                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1761                         break;
1762                 }
1763         }
1764 }
1765
1766 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1767                 struct usb_request *request)
1768 {
1769         struct dwc3_request             *req = to_dwc3_request(request);
1770         struct dwc3_request             *r = NULL;
1771
1772         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1773         struct dwc3                     *dwc = dep->dwc;
1774
1775         unsigned long                   flags;
1776         int                             ret = 0;
1777
1778         trace_dwc3_ep_dequeue(req);
1779
1780         spin_lock_irqsave(&dwc->lock, flags);
1781
1782         list_for_each_entry(r, &dep->cancelled_list, list) {
1783                 if (r == req)
1784                         goto out;
1785         }
1786
1787         list_for_each_entry(r, &dep->pending_list, list) {
1788                 if (r == req) {
1789                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1790                         goto out;
1791                 }
1792         }
1793
1794         list_for_each_entry(r, &dep->started_list, list) {
1795                 if (r == req) {
1796                         struct dwc3_request *t;
1797
1798                         /* wait until it is processed */
1799                         dwc3_stop_active_transfer(dep, true, true);
1800
1801                         /*
1802                          * Remove any started request if the transfer is
1803                          * cancelled.
1804                          */
1805                         list_for_each_entry_safe(r, t, &dep->started_list, list)
1806                                 dwc3_gadget_move_cancelled_request(r,
1807                                                 DWC3_REQUEST_STATUS_DEQUEUED);
1808
1809                         dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1810
1811                         goto out;
1812                 }
1813         }
1814
1815         dev_err(dwc->dev, "request %pK was not queued to %s\n",
1816                 request, ep->name);
1817         ret = -EINVAL;
1818 out:
1819         spin_unlock_irqrestore(&dwc->lock, flags);
1820
1821         return ret;
1822 }
1823
1824 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1825 {
1826         struct dwc3_gadget_ep_cmd_params        params;
1827         struct dwc3                             *dwc = dep->dwc;
1828         struct dwc3_request                     *req;
1829         struct dwc3_request                     *tmp;
1830         int                                     ret;
1831
1832         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1833                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1834                 return -EINVAL;
1835         }
1836
1837         memset(&params, 0x00, sizeof(params));
1838
1839         if (value) {
1840                 struct dwc3_trb *trb;
1841
1842                 unsigned int transfer_in_flight;
1843                 unsigned int started;
1844
1845                 if (dep->number > 1)
1846                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1847                 else
1848                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1849
1850                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1851                 started = !list_empty(&dep->started_list);
1852
1853                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1854                                 (!dep->direction && started))) {
1855                         return -EAGAIN;
1856                 }
1857
1858                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1859                                 &params);
1860                 if (ret)
1861                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1862                                         dep->name);
1863                 else
1864                         dep->flags |= DWC3_EP_STALL;
1865         } else {
1866                 /*
1867                  * Don't issue CLEAR_STALL command to control endpoints. The
1868                  * controller automatically clears the STALL when it receives
1869                  * the SETUP token.
1870                  */
1871                 if (dep->number <= 1) {
1872                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1873                         return 0;
1874                 }
1875
1876                 dwc3_stop_active_transfer(dep, true, true);
1877
1878                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1879                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
1880
1881                 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1882                         dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1883                         return 0;
1884                 }
1885
1886                 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1887
1888                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1889                 if (ret) {
1890                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1891                                         dep->name);
1892                         return ret;
1893                 }
1894
1895                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1896
1897                 if ((dep->flags & DWC3_EP_DELAY_START) &&
1898                     !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1899                         __dwc3_gadget_kick_transfer(dep);
1900
1901                 dep->flags &= ~DWC3_EP_DELAY_START;
1902         }
1903
1904         return ret;
1905 }
1906
1907 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1908 {
1909         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1910         struct dwc3                     *dwc = dep->dwc;
1911
1912         unsigned long                   flags;
1913
1914         int                             ret;
1915
1916         spin_lock_irqsave(&dwc->lock, flags);
1917         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1918         spin_unlock_irqrestore(&dwc->lock, flags);
1919
1920         return ret;
1921 }
1922
1923 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1924 {
1925         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1926         struct dwc3                     *dwc = dep->dwc;
1927         unsigned long                   flags;
1928         int                             ret;
1929
1930         spin_lock_irqsave(&dwc->lock, flags);
1931         dep->flags |= DWC3_EP_WEDGE;
1932
1933         if (dep->number == 0 || dep->number == 1)
1934                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1935         else
1936                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1937         spin_unlock_irqrestore(&dwc->lock, flags);
1938
1939         return ret;
1940 }
1941
1942 /* -------------------------------------------------------------------------- */
1943
1944 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1945         .bLength        = USB_DT_ENDPOINT_SIZE,
1946         .bDescriptorType = USB_DT_ENDPOINT,
1947         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1948 };
1949
1950 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1951         .enable         = dwc3_gadget_ep0_enable,
1952         .disable        = dwc3_gadget_ep0_disable,
1953         .alloc_request  = dwc3_gadget_ep_alloc_request,
1954         .free_request   = dwc3_gadget_ep_free_request,
1955         .queue          = dwc3_gadget_ep0_queue,
1956         .dequeue        = dwc3_gadget_ep_dequeue,
1957         .set_halt       = dwc3_gadget_ep0_set_halt,
1958         .set_wedge      = dwc3_gadget_ep_set_wedge,
1959 };
1960
1961 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1962         .enable         = dwc3_gadget_ep_enable,
1963         .disable        = dwc3_gadget_ep_disable,
1964         .alloc_request  = dwc3_gadget_ep_alloc_request,
1965         .free_request   = dwc3_gadget_ep_free_request,
1966         .queue          = dwc3_gadget_ep_queue,
1967         .dequeue        = dwc3_gadget_ep_dequeue,
1968         .set_halt       = dwc3_gadget_ep_set_halt,
1969         .set_wedge      = dwc3_gadget_ep_set_wedge,
1970 };
1971
1972 /* -------------------------------------------------------------------------- */
1973
1974 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1975 {
1976         struct dwc3             *dwc = gadget_to_dwc(g);
1977
1978         return __dwc3_gadget_get_frame(dwc);
1979 }
1980
1981 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1982 {
1983         int                     retries;
1984
1985         int                     ret;
1986         u32                     reg;
1987
1988         u8                      link_state;
1989
1990         /*
1991          * According to the Databook Remote wakeup request should
1992          * be issued only when the device is in early suspend state.
1993          *
1994          * We can check that via USB Link State bits in DSTS register.
1995          */
1996         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1997
1998         link_state = DWC3_DSTS_USBLNKST(reg);
1999
2000         switch (link_state) {
2001         case DWC3_LINK_STATE_RESET:
2002         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
2003         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
2004         case DWC3_LINK_STATE_U2:        /* in HS, means Sleep (L1) */
2005         case DWC3_LINK_STATE_U1:
2006         case DWC3_LINK_STATE_RESUME:
2007                 break;
2008         default:
2009                 return -EINVAL;
2010         }
2011
2012         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2013         if (ret < 0) {
2014                 dev_err(dwc->dev, "failed to put link in Recovery\n");
2015                 return ret;
2016         }
2017
2018         /* Recent versions do this automatically */
2019         if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2020                 /* write zeroes to Link Change Request */
2021                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2022                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2023                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2024         }
2025
2026         /* poll until Link State changes to ON */
2027         retries = 20000;
2028
2029         while (retries--) {
2030                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2031
2032                 /* in HS, means ON */
2033                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2034                         break;
2035         }
2036
2037         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2038                 dev_err(dwc->dev, "failed to send remote wakeup\n");
2039                 return -EINVAL;
2040         }
2041
2042         return 0;
2043 }
2044
2045 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2046 {
2047         struct dwc3             *dwc = gadget_to_dwc(g);
2048         unsigned long           flags;
2049         int                     ret;
2050
2051         spin_lock_irqsave(&dwc->lock, flags);
2052         ret = __dwc3_gadget_wakeup(dwc);
2053         spin_unlock_irqrestore(&dwc->lock, flags);
2054
2055         return ret;
2056 }
2057
2058 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2059                 int is_selfpowered)
2060 {
2061         struct dwc3             *dwc = gadget_to_dwc(g);
2062         unsigned long           flags;
2063
2064         spin_lock_irqsave(&dwc->lock, flags);
2065         g->is_selfpowered = !!is_selfpowered;
2066         spin_unlock_irqrestore(&dwc->lock, flags);
2067
2068         return 0;
2069 }
2070
2071 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2072 {
2073         u32 epnum;
2074
2075         for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2076                 struct dwc3_ep *dep;
2077
2078                 dep = dwc->eps[epnum];
2079                 if (!dep)
2080                         continue;
2081
2082                 dwc3_remove_requests(dwc, dep);
2083         }
2084 }
2085
2086 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2087 {
2088         enum usb_ssp_rate       ssp_rate = dwc->gadget_ssp_rate;
2089         u32                     reg;
2090
2091         if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2092                 ssp_rate = dwc->max_ssp_rate;
2093
2094         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2095         reg &= ~DWC3_DCFG_SPEED_MASK;
2096         reg &= ~DWC3_DCFG_NUMLANES(~0);
2097
2098         if (ssp_rate == USB_SSP_GEN_1x2)
2099                 reg |= DWC3_DCFG_SUPERSPEED;
2100         else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2101                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2102
2103         if (ssp_rate != USB_SSP_GEN_2x1 &&
2104             dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2105                 reg |= DWC3_DCFG_NUMLANES(1);
2106
2107         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2108 }
2109
2110 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2111 {
2112         enum usb_device_speed   speed;
2113         u32                     reg;
2114
2115         speed = dwc->gadget_max_speed;
2116         if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2117                 speed = dwc->maximum_speed;
2118
2119         if (speed == USB_SPEED_SUPER_PLUS &&
2120             DWC3_IP_IS(DWC32)) {
2121                 __dwc3_gadget_set_ssp_rate(dwc);
2122                 return;
2123         }
2124
2125         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2126         reg &= ~(DWC3_DCFG_SPEED_MASK);
2127
2128         /*
2129          * WORKAROUND: DWC3 revision < 2.20a have an issue
2130          * which would cause metastability state on Run/Stop
2131          * bit if we try to force the IP to USB2-only mode.
2132          *
2133          * Because of that, we cannot configure the IP to any
2134          * speed other than the SuperSpeed
2135          *
2136          * Refers to:
2137          *
2138          * STAR#9000525659: Clock Domain Crossing on DCTL in
2139          * USB 2.0 Mode
2140          */
2141         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2142             !dwc->dis_metastability_quirk) {
2143                 reg |= DWC3_DCFG_SUPERSPEED;
2144         } else {
2145                 switch (speed) {
2146                 case USB_SPEED_FULL:
2147                         reg |= DWC3_DCFG_FULLSPEED;
2148                         break;
2149                 case USB_SPEED_HIGH:
2150                         reg |= DWC3_DCFG_HIGHSPEED;
2151                         break;
2152                 case USB_SPEED_SUPER:
2153                         reg |= DWC3_DCFG_SUPERSPEED;
2154                         break;
2155                 case USB_SPEED_SUPER_PLUS:
2156                         if (DWC3_IP_IS(DWC3))
2157                                 reg |= DWC3_DCFG_SUPERSPEED;
2158                         else
2159                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2160                         break;
2161                 default:
2162                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2163
2164                         if (DWC3_IP_IS(DWC3))
2165                                 reg |= DWC3_DCFG_SUPERSPEED;
2166                         else
2167                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2168                 }
2169         }
2170
2171         if (DWC3_IP_IS(DWC32) &&
2172             speed > USB_SPEED_UNKNOWN &&
2173             speed < USB_SPEED_SUPER_PLUS)
2174                 reg &= ~DWC3_DCFG_NUMLANES(~0);
2175
2176         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2177 }
2178
2179 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2180 {
2181         u32                     reg;
2182         u32                     timeout = 500;
2183
2184         if (pm_runtime_suspended(dwc->dev))
2185                 return 0;
2186
2187         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2188         if (is_on) {
2189                 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2190                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
2191                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
2192                 }
2193
2194                 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2195                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2196                 reg |= DWC3_DCTL_RUN_STOP;
2197
2198                 if (dwc->has_hibernation)
2199                         reg |= DWC3_DCTL_KEEP_CONNECT;
2200
2201                 __dwc3_gadget_set_speed(dwc);
2202                 dwc->pullups_connected = true;
2203         } else {
2204                 reg &= ~DWC3_DCTL_RUN_STOP;
2205
2206                 if (dwc->has_hibernation && !suspend)
2207                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2208
2209                 dwc->pullups_connected = false;
2210         }
2211
2212         dwc3_gadget_dctl_write_safe(dwc, reg);
2213
2214         do {
2215                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2216                 reg &= DWC3_DSTS_DEVCTRLHLT;
2217         } while (--timeout && !(!is_on ^ !reg));
2218
2219         if (!timeout)
2220                 return -ETIMEDOUT;
2221
2222         return 0;
2223 }
2224
2225 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2226 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2227 static int __dwc3_gadget_start(struct dwc3 *dwc);
2228
2229 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2230 {
2231         struct dwc3             *dwc = gadget_to_dwc(g);
2232         unsigned long           flags;
2233         int                     ret;
2234
2235         is_on = !!is_on;
2236
2237         /*
2238          * Per databook, when we want to stop the gadget, if a control transfer
2239          * is still in process, complete it and get the core into setup phase.
2240          */
2241         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2242                 reinit_completion(&dwc->ep0_in_setup);
2243
2244                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2245                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2246                 if (ret == 0)
2247                         dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2248         }
2249
2250         /*
2251          * Avoid issuing a runtime resume if the device is already in the
2252          * suspended state during gadget disconnect.  DWC3 gadget was already
2253          * halted/stopped during runtime suspend.
2254          */
2255         if (!is_on) {
2256                 pm_runtime_barrier(dwc->dev);
2257                 if (pm_runtime_suspended(dwc->dev))
2258                         return 0;
2259         }
2260
2261         /*
2262          * Check the return value for successful resume, or error.  For a
2263          * successful resume, the DWC3 runtime PM resume routine will handle
2264          * the run stop sequence, so avoid duplicate operations here.
2265          */
2266         ret = pm_runtime_get_sync(dwc->dev);
2267         if (!ret || ret < 0) {
2268                 pm_runtime_put(dwc->dev);
2269                 return 0;
2270         }
2271
2272         /*
2273          * Synchronize and disable any further event handling while controller
2274          * is being enabled/disabled.
2275          */
2276         disable_irq(dwc->irq_gadget);
2277
2278         spin_lock_irqsave(&dwc->lock, flags);
2279
2280         if (!is_on) {
2281                 u32 count;
2282
2283                 dwc->connected = false;
2284                 /*
2285                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2286                  * Section 4.1.8 Table 4-7, it states that for a device-initiated
2287                  * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2288                  * command for any active transfers" before clearing the RunStop
2289                  * bit.
2290                  */
2291                 dwc3_stop_active_transfers(dwc);
2292                 __dwc3_gadget_stop(dwc);
2293
2294                 /*
2295                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2296                  * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2297                  * "software needs to acknowledge the events that are generated
2298                  * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2299                  * to be set to '1'."
2300                  */
2301                 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2302                 count &= DWC3_GEVNTCOUNT_MASK;
2303                 if (count > 0) {
2304                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2305                         dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2306                                                 dwc->ev_buf->length;
2307                 }
2308         } else {
2309                 __dwc3_gadget_start(dwc);
2310         }
2311
2312         ret = dwc3_gadget_run_stop(dwc, is_on, false);
2313         spin_unlock_irqrestore(&dwc->lock, flags);
2314         enable_irq(dwc->irq_gadget);
2315
2316         pm_runtime_put(dwc->dev);
2317
2318         return ret;
2319 }
2320
2321 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2322 {
2323         u32                     reg;
2324
2325         /* Enable all but Start and End of Frame IRQs */
2326         reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2327                         DWC3_DEVTEN_CMDCMPLTEN |
2328                         DWC3_DEVTEN_ERRTICERREN |
2329                         DWC3_DEVTEN_WKUPEVTEN |
2330                         DWC3_DEVTEN_CONNECTDONEEN |
2331                         DWC3_DEVTEN_USBRSTEN |
2332                         DWC3_DEVTEN_DISCONNEVTEN);
2333
2334         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2335                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2336
2337         /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2338         if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2339                 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2340
2341         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2342 }
2343
2344 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2345 {
2346         /* mask all interrupts */
2347         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2348 }
2349
2350 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2351 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2352
2353 /**
2354  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2355  * @dwc: pointer to our context structure
2356  *
2357  * The following looks like complex but it's actually very simple. In order to
2358  * calculate the number of packets we can burst at once on OUT transfers, we're
2359  * gonna use RxFIFO size.
2360  *
2361  * To calculate RxFIFO size we need two numbers:
2362  * MDWIDTH = size, in bits, of the internal memory bus
2363  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2364  *
2365  * Given these two numbers, the formula is simple:
2366  *
2367  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2368  *
2369  * 24 bytes is for 3x SETUP packets
2370  * 16 bytes is a clock domain crossing tolerance
2371  *
2372  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2373  */
2374 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2375 {
2376         u32 ram2_depth;
2377         u32 mdwidth;
2378         u32 nump;
2379         u32 reg;
2380
2381         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2382         mdwidth = dwc3_mdwidth(dwc);
2383
2384         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2385         nump = min_t(u32, nump, 16);
2386
2387         /* update NumP */
2388         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2389         reg &= ~DWC3_DCFG_NUMP_MASK;
2390         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2391         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2392 }
2393
2394 static int __dwc3_gadget_start(struct dwc3 *dwc)
2395 {
2396         struct dwc3_ep          *dep;
2397         int                     ret = 0;
2398         u32                     reg;
2399
2400         /*
2401          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2402          * the core supports IMOD, disable it.
2403          */
2404         if (dwc->imod_interval) {
2405                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2406                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2407         } else if (dwc3_has_imod(dwc)) {
2408                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2409         }
2410
2411         /*
2412          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2413          * field instead of letting dwc3 itself calculate that automatically.
2414          *
2415          * This way, we maximize the chances that we'll be able to get several
2416          * bursts of data without going through any sort of endpoint throttling.
2417          */
2418         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2419         if (DWC3_IP_IS(DWC3))
2420                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2421         else
2422                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2423
2424         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2425
2426         dwc3_gadget_setup_nump(dwc);
2427
2428         /*
2429          * Currently the controller handles single stream only. So, Ignore
2430          * Packet Pending bit for stream selection and don't search for another
2431          * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2432          * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2433          * the stream performance.
2434          */
2435         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2436         reg |= DWC3_DCFG_IGNSTRMPP;
2437         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2438
2439         /* Start with SuperSpeed Default */
2440         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2441
2442         dep = dwc->eps[0];
2443         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2444         if (ret) {
2445                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2446                 goto err0;
2447         }
2448
2449         dep = dwc->eps[1];
2450         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2451         if (ret) {
2452                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2453                 goto err1;
2454         }
2455
2456         /* begin to receive SETUP packets */
2457         dwc->ep0state = EP0_SETUP_PHASE;
2458         dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2459         dwc->delayed_status = false;
2460         dwc3_ep0_out_start(dwc);
2461
2462         dwc3_gadget_enable_irq(dwc);
2463
2464         return 0;
2465
2466 err1:
2467         __dwc3_gadget_ep_disable(dwc->eps[0]);
2468
2469 err0:
2470         return ret;
2471 }
2472
2473 static int dwc3_gadget_start(struct usb_gadget *g,
2474                 struct usb_gadget_driver *driver)
2475 {
2476         struct dwc3             *dwc = gadget_to_dwc(g);
2477         unsigned long           flags;
2478         int                     ret;
2479         int                     irq;
2480
2481         irq = dwc->irq_gadget;
2482         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2483                         IRQF_SHARED, "dwc3", dwc->ev_buf);
2484         if (ret) {
2485                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2486                                 irq, ret);
2487                 return ret;
2488         }
2489
2490         spin_lock_irqsave(&dwc->lock, flags);
2491         dwc->gadget_driver      = driver;
2492         spin_unlock_irqrestore(&dwc->lock, flags);
2493
2494         return 0;
2495 }
2496
2497 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2498 {
2499         dwc3_gadget_disable_irq(dwc);
2500         __dwc3_gadget_ep_disable(dwc->eps[0]);
2501         __dwc3_gadget_ep_disable(dwc->eps[1]);
2502 }
2503
2504 static int dwc3_gadget_stop(struct usb_gadget *g)
2505 {
2506         struct dwc3             *dwc = gadget_to_dwc(g);
2507         unsigned long           flags;
2508
2509         spin_lock_irqsave(&dwc->lock, flags);
2510         dwc->gadget_driver      = NULL;
2511         spin_unlock_irqrestore(&dwc->lock, flags);
2512
2513         free_irq(dwc->irq_gadget, dwc->ev_buf);
2514
2515         return 0;
2516 }
2517
2518 static void dwc3_gadget_config_params(struct usb_gadget *g,
2519                                       struct usb_dcd_config_params *params)
2520 {
2521         struct dwc3             *dwc = gadget_to_dwc(g);
2522
2523         params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2524         params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2525
2526         /* Recommended BESL */
2527         if (!dwc->dis_enblslpm_quirk) {
2528                 /*
2529                  * If the recommended BESL baseline is 0 or if the BESL deep is
2530                  * less than 2, Microsoft's Windows 10 host usb stack will issue
2531                  * a usb reset immediately after it receives the extended BOS
2532                  * descriptor and the enumeration will fail. To maintain
2533                  * compatibility with the Windows' usb stack, let's set the
2534                  * recommended BESL baseline to 1 and clamp the BESL deep to be
2535                  * within 2 to 15.
2536                  */
2537                 params->besl_baseline = 1;
2538                 if (dwc->is_utmi_l1_suspend)
2539                         params->besl_deep =
2540                                 clamp_t(u8, dwc->hird_threshold, 2, 15);
2541         }
2542
2543         /* U1 Device exit Latency */
2544         if (dwc->dis_u1_entry_quirk)
2545                 params->bU1devExitLat = 0;
2546         else
2547                 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2548
2549         /* U2 Device exit Latency */
2550         if (dwc->dis_u2_entry_quirk)
2551                 params->bU2DevExitLat = 0;
2552         else
2553                 params->bU2DevExitLat =
2554                                 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2555 }
2556
2557 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2558                                   enum usb_device_speed speed)
2559 {
2560         struct dwc3             *dwc = gadget_to_dwc(g);
2561         unsigned long           flags;
2562
2563         spin_lock_irqsave(&dwc->lock, flags);
2564         dwc->gadget_max_speed = speed;
2565         spin_unlock_irqrestore(&dwc->lock, flags);
2566 }
2567
2568 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2569                                      enum usb_ssp_rate rate)
2570 {
2571         struct dwc3             *dwc = gadget_to_dwc(g);
2572         unsigned long           flags;
2573
2574         spin_lock_irqsave(&dwc->lock, flags);
2575         dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2576         dwc->gadget_ssp_rate = rate;
2577         spin_unlock_irqrestore(&dwc->lock, flags);
2578 }
2579
2580 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2581 {
2582         struct dwc3             *dwc = gadget_to_dwc(g);
2583         union power_supply_propval      val = {0};
2584         int                             ret;
2585
2586         if (dwc->usb2_phy)
2587                 return usb_phy_set_power(dwc->usb2_phy, mA);
2588
2589         if (!dwc->usb_psy)
2590                 return -EOPNOTSUPP;
2591
2592         val.intval = 1000 * mA;
2593         ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2594
2595         return ret;
2596 }
2597
2598 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2599 {
2600         struct dwc3             *dwc = gadget_to_dwc(g);
2601         unsigned long           flags;
2602
2603         spin_lock_irqsave(&dwc->lock, flags);
2604         dwc->async_callbacks = enable;
2605         spin_unlock_irqrestore(&dwc->lock, flags);
2606 }
2607
2608 static const struct usb_gadget_ops dwc3_gadget_ops = {
2609         .get_frame              = dwc3_gadget_get_frame,
2610         .wakeup                 = dwc3_gadget_wakeup,
2611         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2612         .pullup                 = dwc3_gadget_pullup,
2613         .udc_start              = dwc3_gadget_start,
2614         .udc_stop               = dwc3_gadget_stop,
2615         .udc_set_speed          = dwc3_gadget_set_speed,
2616         .udc_set_ssp_rate       = dwc3_gadget_set_ssp_rate,
2617         .get_config_params      = dwc3_gadget_config_params,
2618         .vbus_draw              = dwc3_gadget_vbus_draw,
2619         .udc_async_callbacks    = dwc3_gadget_async_callbacks,
2620 };
2621
2622 /* -------------------------------------------------------------------------- */
2623
2624 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2625 {
2626         struct dwc3 *dwc = dep->dwc;
2627
2628         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2629         dep->endpoint.maxburst = 1;
2630         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2631         if (!dep->direction)
2632                 dwc->gadget->ep0 = &dep->endpoint;
2633
2634         dep->endpoint.caps.type_control = true;
2635
2636         return 0;
2637 }
2638
2639 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2640 {
2641         struct dwc3 *dwc = dep->dwc;
2642         u32 mdwidth;
2643         int size;
2644
2645         mdwidth = dwc3_mdwidth(dwc);
2646
2647         /* MDWIDTH is represented in bits, we need it in bytes */
2648         mdwidth /= 8;
2649
2650         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2651         if (DWC3_IP_IS(DWC3))
2652                 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2653         else
2654                 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2655
2656         /* FIFO Depth is in MDWDITH bytes. Multiply */
2657         size *= mdwidth;
2658
2659         /*
2660          * To meet performance requirement, a minimum TxFIFO size of 3x
2661          * MaxPacketSize is recommended for endpoints that support burst and a
2662          * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2663          * support burst. Use those numbers and we can calculate the max packet
2664          * limit as below.
2665          */
2666         if (dwc->maximum_speed >= USB_SPEED_SUPER)
2667                 size /= 3;
2668         else
2669                 size /= 2;
2670
2671         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2672
2673         dep->endpoint.max_streams = 16;
2674         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2675         list_add_tail(&dep->endpoint.ep_list,
2676                         &dwc->gadget->ep_list);
2677         dep->endpoint.caps.type_iso = true;
2678         dep->endpoint.caps.type_bulk = true;
2679         dep->endpoint.caps.type_int = true;
2680
2681         return dwc3_alloc_trb_pool(dep);
2682 }
2683
2684 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2685 {
2686         struct dwc3 *dwc = dep->dwc;
2687         u32 mdwidth;
2688         int size;
2689
2690         mdwidth = dwc3_mdwidth(dwc);
2691
2692         /* MDWIDTH is represented in bits, convert to bytes */
2693         mdwidth /= 8;
2694
2695         /* All OUT endpoints share a single RxFIFO space */
2696         size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2697         if (DWC3_IP_IS(DWC3))
2698                 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2699         else
2700                 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2701
2702         /* FIFO depth is in MDWDITH bytes */
2703         size *= mdwidth;
2704
2705         /*
2706          * To meet performance requirement, a minimum recommended RxFIFO size
2707          * is defined as follow:
2708          * RxFIFO size >= (3 x MaxPacketSize) +
2709          * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2710          *
2711          * Then calculate the max packet limit as below.
2712          */
2713         size -= (3 * 8) + 16;
2714         if (size < 0)
2715                 size = 0;
2716         else
2717                 size /= 3;
2718
2719         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2720         dep->endpoint.max_streams = 16;
2721         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2722         list_add_tail(&dep->endpoint.ep_list,
2723                         &dwc->gadget->ep_list);
2724         dep->endpoint.caps.type_iso = true;
2725         dep->endpoint.caps.type_bulk = true;
2726         dep->endpoint.caps.type_int = true;
2727
2728         return dwc3_alloc_trb_pool(dep);
2729 }
2730
2731 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2732 {
2733         struct dwc3_ep                  *dep;
2734         bool                            direction = epnum & 1;
2735         int                             ret;
2736         u8                              num = epnum >> 1;
2737
2738         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2739         if (!dep)
2740                 return -ENOMEM;
2741
2742         dep->dwc = dwc;
2743         dep->number = epnum;
2744         dep->direction = direction;
2745         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2746         dwc->eps[epnum] = dep;
2747         dep->combo_num = 0;
2748         dep->start_cmd_status = 0;
2749
2750         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2751                         direction ? "in" : "out");
2752
2753         dep->endpoint.name = dep->name;
2754
2755         if (!(dep->number > 1)) {
2756                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2757                 dep->endpoint.comp_desc = NULL;
2758         }
2759
2760         if (num == 0)
2761                 ret = dwc3_gadget_init_control_endpoint(dep);
2762         else if (direction)
2763                 ret = dwc3_gadget_init_in_endpoint(dep);
2764         else
2765                 ret = dwc3_gadget_init_out_endpoint(dep);
2766
2767         if (ret)
2768                 return ret;
2769
2770         dep->endpoint.caps.dir_in = direction;
2771         dep->endpoint.caps.dir_out = !direction;
2772
2773         INIT_LIST_HEAD(&dep->pending_list);
2774         INIT_LIST_HEAD(&dep->started_list);
2775         INIT_LIST_HEAD(&dep->cancelled_list);
2776
2777         dwc3_debugfs_create_endpoint_dir(dep);
2778
2779         return 0;
2780 }
2781
2782 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2783 {
2784         u8                              epnum;
2785
2786         INIT_LIST_HEAD(&dwc->gadget->ep_list);
2787
2788         for (epnum = 0; epnum < total; epnum++) {
2789                 int                     ret;
2790
2791                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2792                 if (ret)
2793                         return ret;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2800 {
2801         struct dwc3_ep                  *dep;
2802         u8                              epnum;
2803
2804         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2805                 dep = dwc->eps[epnum];
2806                 if (!dep)
2807                         continue;
2808                 /*
2809                  * Physical endpoints 0 and 1 are special; they form the
2810                  * bi-directional USB endpoint 0.
2811                  *
2812                  * For those two physical endpoints, we don't allocate a TRB
2813                  * pool nor do we add them the endpoints list. Due to that, we
2814                  * shouldn't do these two operations otherwise we would end up
2815                  * with all sorts of bugs when removing dwc3.ko.
2816                  */
2817                 if (epnum != 0 && epnum != 1) {
2818                         dwc3_free_trb_pool(dep);
2819                         list_del(&dep->endpoint.ep_list);
2820                 }
2821
2822                 debugfs_remove_recursive(debugfs_lookup(dep->name,
2823                                 debugfs_lookup(dev_name(dep->dwc->dev),
2824                                                usb_debug_root)));
2825                 kfree(dep);
2826         }
2827 }
2828
2829 /* -------------------------------------------------------------------------- */
2830
2831 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2832                 struct dwc3_request *req, struct dwc3_trb *trb,
2833                 const struct dwc3_event_depevt *event, int status, int chain)
2834 {
2835         unsigned int            count;
2836
2837         dwc3_ep_inc_deq(dep);
2838
2839         trace_dwc3_complete_trb(dep, trb);
2840         req->num_trbs--;
2841
2842         /*
2843          * If we're in the middle of series of chained TRBs and we
2844          * receive a short transfer along the way, DWC3 will skip
2845          * through all TRBs including the last TRB in the chain (the
2846          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2847          * bit and SW has to do it manually.
2848          *
2849          * We're going to do that here to avoid problems of HW trying
2850          * to use bogus TRBs for transfers.
2851          */
2852         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2853                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2854
2855         /*
2856          * For isochronous transfers, the first TRB in a service interval must
2857          * have the Isoc-First type. Track and report its interval frame number.
2858          */
2859         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2860             (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2861                 unsigned int frame_number;
2862
2863                 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2864                 frame_number &= ~(dep->interval - 1);
2865                 req->request.frame_number = frame_number;
2866         }
2867
2868         /*
2869          * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2870          * this TRB points to the bounce buffer address, it's a MPS alignment
2871          * TRB. Don't add it to req->remaining calculation.
2872          */
2873         if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2874             trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2875                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2876                 return 1;
2877         }
2878
2879         count = trb->size & DWC3_TRB_SIZE_MASK;
2880         req->remaining += count;
2881
2882         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2883                 return 1;
2884
2885         if (event->status & DEPEVT_STATUS_SHORT && !chain)
2886                 return 1;
2887
2888         if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2889             (trb->ctrl & DWC3_TRB_CTRL_LST))
2890                 return 1;
2891
2892         return 0;
2893 }
2894
2895 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2896                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2897                 int status)
2898 {
2899         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2900         struct scatterlist *sg = req->sg;
2901         struct scatterlist *s;
2902         unsigned int num_queued = req->num_queued_sgs;
2903         unsigned int i;
2904         int ret = 0;
2905
2906         for_each_sg(sg, s, num_queued, i) {
2907                 trb = &dep->trb_pool[dep->trb_dequeue];
2908
2909                 req->sg = sg_next(s);
2910                 req->num_queued_sgs--;
2911
2912                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2913                                 trb, event, status, true);
2914                 if (ret)
2915                         break;
2916         }
2917
2918         return ret;
2919 }
2920
2921 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2922                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2923                 int status)
2924 {
2925         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2926
2927         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2928                         event, status, false);
2929 }
2930
2931 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2932 {
2933         return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
2934 }
2935
2936 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2937                 const struct dwc3_event_depevt *event,
2938                 struct dwc3_request *req, int status)
2939 {
2940         int ret;
2941
2942         if (req->request.num_mapped_sgs)
2943                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2944                                 status);
2945         else
2946                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2947                                 status);
2948
2949         req->request.actual = req->request.length - req->remaining;
2950
2951         if (!dwc3_gadget_ep_request_completed(req))
2952                 goto out;
2953
2954         if (req->needs_extra_trb) {
2955                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2956                                 status);
2957                 req->needs_extra_trb = false;
2958         }
2959
2960         dwc3_gadget_giveback(dep, req, status);
2961
2962 out:
2963         return ret;
2964 }
2965
2966 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2967                 const struct dwc3_event_depevt *event, int status)
2968 {
2969         struct dwc3_request     *req;
2970         struct dwc3_request     *tmp;
2971
2972         list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2973                 int ret;
2974
2975                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2976                                 req, status);
2977                 if (ret)
2978                         break;
2979         }
2980 }
2981
2982 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2983 {
2984         struct dwc3_request     *req;
2985         struct dwc3             *dwc = dep->dwc;
2986
2987         if (!dep->endpoint.desc || !dwc->pullups_connected ||
2988             !dwc->connected)
2989                 return false;
2990
2991         if (!list_empty(&dep->pending_list))
2992                 return true;
2993
2994         /*
2995          * We only need to check the first entry of the started list. We can
2996          * assume the completed requests are removed from the started list.
2997          */
2998         req = next_request(&dep->started_list);
2999         if (!req)
3000                 return false;
3001
3002         return !dwc3_gadget_ep_request_completed(req);
3003 }
3004
3005 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3006                 const struct dwc3_event_depevt *event)
3007 {
3008         dep->frame_number = event->parameters;
3009 }
3010
3011 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3012                 const struct dwc3_event_depevt *event, int status)
3013 {
3014         struct dwc3             *dwc = dep->dwc;
3015         bool                    no_started_trb = true;
3016
3017         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3018
3019         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3020                 goto out;
3021
3022         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3023                 list_empty(&dep->started_list) &&
3024                 (list_empty(&dep->pending_list) || status == -EXDEV))
3025                 dwc3_stop_active_transfer(dep, true, true);
3026         else if (dwc3_gadget_ep_should_continue(dep))
3027                 if (__dwc3_gadget_kick_transfer(dep) == 0)
3028                         no_started_trb = false;
3029
3030 out:
3031         /*
3032          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3033          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3034          */
3035         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3036                 u32             reg;
3037                 int             i;
3038
3039                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3040                         dep = dwc->eps[i];
3041
3042                         if (!(dep->flags & DWC3_EP_ENABLED))
3043                                 continue;
3044
3045                         if (!list_empty(&dep->started_list))
3046                                 return no_started_trb;
3047                 }
3048
3049                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3050                 reg |= dwc->u1u2;
3051                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3052
3053                 dwc->u1u2 = 0;
3054         }
3055
3056         return no_started_trb;
3057 }
3058
3059 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3060                 const struct dwc3_event_depevt *event)
3061 {
3062         int status = 0;
3063
3064         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3065                 dwc3_gadget_endpoint_frame_from_event(dep, event);
3066
3067         if (event->status & DEPEVT_STATUS_BUSERR)
3068                 status = -ECONNRESET;
3069
3070         if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3071                 status = -EXDEV;
3072
3073         dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3074 }
3075
3076 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3077                 const struct dwc3_event_depevt *event)
3078 {
3079         int status = 0;
3080
3081         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3082
3083         if (event->status & DEPEVT_STATUS_BUSERR)
3084                 status = -ECONNRESET;
3085
3086         if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3087                 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3088 }
3089
3090 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3091                 const struct dwc3_event_depevt *event)
3092 {
3093         dwc3_gadget_endpoint_frame_from_event(dep, event);
3094
3095         /*
3096          * The XferNotReady event is generated only once before the endpoint
3097          * starts. It will be generated again when END_TRANSFER command is
3098          * issued. For some controller versions, the XferNotReady event may be
3099          * generated while the END_TRANSFER command is still in process. Ignore
3100          * it and wait for the next XferNotReady event after the command is
3101          * completed.
3102          */
3103         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3104                 return;
3105
3106         (void) __dwc3_gadget_start_isoc(dep);
3107 }
3108
3109 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3110                 const struct dwc3_event_depevt *event)
3111 {
3112         u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3113
3114         if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3115                 return;
3116
3117         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3118         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3119         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3120
3121         if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3122                 struct dwc3 *dwc = dep->dwc;
3123
3124                 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3125                 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3126                         struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3127
3128                         dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3129                         if (dwc->delayed_status)
3130                                 __dwc3_gadget_ep0_set_halt(ep0, 1);
3131                         return;
3132                 }
3133
3134                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3135                 if (dwc->delayed_status)
3136                         dwc3_ep0_send_delayed_status(dwc);
3137         }
3138
3139         if ((dep->flags & DWC3_EP_DELAY_START) &&
3140             !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3141                 __dwc3_gadget_kick_transfer(dep);
3142
3143         dep->flags &= ~DWC3_EP_DELAY_START;
3144 }
3145
3146 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3147                 const struct dwc3_event_depevt *event)
3148 {
3149         struct dwc3 *dwc = dep->dwc;
3150
3151         if (event->status == DEPEVT_STREAMEVT_FOUND) {
3152                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3153                 goto out;
3154         }
3155
3156         /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3157         switch (event->parameters) {
3158         case DEPEVT_STREAM_PRIME:
3159                 /*
3160                  * If the host can properly transition the endpoint state from
3161                  * idle to prime after a NoStream rejection, there's no need to
3162                  * force restarting the endpoint to reinitiate the stream. To
3163                  * simplify the check, assume the host follows the USB spec if
3164                  * it primed the endpoint more than once.
3165                  */
3166                 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3167                         if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3168                                 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3169                         else
3170                                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3171                 }
3172
3173                 break;
3174         case DEPEVT_STREAM_NOSTREAM:
3175                 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3176                     !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3177                     !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3178                         break;
3179
3180                 /*
3181                  * If the host rejects a stream due to no active stream, by the
3182                  * USB and xHCI spec, the endpoint will be put back to idle
3183                  * state. When the host is ready (buffer added/updated), it will
3184                  * prime the endpoint to inform the usb device controller. This
3185                  * triggers the device controller to issue ERDY to restart the
3186                  * stream. However, some hosts don't follow this and keep the
3187                  * endpoint in the idle state. No prime will come despite host
3188                  * streams are updated, and the device controller will not be
3189                  * triggered to generate ERDY to move the next stream data. To
3190                  * workaround this and maintain compatibility with various
3191                  * hosts, force to reinitate the stream until the host is ready
3192                  * instead of waiting for the host to prime the endpoint.
3193                  */
3194                 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3195                         unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3196
3197                         dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3198                 } else {
3199                         dep->flags |= DWC3_EP_DELAY_START;
3200                         dwc3_stop_active_transfer(dep, true, true);
3201                         return;
3202                 }
3203                 break;
3204         }
3205
3206 out:
3207         dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3208 }
3209
3210 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3211                 const struct dwc3_event_depevt *event)
3212 {
3213         struct dwc3_ep          *dep;
3214         u8                      epnum = event->endpoint_number;
3215
3216         dep = dwc->eps[epnum];
3217
3218         if (!(dep->flags & DWC3_EP_ENABLED)) {
3219                 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3220                         return;
3221
3222                 /* Handle only EPCMDCMPLT when EP disabled */
3223                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3224                         return;
3225         }
3226
3227         if (epnum == 0 || epnum == 1) {
3228                 dwc3_ep0_interrupt(dwc, event);
3229                 return;
3230         }
3231
3232         switch (event->endpoint_event) {
3233         case DWC3_DEPEVT_XFERINPROGRESS:
3234                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3235                 break;
3236         case DWC3_DEPEVT_XFERNOTREADY:
3237                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3238                 break;
3239         case DWC3_DEPEVT_EPCMDCMPLT:
3240                 dwc3_gadget_endpoint_command_complete(dep, event);
3241                 break;
3242         case DWC3_DEPEVT_XFERCOMPLETE:
3243                 dwc3_gadget_endpoint_transfer_complete(dep, event);
3244                 break;
3245         case DWC3_DEPEVT_STREAMEVT:
3246                 dwc3_gadget_endpoint_stream_event(dep, event);
3247                 break;
3248         case DWC3_DEPEVT_RXTXFIFOEVT:
3249                 break;
3250         }
3251 }
3252
3253 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3254 {
3255         if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3256                 spin_unlock(&dwc->lock);
3257                 dwc->gadget_driver->disconnect(dwc->gadget);
3258                 spin_lock(&dwc->lock);
3259         }
3260 }
3261
3262 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3263 {
3264         if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3265                 spin_unlock(&dwc->lock);
3266                 dwc->gadget_driver->suspend(dwc->gadget);
3267                 spin_lock(&dwc->lock);
3268         }
3269 }
3270
3271 static void dwc3_resume_gadget(struct dwc3 *dwc)
3272 {
3273         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3274                 spin_unlock(&dwc->lock);
3275                 dwc->gadget_driver->resume(dwc->gadget);
3276                 spin_lock(&dwc->lock);
3277         }
3278 }
3279
3280 static void dwc3_reset_gadget(struct dwc3 *dwc)
3281 {
3282         if (!dwc->gadget_driver)
3283                 return;
3284
3285         if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3286                 spin_unlock(&dwc->lock);
3287                 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3288                 spin_lock(&dwc->lock);
3289         }
3290 }
3291
3292 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3293         bool interrupt)
3294 {
3295         struct dwc3_gadget_ep_cmd_params params;
3296         u32 cmd;
3297         int ret;
3298
3299         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3300             (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3301                 return;
3302
3303         /*
3304          * NOTICE: We are violating what the Databook says about the
3305          * EndTransfer command. Ideally we would _always_ wait for the
3306          * EndTransfer Command Completion IRQ, but that's causing too
3307          * much trouble synchronizing between us and gadget driver.
3308          *
3309          * We have discussed this with the IP Provider and it was
3310          * suggested to giveback all requests here.
3311          *
3312          * Note also that a similar handling was tested by Synopsys
3313          * (thanks a lot Paul) and nothing bad has come out of it.
3314          * In short, what we're doing is issuing EndTransfer with
3315          * CMDIOC bit set and delay kicking transfer until the
3316          * EndTransfer command had completed.
3317          *
3318          * As of IP version 3.10a of the DWC_usb3 IP, the controller
3319          * supports a mode to work around the above limitation. The
3320          * software can poll the CMDACT bit in the DEPCMD register
3321          * after issuing a EndTransfer command. This mode is enabled
3322          * by writing GUCTL2[14]. This polling is already done in the
3323          * dwc3_send_gadget_ep_cmd() function so if the mode is
3324          * enabled, the EndTransfer command will have completed upon
3325          * returning from this function.
3326          *
3327          * This mode is NOT available on the DWC_usb31 IP.
3328          */
3329
3330         cmd = DWC3_DEPCMD_ENDTRANSFER;
3331         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3332         cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3333         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3334         memset(&params, 0, sizeof(params));
3335         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3336         WARN_ON_ONCE(ret);
3337         dep->resource_index = 0;
3338
3339         /*
3340          * The END_TRANSFER command will cause the controller to generate a
3341          * NoStream Event, and it's not due to the host DP NoStream rejection.
3342          * Ignore the next NoStream event.
3343          */
3344         if (dep->stream_capable)
3345                 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3346
3347         if (!interrupt)
3348                 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3349         else
3350                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3351 }
3352
3353 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3354 {
3355         u32 epnum;
3356
3357         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3358                 struct dwc3_ep *dep;
3359                 int ret;
3360
3361                 dep = dwc->eps[epnum];
3362                 if (!dep)
3363                         continue;
3364
3365                 if (!(dep->flags & DWC3_EP_STALL))
3366                         continue;
3367
3368                 dep->flags &= ~DWC3_EP_STALL;
3369
3370                 ret = dwc3_send_clear_stall_ep_cmd(dep);
3371                 WARN_ON_ONCE(ret);
3372         }
3373 }
3374
3375 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3376 {
3377         int                     reg;
3378
3379         dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3380
3381         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3382         reg &= ~DWC3_DCTL_INITU1ENA;
3383         reg &= ~DWC3_DCTL_INITU2ENA;
3384         dwc3_gadget_dctl_write_safe(dwc, reg);
3385
3386         dwc3_disconnect_gadget(dwc);
3387
3388         dwc->gadget->speed = USB_SPEED_UNKNOWN;
3389         dwc->setup_packet_pending = false;
3390         usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3391
3392         dwc->connected = false;
3393 }
3394
3395 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3396 {
3397         u32                     reg;
3398
3399         /*
3400          * Ideally, dwc3_reset_gadget() would trigger the function
3401          * drivers to stop any active transfers through ep disable.
3402          * However, for functions which defer ep disable, such as mass
3403          * storage, we will need to rely on the call to stop active
3404          * transfers here, and avoid allowing of request queuing.
3405          */
3406         dwc->connected = false;
3407
3408         /*
3409          * WORKAROUND: DWC3 revisions <1.88a have an issue which
3410          * would cause a missing Disconnect Event if there's a
3411          * pending Setup Packet in the FIFO.
3412          *
3413          * There's no suggested workaround on the official Bug
3414          * report, which states that "unless the driver/application
3415          * is doing any special handling of a disconnect event,
3416          * there is no functional issue".
3417          *
3418          * Unfortunately, it turns out that we _do_ some special
3419          * handling of a disconnect event, namely complete all
3420          * pending transfers, notify gadget driver of the
3421          * disconnection, and so on.
3422          *
3423          * Our suggested workaround is to follow the Disconnect
3424          * Event steps here, instead, based on a setup_packet_pending
3425          * flag. Such flag gets set whenever we have a SETUP_PENDING
3426          * status for EP0 TRBs and gets cleared on XferComplete for the
3427          * same endpoint.
3428          *
3429          * Refers to:
3430          *
3431          * STAR#9000466709: RTL: Device : Disconnect event not
3432          * generated if setup packet pending in FIFO
3433          */
3434         if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3435                 if (dwc->setup_packet_pending)
3436                         dwc3_gadget_disconnect_interrupt(dwc);
3437         }
3438
3439         dwc3_reset_gadget(dwc);
3440         /*
3441          * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3442          * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3443          * needs to ensure that it sends "a DEPENDXFER command for any active
3444          * transfers."
3445          */
3446         dwc3_stop_active_transfers(dwc);
3447         dwc->connected = true;
3448
3449         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3450         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3451         dwc3_gadget_dctl_write_safe(dwc, reg);
3452         dwc->test_mode = false;
3453         dwc3_clear_stall_all_ep(dwc);
3454
3455         /* Reset device address to zero */
3456         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3457         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3458         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3459 }
3460
3461 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3462 {
3463         struct dwc3_ep          *dep;
3464         int                     ret;
3465         u32                     reg;
3466         u8                      lanes = 1;
3467         u8                      speed;
3468
3469         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3470         speed = reg & DWC3_DSTS_CONNECTSPD;
3471         dwc->speed = speed;
3472
3473         if (DWC3_IP_IS(DWC32))
3474                 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3475
3476         dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3477
3478         /*
3479          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3480          * each time on Connect Done.
3481          *
3482          * Currently we always use the reset value. If any platform
3483          * wants to set this to a different value, we need to add a
3484          * setting and update GCTL.RAMCLKSEL here.
3485          */
3486
3487         switch (speed) {
3488         case DWC3_DSTS_SUPERSPEED_PLUS:
3489                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3490                 dwc->gadget->ep0->maxpacket = 512;
3491                 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3492
3493                 if (lanes > 1)
3494                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3495                 else
3496                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3497                 break;
3498         case DWC3_DSTS_SUPERSPEED:
3499                 /*
3500                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
3501                  * would cause a missing USB3 Reset event.
3502                  *
3503                  * In such situations, we should force a USB3 Reset
3504                  * event by calling our dwc3_gadget_reset_interrupt()
3505                  * routine.
3506                  *
3507                  * Refers to:
3508                  *
3509                  * STAR#9000483510: RTL: SS : USB3 reset event may
3510                  * not be generated always when the link enters poll
3511                  */
3512                 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3513                         dwc3_gadget_reset_interrupt(dwc);
3514
3515                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3516                 dwc->gadget->ep0->maxpacket = 512;
3517                 dwc->gadget->speed = USB_SPEED_SUPER;
3518
3519                 if (lanes > 1) {
3520                         dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3521                         dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3522                 }
3523                 break;
3524         case DWC3_DSTS_HIGHSPEED:
3525                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3526                 dwc->gadget->ep0->maxpacket = 64;
3527                 dwc->gadget->speed = USB_SPEED_HIGH;
3528                 break;
3529         case DWC3_DSTS_FULLSPEED:
3530                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3531                 dwc->gadget->ep0->maxpacket = 64;
3532                 dwc->gadget->speed = USB_SPEED_FULL;
3533                 break;
3534         }
3535
3536         dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3537
3538         /* Enable USB2 LPM Capability */
3539
3540         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3541             !dwc->usb2_gadget_lpm_disable &&
3542             (speed != DWC3_DSTS_SUPERSPEED) &&
3543             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3544                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3545                 reg |= DWC3_DCFG_LPM_CAP;
3546                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3547
3548                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3549                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3550
3551                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3552                                             (dwc->is_utmi_l1_suspend << 4));
3553
3554                 /*
3555                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3556                  * DCFG.LPMCap is set, core responses with an ACK and the
3557                  * BESL value in the LPM token is less than or equal to LPM
3558                  * NYET threshold.
3559                  */
3560                 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3561                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3562
3563                 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3564                         reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3565
3566                 dwc3_gadget_dctl_write_safe(dwc, reg);
3567         } else {
3568                 if (dwc->usb2_gadget_lpm_disable) {
3569                         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3570                         reg &= ~DWC3_DCFG_LPM_CAP;
3571                         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3572                 }
3573
3574                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3575                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3576                 dwc3_gadget_dctl_write_safe(dwc, reg);
3577         }
3578
3579         dep = dwc->eps[0];
3580         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3581         if (ret) {
3582                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3583                 return;
3584         }
3585
3586         dep = dwc->eps[1];
3587         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3588         if (ret) {
3589                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3590                 return;
3591         }
3592
3593         /*
3594          * Configure PHY via GUSB3PIPECTLn if required.
3595          *
3596          * Update GTXFIFOSIZn
3597          *
3598          * In both cases reset values should be sufficient.
3599          */
3600 }
3601
3602 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3603 {
3604         /*
3605          * TODO take core out of low power mode when that's
3606          * implemented.
3607          */
3608
3609         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3610                 spin_unlock(&dwc->lock);
3611                 dwc->gadget_driver->resume(dwc->gadget);
3612                 spin_lock(&dwc->lock);
3613         }
3614 }
3615
3616 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3617                 unsigned int evtinfo)
3618 {
3619         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
3620         unsigned int            pwropt;
3621
3622         /*
3623          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3624          * Hibernation mode enabled which would show up when device detects
3625          * host-initiated U3 exit.
3626          *
3627          * In that case, device will generate a Link State Change Interrupt
3628          * from U3 to RESUME which is only necessary if Hibernation is
3629          * configured in.
3630          *
3631          * There are no functional changes due to such spurious event and we
3632          * just need to ignore it.
3633          *
3634          * Refers to:
3635          *
3636          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3637          * operational mode
3638          */
3639         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3640         if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3641                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3642                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3643                                 (next == DWC3_LINK_STATE_RESUME)) {
3644                         return;
3645                 }
3646         }
3647
3648         /*
3649          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3650          * on the link partner, the USB session might do multiple entry/exit
3651          * of low power states before a transfer takes place.
3652          *
3653          * Due to this problem, we might experience lower throughput. The
3654          * suggested workaround is to disable DCTL[12:9] bits if we're
3655          * transitioning from U1/U2 to U0 and enable those bits again
3656          * after a transfer completes and there are no pending transfers
3657          * on any of the enabled endpoints.
3658          *
3659          * This is the first half of that workaround.
3660          *
3661          * Refers to:
3662          *
3663          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3664          * core send LGO_Ux entering U0
3665          */
3666         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3667                 if (next == DWC3_LINK_STATE_U0) {
3668                         u32     u1u2;
3669                         u32     reg;
3670
3671                         switch (dwc->link_state) {
3672                         case DWC3_LINK_STATE_U1:
3673                         case DWC3_LINK_STATE_U2:
3674                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3675                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3676                                                 | DWC3_DCTL_ACCEPTU2ENA
3677                                                 | DWC3_DCTL_INITU1ENA
3678                                                 | DWC3_DCTL_ACCEPTU1ENA);
3679
3680                                 if (!dwc->u1u2)
3681                                         dwc->u1u2 = reg & u1u2;
3682
3683                                 reg &= ~u1u2;
3684
3685                                 dwc3_gadget_dctl_write_safe(dwc, reg);
3686                                 break;
3687                         default:
3688                                 /* do nothing */
3689                                 break;
3690                         }
3691                 }
3692         }
3693
3694         switch (next) {
3695         case DWC3_LINK_STATE_U1:
3696                 if (dwc->speed == USB_SPEED_SUPER)
3697                         dwc3_suspend_gadget(dwc);
3698                 break;
3699         case DWC3_LINK_STATE_U2:
3700         case DWC3_LINK_STATE_U3:
3701                 dwc3_suspend_gadget(dwc);
3702                 break;
3703         case DWC3_LINK_STATE_RESUME:
3704                 dwc3_resume_gadget(dwc);
3705                 break;
3706         default:
3707                 /* do nothing */
3708                 break;
3709         }
3710
3711         dwc->link_state = next;
3712 }
3713
3714 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3715                                           unsigned int evtinfo)
3716 {
3717         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3718
3719         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3720                 dwc3_suspend_gadget(dwc);
3721
3722         dwc->link_state = next;
3723 }
3724
3725 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3726                 unsigned int evtinfo)
3727 {
3728         unsigned int is_ss = evtinfo & BIT(4);
3729
3730         /*
3731          * WORKAROUND: DWC3 revison 2.20a with hibernation support
3732          * have a known issue which can cause USB CV TD.9.23 to fail
3733          * randomly.
3734          *
3735          * Because of this issue, core could generate bogus hibernation
3736          * events which SW needs to ignore.
3737          *
3738          * Refers to:
3739          *
3740          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3741          * Device Fallback from SuperSpeed
3742          */
3743         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3744                 return;
3745
3746         /* enter hibernation here */
3747 }
3748
3749 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3750                 const struct dwc3_event_devt *event)
3751 {
3752         switch (event->type) {
3753         case DWC3_DEVICE_EVENT_DISCONNECT:
3754                 dwc3_gadget_disconnect_interrupt(dwc);
3755                 break;
3756         case DWC3_DEVICE_EVENT_RESET:
3757                 dwc3_gadget_reset_interrupt(dwc);
3758                 break;
3759         case DWC3_DEVICE_EVENT_CONNECT_DONE:
3760                 dwc3_gadget_conndone_interrupt(dwc);
3761                 break;
3762         case DWC3_DEVICE_EVENT_WAKEUP:
3763                 dwc3_gadget_wakeup_interrupt(dwc);
3764                 break;
3765         case DWC3_DEVICE_EVENT_HIBER_REQ:
3766                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3767                                         "unexpected hibernation event\n"))
3768                         break;
3769
3770                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3771                 break;
3772         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3773                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3774                 break;
3775         case DWC3_DEVICE_EVENT_SUSPEND:
3776                 /* It changed to be suspend event for version 2.30a and above */
3777                 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3778                         /*
3779                          * Ignore suspend event until the gadget enters into
3780                          * USB_STATE_CONFIGURED state.
3781                          */
3782                         if (dwc->gadget->state >= USB_STATE_CONFIGURED)
3783                                 dwc3_gadget_suspend_interrupt(dwc,
3784                                                 event->event_info);
3785                 }
3786                 break;
3787         case DWC3_DEVICE_EVENT_SOF:
3788         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3789         case DWC3_DEVICE_EVENT_CMD_CMPL:
3790         case DWC3_DEVICE_EVENT_OVERFLOW:
3791                 break;
3792         default:
3793                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3794         }
3795 }
3796
3797 static void dwc3_process_event_entry(struct dwc3 *dwc,
3798                 const union dwc3_event *event)
3799 {
3800         trace_dwc3_event(event->raw, dwc);
3801
3802         if (!event->type.is_devspec)
3803                 dwc3_endpoint_interrupt(dwc, &event->depevt);
3804         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3805                 dwc3_gadget_interrupt(dwc, &event->devt);
3806         else
3807                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3808 }
3809
3810 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3811 {
3812         struct dwc3 *dwc = evt->dwc;
3813         irqreturn_t ret = IRQ_NONE;
3814         int left;
3815         u32 reg;
3816
3817         left = evt->count;
3818
3819         if (!(evt->flags & DWC3_EVENT_PENDING))
3820                 return IRQ_NONE;
3821
3822         while (left > 0) {
3823                 union dwc3_event event;
3824
3825                 event.raw = *(u32 *) (evt->cache + evt->lpos);
3826
3827                 dwc3_process_event_entry(dwc, &event);
3828
3829                 /*
3830                  * FIXME we wrap around correctly to the next entry as
3831                  * almost all entries are 4 bytes in size. There is one
3832                  * entry which has 12 bytes which is a regular entry
3833                  * followed by 8 bytes data. ATM I don't know how
3834                  * things are organized if we get next to the a
3835                  * boundary so I worry about that once we try to handle
3836                  * that.
3837                  */
3838                 evt->lpos = (evt->lpos + 4) % evt->length;
3839                 left -= 4;
3840         }
3841
3842         evt->count = 0;
3843         evt->flags &= ~DWC3_EVENT_PENDING;
3844         ret = IRQ_HANDLED;
3845
3846         /* Unmask interrupt */
3847         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3848         reg &= ~DWC3_GEVNTSIZ_INTMASK;
3849         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3850
3851         if (dwc->imod_interval) {
3852                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3853                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3854         }
3855
3856         return ret;
3857 }
3858
3859 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3860 {
3861         struct dwc3_event_buffer *evt = _evt;
3862         struct dwc3 *dwc = evt->dwc;
3863         unsigned long flags;
3864         irqreturn_t ret = IRQ_NONE;
3865
3866         spin_lock_irqsave(&dwc->lock, flags);
3867         ret = dwc3_process_event_buf(evt);
3868         spin_unlock_irqrestore(&dwc->lock, flags);
3869
3870         return ret;
3871 }
3872
3873 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3874 {
3875         struct dwc3 *dwc = evt->dwc;
3876         u32 amount;
3877         u32 count;
3878         u32 reg;
3879
3880         if (pm_runtime_suspended(dwc->dev)) {
3881                 pm_runtime_get(dwc->dev);
3882                 disable_irq_nosync(dwc->irq_gadget);
3883                 dwc->pending_events = true;
3884                 return IRQ_HANDLED;
3885         }
3886
3887         /*
3888          * With PCIe legacy interrupt, test shows that top-half irq handler can
3889          * be called again after HW interrupt deassertion. Check if bottom-half
3890          * irq event handler completes before caching new event to prevent
3891          * losing events.
3892          */
3893         if (evt->flags & DWC3_EVENT_PENDING)
3894                 return IRQ_HANDLED;
3895
3896         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3897         count &= DWC3_GEVNTCOUNT_MASK;
3898         if (!count)
3899                 return IRQ_NONE;
3900
3901         evt->count = count;
3902         evt->flags |= DWC3_EVENT_PENDING;
3903
3904         /* Mask interrupt */
3905         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3906         reg |= DWC3_GEVNTSIZ_INTMASK;
3907         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3908
3909         amount = min(count, evt->length - evt->lpos);
3910         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3911
3912         if (amount < count)
3913                 memcpy(evt->cache, evt->buf, count - amount);
3914
3915         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3916
3917         return IRQ_WAKE_THREAD;
3918 }
3919
3920 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3921 {
3922         struct dwc3_event_buffer        *evt = _evt;
3923
3924         return dwc3_check_event_buf(evt);
3925 }
3926
3927 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3928 {
3929         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3930         int irq;
3931
3932         irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3933         if (irq > 0)
3934                 goto out;
3935
3936         if (irq == -EPROBE_DEFER)
3937                 goto out;
3938
3939         irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3940         if (irq > 0)
3941                 goto out;
3942
3943         if (irq == -EPROBE_DEFER)
3944                 goto out;
3945
3946         irq = platform_get_irq(dwc3_pdev, 0);
3947         if (irq > 0)
3948                 goto out;
3949
3950         if (!irq)
3951                 irq = -EINVAL;
3952
3953 out:
3954         return irq;
3955 }
3956
3957 static void dwc_gadget_release(struct device *dev)
3958 {
3959         struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3960
3961         kfree(gadget);
3962 }
3963
3964 /**
3965  * dwc3_gadget_init - initializes gadget related registers
3966  * @dwc: pointer to our controller context structure
3967  *
3968  * Returns 0 on success otherwise negative errno.
3969  */
3970 int dwc3_gadget_init(struct dwc3 *dwc)
3971 {
3972         int ret;
3973         int irq;
3974         struct device *dev;
3975
3976         irq = dwc3_gadget_get_irq(dwc);
3977         if (irq < 0) {
3978                 ret = irq;
3979                 goto err0;
3980         }
3981
3982         dwc->irq_gadget = irq;
3983
3984         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3985                                           sizeof(*dwc->ep0_trb) * 2,
3986                                           &dwc->ep0_trb_addr, GFP_KERNEL);
3987         if (!dwc->ep0_trb) {
3988                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3989                 ret = -ENOMEM;
3990                 goto err0;
3991         }
3992
3993         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3994         if (!dwc->setup_buf) {
3995                 ret = -ENOMEM;
3996                 goto err1;
3997         }
3998
3999         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4000                         &dwc->bounce_addr, GFP_KERNEL);
4001         if (!dwc->bounce) {
4002                 ret = -ENOMEM;
4003                 goto err2;
4004         }
4005
4006         init_completion(&dwc->ep0_in_setup);
4007         dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4008         if (!dwc->gadget) {
4009                 ret = -ENOMEM;
4010                 goto err3;
4011         }
4012
4013
4014         usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4015         dev                             = &dwc->gadget->dev;
4016         dev->platform_data              = dwc;
4017         dwc->gadget->ops                = &dwc3_gadget_ops;
4018         dwc->gadget->speed              = USB_SPEED_UNKNOWN;
4019         dwc->gadget->ssp_rate           = USB_SSP_GEN_UNKNOWN;
4020         dwc->gadget->sg_supported       = true;
4021         dwc->gadget->name               = "dwc3-gadget";
4022         dwc->gadget->lpm_capable        = !dwc->usb2_gadget_lpm_disable;
4023
4024         /*
4025          * FIXME We might be setting max_speed to <SUPER, however versions
4026          * <2.20a of dwc3 have an issue with metastability (documented
4027          * elsewhere in this driver) which tells us we can't set max speed to
4028          * anything lower than SUPER.
4029          *
4030          * Because gadget.max_speed is only used by composite.c and function
4031          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4032          * to happen so we avoid sending SuperSpeed Capability descriptor
4033          * together with our BOS descriptor as that could confuse host into
4034          * thinking we can handle super speed.
4035          *
4036          * Note that, in fact, we won't even support GetBOS requests when speed
4037          * is less than super speed because we don't have means, yet, to tell
4038          * composite.c that we are USB 2.0 + LPM ECN.
4039          */
4040         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4041             !dwc->dis_metastability_quirk)
4042                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4043                                 dwc->revision);
4044
4045         dwc->gadget->max_speed          = dwc->maximum_speed;
4046         dwc->gadget->max_ssp_rate       = dwc->max_ssp_rate;
4047
4048         /*
4049          * REVISIT: Here we should clear all pending IRQs to be
4050          * sure we're starting from a well known location.
4051          */
4052
4053         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4054         if (ret)
4055                 goto err4;
4056
4057         ret = usb_add_gadget(dwc->gadget);
4058         if (ret) {
4059                 dev_err(dwc->dev, "failed to add gadget\n");
4060                 goto err5;
4061         }
4062
4063         if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4064                 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4065         else
4066                 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4067
4068         return 0;
4069
4070 err5:
4071         dwc3_gadget_free_endpoints(dwc);
4072 err4:
4073         usb_put_gadget(dwc->gadget);
4074         dwc->gadget = NULL;
4075 err3:
4076         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4077                         dwc->bounce_addr);
4078
4079 err2:
4080         kfree(dwc->setup_buf);
4081
4082 err1:
4083         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4084                         dwc->ep0_trb, dwc->ep0_trb_addr);
4085
4086 err0:
4087         return ret;
4088 }
4089
4090 /* -------------------------------------------------------------------------- */
4091
4092 void dwc3_gadget_exit(struct dwc3 *dwc)
4093 {
4094         if (!dwc->gadget)
4095                 return;
4096
4097         usb_del_gadget(dwc->gadget);
4098         dwc3_gadget_free_endpoints(dwc);
4099         usb_put_gadget(dwc->gadget);
4100         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4101                           dwc->bounce_addr);
4102         kfree(dwc->setup_buf);
4103         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4104                           dwc->ep0_trb, dwc->ep0_trb_addr);
4105 }
4106
4107 int dwc3_gadget_suspend(struct dwc3 *dwc)
4108 {
4109         if (!dwc->gadget_driver)
4110                 return 0;
4111
4112         dwc3_gadget_run_stop(dwc, false, false);
4113         dwc3_disconnect_gadget(dwc);
4114         __dwc3_gadget_stop(dwc);
4115
4116         return 0;
4117 }
4118
4119 int dwc3_gadget_resume(struct dwc3 *dwc)
4120 {
4121         int                     ret;
4122
4123         if (!dwc->gadget_driver)
4124                 return 0;
4125
4126         ret = __dwc3_gadget_start(dwc);
4127         if (ret < 0)
4128                 goto err0;
4129
4130         ret = dwc3_gadget_run_stop(dwc, true, false);
4131         if (ret < 0)
4132                 goto err1;
4133
4134         return 0;
4135
4136 err1:
4137         __dwc3_gadget_stop(dwc);
4138
4139 err0:
4140         return ret;
4141 }
4142
4143 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4144 {
4145         if (dwc->pending_events) {
4146                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4147                 dwc->pending_events = false;
4148                 enable_irq(dwc->irq_gadget);
4149         }
4150 }