1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
278 u32 saved_config = 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
313 link_state = dwc3_gadget_get_link_state(dwc);
314 if (link_state == DWC3_LINK_STATE_U1 ||
315 link_state == DWC3_LINK_STATE_U2 ||
316 link_state == DWC3_LINK_STATE_U3) {
317 ret = __dwc3_gadget_wakeup(dwc);
318 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
323 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
324 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
342 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
343 !usb_endpoint_xfer_isoc(desc))
344 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
346 cmd |= DWC3_DEPCMD_CMDACT;
348 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
350 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
351 if (!(reg & DWC3_DEPCMD_CMDACT)) {
352 cmd_status = DWC3_DEPCMD_STATUS(reg);
354 switch (cmd_status) {
358 case DEPEVT_TRANSFER_NO_RESOURCE:
359 dev_WARN(dwc->dev, "No resource for %s\n",
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
387 cmd_status = -ETIMEDOUT;
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
392 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
394 dep->flags |= DWC3_EP_TRANSFER_STARTED;
396 if (ret != -ETIMEDOUT)
397 dwc3_gadget_ep_get_transfer_index(dep);
401 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
411 struct dwc3 *dwc = dep->dwc;
412 struct dwc3_gadget_ep_cmd_params params;
413 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
416 * As of core revision 2.60a the recommended programming model
417 * is to set the ClearPendIN bit when issuing a Clear Stall EP
418 * command for IN endpoints. This is to prevent an issue where
419 * some (non-compliant) hosts may not send ACK TPs for pending
420 * IN transfers due to a mishandled error condition. Synopsys
423 if (dep->direction &&
424 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
425 (dwc->gadget->speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
428 memset(¶ms, 0, sizeof(params));
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
438 return dep->trb_pool_dma + offset;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
443 struct dwc3 *dwc = dep->dwc;
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
475 memset(¶ms, 0x00, sizeof(params));
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
541 ret = dwc3_gadget_set_xfer_resource(dep);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
559 memset(¶ms, 0x00, sizeof(params));
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
568 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
571 params.param0 |= action;
572 if (action == DWC3_DEPCFG_ACTION_RESTORE)
573 params.param2 |= dep->saved_state;
575 if (usb_endpoint_xfer_control(desc))
576 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
578 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
579 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
581 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
582 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
583 | DWC3_DEPCFG_XFER_COMPLETE_EN
584 | DWC3_DEPCFG_STREAM_EVENT_EN;
585 dep->stream_capable = true;
588 if (!usb_endpoint_xfer_control(desc))
589 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
592 * We are doing 1:1 mapping for endpoints, meaning
593 * Physical Endpoints 2 maps to Logical Endpoint 2 and
594 * so on. We consider the direction bit as part of the physical
595 * endpoint number. So USB endpoint 0x81 is 0x03.
597 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
600 * We must use the lower 16 TX FIFOs even though
604 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
606 if (desc->bInterval) {
610 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
612 * NOTE: The programming guide incorrectly stated bInterval_m1
613 * must be set to 0 when operating in fullspeed. Internally the
614 * controller does not have this limitation. See DWC_usb3x
615 * programming guide section 3.2.2.1.
617 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
619 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
620 dwc->gadget->speed == USB_SPEED_FULL)
621 dep->interval = desc->bInterval;
623 dep->interval = 1 << (desc->bInterval - 1);
625 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
628 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
631 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
635 * __dwc3_gadget_ep_enable - initializes a hw endpoint
636 * @dep: endpoint to be initialized
637 * @action: one of INIT, MODIFY or RESTORE
639 * Caller should take care of locking. Execute all necessary commands to
640 * initialize a HW endpoint so it can be used by a gadget driver.
642 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
644 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
645 struct dwc3 *dwc = dep->dwc;
650 if (!(dep->flags & DWC3_EP_ENABLED)) {
651 ret = dwc3_gadget_start_config(dep);
656 ret = dwc3_gadget_set_ep_config(dep, action);
660 if (!(dep->flags & DWC3_EP_ENABLED)) {
661 struct dwc3_trb *trb_st_hw;
662 struct dwc3_trb *trb_link;
664 dep->type = usb_endpoint_type(desc);
665 dep->flags |= DWC3_EP_ENABLED;
667 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
668 reg |= DWC3_DALEPENA_EP(dep->number);
669 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
671 if (usb_endpoint_xfer_control(desc))
674 /* Initialize the TRB ring */
675 dep->trb_dequeue = 0;
676 dep->trb_enqueue = 0;
677 memset(dep->trb_pool, 0,
678 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
680 /* Link TRB. The HWO bit is never reset */
681 trb_st_hw = &dep->trb_pool[0];
683 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
684 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
685 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
686 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
687 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
691 * Issue StartTransfer here with no-op TRB so we can always rely on No
692 * Response Update Transfer command.
694 if (usb_endpoint_xfer_bulk(desc) ||
695 usb_endpoint_xfer_int(desc)) {
696 struct dwc3_gadget_ep_cmd_params params;
697 struct dwc3_trb *trb;
701 memset(¶ms, 0, sizeof(params));
702 trb = &dep->trb_pool[0];
703 trb_dma = dwc3_trb_dma_offset(dep, trb);
705 params.param0 = upper_32_bits(trb_dma);
706 params.param1 = lower_32_bits(trb_dma);
708 cmd = DWC3_DEPCMD_STARTTRANSFER;
710 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
714 if (dep->stream_capable) {
716 * For streams, at start, there maybe a race where the
717 * host primes the endpoint before the function driver
718 * queues a request to initiate a stream. In that case,
719 * the controller will not see the prime to generate the
720 * ERDY and start stream. To workaround this, issue a
721 * no-op TRB as normal, but end it immediately. As a
722 * result, when the function driver queues the request,
723 * the next START_TRANSFER command will cause the
724 * controller to generate an ERDY to initiate the
727 dwc3_stop_active_transfer(dep, true, true);
730 * All stream eps will reinitiate stream on NoStream
731 * rejection until we can determine that the host can
732 * prime after the first transfer.
734 * However, if the controller is capable of
735 * TXF_FLUSH_BYPASS, then IN direction endpoints will
736 * automatically restart the stream without the driver
739 if (!dep->direction ||
740 !(dwc->hwparams.hwparams9 &
741 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
742 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
747 trace_dwc3_gadget_ep_enable(dep);
752 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
754 struct dwc3_request *req;
756 dwc3_stop_active_transfer(dep, true, false);
758 /* - giveback all requests to gadget driver */
759 while (!list_empty(&dep->started_list)) {
760 req = next_request(&dep->started_list);
762 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
765 while (!list_empty(&dep->pending_list)) {
766 req = next_request(&dep->pending_list);
768 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
771 while (!list_empty(&dep->cancelled_list)) {
772 req = next_request(&dep->cancelled_list);
774 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
779 * __dwc3_gadget_ep_disable - disables a hw endpoint
780 * @dep: the endpoint to disable
782 * This function undoes what __dwc3_gadget_ep_enable did and also removes
783 * requests which are currently being processed by the hardware and those which
784 * are not yet scheduled.
786 * Caller should take care of locking.
788 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
790 struct dwc3 *dwc = dep->dwc;
793 trace_dwc3_gadget_ep_disable(dep);
795 /* make sure HW endpoint isn't stalled */
796 if (dep->flags & DWC3_EP_STALL)
797 __dwc3_gadget_ep_set_halt(dep, 0, false);
799 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
800 reg &= ~DWC3_DALEPENA_EP(dep->number);
801 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
803 /* Clear out the ep descriptors for non-ep0 */
804 if (dep->number > 1) {
805 dep->endpoint.comp_desc = NULL;
806 dep->endpoint.desc = NULL;
809 dwc3_remove_requests(dwc, dep);
811 dep->stream_capable = false;
818 /* -------------------------------------------------------------------------- */
820 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
821 const struct usb_endpoint_descriptor *desc)
826 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
831 /* -------------------------------------------------------------------------- */
833 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
834 const struct usb_endpoint_descriptor *desc)
841 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
842 pr_debug("dwc3: invalid parameters\n");
846 if (!desc->wMaxPacketSize) {
847 pr_debug("dwc3: missing wMaxPacketSize\n");
851 dep = to_dwc3_ep(ep);
854 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
855 "%s is already enabled\n",
859 spin_lock_irqsave(&dwc->lock, flags);
860 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
861 spin_unlock_irqrestore(&dwc->lock, flags);
866 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
874 pr_debug("dwc3: invalid parameters\n");
878 dep = to_dwc3_ep(ep);
881 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
882 "%s is already disabled\n",
886 spin_lock_irqsave(&dwc->lock, flags);
887 ret = __dwc3_gadget_ep_disable(dep);
888 spin_unlock_irqrestore(&dwc->lock, flags);
893 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
896 struct dwc3_request *req;
897 struct dwc3_ep *dep = to_dwc3_ep(ep);
899 req = kzalloc(sizeof(*req), gfp_flags);
903 req->direction = dep->direction;
904 req->epnum = dep->number;
906 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
908 trace_dwc3_alloc_request(req);
910 return &req->request;
913 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
914 struct usb_request *request)
916 struct dwc3_request *req = to_dwc3_request(request);
918 trace_dwc3_free_request(req);
923 * dwc3_ep_prev_trb - returns the previous TRB in the ring
924 * @dep: The endpoint with the TRB ring
925 * @index: The index of the current TRB in the ring
927 * Returns the TRB prior to the one pointed to by the index. If the
928 * index is 0, we will wrap backwards, skip the link TRB, and return
929 * the one just before that.
931 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
936 tmp = DWC3_TRB_NUM - 1;
938 return &dep->trb_pool[tmp - 1];
941 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
943 struct dwc3_trb *tmp;
947 * If enqueue & dequeue are equal than it is either full or empty.
949 * One way to know for sure is if the TRB right before us has HWO bit
950 * set or not. If it has, then we're definitely full and can't fit any
951 * more transfers in our ring.
953 if (dep->trb_enqueue == dep->trb_dequeue) {
954 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
955 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
958 return DWC3_TRB_NUM - 1;
961 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
962 trbs_left &= (DWC3_TRB_NUM - 1);
964 if (dep->trb_dequeue < dep->trb_enqueue)
970 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
971 dma_addr_t dma, unsigned int length, unsigned int chain,
972 unsigned int node, unsigned int stream_id,
973 unsigned int short_not_ok, unsigned int no_interrupt,
974 unsigned int is_last, bool must_interrupt)
976 struct dwc3 *dwc = dep->dwc;
977 struct usb_gadget *gadget = dwc->gadget;
978 enum usb_device_speed speed = gadget->speed;
980 trb->size = DWC3_TRB_SIZE_LENGTH(length);
981 trb->bpl = lower_32_bits(dma);
982 trb->bph = upper_32_bits(dma);
984 switch (usb_endpoint_type(dep->endpoint.desc)) {
985 case USB_ENDPOINT_XFER_CONTROL:
986 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
989 case USB_ENDPOINT_XFER_ISOC:
991 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
994 * USB Specification 2.0 Section 5.9.2 states that: "If
995 * there is only a single transaction in the microframe,
996 * only a DATA0 data packet PID is used. If there are
997 * two transactions per microframe, DATA1 is used for
998 * the first transaction data packet and DATA0 is used
999 * for the second transaction data packet. If there are
1000 * three transactions per microframe, DATA2 is used for
1001 * the first transaction data packet, DATA1 is used for
1002 * the second, and DATA0 is used for the third."
1004 * IOW, we should satisfy the following cases:
1006 * 1) length <= maxpacket
1009 * 2) maxpacket < length <= (2 * maxpacket)
1012 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1013 * - DATA2, DATA1, DATA0
1015 if (speed == USB_SPEED_HIGH) {
1016 struct usb_ep *ep = &dep->endpoint;
1017 unsigned int mult = 2;
1018 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1020 if (length <= (2 * maxp))
1026 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1029 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1032 /* always enable Interrupt on Missed ISOC */
1033 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1036 case USB_ENDPOINT_XFER_BULK:
1037 case USB_ENDPOINT_XFER_INT:
1038 trb->ctrl = DWC3_TRBCTL_NORMAL;
1042 * This is only possible with faulty memory because we
1043 * checked it already :)
1045 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1046 usb_endpoint_type(dep->endpoint.desc));
1050 * Enable Continue on Short Packet
1051 * when endpoint is not a stream capable
1053 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1054 if (!dep->stream_capable)
1055 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1058 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1061 if ((!no_interrupt && !chain) || must_interrupt)
1062 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1065 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1066 else if (dep->stream_capable && is_last)
1067 trb->ctrl |= DWC3_TRB_CTRL_LST;
1069 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1070 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1072 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1074 dwc3_ep_inc_enq(dep);
1076 trace_dwc3_prepare_trb(dep, trb);
1080 * dwc3_prepare_one_trb - setup one TRB from one request
1081 * @dep: endpoint for which this request is prepared
1082 * @req: dwc3_request pointer
1083 * @trb_length: buffer size of the TRB
1084 * @chain: should this TRB be chained to the next?
1085 * @node: only for isochronous endpoints. First TRB needs different type.
1086 * @use_bounce_buffer: set to use bounce buffer
1087 * @must_interrupt: set to interrupt on TRB completion
1089 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1090 struct dwc3_request *req, unsigned int trb_length,
1091 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1092 bool must_interrupt)
1094 struct dwc3_trb *trb;
1096 unsigned int stream_id = req->request.stream_id;
1097 unsigned int short_not_ok = req->request.short_not_ok;
1098 unsigned int no_interrupt = req->request.no_interrupt;
1099 unsigned int is_last = req->request.is_last;
1101 if (use_bounce_buffer)
1102 dma = dep->dwc->bounce_addr;
1103 else if (req->request.num_sgs > 0)
1104 dma = sg_dma_address(req->start_sg);
1106 dma = req->request.dma;
1108 trb = &dep->trb_pool[dep->trb_enqueue];
1111 dwc3_gadget_move_started_request(req);
1113 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1118 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1119 stream_id, short_not_ok, no_interrupt, is_last,
1123 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1125 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1126 unsigned int rem = req->request.length % maxp;
1128 if ((req->request.length && req->request.zero && !rem &&
1129 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1130 (!req->direction && rem))
1137 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1138 * @dep: The endpoint that the request belongs to
1139 * @req: The request to prepare
1140 * @entry_length: The last SG entry size
1141 * @node: Indicates whether this is not the first entry (for isoc only)
1143 * Return the number of TRBs prepared.
1145 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1146 struct dwc3_request *req, unsigned int entry_length,
1149 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1150 unsigned int rem = req->request.length % maxp;
1151 unsigned int num_trbs = 1;
1153 if (dwc3_needs_extra_trb(dep, req))
1156 if (dwc3_calc_trbs_left(dep) < num_trbs)
1159 req->needs_extra_trb = num_trbs > 1;
1161 /* Prepare a normal TRB */
1162 if (req->direction || req->request.length)
1163 dwc3_prepare_one_trb(dep, req, entry_length,
1164 req->needs_extra_trb, node, false, false);
1166 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1167 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1168 dwc3_prepare_one_trb(dep, req,
1169 req->direction ? 0 : maxp - rem,
1170 false, 1, true, false);
1175 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1176 struct dwc3_request *req)
1178 struct scatterlist *sg = req->start_sg;
1179 struct scatterlist *s;
1181 unsigned int length = req->request.length;
1182 unsigned int remaining = req->request.num_mapped_sgs
1183 - req->num_queued_sgs;
1184 unsigned int num_trbs = req->num_trbs;
1185 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1188 * If we resume preparing the request, then get the remaining length of
1189 * the request and resume where we left off.
1191 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1192 length -= sg_dma_len(s);
1194 for_each_sg(sg, s, remaining, i) {
1195 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1196 unsigned int trb_length;
1197 bool must_interrupt = false;
1198 bool last_sg = false;
1200 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1202 length -= trb_length;
1205 * IOMMU driver is coalescing the list of sgs which shares a
1206 * page boundary into one and giving it to USB driver. With
1207 * this the number of sgs mapped is not equal to the number of
1208 * sgs passed. So mark the chain bit to false if it isthe last
1211 if ((i == remaining - 1) || !length)
1218 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1222 * Look ahead to check if we have enough TRBs for the
1223 * next SG entry. If not, set interrupt on this TRB to
1224 * resume preparing the next SG entry when more TRBs are
1227 if (num_trbs_left == 1 || (needs_extra_trb &&
1228 num_trbs_left <= 2 &&
1229 sg_dma_len(sg_next(s)) >= length))
1230 must_interrupt = true;
1232 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1237 * There can be a situation where all sgs in sglist are not
1238 * queued because of insufficient trb number. To handle this
1239 * case, update start_sg to next sg to be queued, so that
1240 * we have free trbs we can continue queuing from where we
1241 * previously stopped
1244 req->start_sg = sg_next(s);
1246 req->num_queued_sgs++;
1249 * The number of pending SG entries may not correspond to the
1250 * number of mapped SG entries. If all the data are queued, then
1251 * don't include unused SG entries.
1254 req->num_pending_sgs -= req->request.num_mapped_sgs - req->num_queued_sgs;
1262 return req->num_trbs - num_trbs;
1265 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1266 struct dwc3_request *req)
1268 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1272 * dwc3_prepare_trbs - setup TRBs from requests
1273 * @dep: endpoint for which requests are being prepared
1275 * The function goes through the requests list and sets up TRBs for the
1276 * transfers. The function returns once there are no more TRBs available or
1277 * it runs out of requests.
1279 * Returns the number of TRBs prepared or negative errno.
1281 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1283 struct dwc3_request *req, *n;
1286 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1289 * We can get in a situation where there's a request in the started list
1290 * but there weren't enough TRBs to fully kick it in the first time
1291 * around, so it has been waiting for more TRBs to be freed up.
1293 * In that case, we should check if we have a request with pending_sgs
1294 * in the started list and prepare TRBs for that request first,
1295 * otherwise we will prepare TRBs completely out of order and that will
1298 list_for_each_entry(req, &dep->started_list, list) {
1299 if (req->num_pending_sgs > 0) {
1300 ret = dwc3_prepare_trbs_sg(dep, req);
1301 if (!ret || req->num_pending_sgs)
1305 if (!dwc3_calc_trbs_left(dep))
1309 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1310 * burst capability may try to read and use TRBs beyond the
1311 * active transfer instead of stopping.
1313 if (dep->stream_capable && req->request.is_last)
1317 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1318 struct dwc3 *dwc = dep->dwc;
1320 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1325 req->sg = req->request.sg;
1326 req->start_sg = req->sg;
1327 req->num_queued_sgs = 0;
1328 req->num_pending_sgs = req->request.num_mapped_sgs;
1330 if (req->num_pending_sgs > 0) {
1331 ret = dwc3_prepare_trbs_sg(dep, req);
1332 if (req->num_pending_sgs)
1335 ret = dwc3_prepare_trbs_linear(dep, req);
1338 if (!ret || !dwc3_calc_trbs_left(dep))
1342 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1343 * burst capability may try to read and use TRBs beyond the
1344 * active transfer instead of stopping.
1346 if (dep->stream_capable && req->request.is_last)
1353 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1355 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1357 struct dwc3_gadget_ep_cmd_params params;
1358 struct dwc3_request *req;
1364 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1365 * This happens when we need to stop and restart a transfer such as in
1366 * the case of reinitiating a stream or retrying an isoc transfer.
1368 ret = dwc3_prepare_trbs(dep);
1372 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1375 * If there's no new TRB prepared and we don't need to restart a
1376 * transfer, there's no need to update the transfer.
1378 if (!ret && !starting)
1381 req = next_request(&dep->started_list);
1383 dep->flags |= DWC3_EP_PENDING_REQUEST;
1387 memset(¶ms, 0, sizeof(params));
1390 params.param0 = upper_32_bits(req->trb_dma);
1391 params.param1 = lower_32_bits(req->trb_dma);
1392 cmd = DWC3_DEPCMD_STARTTRANSFER;
1394 if (dep->stream_capable)
1395 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1397 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1398 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1400 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1401 DWC3_DEPCMD_PARAM(dep->resource_index);
1404 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1406 struct dwc3_request *tmp;
1411 dwc3_stop_active_transfer(dep, true, true);
1413 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1414 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1416 /* If ep isn't started, then there's no end transfer pending */
1417 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1418 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1423 if (dep->stream_capable && req->request.is_last)
1424 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1429 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1433 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1434 return DWC3_DSTS_SOFFN(reg);
1438 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1439 * @dep: isoc endpoint
1441 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1442 * microframe number reported by the XferNotReady event for the future frame
1443 * number to start the isoc transfer.
1445 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1446 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1447 * XferNotReady event are invalid. The driver uses this number to schedule the
1448 * isochronous transfer and passes it to the START TRANSFER command. Because
1449 * this number is invalid, the command may fail. If BIT[15:14] matches the
1450 * internal 16-bit microframe, the START TRANSFER command will pass and the
1451 * transfer will start at the scheduled time, if it is off by 1, the command
1452 * will still pass, but the transfer will start 2 seconds in the future. For all
1453 * other conditions, the START TRANSFER command will fail with bus-expiry.
1455 * In order to workaround this issue, we can test for the correct combination of
1456 * BIT[15:14] by sending START TRANSFER commands with different values of
1457 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1458 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1459 * As the result, within the 4 possible combinations for BIT[15:14], there will
1460 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1461 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1462 * value is the correct combination.
1464 * Since there are only 4 outcomes and the results are ordered, we can simply
1465 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1466 * deduce the smaller successful combination.
1468 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1469 * of BIT[15:14]. The correct combination is as follow:
1471 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1472 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1473 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1474 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1476 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1479 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1485 while (dep->combo_num < 2) {
1486 struct dwc3_gadget_ep_cmd_params params;
1487 u32 test_frame_number;
1491 * Check if we can start isoc transfer on the next interval or
1492 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1494 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1495 test_frame_number |= dep->combo_num << 14;
1496 test_frame_number += max_t(u32, 4, dep->interval);
1498 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1499 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1501 cmd = DWC3_DEPCMD_STARTTRANSFER;
1502 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1503 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1505 /* Redo if some other failure beside bus-expiry is received */
1506 if (cmd_status && cmd_status != -EAGAIN) {
1507 dep->start_cmd_status = 0;
1512 /* Store the first test status */
1513 if (dep->combo_num == 0)
1514 dep->start_cmd_status = cmd_status;
1519 * End the transfer if the START_TRANSFER command is successful
1520 * to wait for the next XferNotReady to test the command again
1522 if (cmd_status == 0) {
1523 dwc3_stop_active_transfer(dep, true, true);
1528 /* test0 and test1 are both completed at this point */
1529 test0 = (dep->start_cmd_status == 0);
1530 test1 = (cmd_status == 0);
1532 if (!test0 && test1)
1534 else if (!test0 && !test1)
1536 else if (test0 && !test1)
1538 else if (test0 && test1)
1541 dep->frame_number &= DWC3_FRNUMBER_MASK;
1542 dep->frame_number |= dep->combo_num << 14;
1543 dep->frame_number += max_t(u32, 4, dep->interval);
1545 /* Reinitialize test variables */
1546 dep->start_cmd_status = 0;
1549 return __dwc3_gadget_kick_transfer(dep);
1552 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1554 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1555 struct dwc3 *dwc = dep->dwc;
1559 if (list_empty(&dep->pending_list) &&
1560 list_empty(&dep->started_list)) {
1561 dep->flags |= DWC3_EP_PENDING_REQUEST;
1565 if (!dwc->dis_start_transfer_quirk &&
1566 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1567 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1568 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1569 return dwc3_gadget_start_isoc_quirk(dep);
1572 if (desc->bInterval <= 14 &&
1573 dwc->gadget->speed >= USB_SPEED_HIGH) {
1574 u32 frame = __dwc3_gadget_get_frame(dwc);
1575 bool rollover = frame <
1576 (dep->frame_number & DWC3_FRNUMBER_MASK);
1579 * frame_number is set from XferNotReady and may be already
1580 * out of date. DSTS only provides the lower 14 bit of the
1581 * current frame number. So add the upper two bits of
1582 * frame_number and handle a possible rollover.
1583 * This will provide the correct frame_number unless more than
1584 * rollover has happened since XferNotReady.
1587 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1590 dep->frame_number += BIT(14);
1593 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1594 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1596 ret = __dwc3_gadget_kick_transfer(dep);
1602 * After a number of unsuccessful start attempts due to bus-expiry
1603 * status, issue END_TRANSFER command and retry on the next XferNotReady
1606 if (ret == -EAGAIN) {
1607 struct dwc3_gadget_ep_cmd_params params;
1610 cmd = DWC3_DEPCMD_ENDTRANSFER |
1611 DWC3_DEPCMD_CMDIOC |
1612 DWC3_DEPCMD_PARAM(dep->resource_index);
1614 dep->resource_index = 0;
1615 memset(¶ms, 0, sizeof(params));
1617 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1619 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1625 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1627 struct dwc3 *dwc = dep->dwc;
1629 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1630 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1635 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1636 &req->request, req->dep->name))
1639 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1640 "%s: request %pK already in flight\n",
1641 dep->name, &req->request))
1644 pm_runtime_get(dwc->dev);
1646 req->request.actual = 0;
1647 req->request.status = -EINPROGRESS;
1649 trace_dwc3_ep_queue(req);
1651 list_add_tail(&req->list, &dep->pending_list);
1652 req->status = DWC3_REQUEST_STATUS_QUEUED;
1654 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1658 * Start the transfer only after the END_TRANSFER is completed
1659 * and endpoint STALL is cleared.
1661 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1662 (dep->flags & DWC3_EP_WEDGE) ||
1663 (dep->flags & DWC3_EP_STALL)) {
1664 dep->flags |= DWC3_EP_DELAY_START;
1669 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1670 * wait for a XferNotReady event so we will know what's the current
1671 * (micro-)frame number.
1673 * Without this trick, we are very, very likely gonna get Bus Expiry
1674 * errors which will force us issue EndTransfer command.
1676 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1677 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1678 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1681 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1682 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1683 return __dwc3_gadget_start_isoc(dep);
1687 return __dwc3_gadget_kick_transfer(dep);
1690 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1693 struct dwc3_request *req = to_dwc3_request(request);
1694 struct dwc3_ep *dep = to_dwc3_ep(ep);
1695 struct dwc3 *dwc = dep->dwc;
1697 unsigned long flags;
1701 spin_lock_irqsave(&dwc->lock, flags);
1702 ret = __dwc3_gadget_ep_queue(dep, req);
1703 spin_unlock_irqrestore(&dwc->lock, flags);
1708 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1712 /* If req->trb is not set, then the request has not started */
1717 * If request was already started, this means we had to
1718 * stop the transfer. With that we also need to ignore
1719 * all TRBs used by the request, however TRBs can only
1720 * be modified after completion of END_TRANSFER
1721 * command. So what we do here is that we wait for
1722 * END_TRANSFER completion and only after that, we jump
1723 * over TRBs by clearing HWO and incrementing dequeue
1726 for (i = 0; i < req->num_trbs; i++) {
1727 struct dwc3_trb *trb;
1729 trb = &dep->trb_pool[dep->trb_dequeue];
1730 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1731 dwc3_ep_inc_deq(dep);
1737 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1739 struct dwc3_request *req;
1740 struct dwc3_request *tmp;
1741 struct dwc3 *dwc = dep->dwc;
1743 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1744 dwc3_gadget_ep_skip_trbs(dep, req);
1745 switch (req->status) {
1746 case DWC3_REQUEST_STATUS_DISCONNECTED:
1747 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1749 case DWC3_REQUEST_STATUS_DEQUEUED:
1750 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1752 case DWC3_REQUEST_STATUS_STALLED:
1753 dwc3_gadget_giveback(dep, req, -EPIPE);
1756 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1757 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1763 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1764 struct usb_request *request)
1766 struct dwc3_request *req = to_dwc3_request(request);
1767 struct dwc3_request *r = NULL;
1769 struct dwc3_ep *dep = to_dwc3_ep(ep);
1770 struct dwc3 *dwc = dep->dwc;
1772 unsigned long flags;
1775 trace_dwc3_ep_dequeue(req);
1777 spin_lock_irqsave(&dwc->lock, flags);
1779 list_for_each_entry(r, &dep->cancelled_list, list) {
1784 list_for_each_entry(r, &dep->pending_list, list) {
1786 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1791 list_for_each_entry(r, &dep->started_list, list) {
1793 struct dwc3_request *t;
1795 /* wait until it is processed */
1796 dwc3_stop_active_transfer(dep, true, true);
1799 * Remove any started request if the transfer is
1802 list_for_each_entry_safe(r, t, &dep->started_list, list)
1803 dwc3_gadget_move_cancelled_request(r,
1804 DWC3_REQUEST_STATUS_DEQUEUED);
1806 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1812 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1816 spin_unlock_irqrestore(&dwc->lock, flags);
1821 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1823 struct dwc3_gadget_ep_cmd_params params;
1824 struct dwc3 *dwc = dep->dwc;
1825 struct dwc3_request *req;
1826 struct dwc3_request *tmp;
1829 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1830 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1834 memset(¶ms, 0x00, sizeof(params));
1837 struct dwc3_trb *trb;
1839 unsigned int transfer_in_flight;
1840 unsigned int started;
1842 if (dep->number > 1)
1843 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1845 trb = &dwc->ep0_trb[dep->trb_enqueue];
1847 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1848 started = !list_empty(&dep->started_list);
1850 if (!protocol && ((dep->direction && transfer_in_flight) ||
1851 (!dep->direction && started))) {
1855 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1858 dev_err(dwc->dev, "failed to set STALL on %s\n",
1861 dep->flags |= DWC3_EP_STALL;
1864 * Don't issue CLEAR_STALL command to control endpoints. The
1865 * controller automatically clears the STALL when it receives
1868 if (dep->number <= 1) {
1869 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1873 dwc3_stop_active_transfer(dep, true, true);
1875 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1876 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
1878 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1879 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1883 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1885 ret = dwc3_send_clear_stall_ep_cmd(dep);
1887 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1892 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1894 if ((dep->flags & DWC3_EP_DELAY_START) &&
1895 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1896 __dwc3_gadget_kick_transfer(dep);
1898 dep->flags &= ~DWC3_EP_DELAY_START;
1904 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1906 struct dwc3_ep *dep = to_dwc3_ep(ep);
1907 struct dwc3 *dwc = dep->dwc;
1909 unsigned long flags;
1913 spin_lock_irqsave(&dwc->lock, flags);
1914 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1915 spin_unlock_irqrestore(&dwc->lock, flags);
1920 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1922 struct dwc3_ep *dep = to_dwc3_ep(ep);
1923 struct dwc3 *dwc = dep->dwc;
1924 unsigned long flags;
1927 spin_lock_irqsave(&dwc->lock, flags);
1928 dep->flags |= DWC3_EP_WEDGE;
1930 if (dep->number == 0 || dep->number == 1)
1931 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1933 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1934 spin_unlock_irqrestore(&dwc->lock, flags);
1939 /* -------------------------------------------------------------------------- */
1941 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1942 .bLength = USB_DT_ENDPOINT_SIZE,
1943 .bDescriptorType = USB_DT_ENDPOINT,
1944 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1947 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1948 .enable = dwc3_gadget_ep0_enable,
1949 .disable = dwc3_gadget_ep0_disable,
1950 .alloc_request = dwc3_gadget_ep_alloc_request,
1951 .free_request = dwc3_gadget_ep_free_request,
1952 .queue = dwc3_gadget_ep0_queue,
1953 .dequeue = dwc3_gadget_ep_dequeue,
1954 .set_halt = dwc3_gadget_ep0_set_halt,
1955 .set_wedge = dwc3_gadget_ep_set_wedge,
1958 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1959 .enable = dwc3_gadget_ep_enable,
1960 .disable = dwc3_gadget_ep_disable,
1961 .alloc_request = dwc3_gadget_ep_alloc_request,
1962 .free_request = dwc3_gadget_ep_free_request,
1963 .queue = dwc3_gadget_ep_queue,
1964 .dequeue = dwc3_gadget_ep_dequeue,
1965 .set_halt = dwc3_gadget_ep_set_halt,
1966 .set_wedge = dwc3_gadget_ep_set_wedge,
1969 /* -------------------------------------------------------------------------- */
1971 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1973 struct dwc3 *dwc = gadget_to_dwc(g);
1975 return __dwc3_gadget_get_frame(dwc);
1978 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1988 * According to the Databook Remote wakeup request should
1989 * be issued only when the device is in early suspend state.
1991 * We can check that via USB Link State bits in DSTS register.
1993 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1995 link_state = DWC3_DSTS_USBLNKST(reg);
1997 switch (link_state) {
1998 case DWC3_LINK_STATE_RESET:
1999 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2000 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2001 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2002 case DWC3_LINK_STATE_U1:
2003 case DWC3_LINK_STATE_RESUME:
2009 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2011 dev_err(dwc->dev, "failed to put link in Recovery\n");
2015 /* Recent versions do this automatically */
2016 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2017 /* write zeroes to Link Change Request */
2018 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2019 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2020 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2023 /* poll until Link State changes to ON */
2027 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2029 /* in HS, means ON */
2030 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2034 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2035 dev_err(dwc->dev, "failed to send remote wakeup\n");
2042 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2044 struct dwc3 *dwc = gadget_to_dwc(g);
2045 unsigned long flags;
2048 spin_lock_irqsave(&dwc->lock, flags);
2049 ret = __dwc3_gadget_wakeup(dwc);
2050 spin_unlock_irqrestore(&dwc->lock, flags);
2055 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2058 struct dwc3 *dwc = gadget_to_dwc(g);
2059 unsigned long flags;
2061 spin_lock_irqsave(&dwc->lock, flags);
2062 g->is_selfpowered = !!is_selfpowered;
2063 spin_unlock_irqrestore(&dwc->lock, flags);
2068 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2072 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2073 struct dwc3_ep *dep;
2075 dep = dwc->eps[epnum];
2079 dwc3_remove_requests(dwc, dep);
2083 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2085 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2088 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2089 ssp_rate = dwc->max_ssp_rate;
2091 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2092 reg &= ~DWC3_DCFG_SPEED_MASK;
2093 reg &= ~DWC3_DCFG_NUMLANES(~0);
2095 if (ssp_rate == USB_SSP_GEN_1x2)
2096 reg |= DWC3_DCFG_SUPERSPEED;
2097 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2098 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2100 if (ssp_rate != USB_SSP_GEN_2x1 &&
2101 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2102 reg |= DWC3_DCFG_NUMLANES(1);
2104 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2107 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2109 enum usb_device_speed speed;
2112 speed = dwc->gadget_max_speed;
2113 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2114 speed = dwc->maximum_speed;
2116 if (speed == USB_SPEED_SUPER_PLUS &&
2117 DWC3_IP_IS(DWC32)) {
2118 __dwc3_gadget_set_ssp_rate(dwc);
2122 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2123 reg &= ~(DWC3_DCFG_SPEED_MASK);
2126 * WORKAROUND: DWC3 revision < 2.20a have an issue
2127 * which would cause metastability state on Run/Stop
2128 * bit if we try to force the IP to USB2-only mode.
2130 * Because of that, we cannot configure the IP to any
2131 * speed other than the SuperSpeed
2135 * STAR#9000525659: Clock Domain Crossing on DCTL in
2138 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2139 !dwc->dis_metastability_quirk) {
2140 reg |= DWC3_DCFG_SUPERSPEED;
2143 case USB_SPEED_FULL:
2144 reg |= DWC3_DCFG_FULLSPEED;
2146 case USB_SPEED_HIGH:
2147 reg |= DWC3_DCFG_HIGHSPEED;
2149 case USB_SPEED_SUPER:
2150 reg |= DWC3_DCFG_SUPERSPEED;
2152 case USB_SPEED_SUPER_PLUS:
2153 if (DWC3_IP_IS(DWC3))
2154 reg |= DWC3_DCFG_SUPERSPEED;
2156 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2159 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2161 if (DWC3_IP_IS(DWC3))
2162 reg |= DWC3_DCFG_SUPERSPEED;
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2168 if (DWC3_IP_IS(DWC32) &&
2169 speed > USB_SPEED_UNKNOWN &&
2170 speed < USB_SPEED_SUPER_PLUS)
2171 reg &= ~DWC3_DCFG_NUMLANES(~0);
2173 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2176 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2181 if (pm_runtime_suspended(dwc->dev))
2184 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2186 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2187 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2188 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2191 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2192 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2193 reg |= DWC3_DCTL_RUN_STOP;
2195 if (dwc->has_hibernation)
2196 reg |= DWC3_DCTL_KEEP_CONNECT;
2198 __dwc3_gadget_set_speed(dwc);
2199 dwc->pullups_connected = true;
2201 reg &= ~DWC3_DCTL_RUN_STOP;
2203 if (dwc->has_hibernation && !suspend)
2204 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2206 dwc->pullups_connected = false;
2209 dwc3_gadget_dctl_write_safe(dwc, reg);
2212 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2213 reg &= DWC3_DSTS_DEVCTRLHLT;
2214 } while (--timeout && !(!is_on ^ !reg));
2222 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2223 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2224 static int __dwc3_gadget_start(struct dwc3 *dwc);
2226 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2228 struct dwc3 *dwc = gadget_to_dwc(g);
2229 unsigned long flags;
2235 * Per databook, when we want to stop the gadget, if a control transfer
2236 * is still in process, complete it and get the core into setup phase.
2238 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2239 reinit_completion(&dwc->ep0_in_setup);
2241 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2242 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2244 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
2250 * Check the return value for successful resume, or error. For a
2251 * successful resume, the DWC3 runtime PM resume routine will handle
2252 * the run stop sequence, so avoid duplicate operations here.
2254 ret = pm_runtime_get_sync(dwc->dev);
2255 if (!ret || ret < 0) {
2256 pm_runtime_put(dwc->dev);
2261 * Synchronize any pending event handling before executing the controller
2265 dwc3_gadget_disable_irq(dwc);
2266 synchronize_irq(dwc->irq_gadget);
2269 spin_lock_irqsave(&dwc->lock, flags);
2274 dwc->connected = false;
2276 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2277 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2278 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2279 * command for any active transfers" before clearing the RunStop
2282 dwc3_stop_active_transfers(dwc);
2283 __dwc3_gadget_stop(dwc);
2286 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2287 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2288 * "software needs to acknowledge the events that are generated
2289 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2290 * to be set to '1'."
2292 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2293 count &= DWC3_GEVNTCOUNT_MASK;
2295 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2296 dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2297 dwc->ev_buf->length;
2300 __dwc3_gadget_start(dwc);
2303 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2304 spin_unlock_irqrestore(&dwc->lock, flags);
2305 pm_runtime_put(dwc->dev);
2310 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2314 /* Enable all but Start and End of Frame IRQs */
2315 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2316 DWC3_DEVTEN_CMDCMPLTEN |
2317 DWC3_DEVTEN_ERRTICERREN |
2318 DWC3_DEVTEN_WKUPEVTEN |
2319 DWC3_DEVTEN_CONNECTDONEEN |
2320 DWC3_DEVTEN_USBRSTEN |
2321 DWC3_DEVTEN_DISCONNEVTEN);
2323 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2324 reg |= DWC3_DEVTEN_ULSTCNGEN;
2326 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2329 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2331 /* mask all interrupts */
2332 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2335 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2336 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2339 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2340 * @dwc: pointer to our context structure
2342 * The following looks like complex but it's actually very simple. In order to
2343 * calculate the number of packets we can burst at once on OUT transfers, we're
2344 * gonna use RxFIFO size.
2346 * To calculate RxFIFO size we need two numbers:
2347 * MDWIDTH = size, in bits, of the internal memory bus
2348 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2350 * Given these two numbers, the formula is simple:
2352 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2354 * 24 bytes is for 3x SETUP packets
2355 * 16 bytes is a clock domain crossing tolerance
2357 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2359 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2366 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2367 mdwidth = dwc3_mdwidth(dwc);
2369 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2370 nump = min_t(u32, nump, 16);
2373 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2374 reg &= ~DWC3_DCFG_NUMP_MASK;
2375 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2376 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2379 static int __dwc3_gadget_start(struct dwc3 *dwc)
2381 struct dwc3_ep *dep;
2386 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2387 * the core supports IMOD, disable it.
2389 if (dwc->imod_interval) {
2390 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2391 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2392 } else if (dwc3_has_imod(dwc)) {
2393 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2397 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2398 * field instead of letting dwc3 itself calculate that automatically.
2400 * This way, we maximize the chances that we'll be able to get several
2401 * bursts of data without going through any sort of endpoint throttling.
2403 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2404 if (DWC3_IP_IS(DWC3))
2405 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2407 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2409 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2411 dwc3_gadget_setup_nump(dwc);
2414 * Currently the controller handles single stream only. So, Ignore
2415 * Packet Pending bit for stream selection and don't search for another
2416 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2417 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2418 * the stream performance.
2420 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2421 reg |= DWC3_DCFG_IGNSTRMPP;
2422 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2424 /* Start with SuperSpeed Default */
2425 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2428 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2430 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2435 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2437 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2441 /* begin to receive SETUP packets */
2442 dwc->ep0state = EP0_SETUP_PHASE;
2443 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2444 dwc3_ep0_out_start(dwc);
2446 dwc3_gadget_enable_irq(dwc);
2451 __dwc3_gadget_ep_disable(dwc->eps[0]);
2457 static int dwc3_gadget_start(struct usb_gadget *g,
2458 struct usb_gadget_driver *driver)
2460 struct dwc3 *dwc = gadget_to_dwc(g);
2461 unsigned long flags;
2465 irq = dwc->irq_gadget;
2466 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2467 IRQF_SHARED, "dwc3", dwc->ev_buf);
2469 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2474 spin_lock_irqsave(&dwc->lock, flags);
2475 dwc->gadget_driver = driver;
2476 spin_unlock_irqrestore(&dwc->lock, flags);
2481 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2483 dwc3_gadget_disable_irq(dwc);
2484 __dwc3_gadget_ep_disable(dwc->eps[0]);
2485 __dwc3_gadget_ep_disable(dwc->eps[1]);
2488 static int dwc3_gadget_stop(struct usb_gadget *g)
2490 struct dwc3 *dwc = gadget_to_dwc(g);
2491 unsigned long flags;
2493 spin_lock_irqsave(&dwc->lock, flags);
2494 dwc->gadget_driver = NULL;
2495 spin_unlock_irqrestore(&dwc->lock, flags);
2497 free_irq(dwc->irq_gadget, dwc->ev_buf);
2502 static void dwc3_gadget_config_params(struct usb_gadget *g,
2503 struct usb_dcd_config_params *params)
2505 struct dwc3 *dwc = gadget_to_dwc(g);
2507 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2508 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2510 /* Recommended BESL */
2511 if (!dwc->dis_enblslpm_quirk) {
2513 * If the recommended BESL baseline is 0 or if the BESL deep is
2514 * less than 2, Microsoft's Windows 10 host usb stack will issue
2515 * a usb reset immediately after it receives the extended BOS
2516 * descriptor and the enumeration will fail. To maintain
2517 * compatibility with the Windows' usb stack, let's set the
2518 * recommended BESL baseline to 1 and clamp the BESL deep to be
2521 params->besl_baseline = 1;
2522 if (dwc->is_utmi_l1_suspend)
2524 clamp_t(u8, dwc->hird_threshold, 2, 15);
2527 /* U1 Device exit Latency */
2528 if (dwc->dis_u1_entry_quirk)
2529 params->bU1devExitLat = 0;
2531 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2533 /* U2 Device exit Latency */
2534 if (dwc->dis_u2_entry_quirk)
2535 params->bU2DevExitLat = 0;
2537 params->bU2DevExitLat =
2538 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2541 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2542 enum usb_device_speed speed)
2544 struct dwc3 *dwc = gadget_to_dwc(g);
2545 unsigned long flags;
2547 spin_lock_irqsave(&dwc->lock, flags);
2548 dwc->gadget_max_speed = speed;
2549 spin_unlock_irqrestore(&dwc->lock, flags);
2552 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2553 enum usb_ssp_rate rate)
2555 struct dwc3 *dwc = gadget_to_dwc(g);
2556 unsigned long flags;
2558 spin_lock_irqsave(&dwc->lock, flags);
2559 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2560 dwc->gadget_ssp_rate = rate;
2561 spin_unlock_irqrestore(&dwc->lock, flags);
2564 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2566 struct dwc3 *dwc = gadget_to_dwc(g);
2567 union power_supply_propval val = {0};
2571 return usb_phy_set_power(dwc->usb2_phy, mA);
2576 val.intval = 1000 * mA;
2577 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2582 static const struct usb_gadget_ops dwc3_gadget_ops = {
2583 .get_frame = dwc3_gadget_get_frame,
2584 .wakeup = dwc3_gadget_wakeup,
2585 .set_selfpowered = dwc3_gadget_set_selfpowered,
2586 .pullup = dwc3_gadget_pullup,
2587 .udc_start = dwc3_gadget_start,
2588 .udc_stop = dwc3_gadget_stop,
2589 .udc_set_speed = dwc3_gadget_set_speed,
2590 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
2591 .get_config_params = dwc3_gadget_config_params,
2592 .vbus_draw = dwc3_gadget_vbus_draw,
2595 /* -------------------------------------------------------------------------- */
2597 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2599 struct dwc3 *dwc = dep->dwc;
2601 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2602 dep->endpoint.maxburst = 1;
2603 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2604 if (!dep->direction)
2605 dwc->gadget->ep0 = &dep->endpoint;
2607 dep->endpoint.caps.type_control = true;
2612 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2614 struct dwc3 *dwc = dep->dwc;
2618 mdwidth = dwc3_mdwidth(dwc);
2620 /* MDWIDTH is represented in bits, we need it in bytes */
2623 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2624 if (DWC3_IP_IS(DWC3))
2625 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2627 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2629 /* FIFO Depth is in MDWDITH bytes. Multiply */
2633 * To meet performance requirement, a minimum TxFIFO size of 3x
2634 * MaxPacketSize is recommended for endpoints that support burst and a
2635 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2636 * support burst. Use those numbers and we can calculate the max packet
2639 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2644 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2646 dep->endpoint.max_streams = 16;
2647 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2648 list_add_tail(&dep->endpoint.ep_list,
2649 &dwc->gadget->ep_list);
2650 dep->endpoint.caps.type_iso = true;
2651 dep->endpoint.caps.type_bulk = true;
2652 dep->endpoint.caps.type_int = true;
2654 return dwc3_alloc_trb_pool(dep);
2657 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2659 struct dwc3 *dwc = dep->dwc;
2663 mdwidth = dwc3_mdwidth(dwc);
2665 /* MDWIDTH is represented in bits, convert to bytes */
2668 /* All OUT endpoints share a single RxFIFO space */
2669 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2670 if (DWC3_IP_IS(DWC3))
2671 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2673 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2675 /* FIFO depth is in MDWDITH bytes */
2679 * To meet performance requirement, a minimum recommended RxFIFO size
2680 * is defined as follow:
2681 * RxFIFO size >= (3 x MaxPacketSize) +
2682 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2684 * Then calculate the max packet limit as below.
2686 size -= (3 * 8) + 16;
2692 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2693 dep->endpoint.max_streams = 16;
2694 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2695 list_add_tail(&dep->endpoint.ep_list,
2696 &dwc->gadget->ep_list);
2697 dep->endpoint.caps.type_iso = true;
2698 dep->endpoint.caps.type_bulk = true;
2699 dep->endpoint.caps.type_int = true;
2701 return dwc3_alloc_trb_pool(dep);
2704 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2706 struct dwc3_ep *dep;
2707 bool direction = epnum & 1;
2709 u8 num = epnum >> 1;
2711 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2716 dep->number = epnum;
2717 dep->direction = direction;
2718 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2719 dwc->eps[epnum] = dep;
2721 dep->start_cmd_status = 0;
2723 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2724 direction ? "in" : "out");
2726 dep->endpoint.name = dep->name;
2728 if (!(dep->number > 1)) {
2729 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2730 dep->endpoint.comp_desc = NULL;
2734 ret = dwc3_gadget_init_control_endpoint(dep);
2736 ret = dwc3_gadget_init_in_endpoint(dep);
2738 ret = dwc3_gadget_init_out_endpoint(dep);
2743 dep->endpoint.caps.dir_in = direction;
2744 dep->endpoint.caps.dir_out = !direction;
2746 INIT_LIST_HEAD(&dep->pending_list);
2747 INIT_LIST_HEAD(&dep->started_list);
2748 INIT_LIST_HEAD(&dep->cancelled_list);
2753 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2757 INIT_LIST_HEAD(&dwc->gadget->ep_list);
2759 for (epnum = 0; epnum < total; epnum++) {
2762 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2770 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2772 struct dwc3_ep *dep;
2775 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2776 dep = dwc->eps[epnum];
2780 * Physical endpoints 0 and 1 are special; they form the
2781 * bi-directional USB endpoint 0.
2783 * For those two physical endpoints, we don't allocate a TRB
2784 * pool nor do we add them the endpoints list. Due to that, we
2785 * shouldn't do these two operations otherwise we would end up
2786 * with all sorts of bugs when removing dwc3.ko.
2788 if (epnum != 0 && epnum != 1) {
2789 dwc3_free_trb_pool(dep);
2790 list_del(&dep->endpoint.ep_list);
2797 /* -------------------------------------------------------------------------- */
2799 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2800 struct dwc3_request *req, struct dwc3_trb *trb,
2801 const struct dwc3_event_depevt *event, int status, int chain)
2805 dwc3_ep_inc_deq(dep);
2807 trace_dwc3_complete_trb(dep, trb);
2811 * If we're in the middle of series of chained TRBs and we
2812 * receive a short transfer along the way, DWC3 will skip
2813 * through all TRBs including the last TRB in the chain (the
2814 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2815 * bit and SW has to do it manually.
2817 * We're going to do that here to avoid problems of HW trying
2818 * to use bogus TRBs for transfers.
2820 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2821 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2824 * For isochronous transfers, the first TRB in a service interval must
2825 * have the Isoc-First type. Track and report its interval frame number.
2827 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2828 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2829 unsigned int frame_number;
2831 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2832 frame_number &= ~(dep->interval - 1);
2833 req->request.frame_number = frame_number;
2837 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2838 * this TRB points to the bounce buffer address, it's a MPS alignment
2839 * TRB. Don't add it to req->remaining calculation.
2841 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2842 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2843 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2847 count = trb->size & DWC3_TRB_SIZE_MASK;
2848 req->remaining += count;
2850 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2853 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2856 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2857 (trb->ctrl & DWC3_TRB_CTRL_LST))
2863 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2864 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2867 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2868 struct scatterlist *sg = req->sg;
2869 struct scatterlist *s;
2870 unsigned int pending = req->num_pending_sgs;
2874 for_each_sg(sg, s, pending, i) {
2875 trb = &dep->trb_pool[dep->trb_dequeue];
2877 req->sg = sg_next(s);
2878 req->num_pending_sgs--;
2880 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2881 trb, event, status, true);
2889 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2890 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2893 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2895 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2896 event, status, false);
2899 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2901 return req->num_pending_sgs == 0;
2904 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2905 const struct dwc3_event_depevt *event,
2906 struct dwc3_request *req, int status)
2910 if (req->num_pending_sgs)
2911 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2914 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2917 req->request.actual = req->request.length - req->remaining;
2919 if (!dwc3_gadget_ep_request_completed(req))
2922 if (req->needs_extra_trb) {
2923 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2925 req->needs_extra_trb = false;
2928 dwc3_gadget_giveback(dep, req, status);
2934 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2935 const struct dwc3_event_depevt *event, int status)
2937 struct dwc3_request *req;
2938 struct dwc3_request *tmp;
2940 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2943 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2950 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2952 struct dwc3_request *req;
2953 struct dwc3 *dwc = dep->dwc;
2955 if (!dep->endpoint.desc || !dwc->pullups_connected ||
2959 if (!list_empty(&dep->pending_list))
2963 * We only need to check the first entry of the started list. We can
2964 * assume the completed requests are removed from the started list.
2966 req = next_request(&dep->started_list);
2970 return !dwc3_gadget_ep_request_completed(req);
2973 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2974 const struct dwc3_event_depevt *event)
2976 dep->frame_number = event->parameters;
2979 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
2980 const struct dwc3_event_depevt *event, int status)
2982 struct dwc3 *dwc = dep->dwc;
2983 bool no_started_trb = true;
2985 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2987 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2990 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2991 list_empty(&dep->started_list) &&
2992 (list_empty(&dep->pending_list) || status == -EXDEV))
2993 dwc3_stop_active_transfer(dep, true, true);
2994 else if (dwc3_gadget_ep_should_continue(dep))
2995 if (__dwc3_gadget_kick_transfer(dep) == 0)
2996 no_started_trb = false;
3000 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3001 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3003 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3007 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3010 if (!(dep->flags & DWC3_EP_ENABLED))
3013 if (!list_empty(&dep->started_list))
3014 return no_started_trb;
3017 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3019 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3024 return no_started_trb;
3027 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3028 const struct dwc3_event_depevt *event)
3032 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3033 dwc3_gadget_endpoint_frame_from_event(dep, event);
3035 if (event->status & DEPEVT_STATUS_BUSERR)
3036 status = -ECONNRESET;
3038 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3041 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3044 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3045 const struct dwc3_event_depevt *event)
3049 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3051 if (event->status & DEPEVT_STATUS_BUSERR)
3052 status = -ECONNRESET;
3054 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3055 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3058 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3059 const struct dwc3_event_depevt *event)
3061 dwc3_gadget_endpoint_frame_from_event(dep, event);
3064 * The XferNotReady event is generated only once before the endpoint
3065 * starts. It will be generated again when END_TRANSFER command is
3066 * issued. For some controller versions, the XferNotReady event may be
3067 * generated while the END_TRANSFER command is still in process. Ignore
3068 * it and wait for the next XferNotReady event after the command is
3071 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3074 (void) __dwc3_gadget_start_isoc(dep);
3077 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3078 const struct dwc3_event_depevt *event)
3080 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3082 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3085 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3086 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3087 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3089 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3090 struct dwc3 *dwc = dep->dwc;
3092 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3093 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3094 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3096 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3097 if (dwc->delayed_status)
3098 __dwc3_gadget_ep0_set_halt(ep0, 1);
3102 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3103 if (dwc->delayed_status)
3104 dwc3_ep0_send_delayed_status(dwc);
3107 if ((dep->flags & DWC3_EP_DELAY_START) &&
3108 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3109 __dwc3_gadget_kick_transfer(dep);
3111 dep->flags &= ~DWC3_EP_DELAY_START;
3114 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3115 const struct dwc3_event_depevt *event)
3117 struct dwc3 *dwc = dep->dwc;
3119 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3120 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3124 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3125 switch (event->parameters) {
3126 case DEPEVT_STREAM_PRIME:
3128 * If the host can properly transition the endpoint state from
3129 * idle to prime after a NoStream rejection, there's no need to
3130 * force restarting the endpoint to reinitiate the stream. To
3131 * simplify the check, assume the host follows the USB spec if
3132 * it primed the endpoint more than once.
3134 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3135 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3136 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3138 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3142 case DEPEVT_STREAM_NOSTREAM:
3143 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3144 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3145 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3149 * If the host rejects a stream due to no active stream, by the
3150 * USB and xHCI spec, the endpoint will be put back to idle
3151 * state. When the host is ready (buffer added/updated), it will
3152 * prime the endpoint to inform the usb device controller. This
3153 * triggers the device controller to issue ERDY to restart the
3154 * stream. However, some hosts don't follow this and keep the
3155 * endpoint in the idle state. No prime will come despite host
3156 * streams are updated, and the device controller will not be
3157 * triggered to generate ERDY to move the next stream data. To
3158 * workaround this and maintain compatibility with various
3159 * hosts, force to reinitate the stream until the host is ready
3160 * instead of waiting for the host to prime the endpoint.
3162 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3163 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3165 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3167 dep->flags |= DWC3_EP_DELAY_START;
3168 dwc3_stop_active_transfer(dep, true, true);
3175 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3178 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3179 const struct dwc3_event_depevt *event)
3181 struct dwc3_ep *dep;
3182 u8 epnum = event->endpoint_number;
3184 dep = dwc->eps[epnum];
3186 if (!(dep->flags & DWC3_EP_ENABLED)) {
3187 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3190 /* Handle only EPCMDCMPLT when EP disabled */
3191 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3195 if (epnum == 0 || epnum == 1) {
3196 dwc3_ep0_interrupt(dwc, event);
3200 switch (event->endpoint_event) {
3201 case DWC3_DEPEVT_XFERINPROGRESS:
3202 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3204 case DWC3_DEPEVT_XFERNOTREADY:
3205 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3207 case DWC3_DEPEVT_EPCMDCMPLT:
3208 dwc3_gadget_endpoint_command_complete(dep, event);
3210 case DWC3_DEPEVT_XFERCOMPLETE:
3211 dwc3_gadget_endpoint_transfer_complete(dep, event);
3213 case DWC3_DEPEVT_STREAMEVT:
3214 dwc3_gadget_endpoint_stream_event(dep, event);
3216 case DWC3_DEPEVT_RXTXFIFOEVT:
3221 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3223 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
3224 spin_unlock(&dwc->lock);
3225 dwc->gadget_driver->disconnect(dwc->gadget);
3226 spin_lock(&dwc->lock);
3230 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3232 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
3233 spin_unlock(&dwc->lock);
3234 dwc->gadget_driver->suspend(dwc->gadget);
3235 spin_lock(&dwc->lock);
3239 static void dwc3_resume_gadget(struct dwc3 *dwc)
3241 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3242 spin_unlock(&dwc->lock);
3243 dwc->gadget_driver->resume(dwc->gadget);
3244 spin_lock(&dwc->lock);
3248 static void dwc3_reset_gadget(struct dwc3 *dwc)
3250 if (!dwc->gadget_driver)
3253 if (dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3254 spin_unlock(&dwc->lock);
3255 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3256 spin_lock(&dwc->lock);
3260 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3263 struct dwc3_gadget_ep_cmd_params params;
3267 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3268 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3272 * NOTICE: We are violating what the Databook says about the
3273 * EndTransfer command. Ideally we would _always_ wait for the
3274 * EndTransfer Command Completion IRQ, but that's causing too
3275 * much trouble synchronizing between us and gadget driver.
3277 * We have discussed this with the IP Provider and it was
3278 * suggested to giveback all requests here.
3280 * Note also that a similar handling was tested by Synopsys
3281 * (thanks a lot Paul) and nothing bad has come out of it.
3282 * In short, what we're doing is issuing EndTransfer with
3283 * CMDIOC bit set and delay kicking transfer until the
3284 * EndTransfer command had completed.
3286 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3287 * supports a mode to work around the above limitation. The
3288 * software can poll the CMDACT bit in the DEPCMD register
3289 * after issuing a EndTransfer command. This mode is enabled
3290 * by writing GUCTL2[14]. This polling is already done in the
3291 * dwc3_send_gadget_ep_cmd() function so if the mode is
3292 * enabled, the EndTransfer command will have completed upon
3293 * returning from this function.
3295 * This mode is NOT available on the DWC_usb31 IP.
3298 cmd = DWC3_DEPCMD_ENDTRANSFER;
3299 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3300 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3301 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3302 memset(¶ms, 0, sizeof(params));
3303 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3305 dep->resource_index = 0;
3308 * The END_TRANSFER command will cause the controller to generate a
3309 * NoStream Event, and it's not due to the host DP NoStream rejection.
3310 * Ignore the next NoStream event.
3312 if (dep->stream_capable)
3313 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3316 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3318 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3321 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3325 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3326 struct dwc3_ep *dep;
3329 dep = dwc->eps[epnum];
3333 if (!(dep->flags & DWC3_EP_STALL))
3336 dep->flags &= ~DWC3_EP_STALL;
3338 ret = dwc3_send_clear_stall_ep_cmd(dep);
3343 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3347 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3349 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3350 reg &= ~DWC3_DCTL_INITU1ENA;
3351 reg &= ~DWC3_DCTL_INITU2ENA;
3352 dwc3_gadget_dctl_write_safe(dwc, reg);
3354 dwc3_disconnect_gadget(dwc);
3356 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3357 dwc->setup_packet_pending = false;
3358 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3360 dwc->connected = false;
3363 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3368 * Ideally, dwc3_reset_gadget() would trigger the function
3369 * drivers to stop any active transfers through ep disable.
3370 * However, for functions which defer ep disable, such as mass
3371 * storage, we will need to rely on the call to stop active
3372 * transfers here, and avoid allowing of request queuing.
3374 dwc->connected = false;
3377 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3378 * would cause a missing Disconnect Event if there's a
3379 * pending Setup Packet in the FIFO.
3381 * There's no suggested workaround on the official Bug
3382 * report, which states that "unless the driver/application
3383 * is doing any special handling of a disconnect event,
3384 * there is no functional issue".
3386 * Unfortunately, it turns out that we _do_ some special
3387 * handling of a disconnect event, namely complete all
3388 * pending transfers, notify gadget driver of the
3389 * disconnection, and so on.
3391 * Our suggested workaround is to follow the Disconnect
3392 * Event steps here, instead, based on a setup_packet_pending
3393 * flag. Such flag gets set whenever we have a SETUP_PENDING
3394 * status for EP0 TRBs and gets cleared on XferComplete for the
3399 * STAR#9000466709: RTL: Device : Disconnect event not
3400 * generated if setup packet pending in FIFO
3402 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3403 if (dwc->setup_packet_pending)
3404 dwc3_gadget_disconnect_interrupt(dwc);
3407 dwc3_reset_gadget(dwc);
3409 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3410 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3411 * needs to ensure that it sends "a DEPENDXFER command for any active
3414 dwc3_stop_active_transfers(dwc);
3415 dwc->connected = true;
3417 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3418 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3419 dwc3_gadget_dctl_write_safe(dwc, reg);
3420 dwc->test_mode = false;
3421 dwc3_clear_stall_all_ep(dwc);
3423 /* Reset device address to zero */
3424 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3425 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3426 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3429 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3431 struct dwc3_ep *dep;
3437 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3438 speed = reg & DWC3_DSTS_CONNECTSPD;
3441 if (DWC3_IP_IS(DWC32))
3442 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3444 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3447 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3448 * each time on Connect Done.
3450 * Currently we always use the reset value. If any platform
3451 * wants to set this to a different value, we need to add a
3452 * setting and update GCTL.RAMCLKSEL here.
3456 case DWC3_DSTS_SUPERSPEED_PLUS:
3457 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3458 dwc->gadget->ep0->maxpacket = 512;
3459 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3462 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3464 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3466 case DWC3_DSTS_SUPERSPEED:
3468 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3469 * would cause a missing USB3 Reset event.
3471 * In such situations, we should force a USB3 Reset
3472 * event by calling our dwc3_gadget_reset_interrupt()
3477 * STAR#9000483510: RTL: SS : USB3 reset event may
3478 * not be generated always when the link enters poll
3480 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3481 dwc3_gadget_reset_interrupt(dwc);
3483 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3484 dwc->gadget->ep0->maxpacket = 512;
3485 dwc->gadget->speed = USB_SPEED_SUPER;
3488 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3489 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3492 case DWC3_DSTS_HIGHSPEED:
3493 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3494 dwc->gadget->ep0->maxpacket = 64;
3495 dwc->gadget->speed = USB_SPEED_HIGH;
3497 case DWC3_DSTS_FULLSPEED:
3498 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3499 dwc->gadget->ep0->maxpacket = 64;
3500 dwc->gadget->speed = USB_SPEED_FULL;
3504 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3506 /* Enable USB2 LPM Capability */
3508 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3509 !dwc->usb2_gadget_lpm_disable &&
3510 (speed != DWC3_DSTS_SUPERSPEED) &&
3511 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3512 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3513 reg |= DWC3_DCFG_LPM_CAP;
3514 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3516 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3517 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3519 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3520 (dwc->is_utmi_l1_suspend << 4));
3523 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3524 * DCFG.LPMCap is set, core responses with an ACK and the
3525 * BESL value in the LPM token is less than or equal to LPM
3528 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3529 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3531 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3532 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3534 dwc3_gadget_dctl_write_safe(dwc, reg);
3536 if (dwc->usb2_gadget_lpm_disable) {
3537 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3538 reg &= ~DWC3_DCFG_LPM_CAP;
3539 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3542 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3543 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3544 dwc3_gadget_dctl_write_safe(dwc, reg);
3548 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3550 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3555 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3557 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3562 * Configure PHY via GUSB3PIPECTLn if required.
3564 * Update GTXFIFOSIZn
3566 * In both cases reset values should be sufficient.
3570 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3573 * TODO take core out of low power mode when that's
3577 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3578 spin_unlock(&dwc->lock);
3579 dwc->gadget_driver->resume(dwc->gadget);
3580 spin_lock(&dwc->lock);
3584 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3585 unsigned int evtinfo)
3587 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3588 unsigned int pwropt;
3591 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3592 * Hibernation mode enabled which would show up when device detects
3593 * host-initiated U3 exit.
3595 * In that case, device will generate a Link State Change Interrupt
3596 * from U3 to RESUME which is only necessary if Hibernation is
3599 * There are no functional changes due to such spurious event and we
3600 * just need to ignore it.
3604 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3607 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3608 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3609 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3610 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3611 (next == DWC3_LINK_STATE_RESUME)) {
3617 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3618 * on the link partner, the USB session might do multiple entry/exit
3619 * of low power states before a transfer takes place.
3621 * Due to this problem, we might experience lower throughput. The
3622 * suggested workaround is to disable DCTL[12:9] bits if we're
3623 * transitioning from U1/U2 to U0 and enable those bits again
3624 * after a transfer completes and there are no pending transfers
3625 * on any of the enabled endpoints.
3627 * This is the first half of that workaround.
3631 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3632 * core send LGO_Ux entering U0
3634 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3635 if (next == DWC3_LINK_STATE_U0) {
3639 switch (dwc->link_state) {
3640 case DWC3_LINK_STATE_U1:
3641 case DWC3_LINK_STATE_U2:
3642 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3643 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3644 | DWC3_DCTL_ACCEPTU2ENA
3645 | DWC3_DCTL_INITU1ENA
3646 | DWC3_DCTL_ACCEPTU1ENA);
3649 dwc->u1u2 = reg & u1u2;
3653 dwc3_gadget_dctl_write_safe(dwc, reg);
3663 case DWC3_LINK_STATE_U1:
3664 if (dwc->speed == USB_SPEED_SUPER)
3665 dwc3_suspend_gadget(dwc);
3667 case DWC3_LINK_STATE_U2:
3668 case DWC3_LINK_STATE_U3:
3669 dwc3_suspend_gadget(dwc);
3671 case DWC3_LINK_STATE_RESUME:
3672 dwc3_resume_gadget(dwc);
3679 dwc->link_state = next;
3682 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3683 unsigned int evtinfo)
3685 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3687 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3688 dwc3_suspend_gadget(dwc);
3690 dwc->link_state = next;
3693 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3694 unsigned int evtinfo)
3696 unsigned int is_ss = evtinfo & BIT(4);
3699 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3700 * have a known issue which can cause USB CV TD.9.23 to fail
3703 * Because of this issue, core could generate bogus hibernation
3704 * events which SW needs to ignore.
3708 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3709 * Device Fallback from SuperSpeed
3711 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3714 /* enter hibernation here */
3717 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3718 const struct dwc3_event_devt *event)
3720 switch (event->type) {
3721 case DWC3_DEVICE_EVENT_DISCONNECT:
3722 dwc3_gadget_disconnect_interrupt(dwc);
3724 case DWC3_DEVICE_EVENT_RESET:
3725 dwc3_gadget_reset_interrupt(dwc);
3727 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3728 dwc3_gadget_conndone_interrupt(dwc);
3730 case DWC3_DEVICE_EVENT_WAKEUP:
3731 dwc3_gadget_wakeup_interrupt(dwc);
3733 case DWC3_DEVICE_EVENT_HIBER_REQ:
3734 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3735 "unexpected hibernation event\n"))
3738 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3740 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3741 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3743 case DWC3_DEVICE_EVENT_EOPF:
3744 /* It changed to be suspend event for version 2.30a and above */
3745 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3747 * Ignore suspend event until the gadget enters into
3748 * USB_STATE_CONFIGURED state.
3750 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
3751 dwc3_gadget_suspend_interrupt(dwc,
3755 case DWC3_DEVICE_EVENT_SOF:
3756 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3757 case DWC3_DEVICE_EVENT_CMD_CMPL:
3758 case DWC3_DEVICE_EVENT_OVERFLOW:
3761 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3765 static void dwc3_process_event_entry(struct dwc3 *dwc,
3766 const union dwc3_event *event)
3768 trace_dwc3_event(event->raw, dwc);
3770 if (!event->type.is_devspec)
3771 dwc3_endpoint_interrupt(dwc, &event->depevt);
3772 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3773 dwc3_gadget_interrupt(dwc, &event->devt);
3775 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3778 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3780 struct dwc3 *dwc = evt->dwc;
3781 irqreturn_t ret = IRQ_NONE;
3787 if (!(evt->flags & DWC3_EVENT_PENDING))
3791 union dwc3_event event;
3793 event.raw = *(u32 *) (evt->cache + evt->lpos);
3795 dwc3_process_event_entry(dwc, &event);
3798 * FIXME we wrap around correctly to the next entry as
3799 * almost all entries are 4 bytes in size. There is one
3800 * entry which has 12 bytes which is a regular entry
3801 * followed by 8 bytes data. ATM I don't know how
3802 * things are organized if we get next to the a
3803 * boundary so I worry about that once we try to handle
3806 evt->lpos = (evt->lpos + 4) % evt->length;
3811 evt->flags &= ~DWC3_EVENT_PENDING;
3814 /* Unmask interrupt */
3815 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3816 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3817 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3819 if (dwc->imod_interval) {
3820 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3821 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3827 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3829 struct dwc3_event_buffer *evt = _evt;
3830 struct dwc3 *dwc = evt->dwc;
3831 unsigned long flags;
3832 irqreturn_t ret = IRQ_NONE;
3834 spin_lock_irqsave(&dwc->lock, flags);
3835 ret = dwc3_process_event_buf(evt);
3836 spin_unlock_irqrestore(&dwc->lock, flags);
3841 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3843 struct dwc3 *dwc = evt->dwc;
3848 if (pm_runtime_suspended(dwc->dev)) {
3849 pm_runtime_get(dwc->dev);
3850 disable_irq_nosync(dwc->irq_gadget);
3851 dwc->pending_events = true;
3856 * With PCIe legacy interrupt, test shows that top-half irq handler can
3857 * be called again after HW interrupt deassertion. Check if bottom-half
3858 * irq event handler completes before caching new event to prevent
3861 if (evt->flags & DWC3_EVENT_PENDING)
3864 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3865 count &= DWC3_GEVNTCOUNT_MASK;
3870 evt->flags |= DWC3_EVENT_PENDING;
3872 /* Mask interrupt */
3873 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3874 reg |= DWC3_GEVNTSIZ_INTMASK;
3875 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3877 amount = min(count, evt->length - evt->lpos);
3878 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3881 memcpy(evt->cache, evt->buf, count - amount);
3883 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3885 return IRQ_WAKE_THREAD;
3888 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3890 struct dwc3_event_buffer *evt = _evt;
3892 return dwc3_check_event_buf(evt);
3895 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3897 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3900 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3904 if (irq == -EPROBE_DEFER)
3907 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3911 if (irq == -EPROBE_DEFER)
3914 irq = platform_get_irq(dwc3_pdev, 0);
3925 static void dwc_gadget_release(struct device *dev)
3927 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3933 * dwc3_gadget_init - initializes gadget related registers
3934 * @dwc: pointer to our controller context structure
3936 * Returns 0 on success otherwise negative errno.
3938 int dwc3_gadget_init(struct dwc3 *dwc)
3944 irq = dwc3_gadget_get_irq(dwc);
3950 dwc->irq_gadget = irq;
3952 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3953 sizeof(*dwc->ep0_trb) * 2,
3954 &dwc->ep0_trb_addr, GFP_KERNEL);
3955 if (!dwc->ep0_trb) {
3956 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3961 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3962 if (!dwc->setup_buf) {
3967 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3968 &dwc->bounce_addr, GFP_KERNEL);
3974 init_completion(&dwc->ep0_in_setup);
3975 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
3982 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
3983 dev = &dwc->gadget->dev;
3984 dev->platform_data = dwc;
3985 dwc->gadget->ops = &dwc3_gadget_ops;
3986 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3987 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3988 dwc->gadget->sg_supported = true;
3989 dwc->gadget->name = "dwc3-gadget";
3990 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
3993 * FIXME We might be setting max_speed to <SUPER, however versions
3994 * <2.20a of dwc3 have an issue with metastability (documented
3995 * elsewhere in this driver) which tells us we can't set max speed to
3996 * anything lower than SUPER.
3998 * Because gadget.max_speed is only used by composite.c and function
3999 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4000 * to happen so we avoid sending SuperSpeed Capability descriptor
4001 * together with our BOS descriptor as that could confuse host into
4002 * thinking we can handle super speed.
4004 * Note that, in fact, we won't even support GetBOS requests when speed
4005 * is less than super speed because we don't have means, yet, to tell
4006 * composite.c that we are USB 2.0 + LPM ECN.
4008 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4009 !dwc->dis_metastability_quirk)
4010 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4013 dwc->gadget->max_speed = dwc->maximum_speed;
4014 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4017 * REVISIT: Here we should clear all pending IRQs to be
4018 * sure we're starting from a well known location.
4021 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4025 ret = usb_add_gadget(dwc->gadget);
4027 dev_err(dwc->dev, "failed to add gadget\n");
4031 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4032 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4034 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4039 dwc3_gadget_free_endpoints(dwc);
4041 usb_put_gadget(dwc->gadget);
4043 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4047 kfree(dwc->setup_buf);
4050 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4051 dwc->ep0_trb, dwc->ep0_trb_addr);
4057 /* -------------------------------------------------------------------------- */
4059 void dwc3_gadget_exit(struct dwc3 *dwc)
4061 usb_del_gadget_udc(dwc->gadget);
4062 dwc3_gadget_free_endpoints(dwc);
4063 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4065 kfree(dwc->setup_buf);
4066 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4067 dwc->ep0_trb, dwc->ep0_trb_addr);
4070 int dwc3_gadget_suspend(struct dwc3 *dwc)
4072 if (!dwc->gadget_driver)
4075 dwc3_gadget_run_stop(dwc, false, false);
4076 dwc3_disconnect_gadget(dwc);
4077 __dwc3_gadget_stop(dwc);
4082 int dwc3_gadget_resume(struct dwc3 *dwc)
4086 if (!dwc->gadget_driver)
4089 ret = __dwc3_gadget_start(dwc);
4093 ret = dwc3_gadget_run_stop(dwc, true, false);
4100 __dwc3_gadget_stop(dwc);
4106 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4108 if (dwc->pending_events) {
4109 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4110 dwc->pending_events = false;
4111 enable_irq(dwc->irq_gadget);