1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
278 u32 saved_config = 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
313 link_state = dwc3_gadget_get_link_state(dwc);
314 if (link_state == DWC3_LINK_STATE_U1 ||
315 link_state == DWC3_LINK_STATE_U2 ||
316 link_state == DWC3_LINK_STATE_U3) {
317 ret = __dwc3_gadget_wakeup(dwc);
318 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
323 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
324 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
342 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
343 !usb_endpoint_xfer_isoc(desc))
344 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
346 cmd |= DWC3_DEPCMD_CMDACT;
348 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
350 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
351 if (!(reg & DWC3_DEPCMD_CMDACT)) {
352 cmd_status = DWC3_DEPCMD_STATUS(reg);
354 switch (cmd_status) {
358 case DEPEVT_TRANSFER_NO_RESOURCE:
359 dev_WARN(dwc->dev, "No resource for %s\n",
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
387 cmd_status = -ETIMEDOUT;
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
392 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
394 dep->flags |= DWC3_EP_TRANSFER_STARTED;
396 if (ret != -ETIMEDOUT)
397 dwc3_gadget_ep_get_transfer_index(dep);
401 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
411 struct dwc3 *dwc = dep->dwc;
412 struct dwc3_gadget_ep_cmd_params params;
413 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
416 * As of core revision 2.60a the recommended programming model
417 * is to set the ClearPendIN bit when issuing a Clear Stall EP
418 * command for IN endpoints. This is to prevent an issue where
419 * some (non-compliant) hosts may not send ACK TPs for pending
420 * IN transfers due to a mishandled error condition. Synopsys
423 if (dep->direction &&
424 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
425 (dwc->gadget->speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
428 memset(¶ms, 0, sizeof(params));
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
438 return dep->trb_pool_dma + offset;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
443 struct dwc3 *dwc = dep->dwc;
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
475 memset(¶ms, 0x00, sizeof(params));
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
541 ret = dwc3_gadget_set_xfer_resource(dep);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
559 memset(¶ms, 0x00, sizeof(params));
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
568 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
571 params.param0 |= action;
572 if (action == DWC3_DEPCFG_ACTION_RESTORE)
573 params.param2 |= dep->saved_state;
575 if (usb_endpoint_xfer_control(desc))
576 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
578 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
579 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
581 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
582 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
583 | DWC3_DEPCFG_XFER_COMPLETE_EN
584 | DWC3_DEPCFG_STREAM_EVENT_EN;
585 dep->stream_capable = true;
588 if (!usb_endpoint_xfer_control(desc))
589 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
592 * We are doing 1:1 mapping for endpoints, meaning
593 * Physical Endpoints 2 maps to Logical Endpoint 2 and
594 * so on. We consider the direction bit as part of the physical
595 * endpoint number. So USB endpoint 0x81 is 0x03.
597 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
600 * We must use the lower 16 TX FIFOs even though
604 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
606 if (desc->bInterval) {
610 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
612 * NOTE: The programming guide incorrectly stated bInterval_m1
613 * must be set to 0 when operating in fullspeed. Internally the
614 * controller does not have this limitation. See DWC_usb3x
615 * programming guide section 3.2.2.1.
617 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
619 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
620 dwc->gadget->speed == USB_SPEED_FULL)
621 dep->interval = desc->bInterval;
623 dep->interval = 1 << (desc->bInterval - 1);
625 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
628 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
631 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
635 * __dwc3_gadget_ep_enable - initializes a hw endpoint
636 * @dep: endpoint to be initialized
637 * @action: one of INIT, MODIFY or RESTORE
639 * Caller should take care of locking. Execute all necessary commands to
640 * initialize a HW endpoint so it can be used by a gadget driver.
642 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
644 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
645 struct dwc3 *dwc = dep->dwc;
650 if (!(dep->flags & DWC3_EP_ENABLED)) {
651 ret = dwc3_gadget_start_config(dep);
656 ret = dwc3_gadget_set_ep_config(dep, action);
660 if (!(dep->flags & DWC3_EP_ENABLED)) {
661 struct dwc3_trb *trb_st_hw;
662 struct dwc3_trb *trb_link;
664 dep->type = usb_endpoint_type(desc);
665 dep->flags |= DWC3_EP_ENABLED;
667 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
668 reg |= DWC3_DALEPENA_EP(dep->number);
669 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
671 if (usb_endpoint_xfer_control(desc))
674 /* Initialize the TRB ring */
675 dep->trb_dequeue = 0;
676 dep->trb_enqueue = 0;
677 memset(dep->trb_pool, 0,
678 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
680 /* Link TRB. The HWO bit is never reset */
681 trb_st_hw = &dep->trb_pool[0];
683 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
684 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
685 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
686 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
687 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
691 * Issue StartTransfer here with no-op TRB so we can always rely on No
692 * Response Update Transfer command.
694 if (usb_endpoint_xfer_bulk(desc) ||
695 usb_endpoint_xfer_int(desc)) {
696 struct dwc3_gadget_ep_cmd_params params;
697 struct dwc3_trb *trb;
701 memset(¶ms, 0, sizeof(params));
702 trb = &dep->trb_pool[0];
703 trb_dma = dwc3_trb_dma_offset(dep, trb);
705 params.param0 = upper_32_bits(trb_dma);
706 params.param1 = lower_32_bits(trb_dma);
708 cmd = DWC3_DEPCMD_STARTTRANSFER;
710 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
714 if (dep->stream_capable) {
716 * For streams, at start, there maybe a race where the
717 * host primes the endpoint before the function driver
718 * queues a request to initiate a stream. In that case,
719 * the controller will not see the prime to generate the
720 * ERDY and start stream. To workaround this, issue a
721 * no-op TRB as normal, but end it immediately. As a
722 * result, when the function driver queues the request,
723 * the next START_TRANSFER command will cause the
724 * controller to generate an ERDY to initiate the
727 dwc3_stop_active_transfer(dep, true, true);
730 * All stream eps will reinitiate stream on NoStream
731 * rejection until we can determine that the host can
732 * prime after the first transfer.
734 * However, if the controller is capable of
735 * TXF_FLUSH_BYPASS, then IN direction endpoints will
736 * automatically restart the stream without the driver
739 if (!dep->direction ||
740 !(dwc->hwparams.hwparams9 &
741 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
742 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
747 trace_dwc3_gadget_ep_enable(dep);
752 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
754 struct dwc3_request *req;
756 dwc3_stop_active_transfer(dep, true, false);
758 /* - giveback all requests to gadget driver */
759 while (!list_empty(&dep->started_list)) {
760 req = next_request(&dep->started_list);
762 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
765 while (!list_empty(&dep->pending_list)) {
766 req = next_request(&dep->pending_list);
768 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
771 while (!list_empty(&dep->cancelled_list)) {
772 req = next_request(&dep->cancelled_list);
774 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
779 * __dwc3_gadget_ep_disable - disables a hw endpoint
780 * @dep: the endpoint to disable
782 * This function undoes what __dwc3_gadget_ep_enable did and also removes
783 * requests which are currently being processed by the hardware and those which
784 * are not yet scheduled.
786 * Caller should take care of locking.
788 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
790 struct dwc3 *dwc = dep->dwc;
793 trace_dwc3_gadget_ep_disable(dep);
795 /* make sure HW endpoint isn't stalled */
796 if (dep->flags & DWC3_EP_STALL)
797 __dwc3_gadget_ep_set_halt(dep, 0, false);
799 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
800 reg &= ~DWC3_DALEPENA_EP(dep->number);
801 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
803 /* Clear out the ep descriptors for non-ep0 */
804 if (dep->number > 1) {
805 dep->endpoint.comp_desc = NULL;
806 dep->endpoint.desc = NULL;
809 dwc3_remove_requests(dwc, dep);
811 dep->stream_capable = false;
818 /* -------------------------------------------------------------------------- */
820 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
821 const struct usb_endpoint_descriptor *desc)
826 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
831 /* -------------------------------------------------------------------------- */
833 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
834 const struct usb_endpoint_descriptor *desc)
841 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
842 pr_debug("dwc3: invalid parameters\n");
846 if (!desc->wMaxPacketSize) {
847 pr_debug("dwc3: missing wMaxPacketSize\n");
851 dep = to_dwc3_ep(ep);
854 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
855 "%s is already enabled\n",
859 spin_lock_irqsave(&dwc->lock, flags);
860 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
861 spin_unlock_irqrestore(&dwc->lock, flags);
866 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
874 pr_debug("dwc3: invalid parameters\n");
878 dep = to_dwc3_ep(ep);
881 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
882 "%s is already disabled\n",
886 spin_lock_irqsave(&dwc->lock, flags);
887 ret = __dwc3_gadget_ep_disable(dep);
888 spin_unlock_irqrestore(&dwc->lock, flags);
893 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
896 struct dwc3_request *req;
897 struct dwc3_ep *dep = to_dwc3_ep(ep);
899 req = kzalloc(sizeof(*req), gfp_flags);
903 req->direction = dep->direction;
904 req->epnum = dep->number;
906 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
908 trace_dwc3_alloc_request(req);
910 return &req->request;
913 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
914 struct usb_request *request)
916 struct dwc3_request *req = to_dwc3_request(request);
918 trace_dwc3_free_request(req);
923 * dwc3_ep_prev_trb - returns the previous TRB in the ring
924 * @dep: The endpoint with the TRB ring
925 * @index: The index of the current TRB in the ring
927 * Returns the TRB prior to the one pointed to by the index. If the
928 * index is 0, we will wrap backwards, skip the link TRB, and return
929 * the one just before that.
931 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
936 tmp = DWC3_TRB_NUM - 1;
938 return &dep->trb_pool[tmp - 1];
941 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
943 struct dwc3_trb *tmp;
947 * If enqueue & dequeue are equal than it is either full or empty.
949 * One way to know for sure is if the TRB right before us has HWO bit
950 * set or not. If it has, then we're definitely full and can't fit any
951 * more transfers in our ring.
953 if (dep->trb_enqueue == dep->trb_dequeue) {
954 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
955 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
958 return DWC3_TRB_NUM - 1;
961 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
962 trbs_left &= (DWC3_TRB_NUM - 1);
964 if (dep->trb_dequeue < dep->trb_enqueue)
970 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
971 dma_addr_t dma, unsigned int length, unsigned int chain,
972 unsigned int node, unsigned int stream_id,
973 unsigned int short_not_ok, unsigned int no_interrupt,
974 unsigned int is_last, bool must_interrupt)
976 struct dwc3 *dwc = dep->dwc;
977 struct usb_gadget *gadget = dwc->gadget;
978 enum usb_device_speed speed = gadget->speed;
980 trb->size = DWC3_TRB_SIZE_LENGTH(length);
981 trb->bpl = lower_32_bits(dma);
982 trb->bph = upper_32_bits(dma);
984 switch (usb_endpoint_type(dep->endpoint.desc)) {
985 case USB_ENDPOINT_XFER_CONTROL:
986 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
989 case USB_ENDPOINT_XFER_ISOC:
991 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
994 * USB Specification 2.0 Section 5.9.2 states that: "If
995 * there is only a single transaction in the microframe,
996 * only a DATA0 data packet PID is used. If there are
997 * two transactions per microframe, DATA1 is used for
998 * the first transaction data packet and DATA0 is used
999 * for the second transaction data packet. If there are
1000 * three transactions per microframe, DATA2 is used for
1001 * the first transaction data packet, DATA1 is used for
1002 * the second, and DATA0 is used for the third."
1004 * IOW, we should satisfy the following cases:
1006 * 1) length <= maxpacket
1009 * 2) maxpacket < length <= (2 * maxpacket)
1012 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1013 * - DATA2, DATA1, DATA0
1015 if (speed == USB_SPEED_HIGH) {
1016 struct usb_ep *ep = &dep->endpoint;
1017 unsigned int mult = 2;
1018 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1020 if (length <= (2 * maxp))
1026 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1029 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1032 /* always enable Interrupt on Missed ISOC */
1033 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1036 case USB_ENDPOINT_XFER_BULK:
1037 case USB_ENDPOINT_XFER_INT:
1038 trb->ctrl = DWC3_TRBCTL_NORMAL;
1042 * This is only possible with faulty memory because we
1043 * checked it already :)
1045 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1046 usb_endpoint_type(dep->endpoint.desc));
1050 * Enable Continue on Short Packet
1051 * when endpoint is not a stream capable
1053 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1054 if (!dep->stream_capable)
1055 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1058 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1061 if ((!no_interrupt && !chain) || must_interrupt)
1062 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1065 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1066 else if (dep->stream_capable && is_last)
1067 trb->ctrl |= DWC3_TRB_CTRL_LST;
1069 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1070 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1072 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1074 dwc3_ep_inc_enq(dep);
1076 trace_dwc3_prepare_trb(dep, trb);
1080 * dwc3_prepare_one_trb - setup one TRB from one request
1081 * @dep: endpoint for which this request is prepared
1082 * @req: dwc3_request pointer
1083 * @trb_length: buffer size of the TRB
1084 * @chain: should this TRB be chained to the next?
1085 * @node: only for isochronous endpoints. First TRB needs different type.
1086 * @use_bounce_buffer: set to use bounce buffer
1087 * @must_interrupt: set to interrupt on TRB completion
1089 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1090 struct dwc3_request *req, unsigned int trb_length,
1091 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1092 bool must_interrupt)
1094 struct dwc3_trb *trb;
1096 unsigned int stream_id = req->request.stream_id;
1097 unsigned int short_not_ok = req->request.short_not_ok;
1098 unsigned int no_interrupt = req->request.no_interrupt;
1099 unsigned int is_last = req->request.is_last;
1101 if (use_bounce_buffer)
1102 dma = dep->dwc->bounce_addr;
1103 else if (req->request.num_sgs > 0)
1104 dma = sg_dma_address(req->start_sg);
1106 dma = req->request.dma;
1108 trb = &dep->trb_pool[dep->trb_enqueue];
1111 dwc3_gadget_move_started_request(req);
1113 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1118 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1119 stream_id, short_not_ok, no_interrupt, is_last,
1123 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1125 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1126 unsigned int rem = req->request.length % maxp;
1128 if ((req->request.length && req->request.zero && !rem &&
1129 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1130 (!req->direction && rem))
1137 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1138 * @dep: The endpoint that the request belongs to
1139 * @req: The request to prepare
1140 * @entry_length: The last SG entry size
1141 * @node: Indicates whether this is not the first entry (for isoc only)
1143 * Return the number of TRBs prepared.
1145 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1146 struct dwc3_request *req, unsigned int entry_length,
1149 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1150 unsigned int rem = req->request.length % maxp;
1151 unsigned int num_trbs = 1;
1153 if (dwc3_needs_extra_trb(dep, req))
1156 if (dwc3_calc_trbs_left(dep) < num_trbs)
1159 req->needs_extra_trb = num_trbs > 1;
1161 /* Prepare a normal TRB */
1162 if (req->direction || req->request.length)
1163 dwc3_prepare_one_trb(dep, req, entry_length,
1164 req->needs_extra_trb, node, false, false);
1166 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1167 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1168 dwc3_prepare_one_trb(dep, req,
1169 req->direction ? 0 : maxp - rem,
1170 false, 1, true, false);
1175 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1176 struct dwc3_request *req)
1178 struct scatterlist *sg = req->start_sg;
1179 struct scatterlist *s;
1181 unsigned int length = req->request.length;
1182 unsigned int remaining = req->request.num_mapped_sgs
1183 - req->num_queued_sgs;
1184 unsigned int num_trbs = req->num_trbs;
1185 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1188 * If we resume preparing the request, then get the remaining length of
1189 * the request and resume where we left off.
1191 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1192 length -= sg_dma_len(s);
1194 for_each_sg(sg, s, remaining, i) {
1195 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1196 unsigned int trb_length;
1197 bool must_interrupt = false;
1198 bool last_sg = false;
1200 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1202 length -= trb_length;
1205 * IOMMU driver is coalescing the list of sgs which shares a
1206 * page boundary into one and giving it to USB driver. With
1207 * this the number of sgs mapped is not equal to the number of
1208 * sgs passed. So mark the chain bit to false if it isthe last
1211 if ((i == remaining - 1) || !length)
1218 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1222 * Look ahead to check if we have enough TRBs for the
1223 * next SG entry. If not, set interrupt on this TRB to
1224 * resume preparing the next SG entry when more TRBs are
1227 if (num_trbs_left == 1 || (needs_extra_trb &&
1228 num_trbs_left <= 2 &&
1229 sg_dma_len(sg_next(s)) >= length))
1230 must_interrupt = true;
1232 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1237 * There can be a situation where all sgs in sglist are not
1238 * queued because of insufficient trb number. To handle this
1239 * case, update start_sg to next sg to be queued, so that
1240 * we have free trbs we can continue queuing from where we
1241 * previously stopped
1244 req->start_sg = sg_next(s);
1246 req->num_queued_sgs++;
1247 req->num_pending_sgs--;
1250 * The number of pending SG entries may not correspond to the
1251 * number of mapped SG entries. If all the data are queued, then
1252 * don't include unused SG entries.
1255 req->num_pending_sgs = 0;
1263 return req->num_trbs - num_trbs;
1266 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1267 struct dwc3_request *req)
1269 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1273 * dwc3_prepare_trbs - setup TRBs from requests
1274 * @dep: endpoint for which requests are being prepared
1276 * The function goes through the requests list and sets up TRBs for the
1277 * transfers. The function returns once there are no more TRBs available or
1278 * it runs out of requests.
1280 * Returns the number of TRBs prepared or negative errno.
1282 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1284 struct dwc3_request *req, *n;
1287 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1290 * We can get in a situation where there's a request in the started list
1291 * but there weren't enough TRBs to fully kick it in the first time
1292 * around, so it has been waiting for more TRBs to be freed up.
1294 * In that case, we should check if we have a request with pending_sgs
1295 * in the started list and prepare TRBs for that request first,
1296 * otherwise we will prepare TRBs completely out of order and that will
1299 list_for_each_entry(req, &dep->started_list, list) {
1300 if (req->num_pending_sgs > 0) {
1301 ret = dwc3_prepare_trbs_sg(dep, req);
1302 if (!ret || req->num_pending_sgs)
1306 if (!dwc3_calc_trbs_left(dep))
1310 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1311 * burst capability may try to read and use TRBs beyond the
1312 * active transfer instead of stopping.
1314 if (dep->stream_capable && req->request.is_last)
1318 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1319 struct dwc3 *dwc = dep->dwc;
1321 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1326 req->sg = req->request.sg;
1327 req->start_sg = req->sg;
1328 req->num_queued_sgs = 0;
1329 req->num_pending_sgs = req->request.num_mapped_sgs;
1331 if (req->num_pending_sgs > 0) {
1332 ret = dwc3_prepare_trbs_sg(dep, req);
1333 if (req->num_pending_sgs)
1336 ret = dwc3_prepare_trbs_linear(dep, req);
1339 if (!ret || !dwc3_calc_trbs_left(dep))
1343 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1344 * burst capability may try to read and use TRBs beyond the
1345 * active transfer instead of stopping.
1347 if (dep->stream_capable && req->request.is_last)
1354 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1356 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1358 struct dwc3_gadget_ep_cmd_params params;
1359 struct dwc3_request *req;
1365 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1366 * This happens when we need to stop and restart a transfer such as in
1367 * the case of reinitiating a stream or retrying an isoc transfer.
1369 ret = dwc3_prepare_trbs(dep);
1373 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1376 * If there's no new TRB prepared and we don't need to restart a
1377 * transfer, there's no need to update the transfer.
1379 if (!ret && !starting)
1382 req = next_request(&dep->started_list);
1384 dep->flags |= DWC3_EP_PENDING_REQUEST;
1388 memset(¶ms, 0, sizeof(params));
1391 params.param0 = upper_32_bits(req->trb_dma);
1392 params.param1 = lower_32_bits(req->trb_dma);
1393 cmd = DWC3_DEPCMD_STARTTRANSFER;
1395 if (dep->stream_capable)
1396 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1398 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1399 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1401 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1402 DWC3_DEPCMD_PARAM(dep->resource_index);
1405 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1407 struct dwc3_request *tmp;
1412 dwc3_stop_active_transfer(dep, true, true);
1414 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1415 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1417 /* If ep isn't started, then there's no end transfer pending */
1418 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1419 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1424 if (dep->stream_capable && req->request.is_last)
1425 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1430 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1434 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1435 return DWC3_DSTS_SOFFN(reg);
1439 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1440 * @dep: isoc endpoint
1442 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1443 * microframe number reported by the XferNotReady event for the future frame
1444 * number to start the isoc transfer.
1446 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1447 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1448 * XferNotReady event are invalid. The driver uses this number to schedule the
1449 * isochronous transfer and passes it to the START TRANSFER command. Because
1450 * this number is invalid, the command may fail. If BIT[15:14] matches the
1451 * internal 16-bit microframe, the START TRANSFER command will pass and the
1452 * transfer will start at the scheduled time, if it is off by 1, the command
1453 * will still pass, but the transfer will start 2 seconds in the future. For all
1454 * other conditions, the START TRANSFER command will fail with bus-expiry.
1456 * In order to workaround this issue, we can test for the correct combination of
1457 * BIT[15:14] by sending START TRANSFER commands with different values of
1458 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1459 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1460 * As the result, within the 4 possible combinations for BIT[15:14], there will
1461 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1462 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1463 * value is the correct combination.
1465 * Since there are only 4 outcomes and the results are ordered, we can simply
1466 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1467 * deduce the smaller successful combination.
1469 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1470 * of BIT[15:14]. The correct combination is as follow:
1472 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1473 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1474 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1475 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1477 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1480 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1486 while (dep->combo_num < 2) {
1487 struct dwc3_gadget_ep_cmd_params params;
1488 u32 test_frame_number;
1492 * Check if we can start isoc transfer on the next interval or
1493 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1495 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1496 test_frame_number |= dep->combo_num << 14;
1497 test_frame_number += max_t(u32, 4, dep->interval);
1499 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1500 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1502 cmd = DWC3_DEPCMD_STARTTRANSFER;
1503 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1504 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1506 /* Redo if some other failure beside bus-expiry is received */
1507 if (cmd_status && cmd_status != -EAGAIN) {
1508 dep->start_cmd_status = 0;
1513 /* Store the first test status */
1514 if (dep->combo_num == 0)
1515 dep->start_cmd_status = cmd_status;
1520 * End the transfer if the START_TRANSFER command is successful
1521 * to wait for the next XferNotReady to test the command again
1523 if (cmd_status == 0) {
1524 dwc3_stop_active_transfer(dep, true, true);
1529 /* test0 and test1 are both completed at this point */
1530 test0 = (dep->start_cmd_status == 0);
1531 test1 = (cmd_status == 0);
1533 if (!test0 && test1)
1535 else if (!test0 && !test1)
1537 else if (test0 && !test1)
1539 else if (test0 && test1)
1542 dep->frame_number &= DWC3_FRNUMBER_MASK;
1543 dep->frame_number |= dep->combo_num << 14;
1544 dep->frame_number += max_t(u32, 4, dep->interval);
1546 /* Reinitialize test variables */
1547 dep->start_cmd_status = 0;
1550 return __dwc3_gadget_kick_transfer(dep);
1553 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1555 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1556 struct dwc3 *dwc = dep->dwc;
1560 if (list_empty(&dep->pending_list) &&
1561 list_empty(&dep->started_list)) {
1562 dep->flags |= DWC3_EP_PENDING_REQUEST;
1566 if (!dwc->dis_start_transfer_quirk &&
1567 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1568 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1569 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1570 return dwc3_gadget_start_isoc_quirk(dep);
1573 if (desc->bInterval <= 14 &&
1574 dwc->gadget->speed >= USB_SPEED_HIGH) {
1575 u32 frame = __dwc3_gadget_get_frame(dwc);
1576 bool rollover = frame <
1577 (dep->frame_number & DWC3_FRNUMBER_MASK);
1580 * frame_number is set from XferNotReady and may be already
1581 * out of date. DSTS only provides the lower 14 bit of the
1582 * current frame number. So add the upper two bits of
1583 * frame_number and handle a possible rollover.
1584 * This will provide the correct frame_number unless more than
1585 * rollover has happened since XferNotReady.
1588 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1591 dep->frame_number += BIT(14);
1594 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1595 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1597 ret = __dwc3_gadget_kick_transfer(dep);
1603 * After a number of unsuccessful start attempts due to bus-expiry
1604 * status, issue END_TRANSFER command and retry on the next XferNotReady
1607 if (ret == -EAGAIN) {
1608 struct dwc3_gadget_ep_cmd_params params;
1611 cmd = DWC3_DEPCMD_ENDTRANSFER |
1612 DWC3_DEPCMD_CMDIOC |
1613 DWC3_DEPCMD_PARAM(dep->resource_index);
1615 dep->resource_index = 0;
1616 memset(¶ms, 0, sizeof(params));
1618 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1620 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1626 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1628 struct dwc3 *dwc = dep->dwc;
1630 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1631 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1636 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1637 &req->request, req->dep->name))
1640 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1641 "%s: request %pK already in flight\n",
1642 dep->name, &req->request))
1645 pm_runtime_get(dwc->dev);
1647 req->request.actual = 0;
1648 req->request.status = -EINPROGRESS;
1650 trace_dwc3_ep_queue(req);
1652 list_add_tail(&req->list, &dep->pending_list);
1653 req->status = DWC3_REQUEST_STATUS_QUEUED;
1655 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1659 * Start the transfer only after the END_TRANSFER is completed
1660 * and endpoint STALL is cleared.
1662 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1663 (dep->flags & DWC3_EP_WEDGE) ||
1664 (dep->flags & DWC3_EP_STALL)) {
1665 dep->flags |= DWC3_EP_DELAY_START;
1670 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1671 * wait for a XferNotReady event so we will know what's the current
1672 * (micro-)frame number.
1674 * Without this trick, we are very, very likely gonna get Bus Expiry
1675 * errors which will force us issue EndTransfer command.
1677 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1678 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1679 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1682 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1683 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1684 return __dwc3_gadget_start_isoc(dep);
1688 __dwc3_gadget_kick_transfer(dep);
1693 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1696 struct dwc3_request *req = to_dwc3_request(request);
1697 struct dwc3_ep *dep = to_dwc3_ep(ep);
1698 struct dwc3 *dwc = dep->dwc;
1700 unsigned long flags;
1704 spin_lock_irqsave(&dwc->lock, flags);
1705 ret = __dwc3_gadget_ep_queue(dep, req);
1706 spin_unlock_irqrestore(&dwc->lock, flags);
1711 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1715 /* If req->trb is not set, then the request has not started */
1720 * If request was already started, this means we had to
1721 * stop the transfer. With that we also need to ignore
1722 * all TRBs used by the request, however TRBs can only
1723 * be modified after completion of END_TRANSFER
1724 * command. So what we do here is that we wait for
1725 * END_TRANSFER completion and only after that, we jump
1726 * over TRBs by clearing HWO and incrementing dequeue
1729 for (i = 0; i < req->num_trbs; i++) {
1730 struct dwc3_trb *trb;
1732 trb = &dep->trb_pool[dep->trb_dequeue];
1733 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1734 dwc3_ep_inc_deq(dep);
1740 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1742 struct dwc3_request *req;
1743 struct dwc3_request *tmp;
1744 struct list_head local;
1745 struct dwc3 *dwc = dep->dwc;
1748 list_replace_init(&dep->cancelled_list, &local);
1750 list_for_each_entry_safe(req, tmp, &local, list) {
1751 dwc3_gadget_ep_skip_trbs(dep, req);
1752 switch (req->status) {
1753 case DWC3_REQUEST_STATUS_DISCONNECTED:
1754 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1756 case DWC3_REQUEST_STATUS_DEQUEUED:
1757 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1759 case DWC3_REQUEST_STATUS_STALLED:
1760 dwc3_gadget_giveback(dep, req, -EPIPE);
1763 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1764 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1769 if (!list_empty(&dep->cancelled_list))
1773 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1774 struct usb_request *request)
1776 struct dwc3_request *req = to_dwc3_request(request);
1777 struct dwc3_request *r = NULL;
1779 struct dwc3_ep *dep = to_dwc3_ep(ep);
1780 struct dwc3 *dwc = dep->dwc;
1782 unsigned long flags;
1785 trace_dwc3_ep_dequeue(req);
1787 spin_lock_irqsave(&dwc->lock, flags);
1789 list_for_each_entry(r, &dep->cancelled_list, list) {
1794 list_for_each_entry(r, &dep->pending_list, list) {
1796 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1801 list_for_each_entry(r, &dep->started_list, list) {
1803 struct dwc3_request *t;
1805 /* wait until it is processed */
1806 dwc3_stop_active_transfer(dep, true, true);
1809 * Remove any started request if the transfer is
1812 list_for_each_entry_safe(r, t, &dep->started_list, list)
1813 dwc3_gadget_move_cancelled_request(r,
1814 DWC3_REQUEST_STATUS_DEQUEUED);
1816 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1822 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1826 spin_unlock_irqrestore(&dwc->lock, flags);
1831 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1833 struct dwc3_gadget_ep_cmd_params params;
1834 struct dwc3 *dwc = dep->dwc;
1835 struct dwc3_request *req;
1836 struct dwc3_request *tmp;
1839 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1840 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1844 memset(¶ms, 0x00, sizeof(params));
1847 struct dwc3_trb *trb;
1849 unsigned int transfer_in_flight;
1850 unsigned int started;
1852 if (dep->number > 1)
1853 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1855 trb = &dwc->ep0_trb[dep->trb_enqueue];
1857 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1858 started = !list_empty(&dep->started_list);
1860 if (!protocol && ((dep->direction && transfer_in_flight) ||
1861 (!dep->direction && started))) {
1865 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1868 dev_err(dwc->dev, "failed to set STALL on %s\n",
1871 dep->flags |= DWC3_EP_STALL;
1874 * Don't issue CLEAR_STALL command to control endpoints. The
1875 * controller automatically clears the STALL when it receives
1878 if (dep->number <= 1) {
1879 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1883 dwc3_stop_active_transfer(dep, true, true);
1885 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1886 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
1888 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1889 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1893 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1895 ret = dwc3_send_clear_stall_ep_cmd(dep);
1897 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1902 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1904 if ((dep->flags & DWC3_EP_DELAY_START) &&
1905 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1906 __dwc3_gadget_kick_transfer(dep);
1908 dep->flags &= ~DWC3_EP_DELAY_START;
1914 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1916 struct dwc3_ep *dep = to_dwc3_ep(ep);
1917 struct dwc3 *dwc = dep->dwc;
1919 unsigned long flags;
1923 spin_lock_irqsave(&dwc->lock, flags);
1924 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1925 spin_unlock_irqrestore(&dwc->lock, flags);
1930 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1932 struct dwc3_ep *dep = to_dwc3_ep(ep);
1933 struct dwc3 *dwc = dep->dwc;
1934 unsigned long flags;
1937 spin_lock_irqsave(&dwc->lock, flags);
1938 dep->flags |= DWC3_EP_WEDGE;
1940 if (dep->number == 0 || dep->number == 1)
1941 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1943 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1944 spin_unlock_irqrestore(&dwc->lock, flags);
1949 /* -------------------------------------------------------------------------- */
1951 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1952 .bLength = USB_DT_ENDPOINT_SIZE,
1953 .bDescriptorType = USB_DT_ENDPOINT,
1954 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1957 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1958 .enable = dwc3_gadget_ep0_enable,
1959 .disable = dwc3_gadget_ep0_disable,
1960 .alloc_request = dwc3_gadget_ep_alloc_request,
1961 .free_request = dwc3_gadget_ep_free_request,
1962 .queue = dwc3_gadget_ep0_queue,
1963 .dequeue = dwc3_gadget_ep_dequeue,
1964 .set_halt = dwc3_gadget_ep0_set_halt,
1965 .set_wedge = dwc3_gadget_ep_set_wedge,
1968 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1969 .enable = dwc3_gadget_ep_enable,
1970 .disable = dwc3_gadget_ep_disable,
1971 .alloc_request = dwc3_gadget_ep_alloc_request,
1972 .free_request = dwc3_gadget_ep_free_request,
1973 .queue = dwc3_gadget_ep_queue,
1974 .dequeue = dwc3_gadget_ep_dequeue,
1975 .set_halt = dwc3_gadget_ep_set_halt,
1976 .set_wedge = dwc3_gadget_ep_set_wedge,
1979 /* -------------------------------------------------------------------------- */
1981 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1983 struct dwc3 *dwc = gadget_to_dwc(g);
1985 return __dwc3_gadget_get_frame(dwc);
1988 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1998 * According to the Databook Remote wakeup request should
1999 * be issued only when the device is in early suspend state.
2001 * We can check that via USB Link State bits in DSTS register.
2003 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2005 link_state = DWC3_DSTS_USBLNKST(reg);
2007 switch (link_state) {
2008 case DWC3_LINK_STATE_RESET:
2009 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2010 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2011 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2012 case DWC3_LINK_STATE_U1:
2013 case DWC3_LINK_STATE_RESUME:
2019 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2021 dev_err(dwc->dev, "failed to put link in Recovery\n");
2025 /* Recent versions do this automatically */
2026 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2027 /* write zeroes to Link Change Request */
2028 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2029 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2030 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2033 /* poll until Link State changes to ON */
2037 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2039 /* in HS, means ON */
2040 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2044 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2045 dev_err(dwc->dev, "failed to send remote wakeup\n");
2052 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2054 struct dwc3 *dwc = gadget_to_dwc(g);
2055 unsigned long flags;
2058 spin_lock_irqsave(&dwc->lock, flags);
2059 ret = __dwc3_gadget_wakeup(dwc);
2060 spin_unlock_irqrestore(&dwc->lock, flags);
2065 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2068 struct dwc3 *dwc = gadget_to_dwc(g);
2069 unsigned long flags;
2071 spin_lock_irqsave(&dwc->lock, flags);
2072 g->is_selfpowered = !!is_selfpowered;
2073 spin_unlock_irqrestore(&dwc->lock, flags);
2078 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2082 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2083 struct dwc3_ep *dep;
2085 dep = dwc->eps[epnum];
2089 dwc3_remove_requests(dwc, dep);
2093 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2095 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2098 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2099 ssp_rate = dwc->max_ssp_rate;
2101 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2102 reg &= ~DWC3_DCFG_SPEED_MASK;
2103 reg &= ~DWC3_DCFG_NUMLANES(~0);
2105 if (ssp_rate == USB_SSP_GEN_1x2)
2106 reg |= DWC3_DCFG_SUPERSPEED;
2107 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2108 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2110 if (ssp_rate != USB_SSP_GEN_2x1 &&
2111 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2112 reg |= DWC3_DCFG_NUMLANES(1);
2114 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2117 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2119 enum usb_device_speed speed;
2122 speed = dwc->gadget_max_speed;
2123 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2124 speed = dwc->maximum_speed;
2126 if (speed == USB_SPEED_SUPER_PLUS &&
2127 DWC3_IP_IS(DWC32)) {
2128 __dwc3_gadget_set_ssp_rate(dwc);
2132 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2133 reg &= ~(DWC3_DCFG_SPEED_MASK);
2136 * WORKAROUND: DWC3 revision < 2.20a have an issue
2137 * which would cause metastability state on Run/Stop
2138 * bit if we try to force the IP to USB2-only mode.
2140 * Because of that, we cannot configure the IP to any
2141 * speed other than the SuperSpeed
2145 * STAR#9000525659: Clock Domain Crossing on DCTL in
2148 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2149 !dwc->dis_metastability_quirk) {
2150 reg |= DWC3_DCFG_SUPERSPEED;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (DWC3_IP_IS(DWC3))
2164 reg |= DWC3_DCFG_SUPERSPEED;
2166 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2171 if (DWC3_IP_IS(DWC3))
2172 reg |= DWC3_DCFG_SUPERSPEED;
2174 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2178 if (DWC3_IP_IS(DWC32) &&
2179 speed > USB_SPEED_UNKNOWN &&
2180 speed < USB_SPEED_SUPER_PLUS)
2181 reg &= ~DWC3_DCFG_NUMLANES(~0);
2183 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2186 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2191 if (pm_runtime_suspended(dwc->dev))
2194 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2196 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2197 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2198 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2201 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2202 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2203 reg |= DWC3_DCTL_RUN_STOP;
2205 if (dwc->has_hibernation)
2206 reg |= DWC3_DCTL_KEEP_CONNECT;
2208 __dwc3_gadget_set_speed(dwc);
2209 dwc->pullups_connected = true;
2211 reg &= ~DWC3_DCTL_RUN_STOP;
2213 if (dwc->has_hibernation && !suspend)
2214 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2216 dwc->pullups_connected = false;
2219 dwc3_gadget_dctl_write_safe(dwc, reg);
2222 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2223 reg &= DWC3_DSTS_DEVCTRLHLT;
2224 } while (--timeout && !(!is_on ^ !reg));
2232 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2233 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2234 static int __dwc3_gadget_start(struct dwc3 *dwc);
2236 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2238 struct dwc3 *dwc = gadget_to_dwc(g);
2239 unsigned long flags;
2245 * Per databook, when we want to stop the gadget, if a control transfer
2246 * is still in process, complete it and get the core into setup phase.
2248 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2249 reinit_completion(&dwc->ep0_in_setup);
2251 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2252 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2254 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
2260 * Avoid issuing a runtime resume if the device is already in the
2261 * suspended state during gadget disconnect. DWC3 gadget was already
2262 * halted/stopped during runtime suspend.
2265 pm_runtime_barrier(dwc->dev);
2266 if (pm_runtime_suspended(dwc->dev))
2271 * Check the return value for successful resume, or error. For a
2272 * successful resume, the DWC3 runtime PM resume routine will handle
2273 * the run stop sequence, so avoid duplicate operations here.
2275 ret = pm_runtime_get_sync(dwc->dev);
2276 if (!ret || ret < 0) {
2277 pm_runtime_put(dwc->dev);
2282 * Synchronize and disable any further event handling while controller
2283 * is being enabled/disabled.
2285 disable_irq(dwc->irq_gadget);
2287 spin_lock_irqsave(&dwc->lock, flags);
2292 dwc->connected = false;
2294 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2295 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2296 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2297 * command for any active transfers" before clearing the RunStop
2300 dwc3_stop_active_transfers(dwc);
2301 __dwc3_gadget_stop(dwc);
2304 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2305 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2306 * "software needs to acknowledge the events that are generated
2307 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2308 * to be set to '1'."
2310 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2311 count &= DWC3_GEVNTCOUNT_MASK;
2313 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2314 dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2315 dwc->ev_buf->length;
2318 __dwc3_gadget_start(dwc);
2321 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2322 spin_unlock_irqrestore(&dwc->lock, flags);
2323 enable_irq(dwc->irq_gadget);
2325 pm_runtime_put(dwc->dev);
2330 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2334 /* Enable all but Start and End of Frame IRQs */
2335 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2336 DWC3_DEVTEN_CMDCMPLTEN |
2337 DWC3_DEVTEN_ERRTICERREN |
2338 DWC3_DEVTEN_WKUPEVTEN |
2339 DWC3_DEVTEN_CONNECTDONEEN |
2340 DWC3_DEVTEN_USBRSTEN |
2341 DWC3_DEVTEN_DISCONNEVTEN);
2343 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2344 reg |= DWC3_DEVTEN_ULSTCNGEN;
2346 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2347 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2348 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2350 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2353 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2355 /* mask all interrupts */
2356 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2359 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2360 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2363 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2364 * @dwc: pointer to our context structure
2366 * The following looks like complex but it's actually very simple. In order to
2367 * calculate the number of packets we can burst at once on OUT transfers, we're
2368 * gonna use RxFIFO size.
2370 * To calculate RxFIFO size we need two numbers:
2371 * MDWIDTH = size, in bits, of the internal memory bus
2372 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2374 * Given these two numbers, the formula is simple:
2376 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2378 * 24 bytes is for 3x SETUP packets
2379 * 16 bytes is a clock domain crossing tolerance
2381 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2383 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2390 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2391 mdwidth = dwc3_mdwidth(dwc);
2393 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2394 nump = min_t(u32, nump, 16);
2397 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2398 reg &= ~DWC3_DCFG_NUMP_MASK;
2399 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2400 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2403 static int __dwc3_gadget_start(struct dwc3 *dwc)
2405 struct dwc3_ep *dep;
2410 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2411 * the core supports IMOD, disable it.
2413 if (dwc->imod_interval) {
2414 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2415 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2416 } else if (dwc3_has_imod(dwc)) {
2417 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2421 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2422 * field instead of letting dwc3 itself calculate that automatically.
2424 * This way, we maximize the chances that we'll be able to get several
2425 * bursts of data without going through any sort of endpoint throttling.
2427 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2428 if (DWC3_IP_IS(DWC3))
2429 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2431 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2433 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2435 dwc3_gadget_setup_nump(dwc);
2438 * Currently the controller handles single stream only. So, Ignore
2439 * Packet Pending bit for stream selection and don't search for another
2440 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2441 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2442 * the stream performance.
2444 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2445 reg |= DWC3_DCFG_IGNSTRMPP;
2446 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2448 /* Start with SuperSpeed Default */
2449 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2452 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2454 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2459 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2461 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2465 /* begin to receive SETUP packets */
2466 dwc->ep0state = EP0_SETUP_PHASE;
2467 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2468 dwc3_ep0_out_start(dwc);
2470 dwc3_gadget_enable_irq(dwc);
2475 __dwc3_gadget_ep_disable(dwc->eps[0]);
2481 static int dwc3_gadget_start(struct usb_gadget *g,
2482 struct usb_gadget_driver *driver)
2484 struct dwc3 *dwc = gadget_to_dwc(g);
2485 unsigned long flags;
2489 irq = dwc->irq_gadget;
2490 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2491 IRQF_SHARED, "dwc3", dwc->ev_buf);
2493 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2498 spin_lock_irqsave(&dwc->lock, flags);
2499 dwc->gadget_driver = driver;
2500 spin_unlock_irqrestore(&dwc->lock, flags);
2505 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2507 dwc3_gadget_disable_irq(dwc);
2508 __dwc3_gadget_ep_disable(dwc->eps[0]);
2509 __dwc3_gadget_ep_disable(dwc->eps[1]);
2512 static int dwc3_gadget_stop(struct usb_gadget *g)
2514 struct dwc3 *dwc = gadget_to_dwc(g);
2515 unsigned long flags;
2517 spin_lock_irqsave(&dwc->lock, flags);
2518 dwc->gadget_driver = NULL;
2519 spin_unlock_irqrestore(&dwc->lock, flags);
2521 free_irq(dwc->irq_gadget, dwc->ev_buf);
2526 static void dwc3_gadget_config_params(struct usb_gadget *g,
2527 struct usb_dcd_config_params *params)
2529 struct dwc3 *dwc = gadget_to_dwc(g);
2531 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2532 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2534 /* Recommended BESL */
2535 if (!dwc->dis_enblslpm_quirk) {
2537 * If the recommended BESL baseline is 0 or if the BESL deep is
2538 * less than 2, Microsoft's Windows 10 host usb stack will issue
2539 * a usb reset immediately after it receives the extended BOS
2540 * descriptor and the enumeration will fail. To maintain
2541 * compatibility with the Windows' usb stack, let's set the
2542 * recommended BESL baseline to 1 and clamp the BESL deep to be
2545 params->besl_baseline = 1;
2546 if (dwc->is_utmi_l1_suspend)
2548 clamp_t(u8, dwc->hird_threshold, 2, 15);
2551 /* U1 Device exit Latency */
2552 if (dwc->dis_u1_entry_quirk)
2553 params->bU1devExitLat = 0;
2555 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2557 /* U2 Device exit Latency */
2558 if (dwc->dis_u2_entry_quirk)
2559 params->bU2DevExitLat = 0;
2561 params->bU2DevExitLat =
2562 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2565 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2566 enum usb_device_speed speed)
2568 struct dwc3 *dwc = gadget_to_dwc(g);
2569 unsigned long flags;
2571 spin_lock_irqsave(&dwc->lock, flags);
2572 dwc->gadget_max_speed = speed;
2573 spin_unlock_irqrestore(&dwc->lock, flags);
2576 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2577 enum usb_ssp_rate rate)
2579 struct dwc3 *dwc = gadget_to_dwc(g);
2580 unsigned long flags;
2582 spin_lock_irqsave(&dwc->lock, flags);
2583 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2584 dwc->gadget_ssp_rate = rate;
2585 spin_unlock_irqrestore(&dwc->lock, flags);
2588 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2590 struct dwc3 *dwc = gadget_to_dwc(g);
2591 union power_supply_propval val = {0};
2595 return usb_phy_set_power(dwc->usb2_phy, mA);
2600 val.intval = 1000 * mA;
2601 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2606 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2608 struct dwc3 *dwc = gadget_to_dwc(g);
2609 unsigned long flags;
2611 spin_lock_irqsave(&dwc->lock, flags);
2612 dwc->async_callbacks = enable;
2613 spin_unlock_irqrestore(&dwc->lock, flags);
2616 static const struct usb_gadget_ops dwc3_gadget_ops = {
2617 .get_frame = dwc3_gadget_get_frame,
2618 .wakeup = dwc3_gadget_wakeup,
2619 .set_selfpowered = dwc3_gadget_set_selfpowered,
2620 .pullup = dwc3_gadget_pullup,
2621 .udc_start = dwc3_gadget_start,
2622 .udc_stop = dwc3_gadget_stop,
2623 .udc_set_speed = dwc3_gadget_set_speed,
2624 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
2625 .get_config_params = dwc3_gadget_config_params,
2626 .vbus_draw = dwc3_gadget_vbus_draw,
2627 .udc_async_callbacks = dwc3_gadget_async_callbacks,
2630 /* -------------------------------------------------------------------------- */
2632 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2634 struct dwc3 *dwc = dep->dwc;
2636 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2637 dep->endpoint.maxburst = 1;
2638 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2639 if (!dep->direction)
2640 dwc->gadget->ep0 = &dep->endpoint;
2642 dep->endpoint.caps.type_control = true;
2647 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2649 struct dwc3 *dwc = dep->dwc;
2653 mdwidth = dwc3_mdwidth(dwc);
2655 /* MDWIDTH is represented in bits, we need it in bytes */
2658 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2659 if (DWC3_IP_IS(DWC3))
2660 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2662 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2664 /* FIFO Depth is in MDWDITH bytes. Multiply */
2668 * To meet performance requirement, a minimum TxFIFO size of 3x
2669 * MaxPacketSize is recommended for endpoints that support burst and a
2670 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2671 * support burst. Use those numbers and we can calculate the max packet
2674 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2679 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2681 dep->endpoint.max_streams = 16;
2682 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2683 list_add_tail(&dep->endpoint.ep_list,
2684 &dwc->gadget->ep_list);
2685 dep->endpoint.caps.type_iso = true;
2686 dep->endpoint.caps.type_bulk = true;
2687 dep->endpoint.caps.type_int = true;
2689 return dwc3_alloc_trb_pool(dep);
2692 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2694 struct dwc3 *dwc = dep->dwc;
2698 mdwidth = dwc3_mdwidth(dwc);
2700 /* MDWIDTH is represented in bits, convert to bytes */
2703 /* All OUT endpoints share a single RxFIFO space */
2704 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2705 if (DWC3_IP_IS(DWC3))
2706 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2708 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2710 /* FIFO depth is in MDWDITH bytes */
2714 * To meet performance requirement, a minimum recommended RxFIFO size
2715 * is defined as follow:
2716 * RxFIFO size >= (3 x MaxPacketSize) +
2717 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2719 * Then calculate the max packet limit as below.
2721 size -= (3 * 8) + 16;
2727 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2728 dep->endpoint.max_streams = 16;
2729 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2730 list_add_tail(&dep->endpoint.ep_list,
2731 &dwc->gadget->ep_list);
2732 dep->endpoint.caps.type_iso = true;
2733 dep->endpoint.caps.type_bulk = true;
2734 dep->endpoint.caps.type_int = true;
2736 return dwc3_alloc_trb_pool(dep);
2739 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2741 struct dwc3_ep *dep;
2742 bool direction = epnum & 1;
2744 u8 num = epnum >> 1;
2746 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2751 dep->number = epnum;
2752 dep->direction = direction;
2753 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2754 dwc->eps[epnum] = dep;
2756 dep->start_cmd_status = 0;
2758 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2759 direction ? "in" : "out");
2761 dep->endpoint.name = dep->name;
2763 if (!(dep->number > 1)) {
2764 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2765 dep->endpoint.comp_desc = NULL;
2769 ret = dwc3_gadget_init_control_endpoint(dep);
2771 ret = dwc3_gadget_init_in_endpoint(dep);
2773 ret = dwc3_gadget_init_out_endpoint(dep);
2778 dep->endpoint.caps.dir_in = direction;
2779 dep->endpoint.caps.dir_out = !direction;
2781 INIT_LIST_HEAD(&dep->pending_list);
2782 INIT_LIST_HEAD(&dep->started_list);
2783 INIT_LIST_HEAD(&dep->cancelled_list);
2785 dwc3_debugfs_create_endpoint_dir(dep);
2790 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2794 INIT_LIST_HEAD(&dwc->gadget->ep_list);
2796 for (epnum = 0; epnum < total; epnum++) {
2799 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2807 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2809 struct dwc3_ep *dep;
2812 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2813 dep = dwc->eps[epnum];
2817 * Physical endpoints 0 and 1 are special; they form the
2818 * bi-directional USB endpoint 0.
2820 * For those two physical endpoints, we don't allocate a TRB
2821 * pool nor do we add them the endpoints list. Due to that, we
2822 * shouldn't do these two operations otherwise we would end up
2823 * with all sorts of bugs when removing dwc3.ko.
2825 if (epnum != 0 && epnum != 1) {
2826 dwc3_free_trb_pool(dep);
2827 list_del(&dep->endpoint.ep_list);
2830 debugfs_remove_recursive(debugfs_lookup(dep->name,
2831 debugfs_lookup(dev_name(dep->dwc->dev),
2837 /* -------------------------------------------------------------------------- */
2839 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2840 struct dwc3_request *req, struct dwc3_trb *trb,
2841 const struct dwc3_event_depevt *event, int status, int chain)
2845 dwc3_ep_inc_deq(dep);
2847 trace_dwc3_complete_trb(dep, trb);
2851 * If we're in the middle of series of chained TRBs and we
2852 * receive a short transfer along the way, DWC3 will skip
2853 * through all TRBs including the last TRB in the chain (the
2854 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2855 * bit and SW has to do it manually.
2857 * We're going to do that here to avoid problems of HW trying
2858 * to use bogus TRBs for transfers.
2860 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2861 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2864 * For isochronous transfers, the first TRB in a service interval must
2865 * have the Isoc-First type. Track and report its interval frame number.
2867 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2868 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2869 unsigned int frame_number;
2871 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2872 frame_number &= ~(dep->interval - 1);
2873 req->request.frame_number = frame_number;
2877 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2878 * this TRB points to the bounce buffer address, it's a MPS alignment
2879 * TRB. Don't add it to req->remaining calculation.
2881 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2882 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2883 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2887 count = trb->size & DWC3_TRB_SIZE_MASK;
2888 req->remaining += count;
2890 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2893 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2896 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2897 (trb->ctrl & DWC3_TRB_CTRL_LST))
2903 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2904 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2907 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2908 struct scatterlist *sg = req->sg;
2909 struct scatterlist *s;
2910 unsigned int num_queued = req->num_queued_sgs;
2914 for_each_sg(sg, s, num_queued, i) {
2915 trb = &dep->trb_pool[dep->trb_dequeue];
2917 req->sg = sg_next(s);
2918 req->num_queued_sgs--;
2920 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2921 trb, event, status, true);
2929 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2930 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2933 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2935 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2936 event, status, false);
2939 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2941 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
2944 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2945 const struct dwc3_event_depevt *event,
2946 struct dwc3_request *req, int status)
2950 if (req->request.num_mapped_sgs)
2951 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2954 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2957 req->request.actual = req->request.length - req->remaining;
2959 if (!dwc3_gadget_ep_request_completed(req))
2962 if (req->needs_extra_trb) {
2963 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2965 req->needs_extra_trb = false;
2968 dwc3_gadget_giveback(dep, req, status);
2974 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2975 const struct dwc3_event_depevt *event, int status)
2977 struct dwc3_request *req;
2978 struct dwc3_request *tmp;
2979 struct list_head local;
2982 list_replace_init(&dep->started_list, &local);
2984 list_for_each_entry_safe(req, tmp, &local, list) {
2987 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2993 if (!list_empty(&dep->started_list))
2997 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2999 struct dwc3_request *req;
3000 struct dwc3 *dwc = dep->dwc;
3002 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3006 if (!list_empty(&dep->pending_list))
3010 * We only need to check the first entry of the started list. We can
3011 * assume the completed requests are removed from the started list.
3013 req = next_request(&dep->started_list);
3017 return !dwc3_gadget_ep_request_completed(req);
3020 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3021 const struct dwc3_event_depevt *event)
3023 dep->frame_number = event->parameters;
3026 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3027 const struct dwc3_event_depevt *event, int status)
3029 struct dwc3 *dwc = dep->dwc;
3030 bool no_started_trb = true;
3032 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3034 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3037 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3038 list_empty(&dep->started_list) &&
3039 (list_empty(&dep->pending_list) || status == -EXDEV))
3040 dwc3_stop_active_transfer(dep, true, true);
3041 else if (dwc3_gadget_ep_should_continue(dep))
3042 if (__dwc3_gadget_kick_transfer(dep) == 0)
3043 no_started_trb = false;
3047 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3048 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3050 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3054 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3057 if (!(dep->flags & DWC3_EP_ENABLED))
3060 if (!list_empty(&dep->started_list))
3061 return no_started_trb;
3064 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3066 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3071 return no_started_trb;
3074 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3075 const struct dwc3_event_depevt *event)
3079 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3080 dwc3_gadget_endpoint_frame_from_event(dep, event);
3082 if (event->status & DEPEVT_STATUS_BUSERR)
3083 status = -ECONNRESET;
3085 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3088 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3091 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3092 const struct dwc3_event_depevt *event)
3096 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3098 if (event->status & DEPEVT_STATUS_BUSERR)
3099 status = -ECONNRESET;
3101 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3102 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3105 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3106 const struct dwc3_event_depevt *event)
3108 dwc3_gadget_endpoint_frame_from_event(dep, event);
3111 * The XferNotReady event is generated only once before the endpoint
3112 * starts. It will be generated again when END_TRANSFER command is
3113 * issued. For some controller versions, the XferNotReady event may be
3114 * generated while the END_TRANSFER command is still in process. Ignore
3115 * it and wait for the next XferNotReady event after the command is
3118 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3121 (void) __dwc3_gadget_start_isoc(dep);
3124 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3125 const struct dwc3_event_depevt *event)
3127 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3129 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3132 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3133 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3134 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3136 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3137 struct dwc3 *dwc = dep->dwc;
3139 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3140 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3141 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3143 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3144 if (dwc->delayed_status)
3145 __dwc3_gadget_ep0_set_halt(ep0, 1);
3149 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3150 if (dwc->delayed_status)
3151 dwc3_ep0_send_delayed_status(dwc);
3154 if ((dep->flags & DWC3_EP_DELAY_START) &&
3155 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3156 __dwc3_gadget_kick_transfer(dep);
3158 dep->flags &= ~DWC3_EP_DELAY_START;
3161 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3162 const struct dwc3_event_depevt *event)
3164 struct dwc3 *dwc = dep->dwc;
3166 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3167 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3171 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3172 switch (event->parameters) {
3173 case DEPEVT_STREAM_PRIME:
3175 * If the host can properly transition the endpoint state from
3176 * idle to prime after a NoStream rejection, there's no need to
3177 * force restarting the endpoint to reinitiate the stream. To
3178 * simplify the check, assume the host follows the USB spec if
3179 * it primed the endpoint more than once.
3181 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3182 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3183 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3185 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3189 case DEPEVT_STREAM_NOSTREAM:
3190 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3191 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3192 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3196 * If the host rejects a stream due to no active stream, by the
3197 * USB and xHCI spec, the endpoint will be put back to idle
3198 * state. When the host is ready (buffer added/updated), it will
3199 * prime the endpoint to inform the usb device controller. This
3200 * triggers the device controller to issue ERDY to restart the
3201 * stream. However, some hosts don't follow this and keep the
3202 * endpoint in the idle state. No prime will come despite host
3203 * streams are updated, and the device controller will not be
3204 * triggered to generate ERDY to move the next stream data. To
3205 * workaround this and maintain compatibility with various
3206 * hosts, force to reinitate the stream until the host is ready
3207 * instead of waiting for the host to prime the endpoint.
3209 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3210 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3212 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3214 dep->flags |= DWC3_EP_DELAY_START;
3215 dwc3_stop_active_transfer(dep, true, true);
3222 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3225 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3226 const struct dwc3_event_depevt *event)
3228 struct dwc3_ep *dep;
3229 u8 epnum = event->endpoint_number;
3231 dep = dwc->eps[epnum];
3233 if (!(dep->flags & DWC3_EP_ENABLED)) {
3234 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3237 /* Handle only EPCMDCMPLT when EP disabled */
3238 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3242 if (epnum == 0 || epnum == 1) {
3243 dwc3_ep0_interrupt(dwc, event);
3247 switch (event->endpoint_event) {
3248 case DWC3_DEPEVT_XFERINPROGRESS:
3249 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3251 case DWC3_DEPEVT_XFERNOTREADY:
3252 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3254 case DWC3_DEPEVT_EPCMDCMPLT:
3255 dwc3_gadget_endpoint_command_complete(dep, event);
3257 case DWC3_DEPEVT_XFERCOMPLETE:
3258 dwc3_gadget_endpoint_transfer_complete(dep, event);
3260 case DWC3_DEPEVT_STREAMEVT:
3261 dwc3_gadget_endpoint_stream_event(dep, event);
3263 case DWC3_DEPEVT_RXTXFIFOEVT:
3268 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3270 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3271 spin_unlock(&dwc->lock);
3272 dwc->gadget_driver->disconnect(dwc->gadget);
3273 spin_lock(&dwc->lock);
3277 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3279 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3280 spin_unlock(&dwc->lock);
3281 dwc->gadget_driver->suspend(dwc->gadget);
3282 spin_lock(&dwc->lock);
3286 static void dwc3_resume_gadget(struct dwc3 *dwc)
3288 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3289 spin_unlock(&dwc->lock);
3290 dwc->gadget_driver->resume(dwc->gadget);
3291 spin_lock(&dwc->lock);
3295 static void dwc3_reset_gadget(struct dwc3 *dwc)
3297 if (!dwc->gadget_driver)
3300 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3301 spin_unlock(&dwc->lock);
3302 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3303 spin_lock(&dwc->lock);
3307 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3310 struct dwc3_gadget_ep_cmd_params params;
3314 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3315 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3319 * NOTICE: We are violating what the Databook says about the
3320 * EndTransfer command. Ideally we would _always_ wait for the
3321 * EndTransfer Command Completion IRQ, but that's causing too
3322 * much trouble synchronizing between us and gadget driver.
3324 * We have discussed this with the IP Provider and it was
3325 * suggested to giveback all requests here.
3327 * Note also that a similar handling was tested by Synopsys
3328 * (thanks a lot Paul) and nothing bad has come out of it.
3329 * In short, what we're doing is issuing EndTransfer with
3330 * CMDIOC bit set and delay kicking transfer until the
3331 * EndTransfer command had completed.
3333 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3334 * supports a mode to work around the above limitation. The
3335 * software can poll the CMDACT bit in the DEPCMD register
3336 * after issuing a EndTransfer command. This mode is enabled
3337 * by writing GUCTL2[14]. This polling is already done in the
3338 * dwc3_send_gadget_ep_cmd() function so if the mode is
3339 * enabled, the EndTransfer command will have completed upon
3340 * returning from this function.
3342 * This mode is NOT available on the DWC_usb31 IP.
3345 cmd = DWC3_DEPCMD_ENDTRANSFER;
3346 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3347 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3348 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3349 memset(¶ms, 0, sizeof(params));
3350 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3352 dep->resource_index = 0;
3355 * The END_TRANSFER command will cause the controller to generate a
3356 * NoStream Event, and it's not due to the host DP NoStream rejection.
3357 * Ignore the next NoStream event.
3359 if (dep->stream_capable)
3360 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3363 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3365 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3368 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3372 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3373 struct dwc3_ep *dep;
3376 dep = dwc->eps[epnum];
3380 if (!(dep->flags & DWC3_EP_STALL))
3383 dep->flags &= ~DWC3_EP_STALL;
3385 ret = dwc3_send_clear_stall_ep_cmd(dep);
3390 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3394 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3396 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3397 reg &= ~DWC3_DCTL_INITU1ENA;
3398 reg &= ~DWC3_DCTL_INITU2ENA;
3399 dwc3_gadget_dctl_write_safe(dwc, reg);
3401 dwc3_disconnect_gadget(dwc);
3403 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3404 dwc->setup_packet_pending = false;
3405 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3407 dwc->connected = false;
3410 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3415 * Ideally, dwc3_reset_gadget() would trigger the function
3416 * drivers to stop any active transfers through ep disable.
3417 * However, for functions which defer ep disable, such as mass
3418 * storage, we will need to rely on the call to stop active
3419 * transfers here, and avoid allowing of request queuing.
3421 dwc->connected = false;
3424 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3425 * would cause a missing Disconnect Event if there's a
3426 * pending Setup Packet in the FIFO.
3428 * There's no suggested workaround on the official Bug
3429 * report, which states that "unless the driver/application
3430 * is doing any special handling of a disconnect event,
3431 * there is no functional issue".
3433 * Unfortunately, it turns out that we _do_ some special
3434 * handling of a disconnect event, namely complete all
3435 * pending transfers, notify gadget driver of the
3436 * disconnection, and so on.
3438 * Our suggested workaround is to follow the Disconnect
3439 * Event steps here, instead, based on a setup_packet_pending
3440 * flag. Such flag gets set whenever we have a SETUP_PENDING
3441 * status for EP0 TRBs and gets cleared on XferComplete for the
3446 * STAR#9000466709: RTL: Device : Disconnect event not
3447 * generated if setup packet pending in FIFO
3449 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3450 if (dwc->setup_packet_pending)
3451 dwc3_gadget_disconnect_interrupt(dwc);
3454 dwc3_reset_gadget(dwc);
3456 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3457 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3458 * needs to ensure that it sends "a DEPENDXFER command for any active
3461 dwc3_stop_active_transfers(dwc);
3462 dwc->connected = true;
3464 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3465 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3466 dwc3_gadget_dctl_write_safe(dwc, reg);
3467 dwc->test_mode = false;
3468 dwc3_clear_stall_all_ep(dwc);
3470 /* Reset device address to zero */
3471 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3472 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3473 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3476 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3478 struct dwc3_ep *dep;
3484 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3485 speed = reg & DWC3_DSTS_CONNECTSPD;
3488 if (DWC3_IP_IS(DWC32))
3489 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3491 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3494 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3495 * each time on Connect Done.
3497 * Currently we always use the reset value. If any platform
3498 * wants to set this to a different value, we need to add a
3499 * setting and update GCTL.RAMCLKSEL here.
3503 case DWC3_DSTS_SUPERSPEED_PLUS:
3504 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3505 dwc->gadget->ep0->maxpacket = 512;
3506 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3509 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3511 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3513 case DWC3_DSTS_SUPERSPEED:
3515 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3516 * would cause a missing USB3 Reset event.
3518 * In such situations, we should force a USB3 Reset
3519 * event by calling our dwc3_gadget_reset_interrupt()
3524 * STAR#9000483510: RTL: SS : USB3 reset event may
3525 * not be generated always when the link enters poll
3527 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3528 dwc3_gadget_reset_interrupt(dwc);
3530 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3531 dwc->gadget->ep0->maxpacket = 512;
3532 dwc->gadget->speed = USB_SPEED_SUPER;
3535 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3536 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3539 case DWC3_DSTS_HIGHSPEED:
3540 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3541 dwc->gadget->ep0->maxpacket = 64;
3542 dwc->gadget->speed = USB_SPEED_HIGH;
3544 case DWC3_DSTS_FULLSPEED:
3545 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3546 dwc->gadget->ep0->maxpacket = 64;
3547 dwc->gadget->speed = USB_SPEED_FULL;
3551 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3553 /* Enable USB2 LPM Capability */
3555 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3556 !dwc->usb2_gadget_lpm_disable &&
3557 (speed != DWC3_DSTS_SUPERSPEED) &&
3558 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3559 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3560 reg |= DWC3_DCFG_LPM_CAP;
3561 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3563 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3564 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3566 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3567 (dwc->is_utmi_l1_suspend << 4));
3570 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3571 * DCFG.LPMCap is set, core responses with an ACK and the
3572 * BESL value in the LPM token is less than or equal to LPM
3575 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3576 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3578 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3579 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3581 dwc3_gadget_dctl_write_safe(dwc, reg);
3583 if (dwc->usb2_gadget_lpm_disable) {
3584 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3585 reg &= ~DWC3_DCFG_LPM_CAP;
3586 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3589 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3590 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3591 dwc3_gadget_dctl_write_safe(dwc, reg);
3595 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3597 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3602 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3604 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3609 * Configure PHY via GUSB3PIPECTLn if required.
3611 * Update GTXFIFOSIZn
3613 * In both cases reset values should be sufficient.
3617 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3620 * TODO take core out of low power mode when that's
3624 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3625 spin_unlock(&dwc->lock);
3626 dwc->gadget_driver->resume(dwc->gadget);
3627 spin_lock(&dwc->lock);
3631 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3632 unsigned int evtinfo)
3634 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3635 unsigned int pwropt;
3638 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3639 * Hibernation mode enabled which would show up when device detects
3640 * host-initiated U3 exit.
3642 * In that case, device will generate a Link State Change Interrupt
3643 * from U3 to RESUME which is only necessary if Hibernation is
3646 * There are no functional changes due to such spurious event and we
3647 * just need to ignore it.
3651 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3654 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3655 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3656 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3657 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3658 (next == DWC3_LINK_STATE_RESUME)) {
3664 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3665 * on the link partner, the USB session might do multiple entry/exit
3666 * of low power states before a transfer takes place.
3668 * Due to this problem, we might experience lower throughput. The
3669 * suggested workaround is to disable DCTL[12:9] bits if we're
3670 * transitioning from U1/U2 to U0 and enable those bits again
3671 * after a transfer completes and there are no pending transfers
3672 * on any of the enabled endpoints.
3674 * This is the first half of that workaround.
3678 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3679 * core send LGO_Ux entering U0
3681 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3682 if (next == DWC3_LINK_STATE_U0) {
3686 switch (dwc->link_state) {
3687 case DWC3_LINK_STATE_U1:
3688 case DWC3_LINK_STATE_U2:
3689 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3690 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3691 | DWC3_DCTL_ACCEPTU2ENA
3692 | DWC3_DCTL_INITU1ENA
3693 | DWC3_DCTL_ACCEPTU1ENA);
3696 dwc->u1u2 = reg & u1u2;
3700 dwc3_gadget_dctl_write_safe(dwc, reg);
3710 case DWC3_LINK_STATE_U1:
3711 if (dwc->speed == USB_SPEED_SUPER)
3712 dwc3_suspend_gadget(dwc);
3714 case DWC3_LINK_STATE_U2:
3715 case DWC3_LINK_STATE_U3:
3716 dwc3_suspend_gadget(dwc);
3718 case DWC3_LINK_STATE_RESUME:
3719 dwc3_resume_gadget(dwc);
3726 dwc->link_state = next;
3729 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3730 unsigned int evtinfo)
3732 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3734 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3735 dwc3_suspend_gadget(dwc);
3737 dwc->link_state = next;
3740 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3741 unsigned int evtinfo)
3743 unsigned int is_ss = evtinfo & BIT(4);
3746 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3747 * have a known issue which can cause USB CV TD.9.23 to fail
3750 * Because of this issue, core could generate bogus hibernation
3751 * events which SW needs to ignore.
3755 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3756 * Device Fallback from SuperSpeed
3758 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3761 /* enter hibernation here */
3764 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3765 const struct dwc3_event_devt *event)
3767 switch (event->type) {
3768 case DWC3_DEVICE_EVENT_DISCONNECT:
3769 dwc3_gadget_disconnect_interrupt(dwc);
3771 case DWC3_DEVICE_EVENT_RESET:
3772 dwc3_gadget_reset_interrupt(dwc);
3774 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3775 dwc3_gadget_conndone_interrupt(dwc);
3777 case DWC3_DEVICE_EVENT_WAKEUP:
3778 dwc3_gadget_wakeup_interrupt(dwc);
3780 case DWC3_DEVICE_EVENT_HIBER_REQ:
3781 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3782 "unexpected hibernation event\n"))
3785 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3787 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3788 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3790 case DWC3_DEVICE_EVENT_SUSPEND:
3791 /* It changed to be suspend event for version 2.30a and above */
3792 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3794 * Ignore suspend event until the gadget enters into
3795 * USB_STATE_CONFIGURED state.
3797 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
3798 dwc3_gadget_suspend_interrupt(dwc,
3802 case DWC3_DEVICE_EVENT_SOF:
3803 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3804 case DWC3_DEVICE_EVENT_CMD_CMPL:
3805 case DWC3_DEVICE_EVENT_OVERFLOW:
3808 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3812 static void dwc3_process_event_entry(struct dwc3 *dwc,
3813 const union dwc3_event *event)
3815 trace_dwc3_event(event->raw, dwc);
3817 if (!event->type.is_devspec)
3818 dwc3_endpoint_interrupt(dwc, &event->depevt);
3819 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3820 dwc3_gadget_interrupt(dwc, &event->devt);
3822 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3825 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3827 struct dwc3 *dwc = evt->dwc;
3828 irqreturn_t ret = IRQ_NONE;
3834 if (!(evt->flags & DWC3_EVENT_PENDING))
3838 union dwc3_event event;
3840 event.raw = *(u32 *) (evt->cache + evt->lpos);
3842 dwc3_process_event_entry(dwc, &event);
3845 * FIXME we wrap around correctly to the next entry as
3846 * almost all entries are 4 bytes in size. There is one
3847 * entry which has 12 bytes which is a regular entry
3848 * followed by 8 bytes data. ATM I don't know how
3849 * things are organized if we get next to the a
3850 * boundary so I worry about that once we try to handle
3853 evt->lpos = (evt->lpos + 4) % evt->length;
3858 evt->flags &= ~DWC3_EVENT_PENDING;
3861 /* Unmask interrupt */
3862 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3863 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3864 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3866 if (dwc->imod_interval) {
3867 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3868 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3874 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3876 struct dwc3_event_buffer *evt = _evt;
3877 struct dwc3 *dwc = evt->dwc;
3878 unsigned long flags;
3879 irqreturn_t ret = IRQ_NONE;
3881 spin_lock_irqsave(&dwc->lock, flags);
3882 ret = dwc3_process_event_buf(evt);
3883 spin_unlock_irqrestore(&dwc->lock, flags);
3888 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3890 struct dwc3 *dwc = evt->dwc;
3895 if (pm_runtime_suspended(dwc->dev)) {
3896 pm_runtime_get(dwc->dev);
3897 disable_irq_nosync(dwc->irq_gadget);
3898 dwc->pending_events = true;
3903 * With PCIe legacy interrupt, test shows that top-half irq handler can
3904 * be called again after HW interrupt deassertion. Check if bottom-half
3905 * irq event handler completes before caching new event to prevent
3908 if (evt->flags & DWC3_EVENT_PENDING)
3911 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3912 count &= DWC3_GEVNTCOUNT_MASK;
3917 evt->flags |= DWC3_EVENT_PENDING;
3919 /* Mask interrupt */
3920 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3921 reg |= DWC3_GEVNTSIZ_INTMASK;
3922 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3924 amount = min(count, evt->length - evt->lpos);
3925 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3928 memcpy(evt->cache, evt->buf, count - amount);
3930 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3932 return IRQ_WAKE_THREAD;
3935 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3937 struct dwc3_event_buffer *evt = _evt;
3939 return dwc3_check_event_buf(evt);
3942 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3944 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3947 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3951 if (irq == -EPROBE_DEFER)
3954 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3958 if (irq == -EPROBE_DEFER)
3961 irq = platform_get_irq(dwc3_pdev, 0);
3972 static void dwc_gadget_release(struct device *dev)
3974 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3980 * dwc3_gadget_init - initializes gadget related registers
3981 * @dwc: pointer to our controller context structure
3983 * Returns 0 on success otherwise negative errno.
3985 int dwc3_gadget_init(struct dwc3 *dwc)
3991 irq = dwc3_gadget_get_irq(dwc);
3997 dwc->irq_gadget = irq;
3999 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4000 sizeof(*dwc->ep0_trb) * 2,
4001 &dwc->ep0_trb_addr, GFP_KERNEL);
4002 if (!dwc->ep0_trb) {
4003 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4008 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4009 if (!dwc->setup_buf) {
4014 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4015 &dwc->bounce_addr, GFP_KERNEL);
4021 init_completion(&dwc->ep0_in_setup);
4022 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4029 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4030 dev = &dwc->gadget->dev;
4031 dev->platform_data = dwc;
4032 dwc->gadget->ops = &dwc3_gadget_ops;
4033 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4034 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4035 dwc->gadget->sg_supported = true;
4036 dwc->gadget->name = "dwc3-gadget";
4037 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4040 * FIXME We might be setting max_speed to <SUPER, however versions
4041 * <2.20a of dwc3 have an issue with metastability (documented
4042 * elsewhere in this driver) which tells us we can't set max speed to
4043 * anything lower than SUPER.
4045 * Because gadget.max_speed is only used by composite.c and function
4046 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4047 * to happen so we avoid sending SuperSpeed Capability descriptor
4048 * together with our BOS descriptor as that could confuse host into
4049 * thinking we can handle super speed.
4051 * Note that, in fact, we won't even support GetBOS requests when speed
4052 * is less than super speed because we don't have means, yet, to tell
4053 * composite.c that we are USB 2.0 + LPM ECN.
4055 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4056 !dwc->dis_metastability_quirk)
4057 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4060 dwc->gadget->max_speed = dwc->maximum_speed;
4061 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4064 * REVISIT: Here we should clear all pending IRQs to be
4065 * sure we're starting from a well known location.
4068 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4072 ret = usb_add_gadget(dwc->gadget);
4074 dev_err(dwc->dev, "failed to add gadget\n");
4078 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4079 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4081 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4086 dwc3_gadget_free_endpoints(dwc);
4088 usb_put_gadget(dwc->gadget);
4091 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4095 kfree(dwc->setup_buf);
4098 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4099 dwc->ep0_trb, dwc->ep0_trb_addr);
4105 /* -------------------------------------------------------------------------- */
4107 void dwc3_gadget_exit(struct dwc3 *dwc)
4112 usb_del_gadget(dwc->gadget);
4113 dwc3_gadget_free_endpoints(dwc);
4114 usb_put_gadget(dwc->gadget);
4115 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4117 kfree(dwc->setup_buf);
4118 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4119 dwc->ep0_trb, dwc->ep0_trb_addr);
4122 int dwc3_gadget_suspend(struct dwc3 *dwc)
4124 if (!dwc->gadget_driver)
4127 dwc3_gadget_run_stop(dwc, false, false);
4128 dwc3_disconnect_gadget(dwc);
4129 __dwc3_gadget_stop(dwc);
4134 int dwc3_gadget_resume(struct dwc3 *dwc)
4138 if (!dwc->gadget_driver)
4141 ret = __dwc3_gadget_start(dwc);
4145 ret = dwc3_gadget_run_stop(dwc, true, false);
4152 __dwc3_gadget_stop(dwc);
4158 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4160 if (dwc->pending_events) {
4161 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4162 dwc->pending_events = false;
4163 enable_irq(dwc->irq_gadget);