drivers/tty/synclink_gt.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Device driver for Microgate SyncLink GT serial adapters.
   4  *
   5  * written by Paul Fulghum for Microgate Corporation
   6  * paulkf@microgate.com
   7  *
   8  * Microgate and SyncLink are trademarks of Microgate Corporation
   9  *
  10  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20  * OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 /*
  24  * DEBUG OUTPUT DEFINITIONS
  25  *
  26  * uncomment lines below to enable specific types of debug output
  27  *
  28  * DBGINFO   information - most verbose output
  29  * DBGERR    serious errors
  30  * DBGBH     bottom half service routine debugging
  31  * DBGISR    interrupt service routine debugging
  32  * DBGDATA   output receive and transmit data
  33  * DBGTBUF   output transmit DMA buffers and registers
  34  * DBGRBUF   output receive DMA buffers and registers
  35  */
  36
  37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42 /*#define DBGTBUF(info) dump_tbufs(info)*/
  43 /*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46 #include <linux/module.h>
  47 #include <linux/errno.h>
  48 #include <linux/signal.h>
  49 #include <linux/sched.h>
  50 #include <linux/timer.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/pci.h>
  53 #include <linux/tty.h>
  54 #include <linux/tty_flip.h>
  55 #include <linux/serial.h>
  56 #include <linux/major.h>
  57 #include <linux/string.h>
  58 #include <linux/fcntl.h>
  59 #include <linux/ptrace.h>
  60 #include <linux/ioport.h>
  61 #include <linux/mm.h>
  62 #include <linux/seq_file.h>
  63 #include <linux/slab.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/init.h>
  67 #include <linux/delay.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/termios.h>
  70 #include <linux/bitops.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/hdlc.h>
  73 #include <linux/synclink.h>
  74
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77 #include <asm/dma.h>
  78 #include <asm/types.h>
  79 #include <linux/uaccess.h>
  80
  81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82 #define SYNCLINK_GENERIC_HDLC 1
  83 #else
  84 #define SYNCLINK_GENERIC_HDLC 0
  85 #endif
  86
  87 /*
  88  * module identification
  89  */
  90 static char *driver_name     = "SyncLink GT";
  91 static char *slgt_driver_name = "synclink_gt";
  92 static char *tty_dev_prefix  = "ttySLG";
  93 MODULE_LICENSE("GPL");
  94 #define MGSL_MAGIC 0x5401
  95 #define MAX_DEVICES 32
  96
  97 static const struct pci_device_id pci_table[] = {
  98         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {0,}, /* terminate list */
 103 };
 104 MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107 static void remove_one(struct pci_dev *dev);
 108 static struct pci_driver pci_driver = {
 109         .name           = "synclink_gt",
 110         .id_table       = pci_table,
 111         .probe          = init_one,
 112         .remove         = remove_one,
 113 };
 114
 115 static bool pci_registered;
 116
 117 /*
 118  * module configuration and status
 119  */
 120 static struct slgt_info *slgt_device_list;
 121 static int slgt_device_count;
 122
 123 static int ttymajor;
 124 static int debug_level;
 125 static int maxframe[MAX_DEVICES];
 126
 127 module_param(ttymajor, int, 0);
 128 module_param(debug_level, int, 0);
 129 module_param_array(maxframe, int, NULL, 0);
 130
 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135 /*
 136  * tty support and callbacks
 137  */
 138 static struct tty_driver *serial_driver;
 139
 140 static void wait_until_sent(struct tty_struct *tty, int timeout);
 141 static void flush_buffer(struct tty_struct *tty);
 142 static void tx_release(struct tty_struct *tty);
 143
 144 /*
 145  * generic HDLC support
 146  */
 147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 148
 149
 150 /*
 151  * device specific structures, macros and functions
 152  */
 153
 154 #define SLGT_MAX_PORTS 4
 155 #define SLGT_REG_SIZE  256
 156
 157 /*
 158  * conditional wait facility
 159  */
 160 struct cond_wait {
 161         struct cond_wait *next;
 162         wait_queue_head_t q;
 163         wait_queue_entry_t wait;
 164         unsigned int data;
 165 };
 166 static void flush_cond_wait(struct cond_wait **head);
 167
 168 /*
 169  * DMA buffer descriptor and access macros
 170  */
 171 struct slgt_desc
 172 {
 173         __le16 count;
 174         __le16 status;
 175         __le32 pbuf;  /* physical address of data buffer */
 176         __le32 next;  /* physical address of next descriptor */
 177
 178         /* driver book keeping */
 179         char *buf;          /* virtual  address of data buffer */
 180         unsigned int pdesc; /* physical address of this descriptor */
 181         dma_addr_t buf_dma_addr;
 182         unsigned short buf_count;
 183 };
 184
 185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 186 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 187 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 188 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 190 #define desc_count(a)      (le16_to_cpu((a).count))
 191 #define desc_status(a)     (le16_to_cpu((a).status))
 192 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 193 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 194 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 195 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 196 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 197
 198 struct _input_signal_events {
 199         int ri_up;
 200         int ri_down;
 201         int dsr_up;
 202         int dsr_down;
 203         int dcd_up;
 204         int dcd_down;
 205         int cts_up;
 206         int cts_down;
 207 };
 208
 209 /*
 210  * device instance data structure
 211  */
 212 struct slgt_info {
 213         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 214         struct tty_port port;
 215
 216         struct slgt_info *next_device;  /* device list link */
 217
 218         int magic;
 219
 220         char device_name[25];
 221         struct pci_dev *pdev;
 222
 223         int port_count;  /* count of ports on adapter */
 224         int adapter_num; /* adapter instance number */
 225         int port_num;    /* port instance number */
 226
 227         /* array of pointers to port contexts on this adapter */
 228         struct slgt_info *port_array[SLGT_MAX_PORTS];
 229
 230         int                     line;           /* tty line instance number */
 231
 232         struct mgsl_icount      icount;
 233
 234         int                     timeout;
 235         int                     x_char;         /* xon/xoff character */
 236         unsigned int            read_status_mask;
 237         unsigned int            ignore_status_mask;
 238
 239         wait_queue_head_t       status_event_wait_q;
 240         wait_queue_head_t       event_wait_q;
 241         struct timer_list       tx_timer;
 242         struct timer_list       rx_timer;
 243
 244         unsigned int            gpio_present;
 245         struct cond_wait        *gpio_wait_q;
 246
 247         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 248
 249         struct work_struct task;
 250         u32 pending_bh;
 251         bool bh_requested;
 252         bool bh_running;
 253
 254         int isr_overflow;
 255         bool irq_requested;     /* true if IRQ requested */
 256         bool irq_occurred;      /* for diagnostics use */
 257
 258         /* device configuration */
 259
 260         unsigned int bus_type;
 261         unsigned int irq_level;
 262         unsigned long irq_flags;
 263
 264         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 265         u32 phys_reg_addr;
 266         bool reg_addr_requested;
 267
 268         MGSL_PARAMS params;       /* communications parameters */
 269         u32 idle_mode;
 270         u32 max_frame_size;       /* as set by device config */
 271
 272         unsigned int rbuf_fill_level;
 273         unsigned int rx_pio;
 274         unsigned int if_mode;
 275         unsigned int base_clock;
 276         unsigned int xsync;
 277         unsigned int xctrl;
 278
 279         /* device status */
 280
 281         bool rx_enabled;
 282         bool rx_restart;
 283
 284         bool tx_enabled;
 285         bool tx_active;
 286
 287         unsigned char signals;    /* serial signal states */
 288         int init_error;  /* initialization error */
 289
 290         unsigned char *tx_buf;
 291         int tx_count;
 292
 293         char *flag_buf;
 294         bool drop_rts_on_tx_done;
 295         struct  _input_signal_events    input_signal_events;
 296
 297         int dcd_chkcount;       /* check counts to prevent */
 298         int cts_chkcount;       /* too many IRQs if a signal */
 299         int dsr_chkcount;       /* is floating */
 300         int ri_chkcount;
 301
 302         char *bufs;             /* virtual address of DMA buffer lists */
 303         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 304
 305         unsigned int rbuf_count;
 306         struct slgt_desc *rbufs;
 307         unsigned int rbuf_current;
 308         unsigned int rbuf_index;
 309         unsigned int rbuf_fill_index;
 310         unsigned short rbuf_fill_count;
 311
 312         unsigned int tbuf_count;
 313         struct slgt_desc *tbufs;
 314         unsigned int tbuf_current;
 315         unsigned int tbuf_start;
 316
 317         unsigned char *tmp_rbuf;
 318         unsigned int tmp_rbuf_count;
 319
 320         /* SPPP/Cisco HDLC device parts */
 321
 322         int netcount;
 323         spinlock_t netlock;
 324 #if SYNCLINK_GENERIC_HDLC
 325         struct net_device *netdev;
 326 #endif
 327
 328 };
 329
 330 static MGSL_PARAMS default_params = {
 331         .mode            = MGSL_MODE_HDLC,
 332         .loopback        = 0,
 333         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 334         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 335         .clock_speed     = 0,
 336         .addr_filter     = 0xff,
 337         .crc_type        = HDLC_CRC_16_CCITT,
 338         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 339         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 340         .data_rate       = 9600,
 341         .data_bits       = 8,
 342         .stop_bits       = 1,
 343         .parity          = ASYNC_PARITY_NONE
 344 };
 345
 346
 347 #define BH_RECEIVE  1
 348 #define BH_TRANSMIT 2
 349 #define BH_STATUS   4
 350 #define IO_PIN_SHUTDOWN_LIMIT 100
 351
 352 #define DMABUFSIZE 256
 353 #define DESC_LIST_SIZE 4096
 354
 355 #define MASK_PARITY  BIT1
 356 #define MASK_FRAMING BIT0
 357 #define MASK_BREAK   BIT14
 358 #define MASK_OVERRUN BIT4
 359
 360 #define GSR   0x00 /* global status */
 361 #define JCR   0x04 /* JTAG control */
 362 #define IODR  0x08 /* GPIO direction */
 363 #define IOER  0x0c /* GPIO interrupt enable */
 364 #define IOVR  0x10 /* GPIO value */
 365 #define IOSR  0x14 /* GPIO interrupt status */
 366 #define TDR   0x80 /* tx data */
 367 #define RDR   0x80 /* rx data */
 368 #define TCR   0x82 /* tx control */
 369 #define TIR   0x84 /* tx idle */
 370 #define TPR   0x85 /* tx preamble */
 371 #define RCR   0x86 /* rx control */
 372 #define VCR   0x88 /* V.24 control */
 373 #define CCR   0x89 /* clock control */
 374 #define BDR   0x8a /* baud divisor */
 375 #define SCR   0x8c /* serial control */
 376 #define SSR   0x8e /* serial status */
 377 #define RDCSR 0x90 /* rx DMA control/status */
 378 #define TDCSR 0x94 /* tx DMA control/status */
 379 #define RDDAR 0x98 /* rx DMA descriptor address */
 380 #define TDDAR 0x9c /* tx DMA descriptor address */
 381 #define XSR   0x40 /* extended sync pattern */
 382 #define XCR   0x44 /* extended control */
 383
 384 #define RXIDLE      BIT14
 385 #define RXBREAK     BIT14
 386 #define IRQ_TXDATA  BIT13
 387 #define IRQ_TXIDLE  BIT12
 388 #define IRQ_TXUNDER BIT11 /* HDLC */
 389 #define IRQ_RXDATA  BIT10
 390 #define IRQ_RXIDLE  BIT9  /* HDLC */
 391 #define IRQ_RXBREAK BIT9  /* async */
 392 #define IRQ_RXOVER  BIT8
 393 #define IRQ_DSR     BIT7
 394 #define IRQ_CTS     BIT6
 395 #define IRQ_DCD     BIT5
 396 #define IRQ_RI      BIT4
 397 #define IRQ_ALL     0x3ff0
 398 #define IRQ_MASTER  BIT0
 399
 400 #define slgt_irq_on(info, mask) \
 401         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 402 #define slgt_irq_off(info, mask) \
 403         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 404
 405 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 406 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 408 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 410 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 411
 412 static void  msc_set_vcr(struct slgt_info *info);
 413
 414 static int  startup(struct slgt_info *info);
 415 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 416 static void shutdown(struct slgt_info *info);
 417 static void program_hw(struct slgt_info *info);
 418 static void change_params(struct slgt_info *info);
 419
 420 static int  adapter_test(struct slgt_info *info);
 421
 422 static void reset_port(struct slgt_info *info);
 423 static void async_mode(struct slgt_info *info);
 424 static void sync_mode(struct slgt_info *info);
 425
 426 static void rx_stop(struct slgt_info *info);
 427 static void rx_start(struct slgt_info *info);
 428 static void reset_rbufs(struct slgt_info *info);
 429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 430 static bool rx_get_frame(struct slgt_info *info);
 431 static bool rx_get_buf(struct slgt_info *info);
 432
 433 static void tx_start(struct slgt_info *info);
 434 static void tx_stop(struct slgt_info *info);
 435 static void tx_set_idle(struct slgt_info *info);
 436 static unsigned int tbuf_bytes(struct slgt_info *info);
 437 static void reset_tbufs(struct slgt_info *info);
 438 static void tdma_reset(struct slgt_info *info);
 439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 440
 441 static void get_signals(struct slgt_info *info);
 442 static void set_signals(struct slgt_info *info);
 443 static void set_rate(struct slgt_info *info, u32 data_rate);
 444
 445 static void bh_transmit(struct slgt_info *info);
 446 static void isr_txeom(struct slgt_info *info, unsigned short status);
 447
 448 static void tx_timeout(struct timer_list *t);
 449 static void rx_timeout(struct timer_list *t);
 450
 451 /*
 452  * ioctl handlers
 453  */
 454 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 455 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 456 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 457 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 458 static int  set_txidle(struct slgt_info *info, int idle_mode);
 459 static int  tx_enable(struct slgt_info *info, int enable);
 460 static int  tx_abort(struct slgt_info *info);
 461 static int  rx_enable(struct slgt_info *info, int enable);
 462 static int  modem_input_wait(struct slgt_info *info,int arg);
 463 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 464 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 465 static int  set_interface(struct slgt_info *info, int if_mode);
 466 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 467 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 468 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 469 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 470 static int  set_xsync(struct slgt_info *info, int if_mode);
 471 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 472 static int  set_xctrl(struct slgt_info *info, int if_mode);
 473
 474 /*
 475  * driver functions
 476  */
 477 static void release_resources(struct slgt_info *info);
 478
 479 /*
 480  * DEBUG OUTPUT CODE
 481  */
 482 #ifndef DBGINFO
 483 #define DBGINFO(fmt)
 484 #endif
 485 #ifndef DBGERR
 486 #define DBGERR(fmt)
 487 #endif
 488 #ifndef DBGBH
 489 #define DBGBH(fmt)
 490 #endif
 491 #ifndef DBGISR
 492 #define DBGISR(fmt)
 493 #endif
 494
 495 #ifdef DBGDATA
 496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 497 {
 498         int i;
 499         int linecount;
 500         printk("%s %s data:\n",info->device_name, label);
 501         while(count) {
 502                 linecount = (count > 16) ? 16 : count;
 503                 for(i=0; i < linecount; i++)
 504                         printk("%02X ",(unsigned char)data[i]);
 505                 for(;i<17;i++)
 506                         printk("   ");
 507                 for(i=0;i<linecount;i++) {
 508                         if (data[i]>=040 && data[i]<=0176)
 509                                 printk("%c",data[i]);
 510                         else
 511                                 printk(".");
 512                 }
 513                 printk("\n");
 514                 data  += linecount;
 515                 count -= linecount;
 516         }
 517 }
 518 #else
 519 #define DBGDATA(info, buf, size, label)
 520 #endif
 521
 522 #ifdef DBGTBUF
 523 static void dump_tbufs(struct slgt_info *info)
 524 {
 525         int i;
 526         printk("tbuf_current=%d\n", info->tbuf_current);
 527         for (i=0 ; i < info->tbuf_count ; i++) {
 528                 printk("%d: count=%04X status=%04X\n",
 529                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 530         }
 531 }
 532 #else
 533 #define DBGTBUF(info)
 534 #endif
 535
 536 #ifdef DBGRBUF
 537 static void dump_rbufs(struct slgt_info *info)
 538 {
 539         int i;
 540         printk("rbuf_current=%d\n", info->rbuf_current);
 541         for (i=0 ; i < info->rbuf_count ; i++) {
 542                 printk("%d: count=%04X status=%04X\n",
 543                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 544         }
 545 }
 546 #else
 547 #define DBGRBUF(info)
 548 #endif
 549
 550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 551 {
 552 #ifdef SANITY_CHECK
 553         if (!info) {
 554                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 555                 return 1;
 556         }
 557         if (info->magic != MGSL_MAGIC) {
 558                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 559                 return 1;
 560         }
 561 #else
 562         if (!info)
 563                 return 1;
 564 #endif
 565         return 0;
 566 }
 567
 568 /*
 569  * line discipline callback wrappers
 570  *
 571  * The wrappers maintain line discipline references
 572  * while calling into the line discipline.
 573  *
 574  * ldisc_receive_buf  - pass receive data to line discipline
 575  */
 576 static void ldisc_receive_buf(struct tty_struct *tty,
 577                               const __u8 *data, char *flags, int count)
 578 {
 579         struct tty_ldisc *ld;
 580         if (!tty)
 581                 return;
 582         ld = tty_ldisc_ref(tty);
 583         if (ld) {
 584                 if (ld->ops->receive_buf)
 585                         ld->ops->receive_buf(tty, data, flags, count);
 586                 tty_ldisc_deref(ld);
 587         }
 588 }
 589
 590 /* tty callbacks */
 591
 592 static int open(struct tty_struct *tty, struct file *filp)
 593 {
 594         struct slgt_info *info;
 595         int retval, line;
 596         unsigned long flags;
 597
 598         line = tty->index;
 599         if (line >= slgt_device_count) {
 600                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 601                 return -ENODEV;
 602         }
 603
 604         info = slgt_device_list;
 605         while(info && info->line != line)
 606                 info = info->next_device;
 607         if (sanity_check(info, tty->name, "open"))
 608                 return -ENODEV;
 609         if (info->init_error) {
 610                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 611                 return -ENODEV;
 612         }
 613
 614         tty->driver_data = info;
 615         info->port.tty = tty;
 616
 617         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 618
 619         mutex_lock(&info->port.mutex);
 620
 621         spin_lock_irqsave(&info->netlock, flags);
 622         if (info->netcount) {
 623                 retval = -EBUSY;
 624                 spin_unlock_irqrestore(&info->netlock, flags);
 625                 mutex_unlock(&info->port.mutex);
 626                 goto cleanup;
 627         }
 628         info->port.count++;
 629         spin_unlock_irqrestore(&info->netlock, flags);
 630
 631         if (info->port.count == 1) {
 632                 /* 1st open on this device, init hardware */
 633                 retval = startup(info);
 634                 if (retval < 0) {
 635                         mutex_unlock(&info->port.mutex);
 636                         goto cleanup;
 637                 }
 638         }
 639         mutex_unlock(&info->port.mutex);
 640         retval = block_til_ready(tty, filp, info);
 641         if (retval) {
 642                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 643                 goto cleanup;
 644         }
 645
 646         retval = 0;
 647
 648 cleanup:
 649         if (retval) {
 650                 if (tty->count == 1)
 651                         info->port.tty = NULL; /* tty layer will release tty struct */
 652                 if(info->port.count)
 653                         info->port.count--;
 654         }
 655
 656         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 657         return retval;
 658 }
 659
 660 static void close(struct tty_struct *tty, struct file *filp)
 661 {
 662         struct slgt_info *info = tty->driver_data;
 663
 664         if (sanity_check(info, tty->name, "close"))
 665                 return;
 666         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 667
 668         if (tty_port_close_start(&info->port, tty, filp) == 0)
 669                 goto cleanup;
 670
 671         mutex_lock(&info->port.mutex);
 672         if (tty_port_initialized(&info->port))
 673                 wait_until_sent(tty, info->timeout);
 674         flush_buffer(tty);
 675         tty_ldisc_flush(tty);
 676
 677         shutdown(info);
 678         mutex_unlock(&info->port.mutex);
 679
 680         tty_port_close_end(&info->port, tty);
 681         info->port.tty = NULL;
 682 cleanup:
 683         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 684 }
 685
 686 static void hangup(struct tty_struct *tty)
 687 {
 688         struct slgt_info *info = tty->driver_data;
 689         unsigned long flags;
 690
 691         if (sanity_check(info, tty->name, "hangup"))
 692                 return;
 693         DBGINFO(("%s hangup\n", info->device_name));
 694
 695         flush_buffer(tty);
 696
 697         mutex_lock(&info->port.mutex);
 698         shutdown(info);
 699
 700         spin_lock_irqsave(&info->port.lock, flags);
 701         info->port.count = 0;
 702         info->port.tty = NULL;
 703         spin_unlock_irqrestore(&info->port.lock, flags);
 704         tty_port_set_active(&info->port, 0);
 705         mutex_unlock(&info->port.mutex);
 706
 707         wake_up_interruptible(&info->port.open_wait);
 708 }
 709
 710 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 711 {
 712         struct slgt_info *info = tty->driver_data;
 713         unsigned long flags;
 714
 715         DBGINFO(("%s set_termios\n", tty->driver->name));
 716
 717         change_params(info);
 718
 719         /* Handle transition to B0 status */
 720         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 721                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 722                 spin_lock_irqsave(&info->lock,flags);
 723                 set_signals(info);
 724                 spin_unlock_irqrestore(&info->lock,flags);
 725         }
 726
 727         /* Handle transition away from B0 status */
 728         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 729                 info->signals |= SerialSignal_DTR;
 730                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 731                         info->signals |= SerialSignal_RTS;
 732                 spin_lock_irqsave(&info->lock,flags);
 733                 set_signals(info);
 734                 spin_unlock_irqrestore(&info->lock,flags);
 735         }
 736
 737         /* Handle turning off CRTSCTS */
 738         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 739                 tty->hw_stopped = 0;
 740                 tx_release(tty);
 741         }
 742 }
 743
 744 static void update_tx_timer(struct slgt_info *info)
 745 {
 746         /*
 747          * use worst case speed of 1200bps to calculate transmit timeout
 748          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 749          */
 750         if (info->params.mode == MGSL_MODE_HDLC) {
 751                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 752                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 753         }
 754 }
 755
 756 static int write(struct tty_struct *tty,
 757                  const unsigned char *buf, int count)
 758 {
 759         int ret = 0;
 760         struct slgt_info *info = tty->driver_data;
 761         unsigned long flags;
 762
 763         if (sanity_check(info, tty->name, "write"))
 764                 return -EIO;
 765
 766         DBGINFO(("%s write count=%d\n", info->device_name, count));
 767
 768         if (!info->tx_buf || (count > info->max_frame_size))
 769                 return -EIO;
 770
 771         if (!count || tty->flow.stopped || tty->hw_stopped)
 772                 return 0;
 773
 774         spin_lock_irqsave(&info->lock, flags);
 775
 776         if (info->tx_count) {
 777                 /* send accumulated data from send_char() */
 778                 if (!tx_load(info, info->tx_buf, info->tx_count))
 779                         goto cleanup;
 780                 info->tx_count = 0;
 781         }
 782
 783         if (tx_load(info, buf, count))
 784                 ret = count;
 785
 786 cleanup:
 787         spin_unlock_irqrestore(&info->lock, flags);
 788         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 789         return ret;
 790 }
 791
 792 static int put_char(struct tty_struct *tty, unsigned char ch)
 793 {
 794         struct slgt_info *info = tty->driver_data;
 795         unsigned long flags;
 796         int ret = 0;
 797
 798         if (sanity_check(info, tty->name, "put_char"))
 799                 return 0;
 800         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 801         if (!info->tx_buf)
 802                 return 0;
 803         spin_lock_irqsave(&info->lock,flags);
 804         if (info->tx_count < info->max_frame_size) {
 805                 info->tx_buf[info->tx_count++] = ch;
 806                 ret = 1;
 807         }
 808         spin_unlock_irqrestore(&info->lock,flags);
 809         return ret;
 810 }
 811
 812 static void send_xchar(struct tty_struct *tty, char ch)
 813 {
 814         struct slgt_info *info = tty->driver_data;
 815         unsigned long flags;
 816
 817         if (sanity_check(info, tty->name, "send_xchar"))
 818                 return;
 819         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 820         info->x_char = ch;
 821         if (ch) {
 822                 spin_lock_irqsave(&info->lock,flags);
 823                 if (!info->tx_enabled)
 824                         tx_start(info);
 825                 spin_unlock_irqrestore(&info->lock,flags);
 826         }
 827 }
 828
 829 static void wait_until_sent(struct tty_struct *tty, int timeout)
 830 {
 831         struct slgt_info *info = tty->driver_data;
 832         unsigned long orig_jiffies, char_time;
 833
 834         if (!info )
 835                 return;
 836         if (sanity_check(info, tty->name, "wait_until_sent"))
 837                 return;
 838         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 839         if (!tty_port_initialized(&info->port))
 840                 goto exit;
 841
 842         orig_jiffies = jiffies;
 843
 844         /* Set check interval to 1/5 of estimated time to
 845          * send a character, and make it at least 1. The check
 846          * interval should also be less than the timeout.
 847          * Note: use tight timings here to satisfy the NIST-PCTS.
 848          */
 849
 850         if (info->params.data_rate) {
 851                 char_time = info->timeout/(32 * 5);
 852                 if (!char_time)
 853                         char_time++;
 854         } else
 855                 char_time = 1;
 856
 857         if (timeout)
 858                 char_time = min_t(unsigned long, char_time, timeout);
 859
 860         while (info->tx_active) {
 861                 msleep_interruptible(jiffies_to_msecs(char_time));
 862                 if (signal_pending(current))
 863                         break;
 864                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 865                         break;
 866         }
 867 exit:
 868         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 869 }
 870
 871 static unsigned int write_room(struct tty_struct *tty)
 872 {
 873         struct slgt_info *info = tty->driver_data;
 874         unsigned int ret;
 875
 876         if (sanity_check(info, tty->name, "write_room"))
 877                 return 0;
 878         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 879         DBGINFO(("%s write_room=%u\n", info->device_name, ret));
 880         return ret;
 881 }
 882
 883 static void flush_chars(struct tty_struct *tty)
 884 {
 885         struct slgt_info *info = tty->driver_data;
 886         unsigned long flags;
 887
 888         if (sanity_check(info, tty->name, "flush_chars"))
 889                 return;
 890         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 891
 892         if (info->tx_count <= 0 || tty->flow.stopped ||
 893             tty->hw_stopped || !info->tx_buf)
 894                 return;
 895
 896         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 897
 898         spin_lock_irqsave(&info->lock,flags);
 899         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 900                 info->tx_count = 0;
 901         spin_unlock_irqrestore(&info->lock,flags);
 902 }
 903
 904 static void flush_buffer(struct tty_struct *tty)
 905 {
 906         struct slgt_info *info = tty->driver_data;
 907         unsigned long flags;
 908
 909         if (sanity_check(info, tty->name, "flush_buffer"))
 910                 return;
 911         DBGINFO(("%s flush_buffer\n", info->device_name));
 912
 913         spin_lock_irqsave(&info->lock, flags);
 914         info->tx_count = 0;
 915         spin_unlock_irqrestore(&info->lock, flags);
 916
 917         tty_wakeup(tty);
 918 }
 919
 920 /*
 921  * throttle (stop) transmitter
 922  */
 923 static void tx_hold(struct tty_struct *tty)
 924 {
 925         struct slgt_info *info = tty->driver_data;
 926         unsigned long flags;
 927
 928         if (sanity_check(info, tty->name, "tx_hold"))
 929                 return;
 930         DBGINFO(("%s tx_hold\n", info->device_name));
 931         spin_lock_irqsave(&info->lock,flags);
 932         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 933                 tx_stop(info);
 934         spin_unlock_irqrestore(&info->lock,flags);
 935 }
 936
 937 /*
 938  * release (start) transmitter
 939  */
 940 static void tx_release(struct tty_struct *tty)
 941 {
 942         struct slgt_info *info = tty->driver_data;
 943         unsigned long flags;
 944
 945         if (sanity_check(info, tty->name, "tx_release"))
 946                 return;
 947         DBGINFO(("%s tx_release\n", info->device_name));
 948         spin_lock_irqsave(&info->lock, flags);
 949         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 950                 info->tx_count = 0;
 951         spin_unlock_irqrestore(&info->lock, flags);
 952 }
 953
 954 /*
 955  * Service an IOCTL request
 956  *
 957  * Arguments
 958  *
 959  *      tty     pointer to tty instance data
 960  *      cmd     IOCTL command code
 961  *      arg     command argument/context
 962  *
 963  * Return 0 if success, otherwise error code
 964  */
 965 static int ioctl(struct tty_struct *tty,
 966                  unsigned int cmd, unsigned long arg)
 967 {
 968         struct slgt_info *info = tty->driver_data;
 969         void __user *argp = (void __user *)arg;
 970         int ret;
 971
 972         if (sanity_check(info, tty->name, "ioctl"))
 973                 return -ENODEV;
 974         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
 975
 976         if (cmd != TIOCMIWAIT) {
 977                 if (tty_io_error(tty))
 978                     return -EIO;
 979         }
 980
 981         switch (cmd) {
 982         case MGSL_IOCWAITEVENT:
 983                 return wait_mgsl_event(info, argp);
 984         case TIOCMIWAIT:
 985                 return modem_input_wait(info,(int)arg);
 986         case MGSL_IOCSGPIO:
 987                 return set_gpio(info, argp);
 988         case MGSL_IOCGGPIO:
 989                 return get_gpio(info, argp);
 990         case MGSL_IOCWAITGPIO:
 991                 return wait_gpio(info, argp);
 992         case MGSL_IOCGXSYNC:
 993                 return get_xsync(info, argp);
 994         case MGSL_IOCSXSYNC:
 995                 return set_xsync(info, (int)arg);
 996         case MGSL_IOCGXCTRL:
 997                 return get_xctrl(info, argp);
 998         case MGSL_IOCSXCTRL:
 999                 return set_xctrl(info, (int)arg);
1000         }
1001         mutex_lock(&info->port.mutex);
1002         switch (cmd) {
1003         case MGSL_IOCGPARAMS:
1004                 ret = get_params(info, argp);
1005                 break;
1006         case MGSL_IOCSPARAMS:
1007                 ret = set_params(info, argp);
1008                 break;
1009         case MGSL_IOCGTXIDLE:
1010                 ret = get_txidle(info, argp);
1011                 break;
1012         case MGSL_IOCSTXIDLE:
1013                 ret = set_txidle(info, (int)arg);
1014                 break;
1015         case MGSL_IOCTXENABLE:
1016                 ret = tx_enable(info, (int)arg);
1017                 break;
1018         case MGSL_IOCRXENABLE:
1019                 ret = rx_enable(info, (int)arg);
1020                 break;
1021         case MGSL_IOCTXABORT:
1022                 ret = tx_abort(info);
1023                 break;
1024         case MGSL_IOCGSTATS:
1025                 ret = get_stats(info, argp);
1026                 break;
1027         case MGSL_IOCGIF:
1028                 ret = get_interface(info, argp);
1029                 break;
1030         case MGSL_IOCSIF:
1031                 ret = set_interface(info,(int)arg);
1032                 break;
1033         default:
1034                 ret = -ENOIOCTLCMD;
1035         }
1036         mutex_unlock(&info->port.mutex);
1037         return ret;
1038 }
1039
1040 static int get_icount(struct tty_struct *tty,
1041                                 struct serial_icounter_struct *icount)
1042
1043 {
1044         struct slgt_info *info = tty->driver_data;
1045         struct mgsl_icount cnow;        /* kernel counter temps */
1046         unsigned long flags;
1047
1048         spin_lock_irqsave(&info->lock,flags);
1049         cnow = info->icount;
1050         spin_unlock_irqrestore(&info->lock,flags);
1051
1052         icount->cts = cnow.cts;
1053         icount->dsr = cnow.dsr;
1054         icount->rng = cnow.rng;
1055         icount->dcd = cnow.dcd;
1056         icount->rx = cnow.rx;
1057         icount->tx = cnow.tx;
1058         icount->frame = cnow.frame;
1059         icount->overrun = cnow.overrun;
1060         icount->parity = cnow.parity;
1061         icount->brk = cnow.brk;
1062         icount->buf_overrun = cnow.buf_overrun;
1063
1064         return 0;
1065 }
1066
1067 /*
1068  * support for 32 bit ioctl calls on 64 bit systems
1069  */
1070 #ifdef CONFIG_COMPAT
1071 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1072 {
1073         struct MGSL_PARAMS32 tmp_params;
1074
1075         DBGINFO(("%s get_params32\n", info->device_name));
1076         memset(&tmp_params, 0, sizeof(tmp_params));
1077         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1078         tmp_params.loopback        = info->params.loopback;
1079         tmp_params.flags           = info->params.flags;
1080         tmp_params.encoding        = info->params.encoding;
1081         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1082         tmp_params.addr_filter     = info->params.addr_filter;
1083         tmp_params.crc_type        = info->params.crc_type;
1084         tmp_params.preamble_length = info->params.preamble_length;
1085         tmp_params.preamble        = info->params.preamble;
1086         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1087         tmp_params.data_bits       = info->params.data_bits;
1088         tmp_params.stop_bits       = info->params.stop_bits;
1089         tmp_params.parity          = info->params.parity;
1090         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1091                 return -EFAULT;
1092         return 0;
1093 }
1094
1095 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1096 {
1097         struct MGSL_PARAMS32 tmp_params;
1098
1099         DBGINFO(("%s set_params32\n", info->device_name));
1100         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1101                 return -EFAULT;
1102
1103         spin_lock(&info->lock);
1104         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1105                 info->base_clock = tmp_params.clock_speed;
1106         } else {
1107                 info->params.mode            = tmp_params.mode;
1108                 info->params.loopback        = tmp_params.loopback;
1109                 info->params.flags           = tmp_params.flags;
1110                 info->params.encoding        = tmp_params.encoding;
1111                 info->params.clock_speed     = tmp_params.clock_speed;
1112                 info->params.addr_filter     = tmp_params.addr_filter;
1113                 info->params.crc_type        = tmp_params.crc_type;
1114                 info->params.preamble_length = tmp_params.preamble_length;
1115                 info->params.preamble        = tmp_params.preamble;
1116                 info->params.data_rate       = tmp_params.data_rate;
1117                 info->params.data_bits       = tmp_params.data_bits;
1118                 info->params.stop_bits       = tmp_params.stop_bits;
1119                 info->params.parity          = tmp_params.parity;
1120         }
1121         spin_unlock(&info->lock);
1122
1123         program_hw(info);
1124
1125         return 0;
1126 }
1127
1128 static long slgt_compat_ioctl(struct tty_struct *tty,
1129                          unsigned int cmd, unsigned long arg)
1130 {
1131         struct slgt_info *info = tty->driver_data;
1132         int rc;
1133
1134         if (sanity_check(info, tty->name, "compat_ioctl"))
1135                 return -ENODEV;
1136         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1137
1138         switch (cmd) {
1139         case MGSL_IOCSPARAMS32:
1140                 rc = set_params32(info, compat_ptr(arg));
1141                 break;
1142
1143         case MGSL_IOCGPARAMS32:
1144                 rc = get_params32(info, compat_ptr(arg));
1145                 break;
1146
1147         case MGSL_IOCGPARAMS:
1148         case MGSL_IOCSPARAMS:
1149         case MGSL_IOCGTXIDLE:
1150         case MGSL_IOCGSTATS:
1151         case MGSL_IOCWAITEVENT:
1152         case MGSL_IOCGIF:
1153         case MGSL_IOCSGPIO:
1154         case MGSL_IOCGGPIO:
1155         case MGSL_IOCWAITGPIO:
1156         case MGSL_IOCGXSYNC:
1157         case MGSL_IOCGXCTRL:
1158                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1159                 break;
1160         default:
1161                 rc = ioctl(tty, cmd, arg);
1162         }
1163         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1164         return rc;
1165 }
1166 #else
1167 #define slgt_compat_ioctl NULL
1168 #endif /* ifdef CONFIG_COMPAT */
1169
1170 /*
1171  * proc fs support
1172  */
1173 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1174 {
1175         char stat_buf[30];
1176         unsigned long flags;
1177
1178         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1179                       info->device_name, info->phys_reg_addr,
1180                       info->irq_level, info->max_frame_size);
1181
1182         /* output current serial signal states */
1183         spin_lock_irqsave(&info->lock,flags);
1184         get_signals(info);
1185         spin_unlock_irqrestore(&info->lock,flags);
1186
1187         stat_buf[0] = 0;
1188         stat_buf[1] = 0;
1189         if (info->signals & SerialSignal_RTS)
1190                 strcat(stat_buf, "|RTS");
1191         if (info->signals & SerialSignal_CTS)
1192                 strcat(stat_buf, "|CTS");
1193         if (info->signals & SerialSignal_DTR)
1194                 strcat(stat_buf, "|DTR");
1195         if (info->signals & SerialSignal_DSR)
1196                 strcat(stat_buf, "|DSR");
1197         if (info->signals & SerialSignal_DCD)
1198                 strcat(stat_buf, "|CD");
1199         if (info->signals & SerialSignal_RI)
1200                 strcat(stat_buf, "|RI");
1201
1202         if (info->params.mode != MGSL_MODE_ASYNC) {
1203                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1204                                info->icount.txok, info->icount.rxok);
1205                 if (info->icount.txunder)
1206                         seq_printf(m, " txunder:%d", info->icount.txunder);
1207                 if (info->icount.txabort)
1208                         seq_printf(m, " txabort:%d", info->icount.txabort);
1209                 if (info->icount.rxshort)
1210                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1211                 if (info->icount.rxlong)
1212                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1213                 if (info->icount.rxover)
1214                         seq_printf(m, " rxover:%d", info->icount.rxover);
1215                 if (info->icount.rxcrc)
1216                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1217         } else {
1218                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1219                                info->icount.tx, info->icount.rx);
1220                 if (info->icount.frame)
1221                         seq_printf(m, " fe:%d", info->icount.frame);
1222                 if (info->icount.parity)
1223                         seq_printf(m, " pe:%d", info->icount.parity);
1224                 if (info->icount.brk)
1225                         seq_printf(m, " brk:%d", info->icount.brk);
1226                 if (info->icount.overrun)
1227                         seq_printf(m, " oe:%d", info->icount.overrun);
1228         }
1229
1230         /* Append serial signal status to end */
1231         seq_printf(m, " %s\n", stat_buf+1);
1232
1233         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1234                        info->tx_active,info->bh_requested,info->bh_running,
1235                        info->pending_bh);
1236 }
1237
1238 /* Called to print information about devices
1239  */
1240 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1241 {
1242         struct slgt_info *info;
1243
1244         seq_puts(m, "synclink_gt driver\n");
1245
1246         info = slgt_device_list;
1247         while( info ) {
1248                 line_info(m, info);
1249                 info = info->next_device;
1250         }
1251         return 0;
1252 }
1253
1254 /*
1255  * return count of bytes in transmit buffer
1256  */
1257 static unsigned int chars_in_buffer(struct tty_struct *tty)
1258 {
1259         struct slgt_info *info = tty->driver_data;
1260         unsigned int count;
1261         if (sanity_check(info, tty->name, "chars_in_buffer"))
1262                 return 0;
1263         count = tbuf_bytes(info);
1264         DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1265         return count;
1266 }
1267
1268 /*
1269  * signal remote device to throttle send data (our receive data)
1270  */
1271 static void throttle(struct tty_struct * tty)
1272 {
1273         struct slgt_info *info = tty->driver_data;
1274         unsigned long flags;
1275
1276         if (sanity_check(info, tty->name, "throttle"))
1277                 return;
1278         DBGINFO(("%s throttle\n", info->device_name));
1279         if (I_IXOFF(tty))
1280                 send_xchar(tty, STOP_CHAR(tty));
1281         if (C_CRTSCTS(tty)) {
1282                 spin_lock_irqsave(&info->lock,flags);
1283                 info->signals &= ~SerialSignal_RTS;
1284                 set_signals(info);
1285                 spin_unlock_irqrestore(&info->lock,flags);
1286         }
1287 }
1288
1289 /*
1290  * signal remote device to stop throttling send data (our receive data)
1291  */
1292 static void unthrottle(struct tty_struct * tty)
1293 {
1294         struct slgt_info *info = tty->driver_data;
1295         unsigned long flags;
1296
1297         if (sanity_check(info, tty->name, "unthrottle"))
1298                 return;
1299         DBGINFO(("%s unthrottle\n", info->device_name));
1300         if (I_IXOFF(tty)) {
1301                 if (info->x_char)
1302                         info->x_char = 0;
1303                 else
1304                         send_xchar(tty, START_CHAR(tty));
1305         }
1306         if (C_CRTSCTS(tty)) {
1307                 spin_lock_irqsave(&info->lock,flags);
1308                 info->signals |= SerialSignal_RTS;
1309                 set_signals(info);
1310                 spin_unlock_irqrestore(&info->lock,flags);
1311         }
1312 }
1313
1314 /*
1315  * set or clear transmit break condition
1316  * break_state  -1=set break condition, 0=clear
1317  */
1318 static int set_break(struct tty_struct *tty, int break_state)
1319 {
1320         struct slgt_info *info = tty->driver_data;
1321         unsigned short value;
1322         unsigned long flags;
1323
1324         if (sanity_check(info, tty->name, "set_break"))
1325                 return -EINVAL;
1326         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1327
1328         spin_lock_irqsave(&info->lock,flags);
1329         value = rd_reg16(info, TCR);
1330         if (break_state == -1)
1331                 value |= BIT6;
1332         else
1333                 value &= ~BIT6;
1334         wr_reg16(info, TCR, value);
1335         spin_unlock_irqrestore(&info->lock,flags);
1336         return 0;
1337 }
1338
1339 #if SYNCLINK_GENERIC_HDLC
1340
1341 /**
1342  * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1343  * @dev:      pointer to network device structure
1344  * @encoding: serial encoding setting
1345  * @parity:   FCS setting
1346  *
1347  * Set encoding and frame check sequence (FCS) options.
1348  *
1349  * Return: 0 if success, otherwise error code
1350  */
1351 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1352                           unsigned short parity)
1353 {
1354         struct slgt_info *info = dev_to_port(dev);
1355         unsigned char  new_encoding;
1356         unsigned short new_crctype;
1357
1358         /* return error if TTY interface open */
1359         if (info->port.count)
1360                 return -EBUSY;
1361
1362         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1363
1364         switch (encoding)
1365         {
1366         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1367         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1368         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1369         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1370         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1371         default: return -EINVAL;
1372         }
1373
1374         switch (parity)
1375         {
1376         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1377         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1378         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1379         default: return -EINVAL;
1380         }
1381
1382         info->params.encoding = new_encoding;
1383         info->params.crc_type = new_crctype;
1384
1385         /* if network interface up, reprogram hardware */
1386         if (info->netcount)
1387                 program_hw(info);
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * hdlcdev_xmit - called by generic HDLC layer to send a frame
1394  * @skb: socket buffer containing HDLC frame
1395  * @dev: pointer to network device structure
1396  */
1397 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1398                                       struct net_device *dev)
1399 {
1400         struct slgt_info *info = dev_to_port(dev);
1401         unsigned long flags;
1402
1403         DBGINFO(("%s hdlc_xmit\n", dev->name));
1404
1405         if (!skb->len)
1406                 return NETDEV_TX_OK;
1407
1408         /* stop sending until this frame completes */
1409         netif_stop_queue(dev);
1410
1411         /* update network statistics */
1412         dev->stats.tx_packets++;
1413         dev->stats.tx_bytes += skb->len;
1414
1415         /* save start time for transmit timeout detection */
1416         netif_trans_update(dev);
1417
1418         spin_lock_irqsave(&info->lock, flags);
1419         tx_load(info, skb->data, skb->len);
1420         spin_unlock_irqrestore(&info->lock, flags);
1421
1422         /* done with socket buffer, so free it */
1423         dev_kfree_skb(skb);
1424
1425         return NETDEV_TX_OK;
1426 }
1427
1428 /**
1429  * hdlcdev_open - called by network layer when interface enabled
1430  * @dev: pointer to network device structure
1431  *
1432  * Claim resources and initialize hardware.
1433  *
1434  * Return: 0 if success, otherwise error code
1435  */
1436 static int hdlcdev_open(struct net_device *dev)
1437 {
1438         struct slgt_info *info = dev_to_port(dev);
1439         int rc;
1440         unsigned long flags;
1441
1442         if (!try_module_get(THIS_MODULE))
1443                 return -EBUSY;
1444
1445         DBGINFO(("%s hdlcdev_open\n", dev->name));
1446
1447         /* generic HDLC layer open processing */
1448         rc = hdlc_open(dev);
1449         if (rc)
1450                 return rc;
1451
1452         /* arbitrate between network and tty opens */
1453         spin_lock_irqsave(&info->netlock, flags);
1454         if (info->port.count != 0 || info->netcount != 0) {
1455                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1456                 spin_unlock_irqrestore(&info->netlock, flags);
1457                 return -EBUSY;
1458         }
1459         info->netcount=1;
1460         spin_unlock_irqrestore(&info->netlock, flags);
1461
1462         /* claim resources and init adapter */
1463         if ((rc = startup(info)) != 0) {
1464                 spin_lock_irqsave(&info->netlock, flags);
1465                 info->netcount=0;
1466                 spin_unlock_irqrestore(&info->netlock, flags);
1467                 return rc;
1468         }
1469
1470         /* assert RTS and DTR, apply hardware settings */
1471         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1472         program_hw(info);
1473
1474         /* enable network layer transmit */
1475         netif_trans_update(dev);
1476         netif_start_queue(dev);
1477
1478         /* inform generic HDLC layer of current DCD status */
1479         spin_lock_irqsave(&info->lock, flags);
1480         get_signals(info);
1481         spin_unlock_irqrestore(&info->lock, flags);
1482         if (info->signals & SerialSignal_DCD)
1483                 netif_carrier_on(dev);
1484         else
1485                 netif_carrier_off(dev);
1486         return 0;
1487 }
1488
1489 /**
1490  * hdlcdev_close - called by network layer when interface is disabled
1491  * @dev:  pointer to network device structure
1492  *
1493  * Shutdown hardware and release resources.
1494  *
1495  * Return: 0 if success, otherwise error code
1496  */
1497 static int hdlcdev_close(struct net_device *dev)
1498 {
1499         struct slgt_info *info = dev_to_port(dev);
1500         unsigned long flags;
1501
1502         DBGINFO(("%s hdlcdev_close\n", dev->name));
1503
1504         netif_stop_queue(dev);
1505
1506         /* shutdown adapter and release resources */
1507         shutdown(info);
1508
1509         hdlc_close(dev);
1510
1511         spin_lock_irqsave(&info->netlock, flags);
1512         info->netcount=0;
1513         spin_unlock_irqrestore(&info->netlock, flags);
1514
1515         module_put(THIS_MODULE);
1516         return 0;
1517 }
1518
1519 /**
1520  * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1521  * @dev: pointer to network device structure
1522  * @ifr: pointer to network interface request structure
1523  * @cmd: IOCTL command code
1524  *
1525  * Return: 0 if success, otherwise error code
1526  */
1527 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1528 {
1529         const size_t size = sizeof(sync_serial_settings);
1530         sync_serial_settings new_line;
1531         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1532         struct slgt_info *info = dev_to_port(dev);
1533         unsigned int flags;
1534
1535         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1536
1537         /* return error if TTY interface open */
1538         if (info->port.count)
1539                 return -EBUSY;
1540
1541         if (cmd != SIOCWANDEV)
1542                 return hdlc_ioctl(dev, ifr, cmd);
1543
1544         memset(&new_line, 0, sizeof(new_line));
1545
1546         switch(ifr->ifr_settings.type) {
1547         case IF_GET_IFACE: /* return current sync_serial_settings */
1548
1549                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1550                 if (ifr->ifr_settings.size < size) {
1551                         ifr->ifr_settings.size = size; /* data size wanted */
1552                         return -ENOBUFS;
1553                 }
1554
1555                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1556                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1557                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1558                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1559
1560                 switch (flags){
1561                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1562                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1563                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1564                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1565                 default: new_line.clock_type = CLOCK_DEFAULT;
1566                 }
1567
1568                 new_line.clock_rate = info->params.clock_speed;
1569                 new_line.loopback   = info->params.loopback ? 1:0;
1570
1571                 if (copy_to_user(line, &new_line, size))
1572                         return -EFAULT;
1573                 return 0;
1574
1575         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1576
1577                 if(!capable(CAP_NET_ADMIN))
1578                         return -EPERM;
1579                 if (copy_from_user(&new_line, line, size))
1580                         return -EFAULT;
1581
1582                 switch (new_line.clock_type)
1583                 {
1584                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1585                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1586                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1587                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1588                 case CLOCK_DEFAULT:  flags = info->params.flags &
1589                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1590                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1591                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1592                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1593                 default: return -EINVAL;
1594                 }
1595
1596                 if (new_line.loopback != 0 && new_line.loopback != 1)
1597                         return -EINVAL;
1598
1599                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1600                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1601                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1602                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1603                 info->params.flags |= flags;
1604
1605                 info->params.loopback = new_line.loopback;
1606
1607                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1608                         info->params.clock_speed = new_line.clock_rate;
1609                 else
1610                         info->params.clock_speed = 0;
1611
1612                 /* if network interface up, reprogram hardware */
1613                 if (info->netcount)
1614                         program_hw(info);
1615                 return 0;
1616
1617         default:
1618                 return hdlc_ioctl(dev, ifr, cmd);
1619         }
1620 }
1621
1622 /**
1623  * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1624  * @dev: pointer to network device structure
1625  * @txqueue: unused
1626  */
1627 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1628 {
1629         struct slgt_info *info = dev_to_port(dev);
1630         unsigned long flags;
1631
1632         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1633
1634         dev->stats.tx_errors++;
1635         dev->stats.tx_aborted_errors++;
1636
1637         spin_lock_irqsave(&info->lock,flags);
1638         tx_stop(info);
1639         spin_unlock_irqrestore(&info->lock,flags);
1640
1641         netif_wake_queue(dev);
1642 }
1643
1644 /**
1645  * hdlcdev_tx_done - called by device driver when transmit completes
1646  * @info: pointer to device instance information
1647  *
1648  * Reenable network layer transmit if stopped.
1649  */
1650 static void hdlcdev_tx_done(struct slgt_info *info)
1651 {
1652         if (netif_queue_stopped(info->netdev))
1653                 netif_wake_queue(info->netdev);
1654 }
1655
1656 /**
1657  * hdlcdev_rx - called by device driver when frame received
1658  * @info: pointer to device instance information
1659  * @buf:  pointer to buffer contianing frame data
1660  * @size: count of data bytes in buf
1661  *
1662  * Pass frame to network layer.
1663  */
1664 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1665 {
1666         struct sk_buff *skb = dev_alloc_skb(size);
1667         struct net_device *dev = info->netdev;
1668
1669         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1670
1671         if (skb == NULL) {
1672                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1673                 dev->stats.rx_dropped++;
1674                 return;
1675         }
1676
1677         skb_put_data(skb, buf, size);
1678
1679         skb->protocol = hdlc_type_trans(skb, dev);
1680
1681         dev->stats.rx_packets++;
1682         dev->stats.rx_bytes += size;
1683
1684         netif_rx(skb);
1685 }
1686
1687 static const struct net_device_ops hdlcdev_ops = {
1688         .ndo_open       = hdlcdev_open,
1689         .ndo_stop       = hdlcdev_close,
1690         .ndo_start_xmit = hdlc_start_xmit,
1691         .ndo_do_ioctl   = hdlcdev_ioctl,
1692         .ndo_tx_timeout = hdlcdev_tx_timeout,
1693 };
1694
1695 /**
1696  * hdlcdev_init - called by device driver when adding device instance
1697  * @info: pointer to device instance information
1698  *
1699  * Do generic HDLC initialization.
1700  *
1701  * Return: 0 if success, otherwise error code
1702  */
1703 static int hdlcdev_init(struct slgt_info *info)
1704 {
1705         int rc;
1706         struct net_device *dev;
1707         hdlc_device *hdlc;
1708
1709         /* allocate and initialize network and HDLC layer objects */
1710
1711         dev = alloc_hdlcdev(info);
1712         if (!dev) {
1713                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1714                 return -ENOMEM;
1715         }
1716
1717         /* for network layer reporting purposes only */
1718         dev->mem_start = info->phys_reg_addr;
1719         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1720         dev->irq       = info->irq_level;
1721
1722         /* network layer callbacks and settings */
1723         dev->netdev_ops     = &hdlcdev_ops;
1724         dev->watchdog_timeo = 10 * HZ;
1725         dev->tx_queue_len   = 50;
1726
1727         /* generic HDLC layer callbacks and settings */
1728         hdlc         = dev_to_hdlc(dev);
1729         hdlc->attach = hdlcdev_attach;
1730         hdlc->xmit   = hdlcdev_xmit;
1731
1732         /* register objects with HDLC layer */
1733         rc = register_hdlc_device(dev);
1734         if (rc) {
1735                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1736                 free_netdev(dev);
1737                 return rc;
1738         }
1739
1740         info->netdev = dev;
1741         return 0;
1742 }
1743
1744 /**
1745  * hdlcdev_exit - called by device driver when removing device instance
1746  * @info: pointer to device instance information
1747  *
1748  * Do generic HDLC cleanup.
1749  */
1750 static void hdlcdev_exit(struct slgt_info *info)
1751 {
1752         unregister_hdlc_device(info->netdev);
1753         free_netdev(info->netdev);
1754         info->netdev = NULL;
1755 }
1756
1757 #endif /* ifdef CONFIG_HDLC */
1758
1759 /*
1760  * get async data from rx DMA buffers
1761  */
1762 static void rx_async(struct slgt_info *info)
1763 {
1764         struct mgsl_icount *icount = &info->icount;
1765         unsigned int start, end;
1766         unsigned char *p;
1767         unsigned char status;
1768         struct slgt_desc *bufs = info->rbufs;
1769         int i, count;
1770         int chars = 0;
1771         int stat;
1772         unsigned char ch;
1773
1774         start = end = info->rbuf_current;
1775
1776         while(desc_complete(bufs[end])) {
1777                 count = desc_count(bufs[end]) - info->rbuf_index;
1778                 p     = bufs[end].buf + info->rbuf_index;
1779
1780                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1781                 DBGDATA(info, p, count, "rx");
1782
1783                 for(i=0 ; i < count; i+=2, p+=2) {
1784                         ch = *p;
1785                         icount->rx++;
1786
1787                         stat = 0;
1788
1789                         status = *(p + 1) & (BIT1 + BIT0);
1790                         if (status) {
1791                                 if (status & BIT1)
1792                                         icount->parity++;
1793                                 else if (status & BIT0)
1794                                         icount->frame++;
1795                                 /* discard char if tty control flags say so */
1796                                 if (status & info->ignore_status_mask)
1797                                         continue;
1798                                 if (status & BIT1)
1799                                         stat = TTY_PARITY;
1800                                 else if (status & BIT0)
1801                                         stat = TTY_FRAME;
1802                         }
1803                         tty_insert_flip_char(&info->port, ch, stat);
1804                         chars++;
1805                 }
1806
1807                 if (i < count) {
1808                         /* receive buffer not completed */
1809                         info->rbuf_index += i;
1810                         mod_timer(&info->rx_timer, jiffies + 1);
1811                         break;
1812                 }
1813
1814                 info->rbuf_index = 0;
1815                 free_rbufs(info, end, end);
1816
1817                 if (++end == info->rbuf_count)
1818                         end = 0;
1819
1820                 /* if entire list searched then no frame available */
1821                 if (end == start)
1822                         break;
1823         }
1824
1825         if (chars)
1826                 tty_flip_buffer_push(&info->port);
1827 }
1828
1829 /*
1830  * return next bottom half action to perform
1831  */
1832 static int bh_action(struct slgt_info *info)
1833 {
1834         unsigned long flags;
1835         int rc;
1836
1837         spin_lock_irqsave(&info->lock,flags);
1838
1839         if (info->pending_bh & BH_RECEIVE) {
1840                 info->pending_bh &= ~BH_RECEIVE;
1841                 rc = BH_RECEIVE;
1842         } else if (info->pending_bh & BH_TRANSMIT) {
1843                 info->pending_bh &= ~BH_TRANSMIT;
1844                 rc = BH_TRANSMIT;
1845         } else if (info->pending_bh & BH_STATUS) {
1846                 info->pending_bh &= ~BH_STATUS;
1847                 rc = BH_STATUS;
1848         } else {
1849                 /* Mark BH routine as complete */
1850                 info->bh_running = false;
1851                 info->bh_requested = false;
1852                 rc = 0;
1853         }
1854
1855         spin_unlock_irqrestore(&info->lock,flags);
1856
1857         return rc;
1858 }
1859
1860 /*
1861  * perform bottom half processing
1862  */
1863 static void bh_handler(struct work_struct *work)
1864 {
1865         struct slgt_info *info = container_of(work, struct slgt_info, task);
1866         int action;
1867
1868         info->bh_running = true;
1869
1870         while((action = bh_action(info))) {
1871                 switch (action) {
1872                 case BH_RECEIVE:
1873                         DBGBH(("%s bh receive\n", info->device_name));
1874                         switch(info->params.mode) {
1875                         case MGSL_MODE_ASYNC:
1876                                 rx_async(info);
1877                                 break;
1878                         case MGSL_MODE_HDLC:
1879                                 while(rx_get_frame(info));
1880                                 break;
1881                         case MGSL_MODE_RAW:
1882                         case MGSL_MODE_MONOSYNC:
1883                         case MGSL_MODE_BISYNC:
1884                         case MGSL_MODE_XSYNC:
1885                                 while(rx_get_buf(info));
1886                                 break;
1887                         }
1888                         /* restart receiver if rx DMA buffers exhausted */
1889                         if (info->rx_restart)
1890                                 rx_start(info);
1891                         break;
1892                 case BH_TRANSMIT:
1893                         bh_transmit(info);
1894                         break;
1895                 case BH_STATUS:
1896                         DBGBH(("%s bh status\n", info->device_name));
1897                         info->ri_chkcount = 0;
1898                         info->dsr_chkcount = 0;
1899                         info->dcd_chkcount = 0;
1900                         info->cts_chkcount = 0;
1901                         break;
1902                 default:
1903                         DBGBH(("%s unknown action\n", info->device_name));
1904                         break;
1905                 }
1906         }
1907         DBGBH(("%s bh_handler exit\n", info->device_name));
1908 }
1909
1910 static void bh_transmit(struct slgt_info *info)
1911 {
1912         struct tty_struct *tty = info->port.tty;
1913
1914         DBGBH(("%s bh_transmit\n", info->device_name));
1915         if (tty)
1916                 tty_wakeup(tty);
1917 }
1918
1919 static void dsr_change(struct slgt_info *info, unsigned short status)
1920 {
1921         if (status & BIT3) {
1922                 info->signals |= SerialSignal_DSR;
1923                 info->input_signal_events.dsr_up++;
1924         } else {
1925                 info->signals &= ~SerialSignal_DSR;
1926                 info->input_signal_events.dsr_down++;
1927         }
1928         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1929         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1930                 slgt_irq_off(info, IRQ_DSR);
1931                 return;
1932         }
1933         info->icount.dsr++;
1934         wake_up_interruptible(&info->status_event_wait_q);
1935         wake_up_interruptible(&info->event_wait_q);
1936         info->pending_bh |= BH_STATUS;
1937 }
1938
1939 static void cts_change(struct slgt_info *info, unsigned short status)
1940 {
1941         if (status & BIT2) {
1942                 info->signals |= SerialSignal_CTS;
1943                 info->input_signal_events.cts_up++;
1944         } else {
1945                 info->signals &= ~SerialSignal_CTS;
1946                 info->input_signal_events.cts_down++;
1947         }
1948         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1949         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1950                 slgt_irq_off(info, IRQ_CTS);
1951                 return;
1952         }
1953         info->icount.cts++;
1954         wake_up_interruptible(&info->status_event_wait_q);
1955         wake_up_interruptible(&info->event_wait_q);
1956         info->pending_bh |= BH_STATUS;
1957
1958         if (tty_port_cts_enabled(&info->port)) {
1959                 if (info->port.tty) {
1960                         if (info->port.tty->hw_stopped) {
1961                                 if (info->signals & SerialSignal_CTS) {
1962                                         info->port.tty->hw_stopped = 0;
1963                                         info->pending_bh |= BH_TRANSMIT;
1964                                         return;
1965                                 }
1966                         } else {
1967                                 if (!(info->signals & SerialSignal_CTS))
1968                                         info->port.tty->hw_stopped = 1;
1969                         }
1970                 }
1971         }
1972 }
1973
1974 static void dcd_change(struct slgt_info *info, unsigned short status)
1975 {
1976         if (status & BIT1) {
1977                 info->signals |= SerialSignal_DCD;
1978                 info->input_signal_events.dcd_up++;
1979         } else {
1980                 info->signals &= ~SerialSignal_DCD;
1981                 info->input_signal_events.dcd_down++;
1982         }
1983         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1984         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1985                 slgt_irq_off(info, IRQ_DCD);
1986                 return;
1987         }
1988         info->icount.dcd++;
1989 #if SYNCLINK_GENERIC_HDLC
1990         if (info->netcount) {
1991                 if (info->signals & SerialSignal_DCD)
1992                         netif_carrier_on(info->netdev);
1993                 else
1994                         netif_carrier_off(info->netdev);
1995         }
1996 #endif
1997         wake_up_interruptible(&info->status_event_wait_q);
1998         wake_up_interruptible(&info->event_wait_q);
1999         info->pending_bh |= BH_STATUS;
2000
2001         if (tty_port_check_carrier(&info->port)) {
2002                 if (info->signals & SerialSignal_DCD)
2003                         wake_up_interruptible(&info->port.open_wait);
2004                 else {
2005                         if (info->port.tty)
2006                                 tty_hangup(info->port.tty);
2007                 }
2008         }
2009 }
2010
2011 static void ri_change(struct slgt_info *info, unsigned short status)
2012 {
2013         if (status & BIT0) {
2014                 info->signals |= SerialSignal_RI;
2015                 info->input_signal_events.ri_up++;
2016         } else {
2017                 info->signals &= ~SerialSignal_RI;
2018                 info->input_signal_events.ri_down++;
2019         }
2020         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2021         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2022                 slgt_irq_off(info, IRQ_RI);
2023                 return;
2024         }
2025         info->icount.rng++;
2026         wake_up_interruptible(&info->status_event_wait_q);
2027         wake_up_interruptible(&info->event_wait_q);
2028         info->pending_bh |= BH_STATUS;
2029 }
2030
2031 static void isr_rxdata(struct slgt_info *info)
2032 {
2033         unsigned int count = info->rbuf_fill_count;
2034         unsigned int i = info->rbuf_fill_index;
2035         unsigned short reg;
2036
2037         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2038                 reg = rd_reg16(info, RDR);
2039                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2040                 if (desc_complete(info->rbufs[i])) {
2041                         /* all buffers full */
2042                         rx_stop(info);
2043                         info->rx_restart = true;
2044                         continue;
2045                 }
2046                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2047                 /* async mode saves status byte to buffer for each data byte */
2048                 if (info->params.mode == MGSL_MODE_ASYNC)
2049                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2050                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2051                         /* buffer full or end of frame */
2052                         set_desc_count(info->rbufs[i], count);
2053                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2054                         info->rbuf_fill_count = count = 0;
2055                         if (++i == info->rbuf_count)
2056                                 i = 0;
2057                         info->pending_bh |= BH_RECEIVE;
2058                 }
2059         }
2060
2061         info->rbuf_fill_index = i;
2062         info->rbuf_fill_count = count;
2063 }
2064
2065 static void isr_serial(struct slgt_info *info)
2066 {
2067         unsigned short status = rd_reg16(info, SSR);
2068
2069         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2070
2071         wr_reg16(info, SSR, status); /* clear pending */
2072
2073         info->irq_occurred = true;
2074
2075         if (info->params.mode == MGSL_MODE_ASYNC) {
2076                 if (status & IRQ_TXIDLE) {
2077                         if (info->tx_active)
2078                                 isr_txeom(info, status);
2079                 }
2080                 if (info->rx_pio && (status & IRQ_RXDATA))
2081                         isr_rxdata(info);
2082                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2083                         info->icount.brk++;
2084                         /* process break detection if tty control allows */
2085                         if (info->port.tty) {
2086                                 if (!(status & info->ignore_status_mask)) {
2087                                         if (info->read_status_mask & MASK_BREAK) {
2088                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2089                                                 if (info->port.flags & ASYNC_SAK)
2090                                                         do_SAK(info->port.tty);
2091                                         }
2092                                 }
2093                         }
2094                 }
2095         } else {
2096                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2097                         isr_txeom(info, status);
2098                 if (info->rx_pio && (status & IRQ_RXDATA))
2099                         isr_rxdata(info);
2100                 if (status & IRQ_RXIDLE) {
2101                         if (status & RXIDLE)
2102                                 info->icount.rxidle++;
2103                         else
2104                                 info->icount.exithunt++;
2105                         wake_up_interruptible(&info->event_wait_q);
2106                 }
2107
2108                 if (status & IRQ_RXOVER)
2109                         rx_start(info);
2110         }
2111
2112         if (status & IRQ_DSR)
2113                 dsr_change(info, status);
2114         if (status & IRQ_CTS)
2115                 cts_change(info, status);
2116         if (status & IRQ_DCD)
2117                 dcd_change(info, status);
2118         if (status & IRQ_RI)
2119                 ri_change(info, status);
2120 }
2121
2122 static void isr_rdma(struct slgt_info *info)
2123 {
2124         unsigned int status = rd_reg32(info, RDCSR);
2125
2126         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2127
2128         /* RDCSR (rx DMA control/status)
2129          *
2130          * 31..07  reserved
2131          * 06      save status byte to DMA buffer
2132          * 05      error
2133          * 04      eol (end of list)
2134          * 03      eob (end of buffer)
2135          * 02      IRQ enable
2136          * 01      reset
2137          * 00      enable
2138          */
2139         wr_reg32(info, RDCSR, status);  /* clear pending */
2140
2141         if (status & (BIT5 + BIT4)) {
2142                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2143                 info->rx_restart = true;
2144         }
2145         info->pending_bh |= BH_RECEIVE;
2146 }
2147
2148 static void isr_tdma(struct slgt_info *info)
2149 {
2150         unsigned int status = rd_reg32(info, TDCSR);
2151
2152         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2153
2154         /* TDCSR (tx DMA control/status)
2155          *
2156          * 31..06  reserved
2157          * 05      error
2158          * 04      eol (end of list)
2159          * 03      eob (end of buffer)
2160          * 02      IRQ enable
2161          * 01      reset
2162          * 00      enable
2163          */
2164         wr_reg32(info, TDCSR, status);  /* clear pending */
2165
2166         if (status & (BIT5 + BIT4 + BIT3)) {
2167                 // another transmit buffer has completed
2168                 // run bottom half to get more send data from user
2169                 info->pending_bh |= BH_TRANSMIT;
2170         }
2171 }
2172
2173 /*
2174  * return true if there are unsent tx DMA buffers, otherwise false
2175  *
2176  * if there are unsent buffers then info->tbuf_start
2177  * is set to index of first unsent buffer
2178  */
2179 static bool unsent_tbufs(struct slgt_info *info)
2180 {
2181         unsigned int i = info->tbuf_current;
2182         bool rc = false;
2183
2184         /*
2185          * search backwards from last loaded buffer (precedes tbuf_current)
2186          * for first unsent buffer (desc_count > 0)
2187          */
2188
2189         do {
2190                 if (i)
2191                         i--;
2192                 else
2193                         i = info->tbuf_count - 1;
2194                 if (!desc_count(info->tbufs[i]))
2195                         break;
2196                 info->tbuf_start = i;
2197                 rc = true;
2198         } while (i != info->tbuf_current);
2199
2200         return rc;
2201 }
2202
2203 static void isr_txeom(struct slgt_info *info, unsigned short status)
2204 {
2205         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2206
2207         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2208         tdma_reset(info);
2209         if (status & IRQ_TXUNDER) {
2210                 unsigned short val = rd_reg16(info, TCR);
2211                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2212                 wr_reg16(info, TCR, val); /* clear reset bit */
2213         }
2214
2215         if (info->tx_active) {
2216                 if (info->params.mode != MGSL_MODE_ASYNC) {
2217                         if (status & IRQ_TXUNDER)
2218                                 info->icount.txunder++;
2219                         else if (status & IRQ_TXIDLE)
2220                                 info->icount.txok++;
2221                 }
2222
2223                 if (unsent_tbufs(info)) {
2224                         tx_start(info);
2225                         update_tx_timer(info);
2226                         return;
2227                 }
2228                 info->tx_active = false;
2229
2230                 del_timer(&info->tx_timer);
2231
2232                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2233                         info->signals &= ~SerialSignal_RTS;
2234                         info->drop_rts_on_tx_done = false;
2235                         set_signals(info);
2236                 }
2237
2238 #if SYNCLINK_GENERIC_HDLC
2239                 if (info->netcount)
2240                         hdlcdev_tx_done(info);
2241                 else
2242 #endif
2243                 {
2244                         if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2245                                 tx_stop(info);
2246                                 return;
2247                         }
2248                         info->pending_bh |= BH_TRANSMIT;
2249                 }
2250         }
2251 }
2252
2253 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2254 {
2255         struct cond_wait *w, *prev;
2256
2257         /* wake processes waiting for specific transitions */
2258         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2259                 if (w->data & changed) {
2260                         w->data = state;
2261                         wake_up_interruptible(&w->q);
2262                         if (prev != NULL)
2263                                 prev->next = w->next;
2264                         else
2265                                 info->gpio_wait_q = w->next;
2266                 } else
2267                         prev = w;
2268         }
2269 }
2270
2271 /* interrupt service routine
2272  *
2273  *      irq     interrupt number
2274  *      dev_id  device ID supplied during interrupt registration
2275  */
2276 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2277 {
2278         struct slgt_info *info = dev_id;
2279         unsigned int gsr;
2280         unsigned int i;
2281
2282         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2283
2284         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2285                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2286                 info->irq_occurred = true;
2287                 for(i=0; i < info->port_count ; i++) {
2288                         if (info->port_array[i] == NULL)
2289                                 continue;
2290                         spin_lock(&info->port_array[i]->lock);
2291                         if (gsr & (BIT8 << i))
2292                                 isr_serial(info->port_array[i]);
2293                         if (gsr & (BIT16 << (i*2)))
2294                                 isr_rdma(info->port_array[i]);
2295                         if (gsr & (BIT17 << (i*2)))
2296                                 isr_tdma(info->port_array[i]);
2297                         spin_unlock(&info->port_array[i]->lock);
2298                 }
2299         }
2300
2301         if (info->gpio_present) {
2302                 unsigned int state;
2303                 unsigned int changed;
2304                 spin_lock(&info->lock);
2305                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2306                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2307                         /* read latched state of GPIO signals */
2308                         state = rd_reg32(info, IOVR);
2309                         /* clear pending GPIO interrupt bits */
2310                         wr_reg32(info, IOSR, changed);
2311                         for (i=0 ; i < info->port_count ; i++) {
2312                                 if (info->port_array[i] != NULL)
2313                                         isr_gpio(info->port_array[i], changed, state);
2314                         }
2315                 }
2316                 spin_unlock(&info->lock);
2317         }
2318
2319         for(i=0; i < info->port_count ; i++) {
2320                 struct slgt_info *port = info->port_array[i];
2321                 if (port == NULL)
2322                         continue;
2323                 spin_lock(&port->lock);
2324                 if ((port->port.count || port->netcount) &&
2325                     port->pending_bh && !port->bh_running &&
2326                     !port->bh_requested) {
2327                         DBGISR(("%s bh queued\n", port->device_name));
2328                         schedule_work(&port->task);
2329                         port->bh_requested = true;
2330                 }
2331                 spin_unlock(&port->lock);
2332         }
2333
2334         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2335         return IRQ_HANDLED;
2336 }
2337
2338 static int startup(struct slgt_info *info)
2339 {
2340         DBGINFO(("%s startup\n", info->device_name));
2341
2342         if (tty_port_initialized(&info->port))
2343                 return 0;
2344
2345         if (!info->tx_buf) {
2346                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2347                 if (!info->tx_buf) {
2348                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2349                         return -ENOMEM;
2350                 }
2351         }
2352
2353         info->pending_bh = 0;
2354
2355         memset(&info->icount, 0, sizeof(info->icount));
2356
2357         /* program hardware for current parameters */
2358         change_params(info);
2359
2360         if (info->port.tty)
2361                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2362
2363         tty_port_set_initialized(&info->port, 1);
2364
2365         return 0;
2366 }
2367
2368 /*
2369  *  called by close() and hangup() to shutdown hardware
2370  */
2371 static void shutdown(struct slgt_info *info)
2372 {
2373         unsigned long flags;
2374
2375         if (!tty_port_initialized(&info->port))
2376                 return;
2377
2378         DBGINFO(("%s shutdown\n", info->device_name));
2379
2380         /* clear status wait queue because status changes */
2381         /* can't happen after shutting down the hardware */
2382         wake_up_interruptible(&info->status_event_wait_q);
2383         wake_up_interruptible(&info->event_wait_q);
2384
2385         del_timer_sync(&info->tx_timer);
2386         del_timer_sync(&info->rx_timer);
2387
2388         kfree(info->tx_buf);
2389         info->tx_buf = NULL;
2390
2391         spin_lock_irqsave(&info->lock,flags);
2392
2393         tx_stop(info);
2394         rx_stop(info);
2395
2396         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2397
2398         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2399                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2400                 set_signals(info);
2401         }
2402
2403         flush_cond_wait(&info->gpio_wait_q);
2404
2405         spin_unlock_irqrestore(&info->lock,flags);
2406
2407         if (info->port.tty)
2408                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2409
2410         tty_port_set_initialized(&info->port, 0);
2411 }
2412
2413 static void program_hw(struct slgt_info *info)
2414 {
2415         unsigned long flags;
2416
2417         spin_lock_irqsave(&info->lock,flags);
2418
2419         rx_stop(info);
2420         tx_stop(info);
2421
2422         if (info->params.mode != MGSL_MODE_ASYNC ||
2423             info->netcount)
2424                 sync_mode(info);
2425         else
2426                 async_mode(info);
2427
2428         set_signals(info);
2429
2430         info->dcd_chkcount = 0;
2431         info->cts_chkcount = 0;
2432         info->ri_chkcount = 0;
2433         info->dsr_chkcount = 0;
2434
2435         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2436         get_signals(info);
2437
2438         if (info->netcount ||
2439             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2440                 rx_start(info);
2441
2442         spin_unlock_irqrestore(&info->lock,flags);
2443 }
2444
2445 /*
2446  * reconfigure adapter based on new parameters
2447  */
2448 static void change_params(struct slgt_info *info)
2449 {
2450         unsigned cflag;
2451         int bits_per_char;
2452
2453         if (!info->port.tty)
2454                 return;
2455         DBGINFO(("%s change_params\n", info->device_name));
2456
2457         cflag = info->port.tty->termios.c_cflag;
2458
2459         /* if B0 rate (hangup) specified then negate RTS and DTR */
2460         /* otherwise assert RTS and DTR */
2461         if (cflag & CBAUD)
2462                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2463         else
2464                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2465
2466         /* byte size and parity */
2467
2468         info->params.data_bits = tty_get_char_size(cflag);
2469         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2470
2471         if (cflag & PARENB)
2472                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2473         else
2474                 info->params.parity = ASYNC_PARITY_NONE;
2475
2476         /* calculate number of jiffies to transmit a full
2477          * FIFO (32 bytes) at specified data rate
2478          */
2479         bits_per_char = info->params.data_bits +
2480                         info->params.stop_bits + 1;
2481
2482         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2483
2484         if (info->params.data_rate) {
2485                 info->timeout = (32*HZ*bits_per_char) /
2486                                 info->params.data_rate;
2487         }
2488         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2489
2490         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2491         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2492
2493         /* process tty input control flags */
2494
2495         info->read_status_mask = IRQ_RXOVER;
2496         if (I_INPCK(info->port.tty))
2497                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2498         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2499                 info->read_status_mask |= MASK_BREAK;
2500         if (I_IGNPAR(info->port.tty))
2501                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2502         if (I_IGNBRK(info->port.tty)) {
2503                 info->ignore_status_mask |= MASK_BREAK;
2504                 /* If ignoring parity and break indicators, ignore
2505                  * overruns too.  (For real raw support).
2506                  */
2507                 if (I_IGNPAR(info->port.tty))
2508                         info->ignore_status_mask |= MASK_OVERRUN;
2509         }
2510
2511         program_hw(info);
2512 }
2513
2514 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2515 {
2516         DBGINFO(("%s get_stats\n",  info->device_name));
2517         if (!user_icount) {
2518                 memset(&info->icount, 0, sizeof(info->icount));
2519         } else {
2520                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2521                         return -EFAULT;
2522         }
2523         return 0;
2524 }
2525
2526 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2527 {
2528         DBGINFO(("%s get_params\n", info->device_name));
2529         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2530                 return -EFAULT;
2531         return 0;
2532 }
2533
2534 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2535 {
2536         unsigned long flags;
2537         MGSL_PARAMS tmp_params;
2538
2539         DBGINFO(("%s set_params\n", info->device_name));
2540         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2541                 return -EFAULT;
2542
2543         spin_lock_irqsave(&info->lock, flags);
2544         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2545                 info->base_clock = tmp_params.clock_speed;
2546         else
2547                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2548         spin_unlock_irqrestore(&info->lock, flags);
2549
2550         program_hw(info);
2551
2552         return 0;
2553 }
2554
2555 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2556 {
2557         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2558         if (put_user(info->idle_mode, idle_mode))
2559                 return -EFAULT;
2560         return 0;
2561 }
2562
2563 static int set_txidle(struct slgt_info *info, int idle_mode)
2564 {
2565         unsigned long flags;
2566         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2567         spin_lock_irqsave(&info->lock,flags);
2568         info->idle_mode = idle_mode;
2569         if (info->params.mode != MGSL_MODE_ASYNC)
2570                 tx_set_idle(info);
2571         spin_unlock_irqrestore(&info->lock,flags);
2572         return 0;
2573 }
2574
2575 static int tx_enable(struct slgt_info *info, int enable)
2576 {
2577         unsigned long flags;
2578         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2579         spin_lock_irqsave(&info->lock,flags);
2580         if (enable) {
2581                 if (!info->tx_enabled)
2582                         tx_start(info);
2583         } else {
2584                 if (info->tx_enabled)
2585                         tx_stop(info);
2586         }
2587         spin_unlock_irqrestore(&info->lock,flags);
2588         return 0;
2589 }
2590
2591 /*
2592  * abort transmit HDLC frame
2593  */
2594 static int tx_abort(struct slgt_info *info)
2595 {
2596         unsigned long flags;
2597         DBGINFO(("%s tx_abort\n", info->device_name));
2598         spin_lock_irqsave(&info->lock,flags);
2599         tdma_reset(info);
2600         spin_unlock_irqrestore(&info->lock,flags);
2601         return 0;
2602 }
2603
2604 static int rx_enable(struct slgt_info *info, int enable)
2605 {
2606         unsigned long flags;
2607         unsigned int rbuf_fill_level;
2608         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2609         spin_lock_irqsave(&info->lock,flags);
2610         /*
2611          * enable[31..16] = receive DMA buffer fill level
2612          * 0 = noop (leave fill level unchanged)
2613          * fill level must be multiple of 4 and <= buffer size
2614          */
2615         rbuf_fill_level = ((unsigned int)enable) >> 16;
2616         if (rbuf_fill_level) {
2617                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2618                         spin_unlock_irqrestore(&info->lock, flags);
2619                         return -EINVAL;
2620                 }
2621                 info->rbuf_fill_level = rbuf_fill_level;
2622                 if (rbuf_fill_level < 128)
2623                         info->rx_pio = 1; /* PIO mode */
2624                 else
2625                         info->rx_pio = 0; /* DMA mode */
2626                 rx_stop(info); /* restart receiver to use new fill level */
2627         }
2628
2629         /*
2630          * enable[1..0] = receiver enable command
2631          * 0 = disable
2632          * 1 = enable
2633          * 2 = enable or force hunt mode if already enabled
2634          */
2635         enable &= 3;
2636         if (enable) {
2637                 if (!info->rx_enabled)
2638                         rx_start(info);
2639                 else if (enable == 2) {
2640                         /* force hunt mode (write 1 to RCR[3]) */
2641                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2642                 }
2643         } else {
2644                 if (info->rx_enabled)
2645                         rx_stop(info);
2646         }
2647         spin_unlock_irqrestore(&info->lock,flags);
2648         return 0;
2649 }
2650
2651 /*
2652  *  wait for specified event to occur
2653  */
2654 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2655 {
2656         unsigned long flags;
2657         int s;
2658         int rc=0;
2659         struct mgsl_icount cprev, cnow;
2660         int events;
2661         int mask;
2662         struct  _input_signal_events oldsigs, newsigs;
2663         DECLARE_WAITQUEUE(wait, current);
2664
2665         if (get_user(mask, mask_ptr))
2666                 return -EFAULT;
2667
2668         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2669
2670         spin_lock_irqsave(&info->lock,flags);
2671
2672         /* return immediately if state matches requested events */
2673         get_signals(info);
2674         s = info->signals;
2675
2676         events = mask &
2677                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2678                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2679                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2680                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2681         if (events) {
2682                 spin_unlock_irqrestore(&info->lock,flags);
2683                 goto exit;
2684         }
2685
2686         /* save current irq counts */
2687         cprev = info->icount;
2688         oldsigs = info->input_signal_events;
2689
2690         /* enable hunt and idle irqs if needed */
2691         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2692                 unsigned short val = rd_reg16(info, SCR);
2693                 if (!(val & IRQ_RXIDLE))
2694                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2695         }
2696
2697         set_current_state(TASK_INTERRUPTIBLE);
2698         add_wait_queue(&info->event_wait_q, &wait);
2699
2700         spin_unlock_irqrestore(&info->lock,flags);
2701
2702         for(;;) {
2703                 schedule();
2704                 if (signal_pending(current)) {
2705                         rc = -ERESTARTSYS;
2706                         break;
2707                 }
2708
2709                 /* get current irq counts */
2710                 spin_lock_irqsave(&info->lock,flags);
2711                 cnow = info->icount;
2712                 newsigs = info->input_signal_events;
2713                 set_current_state(TASK_INTERRUPTIBLE);
2714                 spin_unlock_irqrestore(&info->lock,flags);
2715
2716                 /* if no change, wait aborted for some reason */
2717                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2718                     newsigs.dsr_down == oldsigs.dsr_down &&
2719                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2720                     newsigs.dcd_down == oldsigs.dcd_down &&
2721                     newsigs.cts_up   == oldsigs.cts_up   &&
2722                     newsigs.cts_down == oldsigs.cts_down &&
2723                     newsigs.ri_up    == oldsigs.ri_up    &&
2724                     newsigs.ri_down  == oldsigs.ri_down  &&
2725                     cnow.exithunt    == cprev.exithunt   &&
2726                     cnow.rxidle      == cprev.rxidle) {
2727                         rc = -EIO;
2728                         break;
2729                 }
2730
2731                 events = mask &
2732                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2733                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2734                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2735                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2736                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2737                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2738                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2739                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2740                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2741                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2742                 if (events)
2743                         break;
2744
2745                 cprev = cnow;
2746                 oldsigs = newsigs;
2747         }
2748
2749         remove_wait_queue(&info->event_wait_q, &wait);
2750         set_current_state(TASK_RUNNING);
2751
2752
2753         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2754                 spin_lock_irqsave(&info->lock,flags);
2755                 if (!waitqueue_active(&info->event_wait_q)) {
2756                         /* disable enable exit hunt mode/idle rcvd IRQs */
2757                         wr_reg16(info, SCR,
2758                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2759                 }
2760                 spin_unlock_irqrestore(&info->lock,flags);
2761         }
2762 exit:
2763         if (rc == 0)
2764                 rc = put_user(events, mask_ptr);
2765         return rc;
2766 }
2767
2768 static int get_interface(struct slgt_info *info, int __user *if_mode)
2769 {
2770         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2771         if (put_user(info->if_mode, if_mode))
2772                 return -EFAULT;
2773         return 0;
2774 }
2775
2776 static int set_interface(struct slgt_info *info, int if_mode)
2777 {
2778         unsigned long flags;
2779         unsigned short val;
2780
2781         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2782         spin_lock_irqsave(&info->lock,flags);
2783         info->if_mode = if_mode;
2784
2785         msc_set_vcr(info);
2786
2787         /* TCR (tx control) 07  1=RTS driver control */
2788         val = rd_reg16(info, TCR);
2789         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2790                 val |= BIT7;
2791         else
2792                 val &= ~BIT7;
2793         wr_reg16(info, TCR, val);
2794
2795         spin_unlock_irqrestore(&info->lock,flags);
2796         return 0;
2797 }
2798
2799 static int get_xsync(struct slgt_info *info, int __user *xsync)
2800 {
2801         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2802         if (put_user(info->xsync, xsync))
2803                 return -EFAULT;
2804         return 0;
2805 }
2806
2807 /*
2808  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2809  *
2810  * sync pattern is contained in least significant bytes of value
2811  * most significant byte of sync pattern is oldest (1st sent/detected)
2812  */
2813 static int set_xsync(struct slgt_info *info, int xsync)
2814 {
2815         unsigned long flags;
2816
2817         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2818         spin_lock_irqsave(&info->lock, flags);
2819         info->xsync = xsync;
2820         wr_reg32(info, XSR, xsync);
2821         spin_unlock_irqrestore(&info->lock, flags);
2822         return 0;
2823 }
2824
2825 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2826 {
2827         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2828         if (put_user(info->xctrl, xctrl))
2829                 return -EFAULT;
2830         return 0;
2831 }
2832
2833 /*
2834  * set extended control options
2835  *
2836  * xctrl[31:19] reserved, must be zero
2837  * xctrl[18:17] extended sync pattern length in bytes
2838  *              00 = 1 byte  in xsr[7:0]
2839  *              01 = 2 bytes in xsr[15:0]
2840  *              10 = 3 bytes in xsr[23:0]
2841  *              11 = 4 bytes in xsr[31:0]
2842  * xctrl[16]    1 = enable terminal count, 0=disabled
2843  * xctrl[15:0]  receive terminal count for fixed length packets
2844  *              value is count minus one (0 = 1 byte packet)
2845  *              when terminal count is reached, receiver
2846  *              automatically returns to hunt mode and receive
2847  *              FIFO contents are flushed to DMA buffers with
2848  *              end of frame (EOF) status
2849  */
2850 static int set_xctrl(struct slgt_info *info, int xctrl)
2851 {
2852         unsigned long flags;
2853
2854         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2855         spin_lock_irqsave(&info->lock, flags);
2856         info->xctrl = xctrl;
2857         wr_reg32(info, XCR, xctrl);
2858         spin_unlock_irqrestore(&info->lock, flags);
2859         return 0;
2860 }
2861
2862 /*
2863  * set general purpose IO pin state and direction
2864  *
2865  * user_gpio fields:
2866  * state   each bit indicates a pin state
2867  * smask   set bit indicates pin state to set
2868  * dir     each bit indicates a pin direction (0=input, 1=output)
2869  * dmask   set bit indicates pin direction to set
2870  */
2871 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2872 {
2873         unsigned long flags;
2874         struct gpio_desc gpio;
2875         __u32 data;
2876
2877         if (!info->gpio_present)
2878                 return -EINVAL;
2879         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2880                 return -EFAULT;
2881         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2882                  info->device_name, gpio.state, gpio.smask,
2883                  gpio.dir, gpio.dmask));
2884
2885         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2886         if (gpio.dmask) {
2887                 data = rd_reg32(info, IODR);
2888                 data |= gpio.dmask & gpio.dir;
2889                 data &= ~(gpio.dmask & ~gpio.dir);
2890                 wr_reg32(info, IODR, data);
2891         }
2892         if (gpio.smask) {
2893                 data = rd_reg32(info, IOVR);
2894                 data |= gpio.smask & gpio.state;
2895                 data &= ~(gpio.smask & ~gpio.state);
2896                 wr_reg32(info, IOVR, data);
2897         }
2898         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2899
2900         return 0;
2901 }
2902
2903 /*
2904  * get general purpose IO pin state and direction
2905  */
2906 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2907 {
2908         struct gpio_desc gpio;
2909         if (!info->gpio_present)
2910                 return -EINVAL;
2911         gpio.state = rd_reg32(info, IOVR);
2912         gpio.smask = 0xffffffff;
2913         gpio.dir   = rd_reg32(info, IODR);
2914         gpio.dmask = 0xffffffff;
2915         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2916                 return -EFAULT;
2917         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2918                  info->device_name, gpio.state, gpio.dir));
2919         return 0;
2920 }
2921
2922 /*
2923  * conditional wait facility
2924  */
2925 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2926 {
2927         init_waitqueue_head(&w->q);
2928         init_waitqueue_entry(&w->wait, current);
2929         w->data = data;
2930 }
2931
2932 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2933 {
2934         set_current_state(TASK_INTERRUPTIBLE);
2935         add_wait_queue(&w->q, &w->wait);
2936         w->next = *head;
2937         *head = w;
2938 }
2939
2940 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2941 {
2942         struct cond_wait *w, *prev;
2943         remove_wait_queue(&cw->q, &cw->wait);
2944         set_current_state(TASK_RUNNING);
2945         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2946                 if (w == cw) {
2947                         if (prev != NULL)
2948                                 prev->next = w->next;
2949                         else
2950                                 *head = w->next;
2951                         break;
2952                 }
2953         }
2954 }
2955
2956 static void flush_cond_wait(struct cond_wait **head)
2957 {
2958         while (*head != NULL) {
2959                 wake_up_interruptible(&(*head)->q);
2960                 *head = (*head)->next;
2961         }
2962 }
2963
2964 /*
2965  * wait for general purpose I/O pin(s) to enter specified state
2966  *
2967  * user_gpio fields:
2968  * state - bit indicates target pin state
2969  * smask - set bit indicates watched pin
2970  *
2971  * The wait ends when at least one watched pin enters the specified
2972  * state. When 0 (no error) is returned, user_gpio->state is set to the
2973  * state of all GPIO pins when the wait ends.
2974  *
2975  * Note: Each pin may be a dedicated input, dedicated output, or
2976  * configurable input/output. The number and configuration of pins
2977  * varies with the specific adapter model. Only input pins (dedicated
2978  * or configured) can be monitored with this function.
2979  */
2980 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2981 {
2982         unsigned long flags;
2983         int rc = 0;
2984         struct gpio_desc gpio;
2985         struct cond_wait wait;
2986         u32 state;
2987
2988         if (!info->gpio_present)
2989                 return -EINVAL;
2990         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2991                 return -EFAULT;
2992         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2993                  info->device_name, gpio.state, gpio.smask));
2994         /* ignore output pins identified by set IODR bit */
2995         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2996                 return -EINVAL;
2997         init_cond_wait(&wait, gpio.smask);
2998
2999         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3000         /* enable interrupts for watched pins */
3001         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3002         /* get current pin states */
3003         state = rd_reg32(info, IOVR);
3004
3005         if (gpio.smask & ~(state ^ gpio.state)) {
3006                 /* already in target state */
3007                 gpio.state = state;
3008         } else {
3009                 /* wait for target state */
3010                 add_cond_wait(&info->gpio_wait_q, &wait);
3011                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3012                 schedule();
3013                 if (signal_pending(current))
3014                         rc = -ERESTARTSYS;
3015                 else
3016                         gpio.state = wait.data;
3017                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3018                 remove_cond_wait(&info->gpio_wait_q, &wait);
3019         }
3020
3021         /* disable all GPIO interrupts if no waiting processes */
3022         if (info->gpio_wait_q == NULL)
3023                 wr_reg32(info, IOER, 0);
3024         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3025
3026         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3027                 rc = -EFAULT;
3028         return rc;
3029 }
3030
3031 static int modem_input_wait(struct slgt_info *info,int arg)
3032 {
3033         unsigned long flags;
3034         int rc;
3035         struct mgsl_icount cprev, cnow;
3036         DECLARE_WAITQUEUE(wait, current);
3037
3038         /* save current irq counts */
3039         spin_lock_irqsave(&info->lock,flags);
3040         cprev = info->icount;
3041         add_wait_queue(&info->status_event_wait_q, &wait);
3042         set_current_state(TASK_INTERRUPTIBLE);
3043         spin_unlock_irqrestore(&info->lock,flags);
3044
3045         for(;;) {
3046                 schedule();
3047                 if (signal_pending(current)) {
3048                         rc = -ERESTARTSYS;
3049                         break;
3050                 }
3051
3052                 /* get new irq counts */
3053                 spin_lock_irqsave(&info->lock,flags);
3054                 cnow = info->icount;
3055                 set_current_state(TASK_INTERRUPTIBLE);
3056                 spin_unlock_irqrestore(&info->lock,flags);
3057
3058                 /* if no change, wait aborted for some reason */
3059                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3060                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3061                         rc = -EIO;
3062                         break;
3063                 }
3064
3065                 /* check for change in caller specified modem input */
3066                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3067                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3068                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3069                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3070                         rc = 0;
3071                         break;
3072                 }
3073
3074                 cprev = cnow;
3075         }
3076         remove_wait_queue(&info->status_event_wait_q, &wait);
3077         set_current_state(TASK_RUNNING);
3078         return rc;
3079 }
3080
3081 /*
3082  *  return state of serial control and status signals
3083  */
3084 static int tiocmget(struct tty_struct *tty)
3085 {
3086         struct slgt_info *info = tty->driver_data;
3087         unsigned int result;
3088         unsigned long flags;
3089
3090         spin_lock_irqsave(&info->lock,flags);
3091         get_signals(info);
3092         spin_unlock_irqrestore(&info->lock,flags);
3093
3094         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3095                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3096                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3097                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3098                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3099                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3100
3101         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3102         return result;
3103 }
3104
3105 /*
3106  * set modem control signals (DTR/RTS)
3107  *
3108  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3109  *              TIOCMSET = set/clear signal values
3110  *      value   bit mask for command
3111  */
3112 static int tiocmset(struct tty_struct *tty,
3113                     unsigned int set, unsigned int clear)
3114 {
3115         struct slgt_info *info = tty->driver_data;
3116         unsigned long flags;
3117
3118         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3119
3120         if (set & TIOCM_RTS)
3121                 info->signals |= SerialSignal_RTS;
3122         if (set & TIOCM_DTR)
3123                 info->signals |= SerialSignal_DTR;
3124         if (clear & TIOCM_RTS)
3125                 info->signals &= ~SerialSignal_RTS;
3126         if (clear & TIOCM_DTR)
3127                 info->signals &= ~SerialSignal_DTR;
3128
3129         spin_lock_irqsave(&info->lock,flags);
3130         set_signals(info);
3131         spin_unlock_irqrestore(&info->lock,flags);
3132         return 0;
3133 }
3134
3135 static int carrier_raised(struct tty_port *port)
3136 {
3137         unsigned long flags;
3138         struct slgt_info *info = container_of(port, struct slgt_info, port);
3139
3140         spin_lock_irqsave(&info->lock,flags);
3141         get_signals(info);
3142         spin_unlock_irqrestore(&info->lock,flags);
3143         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3144 }
3145
3146 static void dtr_rts(struct tty_port *port, int on)
3147 {
3148         unsigned long flags;
3149         struct slgt_info *info = container_of(port, struct slgt_info, port);
3150
3151         spin_lock_irqsave(&info->lock,flags);
3152         if (on)
3153                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3154         else
3155                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3156         set_signals(info);
3157         spin_unlock_irqrestore(&info->lock,flags);
3158 }
3159
3160
3161 /*
3162  *  block current process until the device is ready to open
3163  */
3164 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3165                            struct slgt_info *info)
3166 {
3167         DECLARE_WAITQUEUE(wait, current);
3168         int             retval;
3169         bool            do_clocal = false;
3170         unsigned long   flags;
3171         int             cd;
3172         struct tty_port *port = &info->port;
3173
3174         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3175
3176         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3177                 /* nonblock mode is set or port is not enabled */
3178                 tty_port_set_active(port, 1);
3179                 return 0;
3180         }
3181
3182         if (C_CLOCAL(tty))
3183                 do_clocal = true;
3184
3185         /* Wait for carrier detect and the line to become
3186          * free (i.e., not in use by the callout).  While we are in
3187          * this loop, port->count is dropped by one, so that
3188          * close() knows when to free things.  We restore it upon
3189          * exit, either normal or abnormal.
3190          */
3191
3192         retval = 0;
3193         add_wait_queue(&port->open_wait, &wait);
3194
3195         spin_lock_irqsave(&info->lock, flags);
3196         port->count--;
3197         spin_unlock_irqrestore(&info->lock, flags);
3198         port->blocked_open++;
3199
3200         while (1) {
3201                 if (C_BAUD(tty) && tty_port_initialized(port))
3202                         tty_port_raise_dtr_rts(port);
3203
3204                 set_current_state(TASK_INTERRUPTIBLE);
3205
3206                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3207                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3208                                         -EAGAIN : -ERESTARTSYS;
3209                         break;
3210                 }
3211
3212                 cd = tty_port_carrier_raised(port);
3213                 if (do_clocal || cd)
3214                         break;
3215
3216                 if (signal_pending(current)) {
3217                         retval = -ERESTARTSYS;
3218                         break;
3219                 }
3220
3221                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3222                 tty_unlock(tty);
3223                 schedule();
3224                 tty_lock(tty);
3225         }
3226
3227         set_current_state(TASK_RUNNING);
3228         remove_wait_queue(&port->open_wait, &wait);
3229
3230         if (!tty_hung_up_p(filp))
3231                 port->count++;
3232         port->blocked_open--;
3233
3234         if (!retval)
3235                 tty_port_set_active(port, 1);
3236
3237         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3238         return retval;
3239 }
3240
3241 /*
3242  * allocate buffers used for calling line discipline receive_buf
3243  * directly in synchronous mode
3244  * note: add 5 bytes to max frame size to allow appending
3245  * 32-bit CRC and status byte when configured to do so
3246  */
3247 static int alloc_tmp_rbuf(struct slgt_info *info)
3248 {
3249         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3250         if (info->tmp_rbuf == NULL)
3251                 return -ENOMEM;
3252         /* unused flag buffer to satisfy receive_buf calling interface */
3253         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3254         if (!info->flag_buf) {
3255                 kfree(info->tmp_rbuf);
3256                 info->tmp_rbuf = NULL;
3257                 return -ENOMEM;
3258         }
3259         return 0;
3260 }
3261
3262 static void free_tmp_rbuf(struct slgt_info *info)
3263 {
3264         kfree(info->tmp_rbuf);
3265         info->tmp_rbuf = NULL;
3266         kfree(info->flag_buf);
3267         info->flag_buf = NULL;
3268 }
3269
3270 /*
3271  * allocate DMA descriptor lists.
3272  */
3273 static int alloc_desc(struct slgt_info *info)
3274 {
3275         unsigned int i;
3276         unsigned int pbufs;
3277
3278         /* allocate memory to hold descriptor lists */
3279         info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3280                                         &info->bufs_dma_addr, GFP_KERNEL);
3281         if (info->bufs == NULL)
3282                 return -ENOMEM;
3283
3284         info->rbufs = (struct slgt_desc*)info->bufs;
3285         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3286
3287         pbufs = (unsigned int)info->bufs_dma_addr;
3288
3289         /*
3290          * Build circular lists of descriptors
3291          */
3292
3293         for (i=0; i < info->rbuf_count; i++) {
3294                 /* physical address of this descriptor */
3295                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3296
3297                 /* physical address of next descriptor */
3298                 if (i == info->rbuf_count - 1)
3299                         info->rbufs[i].next = cpu_to_le32(pbufs);
3300                 else
3301                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3302                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3303         }
3304
3305         for (i=0; i < info->tbuf_count; i++) {
3306                 /* physical address of this descriptor */
3307                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3308
3309                 /* physical address of next descriptor */
3310                 if (i == info->tbuf_count - 1)
3311                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3312                 else
3313                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3314         }
3315
3316         return 0;
3317 }
3318
3319 static void free_desc(struct slgt_info *info)
3320 {
3321         if (info->bufs != NULL) {
3322                 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3323                                   info->bufs, info->bufs_dma_addr);
3324                 info->bufs  = NULL;
3325                 info->rbufs = NULL;
3326                 info->tbufs = NULL;
3327         }
3328 }
3329
3330 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3331 {
3332         int i;
3333         for (i=0; i < count; i++) {
3334                 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3335                                                  &bufs[i].buf_dma_addr, GFP_KERNEL);
3336                 if (!bufs[i].buf)
3337                         return -ENOMEM;
3338                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3339         }
3340         return 0;
3341 }
3342
3343 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3344 {
3345         int i;
3346         for (i=0; i < count; i++) {
3347                 if (bufs[i].buf == NULL)
3348                         continue;
3349                 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3350                                   bufs[i].buf_dma_addr);
3351                 bufs[i].buf = NULL;
3352         }
3353 }
3354
3355 static int alloc_dma_bufs(struct slgt_info *info)
3356 {
3357         info->rbuf_count = 32;
3358         info->tbuf_count = 32;
3359
3360         if (alloc_desc(info) < 0 ||
3361             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3362             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3363             alloc_tmp_rbuf(info) < 0) {
3364                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3365                 return -ENOMEM;
3366         }
3367         reset_rbufs(info);
3368         return 0;
3369 }
3370
3371 static void free_dma_bufs(struct slgt_info *info)
3372 {
3373         if (info->bufs) {
3374                 free_bufs(info, info->rbufs, info->rbuf_count);
3375                 free_bufs(info, info->tbufs, info->tbuf_count);
3376                 free_desc(info);
3377         }
3378         free_tmp_rbuf(info);
3379 }
3380
3381 static int claim_resources(struct slgt_info *info)
3382 {
3383         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3384                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3385                         info->device_name, info->phys_reg_addr));
3386                 info->init_error = DiagStatus_AddressConflict;
3387                 goto errout;
3388         }
3389         else
3390                 info->reg_addr_requested = true;
3391
3392         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3393         if (!info->reg_addr) {
3394                 DBGERR(("%s can't map device registers, addr=%08X\n",
3395                         info->device_name, info->phys_reg_addr));
3396                 info->init_error = DiagStatus_CantAssignPciResources;
3397                 goto errout;
3398         }
3399         return 0;
3400
3401 errout:
3402         release_resources(info);
3403         return -ENODEV;
3404 }
3405
3406 static void release_resources(struct slgt_info *info)
3407 {
3408         if (info->irq_requested) {
3409                 free_irq(info->irq_level, info);
3410                 info->irq_requested = false;
3411         }
3412
3413         if (info->reg_addr_requested) {
3414                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3415                 info->reg_addr_requested = false;
3416         }
3417
3418         if (info->reg_addr) {
3419                 iounmap(info->reg_addr);
3420                 info->reg_addr = NULL;
3421         }
3422 }
3423
3424 /* Add the specified device instance data structure to the
3425  * global linked list of devices and increment the device count.
3426  */
3427 static void add_device(struct slgt_info *info)
3428 {
3429         char *devstr;
3430
3431         info->next_device = NULL;
3432         info->line = slgt_device_count;
3433         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3434
3435         if (info->line < MAX_DEVICES) {
3436                 if (maxframe[info->line])
3437                         info->max_frame_size = maxframe[info->line];
3438         }
3439
3440         slgt_device_count++;
3441
3442         if (!slgt_device_list)
3443                 slgt_device_list = info;
3444         else {
3445                 struct slgt_info *current_dev = slgt_device_list;
3446                 while(current_dev->next_device)
3447                         current_dev = current_dev->next_device;
3448                 current_dev->next_device = info;
3449         }
3450
3451         if (info->max_frame_size < 4096)
3452                 info->max_frame_size = 4096;
3453         else if (info->max_frame_size > 65535)
3454                 info->max_frame_size = 65535;
3455
3456         switch(info->pdev->device) {
3457         case SYNCLINK_GT_DEVICE_ID:
3458                 devstr = "GT";
3459                 break;
3460         case SYNCLINK_GT2_DEVICE_ID:
3461                 devstr = "GT2";
3462                 break;
3463         case SYNCLINK_GT4_DEVICE_ID:
3464                 devstr = "GT4";
3465                 break;
3466         case SYNCLINK_AC_DEVICE_ID:
3467                 devstr = "AC";
3468                 info->params.mode = MGSL_MODE_ASYNC;
3469                 break;
3470         default:
3471                 devstr = "(unknown model)";
3472         }
3473         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3474                 devstr, info->device_name, info->phys_reg_addr,
3475                 info->irq_level, info->max_frame_size);
3476
3477 #if SYNCLINK_GENERIC_HDLC
3478         hdlcdev_init(info);
3479 #endif
3480 }
3481
3482 static const struct tty_port_operations slgt_port_ops = {
3483         .carrier_raised = carrier_raised,
3484         .dtr_rts = dtr_rts,
3485 };
3486
3487 /*
3488  *  allocate device instance structure, return NULL on failure
3489  */
3490 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3491 {
3492         struct slgt_info *info;
3493
3494         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3495
3496         if (!info) {
3497                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3498                         driver_name, adapter_num, port_num));
3499         } else {
3500                 tty_port_init(&info->port);
3501                 info->port.ops = &slgt_port_ops;
3502                 info->magic = MGSL_MAGIC;
3503                 INIT_WORK(&info->task, bh_handler);
3504                 info->max_frame_size = 4096;
3505                 info->base_clock = 14745600;
3506                 info->rbuf_fill_level = DMABUFSIZE;
3507                 init_waitqueue_head(&info->status_event_wait_q);
3508                 init_waitqueue_head(&info->event_wait_q);
3509                 spin_lock_init(&info->netlock);
3510                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3511                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3512                 info->adapter_num = adapter_num;
3513                 info->port_num = port_num;
3514
3515                 timer_setup(&info->tx_timer, tx_timeout, 0);
3516                 timer_setup(&info->rx_timer, rx_timeout, 0);
3517
3518                 /* Copy configuration info to device instance data */
3519                 info->pdev = pdev;
3520                 info->irq_level = pdev->irq;
3521                 info->phys_reg_addr = pci_resource_start(pdev,0);
3522
3523                 info->bus_type = MGSL_BUS_TYPE_PCI;
3524                 info->irq_flags = IRQF_SHARED;
3525
3526                 info->init_error = -1; /* assume error, set to 0 on successful init */
3527         }
3528
3529         return info;
3530 }
3531
3532 static void device_init(int adapter_num, struct pci_dev *pdev)
3533 {
3534         struct slgt_info *port_array[SLGT_MAX_PORTS];
3535         int i;
3536         int port_count = 1;
3537
3538         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3539                 port_count = 2;
3540         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3541                 port_count = 4;
3542
3543         /* allocate device instances for all ports */
3544         for (i=0; i < port_count; ++i) {
3545                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3546                 if (port_array[i] == NULL) {
3547                         for (--i; i >= 0; --i) {
3548                                 tty_port_destroy(&port_array[i]->port);
3549                                 kfree(port_array[i]);
3550                         }
3551                         return;
3552                 }
3553         }
3554
3555         /* give copy of port_array to all ports and add to device list  */
3556         for (i=0; i < port_count; ++i) {
3557                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3558                 add_device(port_array[i]);
3559                 port_array[i]->port_count = port_count;
3560                 spin_lock_init(&port_array[i]->lock);
3561         }
3562
3563         /* Allocate and claim adapter resources */
3564         if (!claim_resources(port_array[0])) {
3565
3566                 alloc_dma_bufs(port_array[0]);
3567
3568                 /* copy resource information from first port to others */
3569                 for (i = 1; i < port_count; ++i) {
3570                         port_array[i]->irq_level = port_array[0]->irq_level;
3571                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3572                         alloc_dma_bufs(port_array[i]);
3573                 }
3574
3575                 if (request_irq(port_array[0]->irq_level,
3576                                         slgt_interrupt,
3577                                         port_array[0]->irq_flags,
3578                                         port_array[0]->device_name,
3579                                         port_array[0]) < 0) {
3580                         DBGERR(("%s request_irq failed IRQ=%d\n",
3581                                 port_array[0]->device_name,
3582                                 port_array[0]->irq_level));
3583                 } else {
3584                         port_array[0]->irq_requested = true;
3585                         adapter_test(port_array[0]);
3586                         for (i=1 ; i < port_count ; i++) {
3587                                 port_array[i]->init_error = port_array[0]->init_error;
3588                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3589                         }
3590                 }
3591         }
3592
3593         for (i = 0; i < port_count; ++i) {
3594                 struct slgt_info *info = port_array[i];
3595                 tty_port_register_device(&info->port, serial_driver, info->line,
3596                                 &info->pdev->dev);
3597         }
3598 }
3599
3600 static int init_one(struct pci_dev *dev,
3601                               const struct pci_device_id *ent)
3602 {
3603         if (pci_enable_device(dev)) {
3604                 printk("error enabling pci device %p\n", dev);
3605                 return -EIO;
3606         }
3607         pci_set_master(dev);
3608         device_init(slgt_device_count, dev);
3609         return 0;
3610 }
3611
3612 static void remove_one(struct pci_dev *dev)
3613 {
3614 }
3615
3616 static const struct tty_operations ops = {
3617         .open = open,
3618         .close = close,
3619         .write = write,
3620         .put_char = put_char,
3621         .flush_chars = flush_chars,
3622         .write_room = write_room,
3623         .chars_in_buffer = chars_in_buffer,
3624         .flush_buffer = flush_buffer,
3625         .ioctl = ioctl,
3626         .compat_ioctl = slgt_compat_ioctl,
3627         .throttle = throttle,
3628         .unthrottle = unthrottle,
3629         .send_xchar = send_xchar,
3630         .break_ctl = set_break,
3631         .wait_until_sent = wait_until_sent,
3632         .set_termios = set_termios,
3633         .stop = tx_hold,
3634         .start = tx_release,
3635         .hangup = hangup,
3636         .tiocmget = tiocmget,
3637         .tiocmset = tiocmset,
3638         .get_icount = get_icount,
3639         .proc_show = synclink_gt_proc_show,
3640 };
3641
3642 static void slgt_cleanup(void)
3643 {
3644         struct slgt_info *info;
3645         struct slgt_info *tmp;
3646
3647         printk(KERN_INFO "unload %s\n", driver_name);
3648
3649         if (serial_driver) {
3650                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3651                         tty_unregister_device(serial_driver, info->line);
3652                 tty_unregister_driver(serial_driver);
3653                 put_tty_driver(serial_driver);
3654         }
3655
3656         /* reset devices */
3657         info = slgt_device_list;
3658         while(info) {
3659                 reset_port(info);
3660                 info = info->next_device;
3661         }
3662
3663         /* release devices */
3664         info = slgt_device_list;
3665         while(info) {
3666 #if SYNCLINK_GENERIC_HDLC
3667                 hdlcdev_exit(info);
3668 #endif
3669                 free_dma_bufs(info);
3670                 free_tmp_rbuf(info);
3671                 if (info->port_num == 0)
3672                         release_resources(info);
3673                 tmp = info;
3674                 info = info->next_device;
3675                 tty_port_destroy(&tmp->port);
3676                 kfree(tmp);
3677         }
3678
3679         if (pci_registered)
3680                 pci_unregister_driver(&pci_driver);
3681 }
3682
3683 /*
3684  *  Driver initialization entry point.
3685  */
3686 static int __init slgt_init(void)
3687 {
3688         int rc;
3689
3690         printk(KERN_INFO "%s\n", driver_name);
3691
3692         serial_driver = alloc_tty_driver(MAX_DEVICES);
3693         if (!serial_driver) {
3694                 printk("%s can't allocate tty driver\n", driver_name);
3695                 return -ENOMEM;
3696         }
3697
3698         /* Initialize the tty_driver structure */
3699
3700         serial_driver->driver_name = slgt_driver_name;
3701         serial_driver->name = tty_dev_prefix;
3702         serial_driver->major = ttymajor;
3703         serial_driver->minor_start = 64;
3704         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3705         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3706         serial_driver->init_termios = tty_std_termios;
3707         serial_driver->init_termios.c_cflag =
3708                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3709         serial_driver->init_termios.c_ispeed = 9600;
3710         serial_driver->init_termios.c_ospeed = 9600;
3711         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3712         tty_set_operations(serial_driver, &ops);
3713         if ((rc = tty_register_driver(serial_driver)) < 0) {
3714                 DBGERR(("%s can't register serial driver\n", driver_name));
3715                 put_tty_driver(serial_driver);
3716                 serial_driver = NULL;
3717                 goto error;
3718         }
3719
3720         printk(KERN_INFO "%s, tty major#%d\n",
3721                driver_name, serial_driver->major);
3722
3723         slgt_device_count = 0;
3724         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3725                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3726                 goto error;
3727         }
3728         pci_registered = true;
3729
3730         if (!slgt_device_list)
3731                 printk("%s no devices found\n",driver_name);
3732
3733         return 0;
3734
3735 error:
3736         slgt_cleanup();
3737         return rc;
3738 }
3739
3740 static void __exit slgt_exit(void)
3741 {
3742         slgt_cleanup();
3743 }
3744
3745 module_init(slgt_init);
3746 module_exit(slgt_exit);
3747
3748 /*
3749  * register access routines
3750  */
3751
3752 #define CALC_REGADDR() \
3753         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3754         if (addr >= 0x80) \
3755                 reg_addr += (info->port_num) * 32; \
3756         else if (addr >= 0x40)  \
3757                 reg_addr += (info->port_num) * 16;
3758
3759 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3760 {
3761         CALC_REGADDR();
3762         return readb((void __iomem *)reg_addr);
3763 }
3764
3765 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3766 {
3767         CALC_REGADDR();
3768         writeb(value, (void __iomem *)reg_addr);
3769 }
3770
3771 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3772 {
3773         CALC_REGADDR();
3774         return readw((void __iomem *)reg_addr);
3775 }
3776
3777 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3778 {
3779         CALC_REGADDR();
3780         writew(value, (void __iomem *)reg_addr);
3781 }
3782
3783 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3784 {
3785         CALC_REGADDR();
3786         return readl((void __iomem *)reg_addr);
3787 }
3788
3789 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3790 {
3791         CALC_REGADDR();
3792         writel(value, (void __iomem *)reg_addr);
3793 }
3794
3795 static void rdma_reset(struct slgt_info *info)
3796 {
3797         unsigned int i;
3798
3799         /* set reset bit */
3800         wr_reg32(info, RDCSR, BIT1);
3801
3802         /* wait for enable bit cleared */
3803         for(i=0 ; i < 1000 ; i++)
3804                 if (!(rd_reg32(info, RDCSR) & BIT0))
3805                         break;
3806 }
3807
3808 static void tdma_reset(struct slgt_info *info)
3809 {
3810         unsigned int i;
3811
3812         /* set reset bit */
3813         wr_reg32(info, TDCSR, BIT1);
3814
3815         /* wait for enable bit cleared */
3816         for(i=0 ; i < 1000 ; i++)
3817                 if (!(rd_reg32(info, TDCSR) & BIT0))
3818                         break;
3819 }
3820
3821 /*
3822  * enable internal loopback
3823  * TxCLK and RxCLK are generated from BRG
3824  * and TxD is looped back to RxD internally.
3825  */
3826 static void enable_loopback(struct slgt_info *info)
3827 {
3828         /* SCR (serial control) BIT2=loopback enable */
3829         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3830
3831         if (info->params.mode != MGSL_MODE_ASYNC) {
3832                 /* CCR (clock control)
3833                  * 07..05  tx clock source (010 = BRG)
3834                  * 04..02  rx clock source (010 = BRG)
3835                  * 01      auxclk enable   (0 = disable)
3836                  * 00      BRG enable      (1 = enable)
3837                  *
3838                  * 0100 1001
3839                  */
3840                 wr_reg8(info, CCR, 0x49);
3841
3842                 /* set speed if available, otherwise use default */
3843                 if (info->params.clock_speed)
3844                         set_rate(info, info->params.clock_speed);
3845                 else
3846                         set_rate(info, 3686400);
3847         }
3848 }
3849
3850 /*
3851  *  set baud rate generator to specified rate
3852  */
3853 static void set_rate(struct slgt_info *info, u32 rate)
3854 {
3855         unsigned int div;
3856         unsigned int osc = info->base_clock;
3857
3858         /* div = osc/rate - 1
3859          *
3860          * Round div up if osc/rate is not integer to
3861          * force to next slowest rate.
3862          */
3863
3864         if (rate) {
3865                 div = osc/rate;
3866                 if (!(osc % rate) && div)
3867                         div--;
3868                 wr_reg16(info, BDR, (unsigned short)div);
3869         }
3870 }
3871
3872 static void rx_stop(struct slgt_info *info)
3873 {
3874         unsigned short val;
3875
3876         /* disable and reset receiver */
3877         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3878         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3879         wr_reg16(info, RCR, val);                  /* clear reset bit */
3880
3881         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3882
3883         /* clear pending rx interrupts */
3884         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3885
3886         rdma_reset(info);
3887
3888         info->rx_enabled = false;
3889         info->rx_restart = false;
3890 }
3891
3892 static void rx_start(struct slgt_info *info)
3893 {
3894         unsigned short val;
3895
3896         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3897
3898         /* clear pending rx overrun IRQ */
3899         wr_reg16(info, SSR, IRQ_RXOVER);
3900
3901         /* reset and disable receiver */
3902         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3903         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3904         wr_reg16(info, RCR, val);                  /* clear reset bit */
3905
3906         rdma_reset(info);
3907         reset_rbufs(info);
3908
3909         if (info->rx_pio) {
3910                 /* rx request when rx FIFO not empty */
3911                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3912                 slgt_irq_on(info, IRQ_RXDATA);
3913                 if (info->params.mode == MGSL_MODE_ASYNC) {
3914                         /* enable saving of rx status */
3915                         wr_reg32(info, RDCSR, BIT6);
3916                 }
3917         } else {
3918                 /* rx request when rx FIFO half full */
3919                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3920                 /* set 1st descriptor address */
3921                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3922
3923                 if (info->params.mode != MGSL_MODE_ASYNC) {
3924                         /* enable rx DMA and DMA interrupt */
3925                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3926                 } else {
3927                         /* enable saving of rx status, rx DMA and DMA interrupt */
3928                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3929                 }
3930         }
3931
3932         slgt_irq_on(info, IRQ_RXOVER);
3933
3934         /* enable receiver */
3935         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3936
3937         info->rx_restart = false;
3938         info->rx_enabled = true;
3939 }
3940
3941 static void tx_start(struct slgt_info *info)
3942 {
3943         if (!info->tx_enabled) {
3944                 wr_reg16(info, TCR,
3945                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3946                 info->tx_enabled = true;
3947         }
3948
3949         if (desc_count(info->tbufs[info->tbuf_start])) {
3950                 info->drop_rts_on_tx_done = false;
3951
3952                 if (info->params.mode != MGSL_MODE_ASYNC) {
3953                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3954                                 get_signals(info);
3955                                 if (!(info->signals & SerialSignal_RTS)) {
3956                                         info->signals |= SerialSignal_RTS;
3957                                         set_signals(info);
3958                                         info->drop_rts_on_tx_done = true;
3959                                 }
3960                         }
3961
3962                         slgt_irq_off(info, IRQ_TXDATA);
3963                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3964                         /* clear tx idle and underrun status bits */
3965                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3966                 } else {
3967                         slgt_irq_off(info, IRQ_TXDATA);
3968                         slgt_irq_on(info, IRQ_TXIDLE);
3969                         /* clear tx idle status bit */
3970                         wr_reg16(info, SSR, IRQ_TXIDLE);
3971                 }
3972                 /* set 1st descriptor address and start DMA */
3973                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3974                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3975                 info->tx_active = true;
3976         }
3977 }
3978
3979 static void tx_stop(struct slgt_info *info)
3980 {
3981         unsigned short val;
3982
3983         del_timer(&info->tx_timer);
3984
3985         tdma_reset(info);
3986
3987         /* reset and disable transmitter */
3988         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3989         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3990
3991         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3992
3993         /* clear tx idle and underrun status bit */
3994         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3995
3996         reset_tbufs(info);
3997
3998         info->tx_enabled = false;
3999         info->tx_active = false;
4000 }
4001
4002 static void reset_port(struct slgt_info *info)
4003 {
4004         if (!info->reg_addr)
4005                 return;
4006
4007         tx_stop(info);
4008         rx_stop(info);
4009
4010         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4011         set_signals(info);
4012
4013         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4014 }
4015
4016 static void reset_adapter(struct slgt_info *info)
4017 {
4018         int i;
4019         for (i=0; i < info->port_count; ++i) {
4020                 if (info->port_array[i])
4021                         reset_port(info->port_array[i]);
4022         }
4023 }
4024
4025 static void async_mode(struct slgt_info *info)
4026 {
4027         unsigned short val;
4028
4029         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4030         tx_stop(info);
4031         rx_stop(info);
4032
4033         /* TCR (tx control)
4034          *
4035          * 15..13  mode, 010=async
4036          * 12..10  encoding, 000=NRZ
4037          * 09      parity enable
4038          * 08      1=odd parity, 0=even parity
4039          * 07      1=RTS driver control
4040          * 06      1=break enable
4041          * 05..04  character length
4042          *         00=5 bits
4043          *         01=6 bits
4044          *         10=7 bits
4045          *         11=8 bits
4046          * 03      0=1 stop bit, 1=2 stop bits
4047          * 02      reset
4048          * 01      enable
4049          * 00      auto-CTS enable
4050          */
4051         val = 0x4000;
4052
4053         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4054                 val |= BIT7;
4055
4056         if (info->params.parity != ASYNC_PARITY_NONE) {
4057                 val |= BIT9;
4058                 if (info->params.parity == ASYNC_PARITY_ODD)
4059                         val |= BIT8;
4060         }
4061
4062         switch (info->params.data_bits)
4063         {
4064         case 6: val |= BIT4; break;
4065         case 7: val |= BIT5; break;
4066         case 8: val |= BIT5 + BIT4; break;
4067         }
4068
4069         if (info->params.stop_bits != 1)
4070                 val |= BIT3;
4071
4072         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4073                 val |= BIT0;
4074
4075         wr_reg16(info, TCR, val);
4076
4077         /* RCR (rx control)
4078          *
4079          * 15..13  mode, 010=async
4080          * 12..10  encoding, 000=NRZ
4081          * 09      parity enable
4082          * 08      1=odd parity, 0=even parity
4083          * 07..06  reserved, must be 0
4084          * 05..04  character length
4085          *         00=5 bits
4086          *         01=6 bits
4087          *         10=7 bits
4088          *         11=8 bits
4089          * 03      reserved, must be zero
4090          * 02      reset
4091          * 01      enable
4092          * 00      auto-DCD enable
4093          */
4094         val = 0x4000;
4095
4096         if (info->params.parity != ASYNC_PARITY_NONE) {
4097                 val |= BIT9;
4098                 if (info->params.parity == ASYNC_PARITY_ODD)
4099                         val |= BIT8;
4100         }
4101
4102         switch (info->params.data_bits)
4103         {
4104         case 6: val |= BIT4; break;
4105         case 7: val |= BIT5; break;
4106         case 8: val |= BIT5 + BIT4; break;
4107         }
4108
4109         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4110                 val |= BIT0;
4111
4112         wr_reg16(info, RCR, val);
4113
4114         /* CCR (clock control)
4115          *
4116          * 07..05  011 = tx clock source is BRG/16
4117          * 04..02  010 = rx clock source is BRG
4118          * 01      0 = auxclk disabled
4119          * 00      1 = BRG enabled
4120          *
4121          * 0110 1001
4122          */
4123         wr_reg8(info, CCR, 0x69);
4124
4125         msc_set_vcr(info);
4126
4127         /* SCR (serial control)
4128          *
4129          * 15  1=tx req on FIFO half empty
4130          * 14  1=rx req on FIFO half full
4131          * 13  tx data  IRQ enable
4132          * 12  tx idle  IRQ enable
4133          * 11  rx break on IRQ enable
4134          * 10  rx data  IRQ enable
4135          * 09  rx break off IRQ enable
4136          * 08  overrun  IRQ enable
4137          * 07  DSR      IRQ enable
4138          * 06  CTS      IRQ enable
4139          * 05  DCD      IRQ enable
4140          * 04  RI       IRQ enable
4141          * 03  0=16x sampling, 1=8x sampling
4142          * 02  1=txd->rxd internal loopback enable
4143          * 01  reserved, must be zero
4144          * 00  1=master IRQ enable
4145          */
4146         val = BIT15 + BIT14 + BIT0;
4147         /* JCR[8] : 1 = x8 async mode feature available */
4148         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4149             ((info->base_clock < (info->params.data_rate * 16)) ||
4150              (info->base_clock % (info->params.data_rate * 16)))) {
4151                 /* use 8x sampling */
4152                 val |= BIT3;
4153                 set_rate(info, info->params.data_rate * 8);
4154         } else {
4155                 /* use 16x sampling */
4156                 set_rate(info, info->params.data_rate * 16);
4157         }
4158         wr_reg16(info, SCR, val);
4159
4160         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4161
4162         if (info->params.loopback)
4163                 enable_loopback(info);
4164 }
4165
4166 static void sync_mode(struct slgt_info *info)
4167 {
4168         unsigned short val;
4169
4170         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4171         tx_stop(info);
4172         rx_stop(info);
4173
4174         /* TCR (tx control)
4175          *
4176          * 15..13  mode
4177          *         000=HDLC/SDLC
4178          *         001=raw bit synchronous
4179          *         010=asynchronous/isochronous
4180          *         011=monosync byte synchronous
4181          *         100=bisync byte synchronous
4182          *         101=xsync byte synchronous
4183          * 12..10  encoding
4184          * 09      CRC enable
4185          * 08      CRC32
4186          * 07      1=RTS driver control
4187          * 06      preamble enable
4188          * 05..04  preamble length
4189          * 03      share open/close flag
4190          * 02      reset
4191          * 01      enable
4192          * 00      auto-CTS enable
4193          */
4194         val = BIT2;
4195
4196         switch(info->params.mode) {
4197         case MGSL_MODE_XSYNC:
4198                 val |= BIT15 + BIT13;
4199                 break;
4200         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4201         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4202         case MGSL_MODE_RAW:      val |= BIT13; break;
4203         }
4204         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4205                 val |= BIT7;
4206
4207         switch(info->params.encoding)
4208         {
4209         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4210         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4211         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4212         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4213         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4214         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4215         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4216         }
4217
4218         switch (info->params.crc_type & HDLC_CRC_MASK)
4219         {
4220         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4221         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4222         }
4223
4224         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4225                 val |= BIT6;
4226
4227         switch (info->params.preamble_length)
4228         {
4229         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4230         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4231         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4232         }
4233
4234         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4235                 val |= BIT0;
4236
4237         wr_reg16(info, TCR, val);
4238
4239         /* TPR (transmit preamble) */
4240
4241         switch (info->params.preamble)
4242         {
4243         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4244         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4245         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4246         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4247         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4248         default:                          val = 0x7e; break;
4249         }
4250         wr_reg8(info, TPR, (unsigned char)val);
4251
4252         /* RCR (rx control)
4253          *
4254          * 15..13  mode
4255          *         000=HDLC/SDLC
4256          *         001=raw bit synchronous
4257          *         010=asynchronous/isochronous
4258          *         011=monosync byte synchronous
4259          *         100=bisync byte synchronous
4260          *         101=xsync byte synchronous
4261          * 12..10  encoding
4262          * 09      CRC enable
4263          * 08      CRC32
4264          * 07..03  reserved, must be 0
4265          * 02      reset
4266          * 01      enable
4267          * 00      auto-DCD enable
4268          */
4269         val = 0;
4270
4271         switch(info->params.mode) {
4272         case MGSL_MODE_XSYNC:
4273                 val |= BIT15 + BIT13;
4274                 break;
4275         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4276         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4277         case MGSL_MODE_RAW:      val |= BIT13; break;
4278         }
4279
4280         switch(info->params.encoding)
4281         {
4282         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4283         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4284         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4285         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4286         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4287         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4288         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4289         }
4290
4291         switch (info->params.crc_type & HDLC_CRC_MASK)
4292         {
4293         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4294         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4295         }
4296
4297         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4298                 val |= BIT0;
4299
4300         wr_reg16(info, RCR, val);
4301
4302         /* CCR (clock control)
4303          *
4304          * 07..05  tx clock source
4305          * 04..02  rx clock source
4306          * 01      auxclk enable
4307          * 00      BRG enable
4308          */
4309         val = 0;
4310
4311         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4312         {
4313                 // when RxC source is DPLL, BRG generates 16X DPLL
4314                 // reference clock, so take TxC from BRG/16 to get
4315                 // transmit clock at actual data rate
4316                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4317                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4318                 else
4319                         val |= BIT6;    /* 010, txclk = BRG */
4320         }
4321         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4322                 val |= BIT7;    /* 100, txclk = DPLL Input */
4323         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4324                 val |= BIT5;    /* 001, txclk = RXC Input */
4325
4326         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4327                 val |= BIT3;    /* 010, rxclk = BRG */
4328         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4329                 val |= BIT4;    /* 100, rxclk = DPLL */
4330         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4331                 val |= BIT2;    /* 001, rxclk = TXC Input */
4332
4333         if (info->params.clock_speed)
4334                 val |= BIT1 + BIT0;
4335
4336         wr_reg8(info, CCR, (unsigned char)val);
4337
4338         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4339         {
4340                 // program DPLL mode
4341                 switch(info->params.encoding)
4342                 {
4343                 case HDLC_ENCODING_BIPHASE_MARK:
4344                 case HDLC_ENCODING_BIPHASE_SPACE:
4345                         val = BIT7; break;
4346                 case HDLC_ENCODING_BIPHASE_LEVEL:
4347                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4348                         val = BIT7 + BIT6; break;
4349                 default: val = BIT6;    // NRZ encodings
4350                 }
4351                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4352
4353                 // DPLL requires a 16X reference clock from BRG
4354                 set_rate(info, info->params.clock_speed * 16);
4355         }
4356         else
4357                 set_rate(info, info->params.clock_speed);
4358
4359         tx_set_idle(info);
4360
4361         msc_set_vcr(info);
4362
4363         /* SCR (serial control)
4364          *
4365          * 15  1=tx req on FIFO half empty
4366          * 14  1=rx req on FIFO half full
4367          * 13  tx data  IRQ enable
4368          * 12  tx idle  IRQ enable
4369          * 11  underrun IRQ enable
4370          * 10  rx data  IRQ enable
4371          * 09  rx idle  IRQ enable
4372          * 08  overrun  IRQ enable
4373          * 07  DSR      IRQ enable
4374          * 06  CTS      IRQ enable
4375          * 05  DCD      IRQ enable
4376          * 04  RI       IRQ enable
4377          * 03  reserved, must be zero
4378          * 02  1=txd->rxd internal loopback enable
4379          * 01  reserved, must be zero
4380          * 00  1=master IRQ enable
4381          */
4382         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4383
4384         if (info->params.loopback)
4385                 enable_loopback(info);
4386 }
4387
4388 /*
4389  *  set transmit idle mode
4390  */
4391 static void tx_set_idle(struct slgt_info *info)
4392 {
4393         unsigned char val;
4394         unsigned short tcr;
4395
4396         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4397          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4398          */
4399         tcr = rd_reg16(info, TCR);
4400         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4401                 /* disable preamble, set idle size to 16 bits */
4402                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4403                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4404                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4405         } else if (!(tcr & BIT6)) {
4406                 /* preamble is disabled, set idle size to 8 bits */
4407                 tcr &= ~(BIT5 + BIT4);
4408         }
4409         wr_reg16(info, TCR, tcr);
4410
4411         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4412                 /* LSB of custom tx idle specified in tx idle register */
4413                 val = (unsigned char)(info->idle_mode & 0xff);
4414         } else {
4415                 /* standard 8 bit idle patterns */
4416                 switch(info->idle_mode)
4417                 {
4418                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4419                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4420                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4421                 case HDLC_TXIDLE_ZEROS:
4422                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4423                 default:                         val = 0xff;
4424                 }
4425         }
4426
4427         wr_reg8(info, TIR, val);
4428 }
4429
4430 /*
4431  * get state of V24 status (input) signals
4432  */
4433 static void get_signals(struct slgt_info *info)
4434 {
4435         unsigned short status = rd_reg16(info, SSR);
4436
4437         /* clear all serial signals except RTS and DTR */
4438         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4439
4440         if (status & BIT3)
4441                 info->signals |= SerialSignal_DSR;
4442         if (status & BIT2)
4443                 info->signals |= SerialSignal_CTS;
4444         if (status & BIT1)
4445                 info->signals |= SerialSignal_DCD;
4446         if (status & BIT0)
4447                 info->signals |= SerialSignal_RI;
4448 }
4449
4450 /*
4451  * set V.24 Control Register based on current configuration
4452  */
4453 static void msc_set_vcr(struct slgt_info *info)
4454 {
4455         unsigned char val = 0;
4456
4457         /* VCR (V.24 control)
4458          *
4459          * 07..04  serial IF select
4460          * 03      DTR
4461          * 02      RTS
4462          * 01      LL
4463          * 00      RL
4464          */
4465
4466         switch(info->if_mode & MGSL_INTERFACE_MASK)
4467         {
4468         case MGSL_INTERFACE_RS232:
4469                 val |= BIT5; /* 0010 */
4470                 break;
4471         case MGSL_INTERFACE_V35:
4472                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4473                 break;
4474         case MGSL_INTERFACE_RS422:
4475                 val |= BIT6; /* 0100 */
4476                 break;
4477         }
4478
4479         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4480                 val |= BIT4;
4481         if (info->signals & SerialSignal_DTR)
4482                 val |= BIT3;
4483         if (info->signals & SerialSignal_RTS)
4484                 val |= BIT2;
4485         if (info->if_mode & MGSL_INTERFACE_LL)
4486                 val |= BIT1;
4487         if (info->if_mode & MGSL_INTERFACE_RL)
4488                 val |= BIT0;
4489         wr_reg8(info, VCR, val);
4490 }
4491
4492 /*
4493  * set state of V24 control (output) signals
4494  */
4495 static void set_signals(struct slgt_info *info)
4496 {
4497         unsigned char val = rd_reg8(info, VCR);
4498         if (info->signals & SerialSignal_DTR)
4499                 val |= BIT3;
4500         else
4501                 val &= ~BIT3;
4502         if (info->signals & SerialSignal_RTS)
4503                 val |= BIT2;
4504         else
4505                 val &= ~BIT2;
4506         wr_reg8(info, VCR, val);
4507 }
4508
4509 /*
4510  * free range of receive DMA buffers (i to last)
4511  */
4512 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4513 {
4514         int done = 0;
4515
4516         while(!done) {
4517                 /* reset current buffer for reuse */
4518                 info->rbufs[i].status = 0;
4519                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4520                 if (i == last)
4521                         done = 1;
4522                 if (++i == info->rbuf_count)
4523                         i = 0;
4524         }
4525         info->rbuf_current = i;
4526 }
4527
4528 /*
4529  * mark all receive DMA buffers as free
4530  */
4531 static void reset_rbufs(struct slgt_info *info)
4532 {
4533         free_rbufs(info, 0, info->rbuf_count - 1);
4534         info->rbuf_fill_index = 0;
4535         info->rbuf_fill_count = 0;
4536 }
4537
4538 /*
4539  * pass receive HDLC frame to upper layer
4540  *
4541  * return true if frame available, otherwise false
4542  */
4543 static bool rx_get_frame(struct slgt_info *info)
4544 {
4545         unsigned int start, end;
4546         unsigned short status;
4547         unsigned int framesize = 0;
4548         unsigned long flags;
4549         struct tty_struct *tty = info->port.tty;
4550         unsigned char addr_field = 0xff;
4551         unsigned int crc_size = 0;
4552
4553         switch (info->params.crc_type & HDLC_CRC_MASK) {
4554         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4555         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4556         }
4557
4558 check_again:
4559
4560         framesize = 0;
4561         addr_field = 0xff;
4562         start = end = info->rbuf_current;
4563
4564         for (;;) {
4565                 if (!desc_complete(info->rbufs[end]))
4566                         goto cleanup;
4567
4568                 if (framesize == 0 && info->params.addr_filter != 0xff)
4569                         addr_field = info->rbufs[end].buf[0];
4570
4571                 framesize += desc_count(info->rbufs[end]);
4572
4573                 if (desc_eof(info->rbufs[end]))
4574                         break;
4575
4576                 if (++end == info->rbuf_count)
4577                         end = 0;
4578
4579                 if (end == info->rbuf_current) {
4580                         if (info->rx_enabled){
4581                                 spin_lock_irqsave(&info->lock,flags);
4582                                 rx_start(info);
4583                                 spin_unlock_irqrestore(&info->lock,flags);
4584                         }
4585                         goto cleanup;
4586                 }
4587         }
4588
4589         /* status
4590          *
4591          * 15      buffer complete
4592          * 14..06  reserved
4593          * 05..04  residue
4594          * 02      eof (end of frame)
4595          * 01      CRC error
4596          * 00      abort
4597          */
4598         status = desc_status(info->rbufs[end]);
4599
4600         /* ignore CRC bit if not using CRC (bit is undefined) */
4601         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4602                 status &= ~BIT1;
4603
4604         if (framesize == 0 ||
4605                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4606                 free_rbufs(info, start, end);
4607                 goto check_again;
4608         }
4609
4610         if (framesize < (2 + crc_size) || status & BIT0) {
4611                 info->icount.rxshort++;
4612                 framesize = 0;
4613         } else if (status & BIT1) {
4614                 info->icount.rxcrc++;
4615                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4616                         framesize = 0;
4617         }
4618
4619 #if SYNCLINK_GENERIC_HDLC
4620         if (framesize == 0) {
4621                 info->netdev->stats.rx_errors++;
4622                 info->netdev->stats.rx_frame_errors++;
4623         }
4624 #endif
4625
4626         DBGBH(("%s rx frame status=%04X size=%d\n",
4627                 info->device_name, status, framesize));
4628         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4629
4630         if (framesize) {
4631                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4632                         framesize -= crc_size;
4633                         crc_size = 0;
4634                 }
4635
4636                 if (framesize > info->max_frame_size + crc_size)
4637                         info->icount.rxlong++;
4638                 else {
4639                         /* copy dma buffer(s) to contiguous temp buffer */
4640                         int copy_count = framesize;
4641                         int i = start;
4642                         unsigned char *p = info->tmp_rbuf;
4643                         info->tmp_rbuf_count = framesize;
4644
4645                         info->icount.rxok++;
4646
4647                         while(copy_count) {
4648                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4649                                 memcpy(p, info->rbufs[i].buf, partial_count);
4650                                 p += partial_count;
4651                                 copy_count -= partial_count;
4652                                 if (++i == info->rbuf_count)
4653                                         i = 0;
4654                         }
4655
4656                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4657                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4658                                 framesize++;
4659                         }
4660
4661 #if SYNCLINK_GENERIC_HDLC
4662                         if (info->netcount)
4663                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4664                         else
4665 #endif
4666                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4667                 }
4668         }
4669         free_rbufs(info, start, end);
4670         return true;
4671
4672 cleanup:
4673         return false;
4674 }
4675
4676 /*
4677  * pass receive buffer (RAW synchronous mode) to tty layer
4678  * return true if buffer available, otherwise false
4679  */
4680 static bool rx_get_buf(struct slgt_info *info)
4681 {
4682         unsigned int i = info->rbuf_current;
4683         unsigned int count;
4684
4685         if (!desc_complete(info->rbufs[i]))
4686                 return false;
4687         count = desc_count(info->rbufs[i]);
4688         switch(info->params.mode) {
4689         case MGSL_MODE_MONOSYNC:
4690         case MGSL_MODE_BISYNC:
4691         case MGSL_MODE_XSYNC:
4692                 /* ignore residue in byte synchronous modes */
4693                 if (desc_residue(info->rbufs[i]))
4694                         count--;
4695                 break;
4696         }
4697         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4698         DBGINFO(("rx_get_buf size=%d\n", count));
4699         if (count)
4700                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4701                                   info->flag_buf, count);
4702         free_rbufs(info, i, i);
4703         return true;
4704 }
4705
4706 static void reset_tbufs(struct slgt_info *info)
4707 {
4708         unsigned int i;
4709         info->tbuf_current = 0;
4710         for (i=0 ; i < info->tbuf_count ; i++) {
4711                 info->tbufs[i].status = 0;
4712                 info->tbufs[i].count  = 0;
4713         }
4714 }
4715
4716 /*
4717  * return number of free transmit DMA buffers
4718  */
4719 static unsigned int free_tbuf_count(struct slgt_info *info)
4720 {
4721         unsigned int count = 0;
4722         unsigned int i = info->tbuf_current;
4723
4724         do
4725         {
4726                 if (desc_count(info->tbufs[i]))
4727                         break; /* buffer in use */
4728                 ++count;
4729                 if (++i == info->tbuf_count)
4730                         i=0;
4731         } while (i != info->tbuf_current);
4732
4733         /* if tx DMA active, last zero count buffer is in use */
4734         if (count && (rd_reg32(info, TDCSR) & BIT0))
4735                 --count;
4736
4737         return count;
4738 }
4739
4740 /*
4741  * return number of bytes in unsent transmit DMA buffers
4742  * and the serial controller tx FIFO
4743  */
4744 static unsigned int tbuf_bytes(struct slgt_info *info)
4745 {
4746         unsigned int total_count = 0;
4747         unsigned int i = info->tbuf_current;
4748         unsigned int reg_value;
4749         unsigned int count;
4750         unsigned int active_buf_count = 0;
4751
4752         /*
4753          * Add descriptor counts for all tx DMA buffers.
4754          * If count is zero (cleared by DMA controller after read),
4755          * the buffer is complete or is actively being read from.
4756          *
4757          * Record buf_count of last buffer with zero count starting
4758          * from current ring position. buf_count is mirror
4759          * copy of count and is not cleared by serial controller.
4760          * If DMA controller is active, that buffer is actively
4761          * being read so add to total.
4762          */
4763         do {
4764                 count = desc_count(info->tbufs[i]);
4765                 if (count)
4766                         total_count += count;
4767                 else if (!total_count)
4768                         active_buf_count = info->tbufs[i].buf_count;
4769                 if (++i == info->tbuf_count)
4770                         i = 0;
4771         } while (i != info->tbuf_current);
4772
4773         /* read tx DMA status register */
4774         reg_value = rd_reg32(info, TDCSR);
4775
4776         /* if tx DMA active, last zero count buffer is in use */
4777         if (reg_value & BIT0)
4778                 total_count += active_buf_count;
4779
4780         /* add tx FIFO count = reg_value[15..8] */
4781         total_count += (reg_value >> 8) & 0xff;
4782
4783         /* if transmitter active add one byte for shift register */
4784         if (info->tx_active)
4785                 total_count++;
4786
4787         return total_count;
4788 }
4789
4790 /*
4791  * load data into transmit DMA buffer ring and start transmitter if needed
4792  * return true if data accepted, otherwise false (buffers full)
4793  */
4794 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4795 {
4796         unsigned short count;
4797         unsigned int i;
4798         struct slgt_desc *d;
4799
4800         /* check required buffer space */
4801         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4802                 return false;
4803
4804         DBGDATA(info, buf, size, "tx");
4805
4806         /*
4807          * copy data to one or more DMA buffers in circular ring
4808          * tbuf_start   = first buffer for this data
4809          * tbuf_current = next free buffer
4810          *
4811          * Copy all data before making data visible to DMA controller by
4812          * setting descriptor count of the first buffer.
4813          * This prevents an active DMA controller from reading the first DMA
4814          * buffers of a frame and stopping before the final buffers are filled.
4815          */
4816
4817         info->tbuf_start = i = info->tbuf_current;
4818
4819         while (size) {
4820                 d = &info->tbufs[i];
4821
4822                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4823                 memcpy(d->buf, buf, count);
4824
4825                 size -= count;
4826                 buf  += count;
4827
4828                 /*
4829                  * set EOF bit for last buffer of HDLC frame or
4830                  * for every buffer in raw mode
4831                  */
4832                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4833                     info->params.mode == MGSL_MODE_RAW)
4834                         set_desc_eof(*d, 1);
4835                 else
4836                         set_desc_eof(*d, 0);
4837
4838                 /* set descriptor count for all but first buffer */
4839                 if (i != info->tbuf_start)
4840                         set_desc_count(*d, count);
4841                 d->buf_count = count;
4842
4843                 if (++i == info->tbuf_count)
4844                         i = 0;
4845         }
4846
4847         info->tbuf_current = i;
4848
4849         /* set first buffer count to make new data visible to DMA controller */
4850         d = &info->tbufs[info->tbuf_start];
4851         set_desc_count(*d, d->buf_count);
4852
4853         /* start transmitter if needed and update transmit timeout */
4854         if (!info->tx_active)
4855                 tx_start(info);
4856         update_tx_timer(info);
4857
4858         return true;
4859 }
4860
4861 static int register_test(struct slgt_info *info)
4862 {
4863         static unsigned short patterns[] =
4864                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4865         static unsigned int count = ARRAY_SIZE(patterns);
4866         unsigned int i;
4867         int rc = 0;
4868
4869         for (i=0 ; i < count ; i++) {
4870                 wr_reg16(info, TIR, patterns[i]);
4871                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4872                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4873                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4874                         rc = -ENODEV;
4875                         break;
4876                 }
4877         }
4878         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4879         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4880         return rc;
4881 }
4882
4883 static int irq_test(struct slgt_info *info)
4884 {
4885         unsigned long timeout;
4886         unsigned long flags;
4887         struct tty_struct *oldtty = info->port.tty;
4888         u32 speed = info->params.data_rate;
4889
4890         info->params.data_rate = 921600;
4891         info->port.tty = NULL;
4892
4893         spin_lock_irqsave(&info->lock, flags);
4894         async_mode(info);
4895         slgt_irq_on(info, IRQ_TXIDLE);
4896
4897         /* enable transmitter */
4898         wr_reg16(info, TCR,
4899                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4900
4901         /* write one byte and wait for tx idle */
4902         wr_reg16(info, TDR, 0);
4903
4904         /* assume failure */
4905         info->init_error = DiagStatus_IrqFailure;
4906         info->irq_occurred = false;
4907
4908         spin_unlock_irqrestore(&info->lock, flags);
4909
4910         timeout=100;
4911         while(timeout-- && !info->irq_occurred)
4912                 msleep_interruptible(10);
4913
4914         spin_lock_irqsave(&info->lock,flags);
4915         reset_port(info);
4916         spin_unlock_irqrestore(&info->lock,flags);
4917
4918         info->params.data_rate = speed;
4919         info->port.tty = oldtty;
4920
4921         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4922         return info->irq_occurred ? 0 : -ENODEV;
4923 }
4924
4925 static int loopback_test_rx(struct slgt_info *info)
4926 {
4927         unsigned char *src, *dest;
4928         int count;
4929
4930         if (desc_complete(info->rbufs[0])) {
4931                 count = desc_count(info->rbufs[0]);
4932                 src   = info->rbufs[0].buf;
4933                 dest  = info->tmp_rbuf;
4934
4935                 for( ; count ; count-=2, src+=2) {
4936                         /* src=data byte (src+1)=status byte */
4937                         if (!(*(src+1) & (BIT9 + BIT8))) {
4938                                 *dest = *src;
4939                                 dest++;
4940                                 info->tmp_rbuf_count++;
4941                         }
4942                 }
4943                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4944                 return 1;
4945         }
4946         return 0;
4947 }
4948
4949 static int loopback_test(struct slgt_info *info)
4950 {
4951 #define TESTFRAMESIZE 20
4952
4953         unsigned long timeout;
4954         u16 count;
4955         unsigned char buf[TESTFRAMESIZE];
4956         int rc = -ENODEV;
4957         unsigned long flags;
4958
4959         struct tty_struct *oldtty = info->port.tty;
4960         MGSL_PARAMS params;
4961
4962         memcpy(&params, &info->params, sizeof(params));
4963
4964         info->params.mode = MGSL_MODE_ASYNC;
4965         info->params.data_rate = 921600;
4966         info->params.loopback = 1;
4967         info->port.tty = NULL;
4968
4969         /* build and send transmit frame */
4970         for (count = 0; count < TESTFRAMESIZE; ++count)
4971                 buf[count] = (unsigned char)count;
4972
4973         info->tmp_rbuf_count = 0;
4974         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4975
4976         /* program hardware for HDLC and enabled receiver */
4977         spin_lock_irqsave(&info->lock,flags);
4978         async_mode(info);
4979         rx_start(info);
4980         tx_load(info, buf, count);
4981         spin_unlock_irqrestore(&info->lock, flags);
4982
4983         /* wait for receive complete */
4984         for (timeout = 100; timeout; --timeout) {
4985                 msleep_interruptible(10);
4986                 if (loopback_test_rx(info)) {
4987                         rc = 0;
4988                         break;
4989                 }
4990         }
4991
4992         /* verify received frame length and contents */
4993         if (!rc && (info->tmp_rbuf_count != count ||
4994                   memcmp(buf, info->tmp_rbuf, count))) {
4995                 rc = -ENODEV;
4996         }
4997
4998         spin_lock_irqsave(&info->lock,flags);
4999         reset_adapter(info);
5000         spin_unlock_irqrestore(&info->lock,flags);
5001
5002         memcpy(&info->params, &params, sizeof(info->params));
5003         info->port.tty = oldtty;
5004
5005         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5006         return rc;
5007 }
5008
5009 static int adapter_test(struct slgt_info *info)
5010 {
5011         DBGINFO(("testing %s\n", info->device_name));
5012         if (register_test(info) < 0) {
5013                 printk("register test failure %s addr=%08X\n",
5014                         info->device_name, info->phys_reg_addr);
5015         } else if (irq_test(info) < 0) {
5016                 printk("IRQ test failure %s IRQ=%d\n",
5017                         info->device_name, info->irq_level);
5018         } else if (loopback_test(info) < 0) {
5019                 printk("loopback test failure %s\n", info->device_name);
5020         }
5021         return info->init_error;
5022 }
5023
5024 /*
5025  * transmit timeout handler
5026  */
5027 static void tx_timeout(struct timer_list *t)
5028 {
5029         struct slgt_info *info = from_timer(info, t, tx_timer);
5030         unsigned long flags;
5031
5032         DBGINFO(("%s tx_timeout\n", info->device_name));
5033         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5034                 info->icount.txtimeout++;
5035         }
5036         spin_lock_irqsave(&info->lock,flags);
5037         tx_stop(info);
5038         spin_unlock_irqrestore(&info->lock,flags);
5039
5040 #if SYNCLINK_GENERIC_HDLC
5041         if (info->netcount)
5042                 hdlcdev_tx_done(info);
5043         else
5044 #endif
5045                 bh_transmit(info);
5046 }
5047
5048 /*
5049  * receive buffer polling timer
5050  */
5051 static void rx_timeout(struct timer_list *t)
5052 {
5053         struct slgt_info *info = from_timer(info, t, rx_timer);
5054         unsigned long flags;
5055
5056         DBGINFO(("%s rx_timeout\n", info->device_name));
5057         spin_lock_irqsave(&info->lock, flags);
5058         info->pending_bh |= BH_RECEIVE;
5059         spin_unlock_irqrestore(&info->lock, flags);
5060         bh_handler(&info->task);
5061 }
5062