drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #include <linux/platform_device.h>
  13 #include <linux/serial.h>
  14 #include <linux/console.h>
  15 #include <linux/serial_core.h>
  16 #include <linux/slab.h>
  17 #include <linux/tty.h>
  18 #include <linux/tty_flip.h>
  19 #include <linux/clk.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/module.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/iopoll.h>
  26
  27 #define CDNS_UART_TTY_NAME      "ttyPS"
  28 #define CDNS_UART_NAME          "xuartps"
  29 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  30 #define CDNS_UART_REGISTER_SPACE        0x1000
  31 #define TX_TIMEOUT              500000
  32
  33 /* Rx Trigger level */
  34 static int rx_trigger_level = 56;
  35 static int uartps_major;
  36 module_param(rx_trigger_level, uint, 0444);
  37 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  38
  39 /* Rx Timeout */
  40 static int rx_timeout = 10;
  41 module_param(rx_timeout, uint, 0444);
  42 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  43
  44 /* Register offsets for the UART. */
  45 #define CDNS_UART_CR            0x00  /* Control Register */
  46 #define CDNS_UART_MR            0x04  /* Mode Register */
  47 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  48 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  49 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  50 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  51 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  52 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  53 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  54 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  55 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  56 #define CDNS_UART_SR            0x2C  /* Channel Status */
  57 #define CDNS_UART_FIFO          0x30  /* FIFO */
  58 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  59 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  60 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  61 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  62 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  63 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  64
  65 /* Control Register Bit Definitions */
  66 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  67 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  68 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  69 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  70 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  71 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  72 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  73 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  74 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  75 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  76 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  77 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  78
  79 /*
  80  * Mode Register:
  81  * The mode register (MR) defines the mode of transfer as well as the data
  82  * format. If this register is modified during transmission or reception,
  83  * data validity cannot be guaranteed.
  84  */
  85 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  86 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  87 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  88 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  89
  90 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  91 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  92
  93 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  94 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  95 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
  96 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
  97 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
  98
  99 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 100 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 101 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 102
 103 /*
 104  * Interrupt Registers:
 105  * Interrupt control logic uses the interrupt enable register (IER) and the
 106  * interrupt disable register (IDR) to set the value of the bits in the
 107  * interrupt mask register (IMR). The IMR determines whether to pass an
 108  * interrupt to the interrupt status register (ISR).
 109  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 110  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 111  * Reading either IER or IDR returns 0x00.
 112  * All four registers have the same bit definitions.
 113  */
 114 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 115 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 116 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 117 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 118 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 119 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 120 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 121 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 122 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 123 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 124 #define CDNS_UART_IXR_RXMASK    0x000021e7 /* Valid RX bit mask */
 125
 126         /*
 127          * Do not enable parity error interrupt for the following
 128          * reason: When parity error interrupt is enabled, each Rx
 129          * parity error always results in 2 events. The first one
 130          * being parity error interrupt and the second one with a
 131          * proper Rx interrupt with the incoming data.  Disabling
 132          * parity error interrupt ensures better handling of parity
 133          * error events. With this change, for a parity error case, we
 134          * get a Rx interrupt with parity error set in ISR register
 135          * and we still handle parity errors in the desired way.
 136          */
 137
 138 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 139                                  CDNS_UART_IXR_OVERRUN | \
 140                                  CDNS_UART_IXR_RXTRIG |  \
 141                                  CDNS_UART_IXR_TOUT)
 142
 143 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 144 #define CDNS_UART_IXR_BRK       0x00002000
 145
 146 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 147 /*
 148  * Modem Control register:
 149  * The read/write Modem Control register controls the interface with the modem
 150  * or data set, or a peripheral device emulating a modem.
 151  */
 152 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 153 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 154 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 155
 156 /*
 157  * Channel Status Register:
 158  * The channel status register (CSR) is provided to enable the control logic
 159  * to monitor the status of bits in the channel interrupt status register,
 160  * even if these are masked out by the interrupt mask register.
 161  */
 162 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 163 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 164 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 165 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 166 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 167
 168 /* baud dividers min/max values */
 169 #define CDNS_UART_BDIV_MIN      4
 170 #define CDNS_UART_BDIV_MAX      255
 171 #define CDNS_UART_CD_MAX        65535
 172 #define UART_AUTOSUSPEND_TIMEOUT        3000
 173
 174 /**
 175  * struct cdns_uart - device data
 176  * @port:               Pointer to the UART port
 177  * @uartclk:            Reference clock
 178  * @pclk:               APB clock
 179  * @cdns_uart_driver:   Pointer to UART driver
 180  * @baud:               Current baud rate
 181  * @id:                 Port ID
 182  * @clk_rate_change_nb: Notifier block for clock changes
 183  * @quirks:             Flags for RXBS support.
 184  */
 185 struct cdns_uart {
 186         struct uart_port        *port;
 187         struct clk              *uartclk;
 188         struct clk              *pclk;
 189         struct uart_driver      *cdns_uart_driver;
 190         unsigned int            baud;
 191         int                     id;
 192         struct notifier_block   clk_rate_change_nb;
 193         u32                     quirks;
 194         bool cts_override;
 195 };
 196 struct cdns_platform_data {
 197         u32 quirks;
 198 };
 199 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 200                 clk_rate_change_nb)
 201
 202 /**
 203  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 204  * @dev_id: Id of the UART port
 205  * @isrstatus: The interrupt status register value as read
 206  * Return: None
 207  */
 208 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 209 {
 210         struct uart_port *port = (struct uart_port *)dev_id;
 211         struct cdns_uart *cdns_uart = port->private_data;
 212         unsigned int data;
 213         unsigned int rxbs_status = 0;
 214         unsigned int status_mask;
 215         unsigned int framerrprocessed = 0;
 216         char status = TTY_NORMAL;
 217         bool is_rxbs_support;
 218
 219         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 220
 221         while ((readl(port->membase + CDNS_UART_SR) &
 222                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 223                 if (is_rxbs_support)
 224                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 225                 data = readl(port->membase + CDNS_UART_FIFO);
 226                 port->icount.rx++;
 227                 /*
 228                  * There is no hardware break detection in Zynq, so we interpret
 229                  * framing error with all-zeros data as a break sequence.
 230                  * Most of the time, there's another non-zero byte at the
 231                  * end of the sequence.
 232                  */
 233                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 234                         if (!data) {
 235                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 236                                 framerrprocessed = 1;
 237                                 continue;
 238                         }
 239                 }
 240                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 241                         port->icount.brk++;
 242                         status = TTY_BREAK;
 243                         if (uart_handle_break(port))
 244                                 continue;
 245                 }
 246
 247                 isrstatus &= port->read_status_mask;
 248                 isrstatus &= ~port->ignore_status_mask;
 249                 status_mask = port->read_status_mask;
 250                 status_mask &= ~port->ignore_status_mask;
 251
 252                 if (data &&
 253                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 254                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 255                         port->icount.brk++;
 256                         if (uart_handle_break(port))
 257                                 continue;
 258                 }
 259
 260                 if (uart_handle_sysrq_char(port, data))
 261                         continue;
 262
 263                 if (is_rxbs_support) {
 264                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 265                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 266                                 port->icount.parity++;
 267                                 status = TTY_PARITY;
 268                         }
 269                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 270                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 271                                 port->icount.frame++;
 272                                 status = TTY_FRAME;
 273                         }
 274                 } else {
 275                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 276                                 port->icount.parity++;
 277                                 status = TTY_PARITY;
 278                         }
 279                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 280                             !framerrprocessed) {
 281                                 port->icount.frame++;
 282                                 status = TTY_FRAME;
 283                         }
 284                 }
 285                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 286                         port->icount.overrun++;
 287                         tty_insert_flip_char(&port->state->port, 0,
 288                                              TTY_OVERRUN);
 289                 }
 290                 tty_insert_flip_char(&port->state->port, data, status);
 291                 isrstatus = 0;
 292         }
 293         spin_unlock(&port->lock);
 294         tty_flip_buffer_push(&port->state->port);
 295         spin_lock(&port->lock);
 296 }
 297
 298 /**
 299  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 300  * @dev_id: Id of the UART port
 301  * Return: None
 302  */
 303 static void cdns_uart_handle_tx(void *dev_id)
 304 {
 305         struct uart_port *port = (struct uart_port *)dev_id;
 306         unsigned int numbytes;
 307
 308         if (uart_circ_empty(&port->state->xmit)) {
 309                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 310         } else {
 311                 numbytes = port->fifosize;
 312                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 313                        !(readl(port->membase + CDNS_UART_SR) &
 314                                                 CDNS_UART_SR_TXFULL)) {
 315                         /*
 316                          * Get the data from the UART circular buffer
 317                          * and write it to the cdns_uart's TX_FIFO
 318                          * register.
 319                          */
 320                         writel(
 321                                 port->state->xmit.buf[port->state->xmit.tail],
 322                                         port->membase + CDNS_UART_FIFO);
 323
 324                         port->icount.tx++;
 325
 326                         /*
 327                          * Adjust the tail of the UART buffer and wrap
 328                          * the buffer if it reaches limit.
 329                          */
 330                         port->state->xmit.tail =
 331                                 (port->state->xmit.tail + 1) &
 332                                         (UART_XMIT_SIZE - 1);
 333
 334                         numbytes--;
 335                 }
 336
 337                 if (uart_circ_chars_pending(
 338                                 &port->state->xmit) < WAKEUP_CHARS)
 339                         uart_write_wakeup(port);
 340         }
 341 }
 342
 343 /**
 344  * cdns_uart_isr - Interrupt handler
 345  * @irq: Irq number
 346  * @dev_id: Id of the port
 347  *
 348  * Return: IRQHANDLED
 349  */
 350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 351 {
 352         struct uart_port *port = (struct uart_port *)dev_id;
 353         unsigned int isrstatus;
 354
 355         spin_lock(&port->lock);
 356
 357         /* Read the interrupt status register to determine which
 358          * interrupt(s) is/are active and clear them.
 359          */
 360         isrstatus = readl(port->membase + CDNS_UART_ISR);
 361         writel(isrstatus, port->membase + CDNS_UART_ISR);
 362
 363         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 364                 cdns_uart_handle_tx(dev_id);
 365                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 366         }
 367
 368         /*
 369          * Skip RX processing if RX is disabled as RXEMPTY will never be set
 370          * as read bytes will not be removed from the FIFO.
 371          */
 372         if (isrstatus & CDNS_UART_IXR_RXMASK &&
 373             !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
 374                 cdns_uart_handle_rx(dev_id, isrstatus);
 375
 376         spin_unlock(&port->lock);
 377         return IRQ_HANDLED;
 378 }
 379
 380 /**
 381  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 382  * @clk: UART module input clock
 383  * @baud: Desired baud rate
 384  * @rbdiv: BDIV value (return value)
 385  * @rcd: CD value (return value)
 386  * @div8: Value for clk_sel bit in mod (return value)
 387  * Return: baud rate, requested baud when possible, or actual baud when there
 388  *      was too much error, zero if no valid divisors are found.
 389  *
 390  * Formula to obtain baud rate is
 391  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 392  *      input_clk = (Uart User Defined Clock or Apb Clock)
 393  *              depends on UCLKEN in MR Reg
 394  *      clk = input_clk or input_clk/8;
 395  *              depends on CLKS in MR reg
 396  *      CD and BDIV depends on values in
 397  *                      baud rate generate register
 398  *                      baud rate clock divisor register
 399  */
 400 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 401                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 402 {
 403         u32 cd, bdiv;
 404         unsigned int calc_baud;
 405         unsigned int bestbaud = 0;
 406         unsigned int bauderror;
 407         unsigned int besterror = ~0;
 408
 409         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 410                 *div8 = 1;
 411                 clk /= 8;
 412         } else {
 413                 *div8 = 0;
 414         }
 415
 416         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 417                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 418                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 419                         continue;
 420
 421                 calc_baud = clk / (cd * (bdiv + 1));
 422
 423                 if (baud > calc_baud)
 424                         bauderror = baud - calc_baud;
 425                 else
 426                         bauderror = calc_baud - baud;
 427
 428                 if (besterror > bauderror) {
 429                         *rbdiv = bdiv;
 430                         *rcd = cd;
 431                         bestbaud = calc_baud;
 432                         besterror = bauderror;
 433                 }
 434         }
 435         /* use the values when percent error is acceptable */
 436         if (((besterror * 100) / baud) < 3)
 437                 bestbaud = baud;
 438
 439         return bestbaud;
 440 }
 441
 442 /**
 443  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 444  * @port: Handle to the uart port structure
 445  * @baud: Baud rate to set
 446  * Return: baud rate, requested baud when possible, or actual baud when there
 447  *         was too much error, zero if no valid divisors are found.
 448  */
 449 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 450                 unsigned int baud)
 451 {
 452         unsigned int calc_baud;
 453         u32 cd = 0, bdiv = 0;
 454         u32 mreg;
 455         int div8;
 456         struct cdns_uart *cdns_uart = port->private_data;
 457
 458         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 459                         &div8);
 460
 461         /* Write new divisors to hardware */
 462         mreg = readl(port->membase + CDNS_UART_MR);
 463         if (div8)
 464                 mreg |= CDNS_UART_MR_CLKSEL;
 465         else
 466                 mreg &= ~CDNS_UART_MR_CLKSEL;
 467         writel(mreg, port->membase + CDNS_UART_MR);
 468         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 469         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 470         cdns_uart->baud = baud;
 471
 472         return calc_baud;
 473 }
 474
 475 #ifdef CONFIG_COMMON_CLK
 476 /**
 477  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 478  * @nb:         Notifier block
 479  * @event:      Notify event
 480  * @data:       Notifier data
 481  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 482  */
 483 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 484                 unsigned long event, void *data)
 485 {
 486         u32 ctrl_reg;
 487         struct uart_port *port;
 488         int locked = 0;
 489         struct clk_notifier_data *ndata = data;
 490         unsigned long flags = 0;
 491         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 492
 493         port = cdns_uart->port;
 494         if (port->suspended)
 495                 return NOTIFY_OK;
 496
 497         switch (event) {
 498         case PRE_RATE_CHANGE:
 499         {
 500                 u32 bdiv, cd;
 501                 int div8;
 502
 503                 /*
 504                  * Find out if current baud-rate can be achieved with new clock
 505                  * frequency.
 506                  */
 507                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 508                                         &bdiv, &cd, &div8)) {
 509                         dev_warn(port->dev, "clock rate change rejected\n");
 510                         return NOTIFY_BAD;
 511                 }
 512
 513                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 514
 515                 /* Disable the TX and RX to set baud rate */
 516                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 517                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 518                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 519
 520                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 521
 522                 return NOTIFY_OK;
 523         }
 524         case POST_RATE_CHANGE:
 525                 /*
 526                  * Set clk dividers to generate correct baud with new clock
 527                  * frequency.
 528                  */
 529
 530                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 531
 532                 locked = 1;
 533                 port->uartclk = ndata->new_rate;
 534
 535                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 536                                 cdns_uart->baud);
 537                 /* fall through */
 538         case ABORT_RATE_CHANGE:
 539                 if (!locked)
 540                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 541
 542                 /* Set TX/RX Reset */
 543                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 544                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 545                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 546
 547                 while (readl(port->membase + CDNS_UART_CR) &
 548                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 549                         cpu_relax();
 550
 551                 /*
 552                  * Clear the RX disable and TX disable bits and then set the TX
 553                  * enable bit and RX enable bit to enable the transmitter and
 554                  * receiver.
 555                  */
 556                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 557                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 558                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 559                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 560                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 561
 562                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 563
 564                 return NOTIFY_OK;
 565         default:
 566                 return NOTIFY_DONE;
 567         }
 568 }
 569 #endif
 570
 571 /**
 572  * cdns_uart_start_tx -  Start transmitting bytes
 573  * @port: Handle to the uart port structure
 574  */
 575 static void cdns_uart_start_tx(struct uart_port *port)
 576 {
 577         unsigned int status;
 578
 579         if (uart_tx_stopped(port))
 580                 return;
 581
 582         /*
 583          * Set the TX enable bit and clear the TX disable bit to enable the
 584          * transmitter.
 585          */
 586         status = readl(port->membase + CDNS_UART_CR);
 587         status &= ~CDNS_UART_CR_TX_DIS;
 588         status |= CDNS_UART_CR_TX_EN;
 589         writel(status, port->membase + CDNS_UART_CR);
 590
 591         if (uart_circ_empty(&port->state->xmit))
 592                 return;
 593
 594         cdns_uart_handle_tx(port);
 595
 596         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 597         /* Enable the TX Empty interrupt */
 598         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 599 }
 600
 601 /**
 602  * cdns_uart_stop_tx - Stop TX
 603  * @port: Handle to the uart port structure
 604  */
 605 static void cdns_uart_stop_tx(struct uart_port *port)
 606 {
 607         unsigned int regval;
 608
 609         regval = readl(port->membase + CDNS_UART_CR);
 610         regval |= CDNS_UART_CR_TX_DIS;
 611         /* Disable the transmitter */
 612         writel(regval, port->membase + CDNS_UART_CR);
 613 }
 614
 615 /**
 616  * cdns_uart_stop_rx - Stop RX
 617  * @port: Handle to the uart port structure
 618  */
 619 static void cdns_uart_stop_rx(struct uart_port *port)
 620 {
 621         unsigned int regval;
 622
 623         /* Disable RX IRQs */
 624         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 625
 626         /* Disable the receiver */
 627         regval = readl(port->membase + CDNS_UART_CR);
 628         regval |= CDNS_UART_CR_RX_DIS;
 629         writel(regval, port->membase + CDNS_UART_CR);
 630 }
 631
 632 /**
 633  * cdns_uart_tx_empty -  Check whether TX is empty
 634  * @port: Handle to the uart port structure
 635  *
 636  * Return: TIOCSER_TEMT on success, 0 otherwise
 637  */
 638 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 639 {
 640         unsigned int status;
 641
 642         status = readl(port->membase + CDNS_UART_SR) &
 643                                 CDNS_UART_SR_TXEMPTY;
 644         return status ? TIOCSER_TEMT : 0;
 645 }
 646
 647 /**
 648  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 649  *                      transmitting char breaks
 650  * @port: Handle to the uart port structure
 651  * @ctl: Value based on which start or stop decision is taken
 652  */
 653 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 654 {
 655         unsigned int status;
 656         unsigned long flags;
 657
 658         spin_lock_irqsave(&port->lock, flags);
 659
 660         status = readl(port->membase + CDNS_UART_CR);
 661
 662         if (ctl == -1)
 663                 writel(CDNS_UART_CR_STARTBRK | status,
 664                                 port->membase + CDNS_UART_CR);
 665         else {
 666                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 667                         writel(CDNS_UART_CR_STOPBRK | status,
 668                                         port->membase + CDNS_UART_CR);
 669         }
 670         spin_unlock_irqrestore(&port->lock, flags);
 671 }
 672
 673 /**
 674  * cdns_uart_set_termios - termios operations, handling data length, parity,
 675  *                              stop bits, flow control, baud rate
 676  * @port: Handle to the uart port structure
 677  * @termios: Handle to the input termios structure
 678  * @old: Values of the previously saved termios structure
 679  */
 680 static void cdns_uart_set_termios(struct uart_port *port,
 681                                 struct ktermios *termios, struct ktermios *old)
 682 {
 683         unsigned int cval = 0;
 684         unsigned int baud, minbaud, maxbaud;
 685         unsigned long flags;
 686         unsigned int ctrl_reg, mode_reg, val;
 687         int err;
 688
 689         /* Wait for the transmit FIFO to empty before making changes */
 690         if (!(readl(port->membase + CDNS_UART_CR) &
 691                                 CDNS_UART_CR_TX_DIS)) {
 692                 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
 693                                          val, (val & CDNS_UART_SR_TXEMPTY),
 694                                          1000, TX_TIMEOUT);
 695                 if (err) {
 696                         dev_err(port->dev, "timed out waiting for tx empty");
 697                         return;
 698                 }
 699         }
 700         spin_lock_irqsave(&port->lock, flags);
 701
 702         /* Disable the TX and RX to set baud rate */
 703         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 704         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 705         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 706
 707         /*
 708          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 709          * min and max baud should be calculated here based on port->uartclk.
 710          * this way we get a valid baud and can safely call set_baud()
 711          */
 712         minbaud = port->uartclk /
 713                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 714         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 715         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 716         baud = cdns_uart_set_baud_rate(port, baud);
 717         if (tty_termios_baud_rate(termios))
 718                 tty_termios_encode_baud_rate(termios, baud, baud);
 719
 720         /* Update the per-port timeout. */
 721         uart_update_timeout(port, termios->c_cflag, baud);
 722
 723         /* Set TX/RX Reset */
 724         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 725         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 726         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 727
 728         while (readl(port->membase + CDNS_UART_CR) &
 729                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 730                 cpu_relax();
 731
 732         /*
 733          * Clear the RX disable and TX disable bits and then set the TX enable
 734          * bit and RX enable bit to enable the transmitter and receiver.
 735          */
 736         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 737         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 738         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 739         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 740
 741         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 742
 743         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 744                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 745         port->ignore_status_mask = 0;
 746
 747         if (termios->c_iflag & INPCK)
 748                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 749                 CDNS_UART_IXR_FRAMING;
 750
 751         if (termios->c_iflag & IGNPAR)
 752                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 753                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 754
 755         /* ignore all characters if CREAD is not set */
 756         if ((termios->c_cflag & CREAD) == 0)
 757                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 758                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 759                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 760
 761         mode_reg = readl(port->membase + CDNS_UART_MR);
 762
 763         /* Handling Data Size */
 764         switch (termios->c_cflag & CSIZE) {
 765         case CS6:
 766                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 767                 break;
 768         case CS7:
 769                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 770                 break;
 771         default:
 772         case CS8:
 773                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 774                 termios->c_cflag &= ~CSIZE;
 775                 termios->c_cflag |= CS8;
 776                 break;
 777         }
 778
 779         /* Handling Parity and Stop Bits length */
 780         if (termios->c_cflag & CSTOPB)
 781                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 782         else
 783                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 784
 785         if (termios->c_cflag & PARENB) {
 786                 /* Mark or Space parity */
 787                 if (termios->c_cflag & CMSPAR) {
 788                         if (termios->c_cflag & PARODD)
 789                                 cval |= CDNS_UART_MR_PARITY_MARK;
 790                         else
 791                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 792                 } else {
 793                         if (termios->c_cflag & PARODD)
 794                                 cval |= CDNS_UART_MR_PARITY_ODD;
 795                         else
 796                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 797                 }
 798         } else {
 799                 cval |= CDNS_UART_MR_PARITY_NONE;
 800         }
 801         cval |= mode_reg & 1;
 802         writel(cval, port->membase + CDNS_UART_MR);
 803
 804         spin_unlock_irqrestore(&port->lock, flags);
 805 }
 806
 807 /**
 808  * cdns_uart_startup - Called when an application opens a cdns_uart port
 809  * @port: Handle to the uart port structure
 810  *
 811  * Return: 0 on success, negative errno otherwise
 812  */
 813 static int cdns_uart_startup(struct uart_port *port)
 814 {
 815         struct cdns_uart *cdns_uart = port->private_data;
 816         bool is_brk_support;
 817         int ret;
 818         unsigned long flags;
 819         unsigned int status = 0;
 820
 821         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 822
 823         spin_lock_irqsave(&port->lock, flags);
 824
 825         /* Disable the TX and RX */
 826         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 827                         port->membase + CDNS_UART_CR);
 828
 829         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 830          * no break chars.
 831          */
 832         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 833                         port->membase + CDNS_UART_CR);
 834
 835         while (readl(port->membase + CDNS_UART_CR) &
 836                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 837                 cpu_relax();
 838
 839         /*
 840          * Clear the RX disable bit and then set the RX enable bit to enable
 841          * the receiver.
 842          */
 843         status = readl(port->membase + CDNS_UART_CR);
 844         status &= ~CDNS_UART_CR_RX_DIS;
 845         status |= CDNS_UART_CR_RX_EN;
 846         writel(status, port->membase + CDNS_UART_CR);
 847
 848         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 849          * no parity.
 850          */
 851         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 852                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 853                 port->membase + CDNS_UART_MR);
 854
 855         /*
 856          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 857          * can be tuned with a module parameter
 858          */
 859         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 860
 861         /*
 862          * Receive Timeout register is enabled but it
 863          * can be tuned with a module parameter
 864          */
 865         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 866
 867         /* Clear out any pending interrupts before enabling them */
 868         writel(readl(port->membase + CDNS_UART_ISR),
 869                         port->membase + CDNS_UART_ISR);
 870
 871         spin_unlock_irqrestore(&port->lock, flags);
 872
 873         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 874         if (ret) {
 875                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 876                         port->irq, ret);
 877                 return ret;
 878         }
 879
 880         /* Set the Interrupt Registers with desired interrupts */
 881         if (is_brk_support)
 882                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 883                                         port->membase + CDNS_UART_IER);
 884         else
 885                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 886
 887         return 0;
 888 }
 889
 890 /**
 891  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 892  * @port: Handle to the uart port structure
 893  */
 894 static void cdns_uart_shutdown(struct uart_port *port)
 895 {
 896         int status;
 897         unsigned long flags;
 898
 899         spin_lock_irqsave(&port->lock, flags);
 900
 901         /* Disable interrupts */
 902         status = readl(port->membase + CDNS_UART_IMR);
 903         writel(status, port->membase + CDNS_UART_IDR);
 904         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 905
 906         /* Disable the TX and RX */
 907         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 908                         port->membase + CDNS_UART_CR);
 909
 910         spin_unlock_irqrestore(&port->lock, flags);
 911
 912         free_irq(port->irq, port);
 913 }
 914
 915 /**
 916  * cdns_uart_type - Set UART type to cdns_uart port
 917  * @port: Handle to the uart port structure
 918  *
 919  * Return: string on success, NULL otherwise
 920  */
 921 static const char *cdns_uart_type(struct uart_port *port)
 922 {
 923         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 924 }
 925
 926 /**
 927  * cdns_uart_verify_port - Verify the port params
 928  * @port: Handle to the uart port structure
 929  * @ser: Handle to the structure whose members are compared
 930  *
 931  * Return: 0 on success, negative errno otherwise.
 932  */
 933 static int cdns_uart_verify_port(struct uart_port *port,
 934                                         struct serial_struct *ser)
 935 {
 936         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 937                 return -EINVAL;
 938         if (port->irq != ser->irq)
 939                 return -EINVAL;
 940         if (ser->io_type != UPIO_MEM)
 941                 return -EINVAL;
 942         if (port->iobase != ser->port)
 943                 return -EINVAL;
 944         if (ser->hub6 != 0)
 945                 return -EINVAL;
 946         return 0;
 947 }
 948
 949 /**
 950  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 951  *                              called when the driver adds a cdns_uart port via
 952  *                              uart_add_one_port()
 953  * @port: Handle to the uart port structure
 954  *
 955  * Return: 0 on success, negative errno otherwise.
 956  */
 957 static int cdns_uart_request_port(struct uart_port *port)
 958 {
 959         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 960                                          CDNS_UART_NAME)) {
 961                 return -ENOMEM;
 962         }
 963
 964         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 965         if (!port->membase) {
 966                 dev_err(port->dev, "Unable to map registers\n");
 967                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 968                 return -ENOMEM;
 969         }
 970         return 0;
 971 }
 972
 973 /**
 974  * cdns_uart_release_port - Release UART port
 975  * @port: Handle to the uart port structure
 976  *
 977  * Release the memory region attached to a cdns_uart port. Called when the
 978  * driver removes a cdns_uart port via uart_remove_one_port().
 979  */
 980 static void cdns_uart_release_port(struct uart_port *port)
 981 {
 982         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 983         iounmap(port->membase);
 984         port->membase = NULL;
 985 }
 986
 987 /**
 988  * cdns_uart_config_port - Configure UART port
 989  * @port: Handle to the uart port structure
 990  * @flags: If any
 991  */
 992 static void cdns_uart_config_port(struct uart_port *port, int flags)
 993 {
 994         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 995                 port->type = PORT_XUARTPS;
 996 }
 997
 998 /**
 999  * cdns_uart_get_mctrl - Get the modem control state
1000  * @port: Handle to the uart port structure
1001  *
1002  * Return: the modem control state
1003  */
1004 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1005 {
1006         struct cdns_uart *cdns_uart_data = port->private_data;
1007
1008         if (cdns_uart_data->cts_override)
1009                 return 0;
1010
1011         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1012 }
1013
1014 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1015 {
1016         u32 val;
1017         u32 mode_reg;
1018         struct cdns_uart *cdns_uart_data = port->private_data;
1019
1020         if (cdns_uart_data->cts_override)
1021                 return;
1022
1023         val = readl(port->membase + CDNS_UART_MODEMCR);
1024         mode_reg = readl(port->membase + CDNS_UART_MR);
1025
1026         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1027                  CDNS_UART_MODEMCR_FCM);
1028         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1029
1030         if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1031                 val |= CDNS_UART_MODEMCR_FCM;
1032         if (mctrl & TIOCM_LOOP)
1033                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1034         else
1035                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1036
1037         writel(val, port->membase + CDNS_UART_MODEMCR);
1038         writel(mode_reg, port->membase + CDNS_UART_MR);
1039 }
1040
1041 #ifdef CONFIG_CONSOLE_POLL
1042 static int cdns_uart_poll_get_char(struct uart_port *port)
1043 {
1044         int c;
1045         unsigned long flags;
1046
1047         spin_lock_irqsave(&port->lock, flags);
1048
1049         /* Check if FIFO is empty */
1050         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1051                 c = NO_POLL_CHAR;
1052         else /* Read a character */
1053                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1054
1055         spin_unlock_irqrestore(&port->lock, flags);
1056
1057         return c;
1058 }
1059
1060 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1061 {
1062         unsigned long flags;
1063
1064         spin_lock_irqsave(&port->lock, flags);
1065
1066         /* Wait until FIFO is empty */
1067         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1068                 cpu_relax();
1069
1070         /* Write a character */
1071         writel(c, port->membase + CDNS_UART_FIFO);
1072
1073         /* Wait until FIFO is empty */
1074         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1075                 cpu_relax();
1076
1077         spin_unlock_irqrestore(&port->lock, flags);
1078 }
1079 #endif
1080
1081 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1082                    unsigned int oldstate)
1083 {
1084         switch (state) {
1085         case UART_PM_STATE_OFF:
1086                 pm_runtime_mark_last_busy(port->dev);
1087                 pm_runtime_put_autosuspend(port->dev);
1088                 break;
1089         default:
1090                 pm_runtime_get_sync(port->dev);
1091                 break;
1092         }
1093 }
1094
1095 static const struct uart_ops cdns_uart_ops = {
1096         .set_mctrl      = cdns_uart_set_mctrl,
1097         .get_mctrl      = cdns_uart_get_mctrl,
1098         .start_tx       = cdns_uart_start_tx,
1099         .stop_tx        = cdns_uart_stop_tx,
1100         .stop_rx        = cdns_uart_stop_rx,
1101         .tx_empty       = cdns_uart_tx_empty,
1102         .break_ctl      = cdns_uart_break_ctl,
1103         .set_termios    = cdns_uart_set_termios,
1104         .startup        = cdns_uart_startup,
1105         .shutdown       = cdns_uart_shutdown,
1106         .pm             = cdns_uart_pm,
1107         .type           = cdns_uart_type,
1108         .verify_port    = cdns_uart_verify_port,
1109         .request_port   = cdns_uart_request_port,
1110         .release_port   = cdns_uart_release_port,
1111         .config_port    = cdns_uart_config_port,
1112 #ifdef CONFIG_CONSOLE_POLL
1113         .poll_get_char  = cdns_uart_poll_get_char,
1114         .poll_put_char  = cdns_uart_poll_put_char,
1115 #endif
1116 };
1117
1118 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1119 /**
1120  * cdns_uart_console_putchar - write the character to the FIFO buffer
1121  * @port: Handle to the uart port structure
1122  * @ch: Character to be written
1123  */
1124 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1125 {
1126         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1127                 cpu_relax();
1128         writel(ch, port->membase + CDNS_UART_FIFO);
1129 }
1130
1131 static void cdns_early_write(struct console *con, const char *s,
1132                                     unsigned n)
1133 {
1134         struct earlycon_device *dev = con->data;
1135
1136         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1137 }
1138
1139 static int __init cdns_early_console_setup(struct earlycon_device *device,
1140                                            const char *opt)
1141 {
1142         struct uart_port *port = &device->port;
1143
1144         if (!port->membase)
1145                 return -ENODEV;
1146
1147         /* initialise control register */
1148         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1149                port->membase + CDNS_UART_CR);
1150
1151         /* only set baud if specified on command line - otherwise
1152          * assume it has been initialized by a boot loader.
1153          */
1154         if (port->uartclk && device->baud) {
1155                 u32 cd = 0, bdiv = 0;
1156                 u32 mr;
1157                 int div8;
1158
1159                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1160                                          &bdiv, &cd, &div8);
1161                 mr = CDNS_UART_MR_PARITY_NONE;
1162                 if (div8)
1163                         mr |= CDNS_UART_MR_CLKSEL;
1164
1165                 writel(mr,   port->membase + CDNS_UART_MR);
1166                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1167                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1168         }
1169
1170         device->con->write = cdns_early_write;
1171
1172         return 0;
1173 }
1174 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1175 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1176 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1177 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1178
1179
1180 /* Static pointer to console port */
1181 static struct uart_port *console_port;
1182
1183 /**
1184  * cdns_uart_console_write - perform write operation
1185  * @co: Console handle
1186  * @s: Pointer to character array
1187  * @count: No of characters
1188  */
1189 static void cdns_uart_console_write(struct console *co, const char *s,
1190                                 unsigned int count)
1191 {
1192         struct uart_port *port = console_port;
1193         unsigned long flags = 0;
1194         unsigned int imr, ctrl;
1195         int locked = 1;
1196
1197         if (port->sysrq)
1198                 locked = 0;
1199         else if (oops_in_progress)
1200                 locked = spin_trylock_irqsave(&port->lock, flags);
1201         else
1202                 spin_lock_irqsave(&port->lock, flags);
1203
1204         /* save and disable interrupt */
1205         imr = readl(port->membase + CDNS_UART_IMR);
1206         writel(imr, port->membase + CDNS_UART_IDR);
1207
1208         /*
1209          * Make sure that the tx part is enabled. Set the TX enable bit and
1210          * clear the TX disable bit to enable the transmitter.
1211          */
1212         ctrl = readl(port->membase + CDNS_UART_CR);
1213         ctrl &= ~CDNS_UART_CR_TX_DIS;
1214         ctrl |= CDNS_UART_CR_TX_EN;
1215         writel(ctrl, port->membase + CDNS_UART_CR);
1216
1217         uart_console_write(port, s, count, cdns_uart_console_putchar);
1218         while ((readl(port->membase + CDNS_UART_SR) &
1219                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1220                         CDNS_UART_SR_TXEMPTY)
1221                 cpu_relax();
1222
1223         /* restore interrupt state */
1224         writel(imr, port->membase + CDNS_UART_IER);
1225
1226         if (locked)
1227                 spin_unlock_irqrestore(&port->lock, flags);
1228 }
1229
1230 /**
1231  * cdns_uart_console_setup - Initialize the uart to default config
1232  * @co: Console handle
1233  * @options: Initial settings of uart
1234  *
1235  * Return: 0 on success, negative errno otherwise.
1236  */
1237 static int cdns_uart_console_setup(struct console *co, char *options)
1238 {
1239         struct uart_port *port = console_port;
1240
1241         int baud = 9600;
1242         int bits = 8;
1243         int parity = 'n';
1244         int flow = 'n';
1245
1246         if (!port->membase) {
1247                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1248                          co->index);
1249                 return -ENODEV;
1250         }
1251
1252         if (options)
1253                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1254
1255         return uart_set_options(port, co, baud, parity, bits, flow);
1256 }
1257 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1258
1259 #ifdef CONFIG_PM_SLEEP
1260 /**
1261  * cdns_uart_suspend - suspend event
1262  * @device: Pointer to the device structure
1263  *
1264  * Return: 0
1265  */
1266 static int cdns_uart_suspend(struct device *device)
1267 {
1268         struct uart_port *port = dev_get_drvdata(device);
1269         struct cdns_uart *cdns_uart = port->private_data;
1270         int may_wake;
1271
1272         may_wake = device_may_wakeup(device);
1273
1274         if (console_suspend_enabled && uart_console(port) && may_wake) {
1275                 unsigned long flags = 0;
1276
1277                 spin_lock_irqsave(&port->lock, flags);
1278                 /* Empty the receive FIFO 1st before making changes */
1279                 while (!(readl(port->membase + CDNS_UART_SR) &
1280                                         CDNS_UART_SR_RXEMPTY))
1281                         readl(port->membase + CDNS_UART_FIFO);
1282                 /* set RX trigger level to 1 */
1283                 writel(1, port->membase + CDNS_UART_RXWM);
1284                 /* disable RX timeout interrups */
1285                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1286                 spin_unlock_irqrestore(&port->lock, flags);
1287         }
1288
1289         /*
1290          * Call the API provided in serial_core.c file which handles
1291          * the suspend.
1292          */
1293         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1294 }
1295
1296 /**
1297  * cdns_uart_resume - Resume after a previous suspend
1298  * @device: Pointer to the device structure
1299  *
1300  * Return: 0
1301  */
1302 static int cdns_uart_resume(struct device *device)
1303 {
1304         struct uart_port *port = dev_get_drvdata(device);
1305         struct cdns_uart *cdns_uart = port->private_data;
1306         unsigned long flags = 0;
1307         u32 ctrl_reg;
1308         int may_wake;
1309
1310         may_wake = device_may_wakeup(device);
1311
1312         if (console_suspend_enabled && uart_console(port) && !may_wake) {
1313                 clk_enable(cdns_uart->pclk);
1314                 clk_enable(cdns_uart->uartclk);
1315
1316                 spin_lock_irqsave(&port->lock, flags);
1317
1318                 /* Set TX/RX Reset */
1319                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1320                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1321                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1322                 while (readl(port->membase + CDNS_UART_CR) &
1323                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1324                         cpu_relax();
1325
1326                 /* restore rx timeout value */
1327                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1328                 /* Enable Tx/Rx */
1329                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1330                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1331                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1332                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1333
1334                 clk_disable(cdns_uart->uartclk);
1335                 clk_disable(cdns_uart->pclk);
1336                 spin_unlock_irqrestore(&port->lock, flags);
1337         } else {
1338                 spin_lock_irqsave(&port->lock, flags);
1339                 /* restore original rx trigger level */
1340                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1341                 /* enable RX timeout interrupt */
1342                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1343                 spin_unlock_irqrestore(&port->lock, flags);
1344         }
1345
1346         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1347 }
1348 #endif /* ! CONFIG_PM_SLEEP */
1349 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1350 {
1351         struct uart_port *port = dev_get_drvdata(dev);
1352         struct cdns_uart *cdns_uart = port->private_data;
1353
1354         clk_disable(cdns_uart->uartclk);
1355         clk_disable(cdns_uart->pclk);
1356         return 0;
1357 };
1358
1359 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1360 {
1361         struct uart_port *port = dev_get_drvdata(dev);
1362         struct cdns_uart *cdns_uart = port->private_data;
1363
1364         clk_enable(cdns_uart->pclk);
1365         clk_enable(cdns_uart->uartclk);
1366         return 0;
1367 };
1368
1369 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1370         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1371         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1372                            cdns_runtime_resume, NULL)
1373 };
1374
1375 static const struct cdns_platform_data zynqmp_uart_def = {
1376                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1377
1378 /* Match table for of_platform binding */
1379 static const struct of_device_id cdns_uart_of_match[] = {
1380         { .compatible = "xlnx,xuartps", },
1381         { .compatible = "cdns,uart-r1p8", },
1382         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1383         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1384         {}
1385 };
1386 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1387
1388 /*
1389  * Maximum number of instances without alias IDs but if there is alias
1390  * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1391  */
1392 #define MAX_UART_INSTANCES      32
1393
1394 /* Stores static aliases list */
1395 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1396 static int alias_bitmap_initialized;
1397
1398 /* Stores actual bitmap of allocated IDs with alias IDs together */
1399 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1400 /* Protect bitmap operations to have unique IDs */
1401 static DEFINE_MUTEX(bitmap_lock);
1402
1403 static int cdns_get_id(struct platform_device *pdev)
1404 {
1405         int id, ret;
1406
1407         mutex_lock(&bitmap_lock);
1408
1409         /* Alias list is stable that's why get alias bitmap only once */
1410         if (!alias_bitmap_initialized) {
1411                 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1412                                               alias_bitmap, MAX_UART_INSTANCES);
1413                 if (ret && ret != -EOVERFLOW) {
1414                         mutex_unlock(&bitmap_lock);
1415                         return ret;
1416                 }
1417
1418                 alias_bitmap_initialized++;
1419         }
1420
1421         /* Make sure that alias ID is not taken by instance without alias */
1422         bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1423
1424         dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1425                 MAX_UART_INSTANCES, bitmap);
1426
1427         /* Look for a serialN alias */
1428         id = of_alias_get_id(pdev->dev.of_node, "serial");
1429         if (id < 0) {
1430                 dev_warn(&pdev->dev,
1431                          "No serial alias passed. Using the first free id\n");
1432
1433                 /*
1434                  * Start with id 0 and check if there is no serial0 alias
1435                  * which points to device which is compatible with this driver.
1436                  * If alias exists then try next free position.
1437                  */
1438                 id = 0;
1439
1440                 for (;;) {
1441                         dev_info(&pdev->dev, "Checking id %d\n", id);
1442                         id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1443
1444                         /* No free empty instance */
1445                         if (id == MAX_UART_INSTANCES) {
1446                                 dev_err(&pdev->dev, "No free ID\n");
1447                                 mutex_unlock(&bitmap_lock);
1448                                 return -EINVAL;
1449                         }
1450
1451                         dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1452                         /* Check if ID is empty */
1453                         if (!test_and_set_bit(id, bitmap)) {
1454                                 /* Break the loop if bit is taken */
1455                                 dev_dbg(&pdev->dev,
1456                                         "Selected ID %d allocation passed\n",
1457                                         id);
1458                                 break;
1459                         }
1460                         dev_dbg(&pdev->dev,
1461                                 "Selected ID %d allocation failed\n", id);
1462                         /* if taking bit fails then try next one */
1463                         id++;
1464                 }
1465         }
1466
1467         mutex_unlock(&bitmap_lock);
1468
1469         return id;
1470 }
1471
1472 /**
1473  * cdns_uart_probe - Platform driver probe
1474  * @pdev: Pointer to the platform device structure
1475  *
1476  * Return: 0 on success, negative errno otherwise
1477  */
1478 static int cdns_uart_probe(struct platform_device *pdev)
1479 {
1480         int rc, irq;
1481         struct uart_port *port;
1482         struct resource *res;
1483         struct cdns_uart *cdns_uart_data;
1484         const struct of_device_id *match;
1485         struct uart_driver *cdns_uart_uart_driver;
1486         char *driver_name;
1487 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1488         struct console *cdns_uart_console;
1489 #endif
1490
1491         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1492                         GFP_KERNEL);
1493         if (!cdns_uart_data)
1494                 return -ENOMEM;
1495         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1496         if (!port)
1497                 return -ENOMEM;
1498
1499         cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1500                                              sizeof(*cdns_uart_uart_driver),
1501                                              GFP_KERNEL);
1502         if (!cdns_uart_uart_driver)
1503                 return -ENOMEM;
1504
1505         cdns_uart_data->id = cdns_get_id(pdev);
1506         if (cdns_uart_data->id < 0)
1507                 return cdns_uart_data->id;
1508
1509         /* There is a need to use unique driver name */
1510         driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1511                                      CDNS_UART_NAME, cdns_uart_data->id);
1512         if (!driver_name) {
1513                 rc = -ENOMEM;
1514                 goto err_out_id;
1515         }
1516
1517         cdns_uart_uart_driver->owner = THIS_MODULE;
1518         cdns_uart_uart_driver->driver_name = driver_name;
1519         cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1520         cdns_uart_uart_driver->major = uartps_major;
1521         cdns_uart_uart_driver->minor = cdns_uart_data->id;
1522         cdns_uart_uart_driver->nr = 1;
1523
1524 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1525         cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1526                                          GFP_KERNEL);
1527         if (!cdns_uart_console) {
1528                 rc = -ENOMEM;
1529                 goto err_out_id;
1530         }
1531
1532         strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1533                 sizeof(cdns_uart_console->name));
1534         cdns_uart_console->index = cdns_uart_data->id;
1535         cdns_uart_console->write = cdns_uart_console_write;
1536         cdns_uart_console->device = uart_console_device;
1537         cdns_uart_console->setup = cdns_uart_console_setup;
1538         cdns_uart_console->flags = CON_PRINTBUFFER;
1539         cdns_uart_console->data = cdns_uart_uart_driver;
1540         cdns_uart_uart_driver->cons = cdns_uart_console;
1541 #endif
1542
1543         rc = uart_register_driver(cdns_uart_uart_driver);
1544         if (rc < 0) {
1545                 dev_err(&pdev->dev, "Failed to register driver\n");
1546                 goto err_out_id;
1547         }
1548
1549         cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1550
1551         /*
1552          * Setting up proper name_base needs to be done after uart
1553          * registration because tty_driver structure is not filled.
1554          * name_base is 0 by default.
1555          */
1556         cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1557
1558         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1559         if (match && match->data) {
1560                 const struct cdns_platform_data *data = match->data;
1561
1562                 cdns_uart_data->quirks = data->quirks;
1563         }
1564
1565         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1566         if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1567                 rc = PTR_ERR(cdns_uart_data->pclk);
1568                 goto err_out_unregister_driver;
1569         }
1570
1571         if (IS_ERR(cdns_uart_data->pclk)) {
1572                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1573                 if (IS_ERR(cdns_uart_data->pclk)) {
1574                         rc = PTR_ERR(cdns_uart_data->pclk);
1575                         goto err_out_unregister_driver;
1576                 }
1577                 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1578         }
1579
1580         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1581         if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1582                 rc = PTR_ERR(cdns_uart_data->uartclk);
1583                 goto err_out_unregister_driver;
1584         }
1585
1586         if (IS_ERR(cdns_uart_data->uartclk)) {
1587                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1588                 if (IS_ERR(cdns_uart_data->uartclk)) {
1589                         rc = PTR_ERR(cdns_uart_data->uartclk);
1590                         goto err_out_unregister_driver;
1591                 }
1592                 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1593         }
1594
1595         rc = clk_prepare_enable(cdns_uart_data->pclk);
1596         if (rc) {
1597                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1598                 goto err_out_unregister_driver;
1599         }
1600         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1601         if (rc) {
1602                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1603                 goto err_out_clk_dis_pclk;
1604         }
1605
1606         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607         if (!res) {
1608                 rc = -ENODEV;
1609                 goto err_out_clk_disable;
1610         }
1611
1612         irq = platform_get_irq(pdev, 0);
1613         if (irq <= 0) {
1614                 rc = -ENXIO;
1615                 goto err_out_clk_disable;
1616         }
1617
1618 #ifdef CONFIG_COMMON_CLK
1619         cdns_uart_data->clk_rate_change_nb.notifier_call =
1620                         cdns_uart_clk_notifier_cb;
1621         if (clk_notifier_register(cdns_uart_data->uartclk,
1622                                 &cdns_uart_data->clk_rate_change_nb))
1623                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1624 #endif
1625
1626         /* At this point, we've got an empty uart_port struct, initialize it */
1627         spin_lock_init(&port->lock);
1628         port->type      = PORT_UNKNOWN;
1629         port->iotype    = UPIO_MEM32;
1630         port->flags     = UPF_BOOT_AUTOCONF;
1631         port->ops       = &cdns_uart_ops;
1632         port->fifosize  = CDNS_UART_FIFO_SIZE;
1633         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1634
1635         /*
1636          * Register the port.
1637          * This function also registers this device with the tty layer
1638          * and triggers invocation of the config_port() entry point.
1639          */
1640         port->mapbase = res->start;
1641         port->irq = irq;
1642         port->dev = &pdev->dev;
1643         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1644         port->private_data = cdns_uart_data;
1645         cdns_uart_data->port = port;
1646         platform_set_drvdata(pdev, port);
1647
1648         pm_runtime_use_autosuspend(&pdev->dev);
1649         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1650         pm_runtime_set_active(&pdev->dev);
1651         pm_runtime_enable(&pdev->dev);
1652         device_init_wakeup(port->dev, true);
1653
1654 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1655         /*
1656          * If console hasn't been found yet try to assign this port
1657          * because it is required to be assigned for console setup function.
1658          * If register_console() don't assign value, then console_port pointer
1659          * is cleanup.
1660          */
1661         if (!console_port)
1662                 console_port = port;
1663 #endif
1664
1665         rc = uart_add_one_port(cdns_uart_uart_driver, port);
1666         if (rc) {
1667                 dev_err(&pdev->dev,
1668                         "uart_add_one_port() failed; err=%i\n", rc);
1669                 goto err_out_pm_disable;
1670         }
1671
1672 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1673         /* This is not port which is used for console that's why clean it up */
1674         if (console_port == port &&
1675             !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1676                 console_port = NULL;
1677 #endif
1678
1679         uartps_major = cdns_uart_uart_driver->tty_driver->major;
1680         cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1681                                                              "cts-override");
1682         return 0;
1683
1684 err_out_pm_disable:
1685         pm_runtime_disable(&pdev->dev);
1686         pm_runtime_set_suspended(&pdev->dev);
1687         pm_runtime_dont_use_autosuspend(&pdev->dev);
1688 #ifdef CONFIG_COMMON_CLK
1689         clk_notifier_unregister(cdns_uart_data->uartclk,
1690                         &cdns_uart_data->clk_rate_change_nb);
1691 #endif
1692 err_out_clk_disable:
1693         clk_disable_unprepare(cdns_uart_data->uartclk);
1694 err_out_clk_dis_pclk:
1695         clk_disable_unprepare(cdns_uart_data->pclk);
1696 err_out_unregister_driver:
1697         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1698 err_out_id:
1699         mutex_lock(&bitmap_lock);
1700         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1701                 clear_bit(cdns_uart_data->id, bitmap);
1702         mutex_unlock(&bitmap_lock);
1703         return rc;
1704 }
1705
1706 /**
1707  * cdns_uart_remove - called when the platform driver is unregistered
1708  * @pdev: Pointer to the platform device structure
1709  *
1710  * Return: 0 on success, negative errno otherwise
1711  */
1712 static int cdns_uart_remove(struct platform_device *pdev)
1713 {
1714         struct uart_port *port = platform_get_drvdata(pdev);
1715         struct cdns_uart *cdns_uart_data = port->private_data;
1716         int rc;
1717
1718         /* Remove the cdns_uart port from the serial core */
1719 #ifdef CONFIG_COMMON_CLK
1720         clk_notifier_unregister(cdns_uart_data->uartclk,
1721                         &cdns_uart_data->clk_rate_change_nb);
1722 #endif
1723         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1724         port->mapbase = 0;
1725         mutex_lock(&bitmap_lock);
1726         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1727                 clear_bit(cdns_uart_data->id, bitmap);
1728         mutex_unlock(&bitmap_lock);
1729         clk_disable_unprepare(cdns_uart_data->uartclk);
1730         clk_disable_unprepare(cdns_uart_data->pclk);
1731         pm_runtime_disable(&pdev->dev);
1732         pm_runtime_set_suspended(&pdev->dev);
1733         pm_runtime_dont_use_autosuspend(&pdev->dev);
1734         device_init_wakeup(&pdev->dev, false);
1735
1736 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1737         if (console_port == port)
1738                 console_port = NULL;
1739 #endif
1740
1741         /* If this is last instance major number should be initialized */
1742         mutex_lock(&bitmap_lock);
1743         if (bitmap_empty(bitmap, MAX_UART_INSTANCES))
1744                 uartps_major = 0;
1745         mutex_unlock(&bitmap_lock);
1746
1747         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1748         return rc;
1749 }
1750
1751 static struct platform_driver cdns_uart_platform_driver = {
1752         .probe   = cdns_uart_probe,
1753         .remove  = cdns_uart_remove,
1754         .driver  = {
1755                 .name = CDNS_UART_NAME,
1756                 .of_match_table = cdns_uart_of_match,
1757                 .pm = &cdns_uart_dev_pm_ops,
1758                 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1759                 },
1760 };
1761
1762 static int __init cdns_uart_init(void)
1763 {
1764         /* Register the platform driver */
1765         return platform_driver_register(&cdns_uart_platform_driver);
1766 }
1767
1768 static void __exit cdns_uart_exit(void)
1769 {
1770         /* Unregister the platform driver */
1771         platform_driver_unregister(&cdns_uart_platform_driver);
1772 }
1773
1774 arch_initcall(cdns_uart_init);
1775 module_exit(cdns_uart_exit);
1776
1777 MODULE_DESCRIPTION("Driver for Cadence UART");
1778 MODULE_AUTHOR("Xilinx Inc.");
1779 MODULE_LICENSE("GPL");